From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Gregory Clement <gregory.clement@free-electrons.com>,
Arnd Bergmann <arnd@arndb.de>, Maen Suleiman <maen@marvell.com>,
Lior Amsalem <alior@marvell.com>,
Thierry Reding <thierry.reding@avionic-design.de>,
Eran Ben-Avi <benavi@marvell.com>,
Nadav Haklai <nadavh@marvell.com>,
Shadi Ammouri <shadi@marvell.com>,
Tawfik Bayouk <tawfik@marvell.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Jason Gunthorpe <jgunthorpe@obsidianresearch.com>,
Russell King - ARM Linux <linux@arm.linux.org.uk>
Subject: [PATCH v2 22/27] arm: mvebu: add PCIe Device Tree informations for Armada XP
Date: Mon, 28 Jan 2013 19:56:31 +0100 [thread overview]
Message-ID: <1359399397-29729-23-git-send-email-thomas.petazzoni@free-electrons.com> (raw)
In-Reply-To: <1359399397-29729-1-git-send-email-thomas.petazzoni@free-electrons.com>
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 92 ++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 105 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 150 ++++++++++++++++++++++++++++++
3 files changed, 347 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index e041f42..6abb0ff 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -70,5 +70,97 @@
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
+
+ /*
+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-370-xp-pcie";
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x00000800 0 0xd0040000 0xd0040000 0 0x00002000 /* port 0.0 registers */
+ 0x00004800 0 0xd0042000 0xd0042000 0 0x00002000 /* port 2.0 registers */
+ 0x00001000 0 0xd0044000 0xd0044000 0 0x00002000 /* port 0.1 registers */
+ 0x00001800 0 0xd0048000 0xd0048000 0 0x00002000 /* port 0.2 registers */
+ 0x00002000 0 0xd004C000 0xd004C000 0 0x00002000 /* port 0.3 registers */
+ 0x81000000 0 0 0xc0000000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0 0xc1000000 0 0x08000000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 1>;
+ interrupt-map = <0x0800 0 0 1 &mpic 58 1
+ 0x1000 0 0 1 &mpic 59 1
+ 0x1800 0 0 1 &mpic 60 1
+ 0x2000 0 0 1 &mpic 61 1
+ 0x4800 0 0 1 &mpic 99 1>;
+
+ pcie@0,0 {
+ device_type = "pciex";
+ reg = <0x0800 0 0xd0040000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@0,1 {
+ device_type = "pciex";
+ reg = <0x1000 0 0xd0044000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ interrupts = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie@0,2 {
+ device_type = "pciex";
+ reg = <0x1800 0 0xd0048000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ interrupts = <1>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie@0,3 {
+ device_type = "pciex";
+ reg = <0x2000 0 0xd004C000 0 0xC000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ interrupts = <1>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pciex";
+ reg = <0x4800 0 0xd0042000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 9e23bd8..ab8c593 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -90,5 +90,110 @@
clocks = <&gateclk 1>;
status = "disabled";
};
+
+ /*
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-370-xp-pcie";
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x00000800 0 0xd0040000 0xd0040000 0 0x00002000 /* port 0.0 registers */
+ 0x00004800 0 0xd0042000 0xd0042000 0 0x00002000 /* port 2.0 registers */
+ 0x00001000 0 0xd0044000 0xd0044000 0 0x00002000 /* port 0.1 registers */
+ 0x00001800 0 0xd0048000 0xd0048000 0 0x00002000 /* port 0.2 registers */
+ 0x00002000 0 0xd004C000 0xd004C000 0 0x00002000 /* port 0.3 registers */
+ 0x00005000 0 0xd0082000 0xd0082000 0 0x00002000 /* port 3.0 registers */
+ 0x81000000 0 0 0xc0000000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0 0xc1000000 0 0x08000000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 1>;
+ interrupt-map = <0x0800 0 0 1 &mpic 58 1
+ 0x1000 0 0 1 &mpic 59 1
+ 0x1800 0 0 1 &mpic 60 1
+ 0x2000 0 0 1 &mpic 61 1
+ 0x4800 0 0 1 &mpic 99 1
+ 0x5000 0 0 1 &mpic 103 1>;
+
+ pcie@0,0 {
+ device_type = "pciex";
+ reg = <0x0800 0 0xd0040000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@0,1 {
+ device_type = "pciex";
+ reg = <0x1000 0 0xd0044000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ interrupts = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie@0,2 {
+ device_type = "pciex";
+ reg = <0x1800 0 0xd0048000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ interrupts = <1>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie@0,3 {
+ device_type = "pciex";
+ reg = <0x2000 0 0xd004C000 0 0xC000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ interrupts = <1>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pciex";
+ reg = <0x4800 0 0xd0042000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie@3,0 {
+ device_type = "pciex";
+ reg = <0x5000 0 0xd0082000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 9659661..00c69aa 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -105,5 +105,155 @@
clocks = <&gateclk 1>;
status = "disabled";
};
+
+ /*
+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. Two units are
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-370-xp-pcie";
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x00000800 0 0xd0040000 0xd0040000 0 0x00002000 /* port 0.0 registers */
+ 0x00004800 0 0xd0042000 0xd0042000 0 0x00002000 /* port 2.0 registers */
+ 0x00001000 0 0xd0044000 0xd0044000 0 0x00002000 /* port 0.1 registers */
+ 0x00001800 0 0xd0048000 0xd0048000 0 0x00002000 /* port 0.2 registers */
+ 0x00002000 0 0xd004C000 0xd004C000 0 0x00002000 /* port 0.3 registers */
+ 0x00002800 0 0xd0080000 0xd0080000 0 0x00002000 /* port 1.0 registers */
+ 0x00005000 0 0xd0082000 0xd0082000 0 0x00002000 /* port 3.0 registers */
+ 0x00003000 0 0xd0084000 0xd0084000 0 0x00002000 /* port 1.1 registers */
+ 0x00003800 0 0xd0088000 0xd0088000 0 0x00002000 /* port 1.2 registers */
+ 0x00004000 0 0xd008C000 0xd008C000 0 0x00002000 /* port 1.3 registers */
+ 0x81000000 0 0 0xc0000000 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0 0xc1000000 0 0x08000000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 1>;
+ interrupt-map = <0x0800 0 0 1 &mpic 58
+ 0x1000 0 0 1 &mpic 59
+ 0x1800 0 0 1 &mpic 60
+ 0x2000 0 0 1 &mpic 61
+ 0x2800 0 0 1 &mpic 62
+ 0x3000 0 0 1 &mpic 63
+ 0x3800 0 0 1 &mpic 64
+ 0x4000 0 0 1 &mpic 65
+ 0x4800 0 0 1 &mpic 99
+ 0x5000 0 0 1 &mpic 103>;
+
+ pcie@0,0 {
+ device_type = "pciex";
+ reg = <0x0800 0 0xd0040000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@0,1 {
+ device_type = "pciex";
+ reg = <0x1000 0 0xd0044000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie@0,2 {
+ device_type = "pciex";
+ reg = <0x1800 0 0xd0048000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie@0,3 {
+ device_type = "pciex";
+ reg = <0x2000 0 0xd004C000 0 0xC000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie@1,0 {
+ device_type = "pciex";
+ reg = <0x2800 0 0xd0080000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+
+ pcie@1,1 {
+ device_type = "pciex";
+ reg = <0x3000 0 0xd0084000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 10>;
+ status = "disabled";
+ };
+
+ pcie@1,2 {
+ device_type = "pciex";
+ reg = <0x3800 0 0xd0088000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 11>;
+ status = "disabled";
+ };
+
+ pcie@1,3 {
+ device_type = "pciex";
+ reg = <0x4000 0 0xd008C000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 12>;
+ status = "disabled";
+ };
+ pcie@2,0 {
+ device_type = "pciex";
+ reg = <0x4800 0 0xd0042000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie@3,0 {
+ device_type = "pciex";
+ reg = <0x5000 0 0xd0082000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
};
};
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 22/27] arm: mvebu: add PCIe Device Tree informations for Armada XP
Date: Mon, 28 Jan 2013 19:56:31 +0100 [thread overview]
Message-ID: <1359399397-29729-23-git-send-email-thomas.petazzoni@free-electrons.com> (raw)
In-Reply-To: <1359399397-29729-1-git-send-email-thomas.petazzoni@free-electrons.com>
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 92 ++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 105 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 150 ++++++++++++++++++++++++++++++
3 files changed, 347 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index e041f42..6abb0ff 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -70,5 +70,97 @@
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
+
+ /*
+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-370-xp-pcie";
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x00000800 0 0xd0040000 0xd0040000 0 0x00002000 /* port 0.0 registers */
+ 0x00004800 0 0xd0042000 0xd0042000 0 0x00002000 /* port 2.0 registers */
+ 0x00001000 0 0xd0044000 0xd0044000 0 0x00002000 /* port 0.1 registers */
+ 0x00001800 0 0xd0048000 0xd0048000 0 0x00002000 /* port 0.2 registers */
+ 0x00002000 0 0xd004C000 0xd004C000 0 0x00002000 /* port 0.3 registers */
+ 0x81000000 0 0 0xc0000000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0 0xc1000000 0 0x08000000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 1>;
+ interrupt-map = <0x0800 0 0 1 &mpic 58 1
+ 0x1000 0 0 1 &mpic 59 1
+ 0x1800 0 0 1 &mpic 60 1
+ 0x2000 0 0 1 &mpic 61 1
+ 0x4800 0 0 1 &mpic 99 1>;
+
+ pcie at 0,0 {
+ device_type = "pciex";
+ reg = <0x0800 0 0xd0040000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 0,1 {
+ device_type = "pciex";
+ reg = <0x1000 0 0xd0044000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ interrupts = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie at 0,2 {
+ device_type = "pciex";
+ reg = <0x1800 0 0xd0048000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ interrupts = <1>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie at 0,3 {
+ device_type = "pciex";
+ reg = <0x2000 0 0xd004C000 0 0xC000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ interrupts = <1>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie at 2,0 {
+ device_type = "pciex";
+ reg = <0x4800 0 0xd0042000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 9e23bd8..ab8c593 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -90,5 +90,110 @@
clocks = <&gateclk 1>;
status = "disabled";
};
+
+ /*
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-370-xp-pcie";
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x00000800 0 0xd0040000 0xd0040000 0 0x00002000 /* port 0.0 registers */
+ 0x00004800 0 0xd0042000 0xd0042000 0 0x00002000 /* port 2.0 registers */
+ 0x00001000 0 0xd0044000 0xd0044000 0 0x00002000 /* port 0.1 registers */
+ 0x00001800 0 0xd0048000 0xd0048000 0 0x00002000 /* port 0.2 registers */
+ 0x00002000 0 0xd004C000 0xd004C000 0 0x00002000 /* port 0.3 registers */
+ 0x00005000 0 0xd0082000 0xd0082000 0 0x00002000 /* port 3.0 registers */
+ 0x81000000 0 0 0xc0000000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0 0xc1000000 0 0x08000000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 1>;
+ interrupt-map = <0x0800 0 0 1 &mpic 58 1
+ 0x1000 0 0 1 &mpic 59 1
+ 0x1800 0 0 1 &mpic 60 1
+ 0x2000 0 0 1 &mpic 61 1
+ 0x4800 0 0 1 &mpic 99 1
+ 0x5000 0 0 1 &mpic 103 1>;
+
+ pcie at 0,0 {
+ device_type = "pciex";
+ reg = <0x0800 0 0xd0040000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 0,1 {
+ device_type = "pciex";
+ reg = <0x1000 0 0xd0044000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ interrupts = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie at 0,2 {
+ device_type = "pciex";
+ reg = <0x1800 0 0xd0048000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ interrupts = <1>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie at 0,3 {
+ device_type = "pciex";
+ reg = <0x2000 0 0xd004C000 0 0xC000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ interrupts = <1>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie at 2,0 {
+ device_type = "pciex";
+ reg = <0x4800 0 0xd0042000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie at 3,0 {
+ device_type = "pciex";
+ reg = <0x5000 0 0xd0082000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ interrupts = <1>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 9659661..00c69aa 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -105,5 +105,155 @@
clocks = <&gateclk 1>;
status = "disabled";
};
+
+ /*
+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. Two units are
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-370-xp-pcie";
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x00000800 0 0xd0040000 0xd0040000 0 0x00002000 /* port 0.0 registers */
+ 0x00004800 0 0xd0042000 0xd0042000 0 0x00002000 /* port 2.0 registers */
+ 0x00001000 0 0xd0044000 0xd0044000 0 0x00002000 /* port 0.1 registers */
+ 0x00001800 0 0xd0048000 0xd0048000 0 0x00002000 /* port 0.2 registers */
+ 0x00002000 0 0xd004C000 0xd004C000 0 0x00002000 /* port 0.3 registers */
+ 0x00002800 0 0xd0080000 0xd0080000 0 0x00002000 /* port 1.0 registers */
+ 0x00005000 0 0xd0082000 0xd0082000 0 0x00002000 /* port 3.0 registers */
+ 0x00003000 0 0xd0084000 0xd0084000 0 0x00002000 /* port 1.1 registers */
+ 0x00003800 0 0xd0088000 0xd0088000 0 0x00002000 /* port 1.2 registers */
+ 0x00004000 0 0xd008C000 0xd008C000 0 0x00002000 /* port 1.3 registers */
+ 0x81000000 0 0 0xc0000000 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0 0xc1000000 0 0x08000000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 1>;
+ interrupt-map = <0x0800 0 0 1 &mpic 58
+ 0x1000 0 0 1 &mpic 59
+ 0x1800 0 0 1 &mpic 60
+ 0x2000 0 0 1 &mpic 61
+ 0x2800 0 0 1 &mpic 62
+ 0x3000 0 0 1 &mpic 63
+ 0x3800 0 0 1 &mpic 64
+ 0x4000 0 0 1 &mpic 65
+ 0x4800 0 0 1 &mpic 99
+ 0x5000 0 0 1 &mpic 103>;
+
+ pcie at 0,0 {
+ device_type = "pciex";
+ reg = <0x0800 0 0xd0040000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 0,1 {
+ device_type = "pciex";
+ reg = <0x1000 0 0xd0044000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie at 0,2 {
+ device_type = "pciex";
+ reg = <0x1800 0 0xd0048000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie at 0,3 {
+ device_type = "pciex";
+ reg = <0x2000 0 0xd004C000 0 0xC000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie at 1,0 {
+ device_type = "pciex";
+ reg = <0x2800 0 0xd0080000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+
+ pcie at 1,1 {
+ device_type = "pciex";
+ reg = <0x3000 0 0xd0084000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 10>;
+ status = "disabled";
+ };
+
+ pcie at 1,2 {
+ device_type = "pciex";
+ reg = <0x3800 0 0xd0088000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 11>;
+ status = "disabled";
+ };
+
+ pcie at 1,3 {
+ device_type = "pciex";
+ reg = <0x4000 0 0xd008C000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 12>;
+ status = "disabled";
+ };
+ pcie at 2,0 {
+ device_type = "pciex";
+ reg = <0x4800 0 0xd0042000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie at 3,0 {
+ device_type = "pciex";
+ reg = <0x5000 0 0xd0082000 0 0x2000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
};
};
--
1.7.9.5
next prev parent reply other threads:[~2013-01-28 18:57 UTC|newest]
Thread overview: 433+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-28 18:56 [PATCH v2] PCIe support for the Armada 370 and Armada XP SoCs Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 01/27] of/pci: Provide support for parsing PCI DT ranges property Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 02/27] of/pci: Add of_pci_get_devfn() function Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 22:00 ` Stephen Warren
2013-01-28 22:00 ` Stephen Warren
2013-01-28 22:16 ` Thierry Reding
2013-01-28 22:16 ` Thierry Reding
2013-01-29 10:04 ` Thomas Petazzoni
2013-01-29 10:04 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 03/27] of/pci: Add of_pci_parse_bus_range() function Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 04/27] ARM: pci: Allow passing per-controller private data Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 05/27] arm: pci: add a align_resource hook Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-29 15:12 ` Thomas Petazzoni
2013-01-29 15:12 ` Thomas Petazzoni
2013-01-29 15:15 ` Russell King - ARM Linux
2013-01-29 15:15 ` Russell King - ARM Linux
2013-01-29 15:23 ` Thomas Petazzoni
2013-01-29 15:23 ` Thomas Petazzoni
2013-01-29 15:25 ` Russell King - ARM Linux
2013-01-29 15:25 ` Russell King - ARM Linux
2013-01-29 15:28 ` Thomas Petazzoni
2013-01-29 15:28 ` Thomas Petazzoni
2013-01-29 15:58 ` Russell King - ARM Linux
2013-01-29 15:58 ` Russell King - ARM Linux
2013-01-29 16:20 ` Thomas Petazzoni
2013-01-29 16:20 ` Thomas Petazzoni
2013-01-29 16:45 ` Arnd Bergmann
2013-01-29 16:45 ` Arnd Bergmann
2013-01-29 17:09 ` Thomas Petazzoni
2013-01-29 17:09 ` Thomas Petazzoni
2013-01-29 20:15 ` Arnd Bergmann
2013-01-29 20:15 ` Arnd Bergmann
2013-01-29 20:33 ` Thomas Petazzoni
2013-01-29 20:33 ` Thomas Petazzoni
2013-01-29 21:59 ` Thomas Petazzoni
2013-01-29 21:59 ` Thomas Petazzoni
2013-01-29 22:17 ` Stephen Warren
2013-01-29 22:17 ` Stephen Warren
2013-01-30 4:49 ` Jason Gunthorpe
2013-01-30 4:49 ` Jason Gunthorpe
2013-01-29 22:54 ` Arnd Bergmann
2013-01-29 22:54 ` Arnd Bergmann
2013-01-30 4:21 ` Jason Gunthorpe
2013-01-30 4:21 ` Jason Gunthorpe
2013-01-30 9:55 ` Arnd Bergmann
2013-01-30 9:55 ` Arnd Bergmann
2013-01-30 11:47 ` Thomas Petazzoni
2013-01-30 11:47 ` Thomas Petazzoni
2013-01-30 16:17 ` Arnd Bergmann
2013-01-30 16:17 ` Arnd Bergmann
2013-01-30 16:38 ` Thomas Petazzoni
2013-01-30 16:38 ` Thomas Petazzoni
2013-01-30 20:48 ` Bjorn Helgaas
2013-01-30 20:48 ` Bjorn Helgaas
2013-01-30 21:06 ` Jason Gunthorpe
2013-01-30 21:06 ` Jason Gunthorpe
2013-01-30 4:56 ` Jason Gunthorpe
2013-01-30 4:56 ` Jason Gunthorpe
2013-01-30 8:19 ` Thomas Petazzoni
2013-01-30 8:19 ` Thomas Petazzoni
2013-01-30 9:46 ` Arnd Bergmann
2013-01-30 9:46 ` Arnd Bergmann
2013-01-30 9:54 ` Thomas Petazzoni
2013-01-30 9:54 ` Thomas Petazzoni
2013-01-30 10:03 ` Arnd Bergmann
2013-01-30 10:03 ` Arnd Bergmann
2013-01-30 11:42 ` Thomas Petazzoni
2013-01-30 11:42 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 06/27] lib: devres: don't enclose pcim_*() functions in CONFIG_HAS_IOPORT Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 07/27] PCI: Add software-emulated host bridge Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 20:18 ` Arnd Bergmann
2013-01-28 20:18 ` Arnd Bergmann
2013-01-28 22:03 ` Stephen Warren
2013-01-28 22:03 ` Stephen Warren
2013-01-28 22:09 ` Jason Gunthorpe
2013-01-28 22:09 ` Jason Gunthorpe
2013-01-28 22:18 ` Thomas Petazzoni
2013-01-28 22:18 ` Thomas Petazzoni
2013-01-28 22:23 ` Jason Gunthorpe
2013-01-28 22:23 ` Jason Gunthorpe
2013-01-28 22:30 ` Thomas Petazzoni
2013-01-28 22:30 ` Thomas Petazzoni
2013-01-28 22:51 ` Jason Gunthorpe
2013-01-28 22:51 ` Jason Gunthorpe
2013-01-29 10:01 ` Thomas Petazzoni
2013-01-29 10:01 ` Thomas Petazzoni
2013-01-29 17:42 ` Jason Gunthorpe
2013-01-29 17:42 ` Jason Gunthorpe
2013-01-29 17:43 ` Thomas Petazzoni
2013-01-29 17:43 ` Thomas Petazzoni
2013-01-29 2:40 ` Bjorn Helgaas
2013-01-29 2:40 ` Bjorn Helgaas
2013-01-29 6:16 ` Jason Gunthorpe
2013-01-29 6:16 ` Jason Gunthorpe
2013-01-28 22:09 ` Thomas Petazzoni
2013-01-28 22:09 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 08/27] pci: implement an emulated PCI-to-PCI bridge Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 19:35 ` Jason Gunthorpe
2013-01-28 19:35 ` Jason Gunthorpe
2013-01-28 19:39 ` Thomas Petazzoni
2013-01-28 19:39 ` Thomas Petazzoni
2013-01-28 19:55 ` Jason Gunthorpe
2013-01-28 19:55 ` Jason Gunthorpe
2013-01-28 22:06 ` Stephen Warren
2013-01-28 22:06 ` Stephen Warren
2013-01-28 22:16 ` Jason Gunthorpe
2013-01-28 22:16 ` Jason Gunthorpe
2013-01-29 22:35 ` Bjorn Helgaas
2013-01-29 22:35 ` Bjorn Helgaas
2013-01-29 23:06 ` Arnd Bergmann
2013-01-29 23:06 ` Arnd Bergmann
2013-01-30 4:12 ` Jason Gunthorpe
2013-01-30 4:12 ` Jason Gunthorpe
2013-01-28 18:56 ` [PATCH v2 09/27] pci: infrastructure to add drivers in drivers/pci/host Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 10/27] arm: mvebu: fix address-cells in mpic DT node Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 11/27] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 22:08 ` Stephen Warren
2013-01-28 22:08 ` Stephen Warren
2013-01-28 22:21 ` Thomas Petazzoni
2013-01-28 22:21 ` Thomas Petazzoni
2013-01-28 22:27 ` Stephen Warren
2013-01-28 22:27 ` Stephen Warren
2013-01-28 22:44 ` Thomas Petazzoni
2013-01-28 22:44 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 12/27] clk: mvebu: add more PCIe clocks for Armada XP Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 13/27] arm: plat-orion: introduce WIN_CTRL_ENABLE in address mapping code Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 14/27] arm: plat-orion: refactor the orion_disable_wins() function Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 15/27] arm: plat-orion: introduce orion_{alloc,free}_cpu_win() functions Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 15/27] arm: plat-orion: introduce orion_{alloc, free}_cpu_win() functions Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 16/27] arm: mvebu: add functions to alloc/free PCIe decoding windows Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 17/27] arm: plat-orion: make common PCIe code usable on mvebu Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 18/27] arm: plat-orion: add more flexible PCI configuration space read/write functions Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 19:51 ` Jason Gunthorpe
2013-01-28 19:51 ` Jason Gunthorpe
2013-01-29 8:40 ` Thomas Petazzoni
2013-01-29 8:40 ` Thomas Petazzoni
2013-01-29 17:40 ` Jason Gunthorpe
2013-01-29 17:40 ` Jason Gunthorpe
2013-01-28 18:56 ` [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 22:21 ` Stephen Warren
2013-01-28 22:21 ` Stephen Warren
2013-01-29 8:41 ` Thomas Petazzoni
2013-01-29 8:41 ` Thomas Petazzoni
2013-01-29 9:20 ` Thierry Reding
2013-01-29 9:20 ` Thierry Reding
2013-01-29 9:21 ` Thomas Petazzoni
2013-01-29 9:21 ` Thomas Petazzoni
2013-02-07 10:24 ` Thomas Petazzoni
2013-02-07 10:24 ` Thomas Petazzoni
2013-02-07 15:46 ` Bjorn Helgaas
2013-02-07 15:46 ` Bjorn Helgaas
2013-02-07 16:00 ` Thomas Petazzoni
2013-02-07 16:00 ` Thomas Petazzoni
2013-02-07 18:08 ` Bjorn Helgaas
2013-02-07 18:08 ` Bjorn Helgaas
2013-02-07 18:15 ` Jason Gunthorpe
2013-02-07 18:15 ` Jason Gunthorpe
2013-02-07 18:30 ` Bjorn Helgaas
2013-02-07 18:30 ` Bjorn Helgaas
2013-02-07 18:43 ` Thierry Reding
2013-02-07 18:43 ` Thierry Reding
2013-01-29 19:47 ` Stephen Warren
2013-01-29 19:47 ` Stephen Warren
2013-01-29 3:29 ` Bjorn Helgaas
2013-01-29 3:29 ` Bjorn Helgaas
2013-01-29 5:55 ` Jason Gunthorpe
2013-01-29 5:55 ` Jason Gunthorpe
2013-01-29 8:00 ` Thomas Petazzoni
2013-01-29 8:00 ` Thomas Petazzoni
2013-01-29 17:47 ` Bjorn Helgaas
2013-01-29 17:47 ` Bjorn Helgaas
2013-01-29 18:14 ` Thomas Petazzoni
2013-01-29 18:14 ` Thomas Petazzoni
2013-01-29 18:41 ` Jason Gunthorpe
2013-01-29 18:41 ` Jason Gunthorpe
2013-01-29 19:07 ` Bjorn Helgaas
2013-01-29 19:07 ` Bjorn Helgaas
2013-01-29 19:18 ` Jason Gunthorpe
2013-01-29 19:18 ` Jason Gunthorpe
2013-01-29 19:38 ` Bjorn Helgaas
2013-01-29 19:38 ` Bjorn Helgaas
2013-01-29 22:27 ` Bjorn Helgaas
2013-01-29 22:27 ` Bjorn Helgaas
2013-01-30 4:24 ` Jason Gunthorpe
2013-01-30 4:24 ` Jason Gunthorpe
2013-01-30 9:35 ` Thomas Petazzoni
2013-01-30 9:35 ` Thomas Petazzoni
2013-01-30 18:52 ` Bjorn Helgaas
2013-01-30 18:52 ` Bjorn Helgaas
2013-01-30 22:28 ` Thomas Petazzoni
2013-01-30 22:28 ` Thomas Petazzoni
2013-01-30 23:10 ` Jason Gunthorpe
2013-01-30 23:10 ` Jason Gunthorpe
2013-01-30 23:48 ` Bjorn Helgaas
2013-01-30 23:48 ` Bjorn Helgaas
2013-01-31 16:04 ` Thomas Petazzoni
2013-01-31 16:04 ` Thomas Petazzoni
2013-01-31 16:30 ` Bjorn Helgaas
2013-01-31 16:30 ` Bjorn Helgaas
2013-01-31 16:33 ` Thomas Petazzoni
2013-01-31 16:33 ` Thomas Petazzoni
2013-01-31 17:03 ` Bjorn Helgaas
2013-01-31 17:03 ` Bjorn Helgaas
2013-01-31 16:42 ` Russell King - ARM Linux
2013-01-31 16:42 ` Russell King - ARM Linux
2013-01-29 13:22 ` Andrew Murray
2013-01-29 13:22 ` Andrew Murray
2013-01-29 13:45 ` Thomas Petazzoni
2013-01-29 13:45 ` Thomas Petazzoni
2013-01-29 14:05 ` Andrew Murray
2013-01-29 14:05 ` Andrew Murray
2013-01-29 14:20 ` Thierry Reding
2013-01-29 14:20 ` Thierry Reding
2013-01-29 14:29 ` Thomas Petazzoni
2013-01-29 14:29 ` Thomas Petazzoni
2013-01-29 15:02 ` Thierry Reding
2013-01-29 15:02 ` Thierry Reding
2013-01-29 15:08 ` Andrew Murray
2013-01-29 15:08 ` Andrew Murray
2013-01-29 15:10 ` Thomas Petazzoni
2013-01-29 15:10 ` Thomas Petazzoni
2013-02-07 14:37 ` Thomas Petazzoni
2013-02-07 14:37 ` Thomas Petazzoni
2013-02-07 15:51 ` Andrew Murray
2013-02-07 15:51 ` Andrew Murray
2013-02-07 16:19 ` Thomas Petazzoni
2013-02-07 16:19 ` Thomas Petazzoni
2013-02-07 16:40 ` Thomas Petazzoni
2013-02-07 16:40 ` Thomas Petazzoni
2013-02-07 16:53 ` Andrew Murray
2013-02-07 16:53 ` Andrew Murray
2013-02-07 17:14 ` Thomas Petazzoni
2013-02-07 17:14 ` Thomas Petazzoni
2013-02-07 17:29 ` Andrew Murray
2013-02-07 17:29 ` Andrew Murray
2013-02-07 17:37 ` Thomas Petazzoni
2013-02-07 17:37 ` Thomas Petazzoni
2013-02-07 18:21 ` Jason Gunthorpe
2013-02-07 18:21 ` Jason Gunthorpe
2013-02-07 23:25 ` Arnd Bergmann
2013-02-07 23:25 ` Arnd Bergmann
2013-02-08 0:44 ` Jason Gunthorpe
2013-02-08 0:44 ` Jason Gunthorpe
2013-02-09 22:23 ` Arnd Bergmann
2013-02-09 22:23 ` Arnd Bergmann
2013-02-12 19:26 ` Jason Gunthorpe
2013-02-12 19:26 ` Jason Gunthorpe
2013-02-07 18:30 ` Andrew Murray
2013-02-07 18:30 ` Andrew Murray
2013-02-07 23:27 ` Arnd Bergmann
2013-02-07 23:27 ` Arnd Bergmann
2013-01-30 11:32 ` Russell King - ARM Linux
2013-01-30 11:32 ` Russell King - ARM Linux
2013-01-30 11:37 ` Thomas Petazzoni
2013-01-30 11:37 ` Thomas Petazzoni
2013-01-30 12:03 ` Thierry Reding
2013-01-30 12:03 ` Thierry Reding
2013-01-30 13:07 ` Thomas Petazzoni
2013-01-30 13:07 ` Thomas Petazzoni
2013-01-30 15:08 ` Russell King - ARM Linux
2013-01-30 15:08 ` Russell King - ARM Linux
2013-01-30 15:19 ` Russell King - ARM Linux
2013-01-30 15:19 ` Russell King - ARM Linux
2013-01-30 15:36 ` Thomas Petazzoni
2013-01-30 15:36 ` Thomas Petazzoni
2013-01-30 15:46 ` Russell King - ARM Linux
2013-01-30 15:46 ` Russell King - ARM Linux
2013-01-31 14:30 ` Thomas Petazzoni
2013-01-31 14:30 ` Thomas Petazzoni
2013-01-31 14:50 ` Russell King - ARM Linux
2013-01-31 14:50 ` Russell King - ARM Linux
2013-01-31 14:57 ` Thomas Petazzoni
2013-01-31 14:57 ` Thomas Petazzoni
2013-01-31 15:08 ` Russell King - ARM Linux
2013-01-31 15:08 ` Russell King - ARM Linux
2013-01-31 15:22 ` Thomas Petazzoni
2013-01-31 15:22 ` Thomas Petazzoni
2013-01-31 15:36 ` Russell King - ARM Linux
2013-01-31 15:36 ` Russell King - ARM Linux
2013-01-31 15:47 ` Thomas Petazzoni
2013-01-31 15:47 ` Thomas Petazzoni
2013-01-31 15:48 ` Russell King - ARM Linux
2013-01-31 15:48 ` Russell King - ARM Linux
2013-01-31 16:18 ` Arnd Bergmann
2013-01-31 16:18 ` Arnd Bergmann
2013-01-31 18:02 ` Jason Gunthorpe
2013-01-31 18:02 ` Jason Gunthorpe
2013-01-31 20:46 ` Arnd Bergmann
2013-01-31 20:46 ` Arnd Bergmann
2013-01-31 22:44 ` Jason Gunthorpe
2013-01-31 22:44 ` Jason Gunthorpe
2013-02-01 11:30 ` Arnd Bergmann
2013-02-01 11:30 ` Arnd Bergmann
2013-02-01 19:52 ` Jason Gunthorpe
2013-02-01 19:52 ` Jason Gunthorpe
2013-02-06 16:51 ` Thomas Petazzoni
2013-02-06 16:51 ` Thomas Petazzoni
2013-02-06 17:09 ` Jason Gunthorpe
2013-02-06 17:09 ` Jason Gunthorpe
2013-02-06 17:18 ` Thomas Petazzoni
2013-02-06 17:18 ` Thomas Petazzoni
2013-02-06 17:50 ` Jason Gunthorpe
2013-02-06 17:50 ` Jason Gunthorpe
2013-02-06 18:02 ` Thomas Petazzoni
2013-02-06 18:02 ` Thomas Petazzoni
2013-02-06 18:22 ` Stephen Warren
2013-02-06 18:22 ` Stephen Warren
2013-02-06 18:39 ` Jason Gunthorpe
2013-02-06 18:39 ` Jason Gunthorpe
2013-02-06 18:42 ` Thomas Petazzoni
2013-02-06 18:42 ` Thomas Petazzoni
2013-02-06 22:04 ` Arnd Bergmann
2013-02-06 22:04 ` Arnd Bergmann
2013-02-07 15:50 ` Giving special alignment/size constraints to the Linux PCI core? Thomas Petazzoni
2013-02-07 23:33 ` Arnd Bergmann
2013-02-07 23:33 ` Arnd Bergmann
2013-02-08 4:21 ` Bjorn Helgaas
2013-02-08 4:21 ` Bjorn Helgaas
2013-02-08 8:14 ` Thomas Petazzoni
2013-02-08 8:14 ` Thomas Petazzoni
2013-02-12 16:00 ` Arnd Bergmann
2013-02-12 16:00 ` Arnd Bergmann
2013-02-12 18:41 ` Jason Gunthorpe
2013-02-12 18:41 ` Jason Gunthorpe
2013-02-12 19:02 ` Arnd Bergmann
2013-02-12 19:02 ` Arnd Bergmann
2013-02-12 19:38 ` Jason Gunthorpe
2013-02-12 19:38 ` Jason Gunthorpe
2013-02-12 23:05 ` Arnd Bergmann
2013-02-12 23:05 ` Arnd Bergmann
2013-02-13 0:32 ` Jason Gunthorpe
2013-02-13 0:32 ` Jason Gunthorpe
2013-02-13 18:53 ` Arnd Bergmann
2013-02-13 18:53 ` Arnd Bergmann
2013-02-13 19:12 ` Jason Gunthorpe
2013-02-13 19:12 ` Jason Gunthorpe
2013-02-13 19:51 ` Thomas Petazzoni
2013-02-13 19:51 ` Thomas Petazzoni
2013-02-13 21:10 ` Arnd Bergmann
2013-02-13 21:10 ` Arnd Bergmann
2013-02-13 21:20 ` Yinghai Lu
2013-02-13 21:20 ` Yinghai Lu
2013-02-13 22:24 ` Arnd Bergmann
2013-02-13 22:24 ` Arnd Bergmann
2013-02-13 21:02 ` Yinghai Lu
2013-02-13 21:02 ` Yinghai Lu
2013-01-31 7:10 ` [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems Thierry Reding
2013-01-31 7:10 ` Thierry Reding
2013-02-01 0:34 ` Stephen Warren
2013-02-01 0:34 ` Stephen Warren
2013-02-01 1:41 ` Jason Gunthorpe
2013-02-01 1:41 ` Jason Gunthorpe
2013-02-01 2:21 ` Stephen Warren
2013-02-01 2:21 ` Stephen Warren
2013-02-01 3:51 ` Jason Gunthorpe
2013-02-01 3:51 ` Jason Gunthorpe
2013-02-01 9:03 ` Thomas Petazzoni
2013-02-01 9:03 ` Thomas Petazzoni
2013-02-01 16:07 ` Arnd Bergmann
2013-02-01 16:07 ` Arnd Bergmann
2013-02-01 16:26 ` Russell King - ARM Linux
2013-02-01 16:26 ` Russell King - ARM Linux
2013-02-01 17:45 ` Arnd Bergmann
2013-02-01 17:45 ` Arnd Bergmann
2013-02-01 19:58 ` Jason Gunthorpe
2013-02-01 19:58 ` Jason Gunthorpe
2013-02-01 8:46 ` Thomas Petazzoni
2013-02-01 8:46 ` Thomas Petazzoni
2013-02-01 16:02 ` Arnd Bergmann
2013-02-01 16:02 ` Arnd Bergmann
2013-02-01 17:57 ` Stephen Warren
2013-02-01 17:57 ` Stephen Warren
2013-02-01 19:39 ` Jason Gunthorpe
2013-02-01 19:39 ` Jason Gunthorpe
2013-02-01 20:30 ` Stephen Warren
2013-02-01 20:30 ` Stephen Warren
2013-01-28 18:56 ` [PATCH v2 20/27] arm: mvebu: PCIe support is now available on mvebu Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 21/27] arm: mvebu: add PCIe Device Tree informations for Armada 370 Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni [this message]
2013-01-28 18:56 ` [PATCH v2 22/27] arm: mvebu: add PCIe Device Tree informations for Armada XP Thomas Petazzoni
2013-02-06 22:41 ` Arnd Bergmann
2013-02-06 22:41 ` Arnd Bergmann
2013-02-06 23:07 ` Thomas Petazzoni
2013-02-06 23:07 ` Thomas Petazzoni
2013-02-07 8:04 ` Arnd Bergmann
2013-02-07 8:04 ` Arnd Bergmann
2013-02-07 8:45 ` Thomas Petazzoni
2013-02-07 8:45 ` Thomas Petazzoni
2013-02-07 9:09 ` Arnd Bergmann
2013-02-07 9:09 ` Arnd Bergmann
2013-02-07 1:05 ` Jason Gunthorpe
2013-02-07 1:05 ` Jason Gunthorpe
2013-02-07 7:28 ` Thierry Reding
2013-02-07 7:28 ` Thierry Reding
2013-02-07 17:49 ` Jason Gunthorpe
2013-02-07 17:49 ` Jason Gunthorpe
2013-02-07 8:24 ` Arnd Bergmann
2013-02-07 8:24 ` Arnd Bergmann
2013-02-07 17:00 ` Jason Gunthorpe
2013-02-07 17:00 ` Jason Gunthorpe
2013-02-07 23:44 ` Arnd Bergmann
2013-02-07 23:44 ` Arnd Bergmann
2013-01-28 18:56 ` [PATCH v2 23/27] arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 24/27] arm: mvebu: PCIe Device Tree informations for Armada XP DB Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 25/27] arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 26/27] arm: mvebu: PCIe Device Tree informations for Armada 370 DB Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
2013-01-28 18:56 ` [PATCH v2 27/27] arm: mvebu: update defconfig with PCI and USB support Thomas Petazzoni
2013-01-28 18:56 ` Thomas Petazzoni
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