From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> To: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, Gregory Clement <gregory.clement@free-electrons.com>, Maen Suleiman <maen@marvell.com>, Lior Amsalem <alior@marvell.com>, Thierry Reding <thierry.reding@avionic-design.de>, Eran Ben-Avi <benavi@marvell.com>, Nadav Haklai <nadavh@marvell.com>, Shadi Ammouri <shadi@marvell.com>, Tawfik Bayouk <tawfik@marvell.com>, Stephen Warren <swarren@wwwdotorg.org>, Russell King - ARM Linux <linux@arm.linux.org.uk> Subject: Re: [PATCH v2 22/27] arm: mvebu: add PCIe Device Tree informations for Armada XP Date: Wed, 6 Feb 2013 18:05:02 -0700 [thread overview] Message-ID: <20130207010502.GA7435@obsidianresearch.com> (raw) In-Reply-To: <201302062241.14444.arnd@arndb.de> On Wed, Feb 06, 2013 at 10:41:14PM +0000, Arnd Bergmann wrote: > This would mean that rather than putting the mapped physical address > (0xc0000000, 0xc1000000, ...) in here, you would actually have 64-bit > address as the destination as well, in whatever format the > address map hardware uses, I assume using a numbered 32 bit > address space for each object that can be remapped. Do you mean like: mbus_matrix { /* At this level addresses are <32 bit MBUS target ID> <32 bit target address offset> target_id is an internal MBUS specification */ #address-cells = <2>; #size-cells = <1>; pex0 { ranges = < // CPU window bridged to PCI MMIO 0x82000000 0x00000000 0x00000000 0x<target_id> 0x0 0x0 0x8000000 // CPU IO window bridged to PCI IO 0x81000000 0x00000000 0x00000000 0x<target_id> 0x0 0x0 0xa0000 ...>; } nand { reg = <0x<target_id> 0 0x200>; }; internal_regs { ranges = <0 0x<target_id> 0 0x10000>; timer { reg = <0x20300 0x20>; }; }; } ? I think the big issue would go back to how to pool all the link decoders together in a way that fits OF and Linux's PCI core will understand? How does of_translate_address work in a world like this? > This would also let you do the PCI memory address assignment for > each port separately, starting at bus address 0, followed by > finding a location in the CPU address space and passing > the start as the sys->mem_offset argument to > pci_add_resource_offset. That goes back to the original problem - the goal is to have only one pci_sys_data, not one for every link. The host driver would have to request a large region of physical address space and still dole it out on a link by link basis. Not sure how to model that in DT?? In any event, changing how all the dynamic windows are configured in DT is a big job (there was another thread about this) it seems orthogonal to the PCI host driver.. > > + pcie@0,0 { > > + device_type = "pciex"; > > + reg = <0x0800 0 0xd0040000 0 0x2000>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + marvell,pcie-port = <0>; > > + marvell,pcie-lane = <0>; > > + interrupts = <1>; > > + clocks = <&gateclk 5>; > > + status = "disabled"; > > + }; > > I think you are missing a "ranges" property here, at least an empty > one, which is required by the standard but not currently enforced > in the code. Maybe.. according to the standard the ranges in this stanza should reflect the bridge configuration, but that isn't known when the DT is written. An empty ranges means identity and that isn't really right either. Also, what should 'reg' be so that the PCI core binds the OF nodes properly? The standard says reg should have the configuration space address of the bridge, and I noticed Thierry was using something that almost looked like a config space address in his driver.. But that seems overly tricky.. When using the link stanzas, shouldn't this scheme be more like this: // The PCI-E host bridge pex@0 { device_type = "pciex"; // <<-- Important!! ranges = < // Driver internal control registers in MMIO space 0x82000000 0x10000000 0xd0040000 0xd0040000 0x0 0x8000000 // CPU 0xe0000000 -> e8000000 bridged to PCI MMIO 0x82000000 0x00000000 0xe0000000 0xe0000000 0x0 0x8000000 // CPU IO bus 0x0000000 -> 0xa0000 bridged to PCI IO 0x81000000 0x00000000 0x00000000 0x00000000 0x0 0xa0000 // CPU 0xe8000000 -> f0000000 bridged to PCI MMIO, prefetchable 0xC2000000 0x00000000 0xe8000000 0xe8000000 0x0 0x8000000 >; //... // PCI-PCI bridge to Physical link 0 pcie@0,0 { device_type = "pciex"; // The configuration space address of the PCI-PCI bridge required by OF reg = <0x80 0 0 0 0>; // Bus 0, Dev 0x10, Fn 0 /* The 'bar' on the PCI-PCI bridge, maps to internal control registers, required by the driver. */ assigned-addresses = <0x82000000 0x10000000 0xd0040000 0 0x2000>; // .. } } Thierry, what do you think? I struggled with this particular area of the OF system recently and Grant Likely was very helpful - the above is based on that discussion.. ====== Thomas, here is one possible alternate idea, not sure on the merit, just including it because it is close to what I've got in my DT right now..: // The entire multi-lane controller and PCI root bus pex@0 { device_type = "pciex"; /* This section configures the Linux PCI host driver. Each line is a physical PCI-Link. (Erorrs included :) */ compatible = "marvell,armada-370-xp-pcie"; regs = <0xd0040000 0x00002000 // port 0.0 0xd0042000 0x00002000 // port 2.0 0xd0044000 0x00002000 // port 0.1 0xd0048000 0x00002000 // port 0.2 0xd004C000 0x00002000>; // port 0.3 io-cpu-window = <0xc0000000 0xa0000>; interrupts = <58 59 60 61 99>; clocks = <&gateclk 5 &gateclk 6 &gateclk 7 &gateclk 8 &gateclk 26> marvell,port-lane <0 0 0 1 0 2 0 3 2 0>; /* Below here configures the aggregate PCI bus the PEX0 stanza describes */ #address-cells = <3>; #size-cells = <2>; // CPU resources allocated to this PCI host bridge bus-range = <0x00 0xff>; ranges = < // CPU 0xe0000000 -> e8000000 bridged to PCI MMIO 0x82000000 0x00000000 0xe0000000 0xe0000000 0x0 0x8000000 // CPU IO bus 0x0000000 -> 0xa0000 bridged to PCI IO 0x81000000 0x00000000 0x00000000 0x00000000 0x0 0xa0000 // CPU 0xe8000000 -> f0000000 bridged to PCI MMIO, prefetchable 0xC2000000 0x00000000 0xe8000000 0xe8000000 0x0 0x8000000 >; /* Any PCI devices associated with this bus go here, relative to the above ranges. As example: */ link@0 { device_type = "pciex"; // Root port at bus 0, device 0x10, function 0 reg = <0x00000080 0 0 0 0>; ep { device_type = "pciex"; // End port on bus 1, device 0, function 0 reg = <0x00000100 0 0 0 0>; } } } Thoughts: - 'regs' in the main stanza, keep to CPU addresses instead of confusing translated fake ranges address - each regs line is matches to an interrupt, clock and port-lane line to describe a link. The above describes 5 links. - The CPU physical address window to use for the IO space is set via io-cpu-window, not much choice here, the PCI format ranges must be 0 based. - It is not necessary to have per-root port stanzas at all with the above. - There is only one PCI bus stanza, the top level. Jason
WARNING: multiple messages have this Message-ID (diff)
From: jgunthorpe@obsidianresearch.com (Jason Gunthorpe) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 22/27] arm: mvebu: add PCIe Device Tree informations for Armada XP Date: Wed, 6 Feb 2013 18:05:02 -0700 [thread overview] Message-ID: <20130207010502.GA7435@obsidianresearch.com> (raw) In-Reply-To: <201302062241.14444.arnd@arndb.de> On Wed, Feb 06, 2013 at 10:41:14PM +0000, Arnd Bergmann wrote: > This would mean that rather than putting the mapped physical address > (0xc0000000, 0xc1000000, ...) in here, you would actually have 64-bit > address as the destination as well, in whatever format the > address map hardware uses, I assume using a numbered 32 bit > address space for each object that can be remapped. Do you mean like: mbus_matrix { /* At this level addresses are <32 bit MBUS target ID> <32 bit target address offset> target_id is an internal MBUS specification */ #address-cells = <2>; #size-cells = <1>; pex0 { ranges = < // CPU window bridged to PCI MMIO 0x82000000 0x00000000 0x00000000 0x<target_id> 0x0 0x0 0x8000000 // CPU IO window bridged to PCI IO 0x81000000 0x00000000 0x00000000 0x<target_id> 0x0 0x0 0xa0000 ...>; } nand { reg = <0x<target_id> 0 0x200>; }; internal_regs { ranges = <0 0x<target_id> 0 0x10000>; timer { reg = <0x20300 0x20>; }; }; } ? I think the big issue would go back to how to pool all the link decoders together in a way that fits OF and Linux's PCI core will understand? How does of_translate_address work in a world like this? > This would also let you do the PCI memory address assignment for > each port separately, starting at bus address 0, followed by > finding a location in the CPU address space and passing > the start as the sys->mem_offset argument to > pci_add_resource_offset. That goes back to the original problem - the goal is to have only one pci_sys_data, not one for every link. The host driver would have to request a large region of physical address space and still dole it out on a link by link basis. Not sure how to model that in DT?? In any event, changing how all the dynamic windows are configured in DT is a big job (there was another thread about this) it seems orthogonal to the PCI host driver.. > > + pcie at 0,0 { > > + device_type = "pciex"; > > + reg = <0x0800 0 0xd0040000 0 0x2000>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + marvell,pcie-port = <0>; > > + marvell,pcie-lane = <0>; > > + interrupts = <1>; > > + clocks = <&gateclk 5>; > > + status = "disabled"; > > + }; > > I think you are missing a "ranges" property here, at least an empty > one, which is required by the standard but not currently enforced > in the code. Maybe.. according to the standard the ranges in this stanza should reflect the bridge configuration, but that isn't known when the DT is written. An empty ranges means identity and that isn't really right either. Also, what should 'reg' be so that the PCI core binds the OF nodes properly? The standard says reg should have the configuration space address of the bridge, and I noticed Thierry was using something that almost looked like a config space address in his driver.. But that seems overly tricky.. When using the link stanzas, shouldn't this scheme be more like this: // The PCI-E host bridge pex at 0 { device_type = "pciex"; // <<-- Important!! ranges = < // Driver internal control registers in MMIO space 0x82000000 0x10000000 0xd0040000 0xd0040000 0x0 0x8000000 // CPU 0xe0000000 -> e8000000 bridged to PCI MMIO 0x82000000 0x00000000 0xe0000000 0xe0000000 0x0 0x8000000 // CPU IO bus 0x0000000 -> 0xa0000 bridged to PCI IO 0x81000000 0x00000000 0x00000000 0x00000000 0x0 0xa0000 // CPU 0xe8000000 -> f0000000 bridged to PCI MMIO, prefetchable 0xC2000000 0x00000000 0xe8000000 0xe8000000 0x0 0x8000000 >; //... // PCI-PCI bridge to Physical link 0 pcie at 0,0 { device_type = "pciex"; // The configuration space address of the PCI-PCI bridge required by OF reg = <0x80 0 0 0 0>; // Bus 0, Dev 0x10, Fn 0 /* The 'bar' on the PCI-PCI bridge, maps to internal control registers, required by the driver. */ assigned-addresses = <0x82000000 0x10000000 0xd0040000 0 0x2000>; // .. } } Thierry, what do you think? I struggled with this particular area of the OF system recently and Grant Likely was very helpful - the above is based on that discussion.. ====== Thomas, here is one possible alternate idea, not sure on the merit, just including it because it is close to what I've got in my DT right now..: // The entire multi-lane controller and PCI root bus pex at 0 { device_type = "pciex"; /* This section configures the Linux PCI host driver. Each line is a physical PCI-Link. (Erorrs included :) */ compatible = "marvell,armada-370-xp-pcie"; regs = <0xd0040000 0x00002000 // port 0.0 0xd0042000 0x00002000 // port 2.0 0xd0044000 0x00002000 // port 0.1 0xd0048000 0x00002000 // port 0.2 0xd004C000 0x00002000>; // port 0.3 io-cpu-window = <0xc0000000 0xa0000>; interrupts = <58 59 60 61 99>; clocks = <&gateclk 5 &gateclk 6 &gateclk 7 &gateclk 8 &gateclk 26> marvell,port-lane <0 0 0 1 0 2 0 3 2 0>; /* Below here configures the aggregate PCI bus the PEX0 stanza describes */ #address-cells = <3>; #size-cells = <2>; // CPU resources allocated to this PCI host bridge bus-range = <0x00 0xff>; ranges = < // CPU 0xe0000000 -> e8000000 bridged to PCI MMIO 0x82000000 0x00000000 0xe0000000 0xe0000000 0x0 0x8000000 // CPU IO bus 0x0000000 -> 0xa0000 bridged to PCI IO 0x81000000 0x00000000 0x00000000 0x00000000 0x0 0xa0000 // CPU 0xe8000000 -> f0000000 bridged to PCI MMIO, prefetchable 0xC2000000 0x00000000 0xe8000000 0xe8000000 0x0 0x8000000 >; /* Any PCI devices associated with this bus go here, relative to the above ranges. As example: */ link at 0 { device_type = "pciex"; // Root port at bus 0, device 0x10, function 0 reg = <0x00000080 0 0 0 0>; ep { device_type = "pciex"; // End port on bus 1, device 0, function 0 reg = <0x00000100 0 0 0 0>; } } } Thoughts: - 'regs' in the main stanza, keep to CPU addresses instead of confusing translated fake ranges address - each regs line is matches to an interrupt, clock and port-lane line to describe a link. The above describes 5 links. - The CPU physical address window to use for the IO space is set via io-cpu-window, not much choice here, the PCI format ranges must be 0 based. - It is not necessary to have per-root port stanzas at all with the above. - There is only one PCI bus stanza, the top level. Jason
next prev parent reply other threads:[~2013-02-07 1:05 UTC|newest] Thread overview: 433+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-01-28 18:56 [PATCH v2] PCIe support for the Armada 370 and Armada XP SoCs Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 01/27] of/pci: Provide support for parsing PCI DT ranges property Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 02/27] of/pci: Add of_pci_get_devfn() function Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 22:00 ` Stephen Warren 2013-01-28 22:00 ` Stephen Warren 2013-01-28 22:16 ` Thierry Reding 2013-01-28 22:16 ` Thierry Reding 2013-01-29 10:04 ` Thomas Petazzoni 2013-01-29 10:04 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 03/27] of/pci: Add of_pci_parse_bus_range() function Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 04/27] ARM: pci: Allow passing per-controller private data Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 05/27] arm: pci: add a align_resource hook Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-29 15:12 ` Thomas Petazzoni 2013-01-29 15:12 ` Thomas Petazzoni 2013-01-29 15:15 ` Russell King - ARM Linux 2013-01-29 15:15 ` Russell King - ARM Linux 2013-01-29 15:23 ` Thomas Petazzoni 2013-01-29 15:23 ` Thomas Petazzoni 2013-01-29 15:25 ` Russell King - ARM Linux 2013-01-29 15:25 ` Russell King - ARM Linux 2013-01-29 15:28 ` Thomas Petazzoni 2013-01-29 15:28 ` Thomas Petazzoni 2013-01-29 15:58 ` Russell King - ARM Linux 2013-01-29 15:58 ` Russell King - ARM Linux 2013-01-29 16:20 ` Thomas Petazzoni 2013-01-29 16:20 ` Thomas Petazzoni 2013-01-29 16:45 ` Arnd Bergmann 2013-01-29 16:45 ` Arnd Bergmann 2013-01-29 17:09 ` Thomas Petazzoni 2013-01-29 17:09 ` Thomas Petazzoni 2013-01-29 20:15 ` Arnd Bergmann 2013-01-29 20:15 ` Arnd Bergmann 2013-01-29 20:33 ` Thomas Petazzoni 2013-01-29 20:33 ` Thomas Petazzoni 2013-01-29 21:59 ` Thomas Petazzoni 2013-01-29 21:59 ` Thomas Petazzoni 2013-01-29 22:17 ` Stephen Warren 2013-01-29 22:17 ` Stephen Warren 2013-01-30 4:49 ` Jason Gunthorpe 2013-01-30 4:49 ` Jason Gunthorpe 2013-01-29 22:54 ` Arnd Bergmann 2013-01-29 22:54 ` Arnd Bergmann 2013-01-30 4:21 ` Jason Gunthorpe 2013-01-30 4:21 ` Jason Gunthorpe 2013-01-30 9:55 ` Arnd Bergmann 2013-01-30 9:55 ` Arnd Bergmann 2013-01-30 11:47 ` Thomas Petazzoni 2013-01-30 11:47 ` Thomas Petazzoni 2013-01-30 16:17 ` Arnd Bergmann 2013-01-30 16:17 ` Arnd Bergmann 2013-01-30 16:38 ` Thomas Petazzoni 2013-01-30 16:38 ` Thomas Petazzoni 2013-01-30 20:48 ` Bjorn Helgaas 2013-01-30 20:48 ` Bjorn Helgaas 2013-01-30 21:06 ` Jason Gunthorpe 2013-01-30 21:06 ` Jason Gunthorpe 2013-01-30 4:56 ` Jason Gunthorpe 2013-01-30 4:56 ` Jason Gunthorpe 2013-01-30 8:19 ` Thomas Petazzoni 2013-01-30 8:19 ` Thomas Petazzoni 2013-01-30 9:46 ` Arnd Bergmann 2013-01-30 9:46 ` Arnd Bergmann 2013-01-30 9:54 ` Thomas Petazzoni 2013-01-30 9:54 ` Thomas Petazzoni 2013-01-30 10:03 ` Arnd Bergmann 2013-01-30 10:03 ` Arnd Bergmann 2013-01-30 11:42 ` Thomas Petazzoni 2013-01-30 11:42 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 06/27] lib: devres: don't enclose pcim_*() functions in CONFIG_HAS_IOPORT Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 07/27] PCI: Add software-emulated host bridge Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 20:18 ` Arnd Bergmann 2013-01-28 20:18 ` Arnd Bergmann 2013-01-28 22:03 ` Stephen Warren 2013-01-28 22:03 ` Stephen Warren 2013-01-28 22:09 ` Jason Gunthorpe 2013-01-28 22:09 ` Jason Gunthorpe 2013-01-28 22:18 ` Thomas Petazzoni 2013-01-28 22:18 ` Thomas Petazzoni 2013-01-28 22:23 ` Jason Gunthorpe 2013-01-28 22:23 ` Jason Gunthorpe 2013-01-28 22:30 ` Thomas Petazzoni 2013-01-28 22:30 ` Thomas Petazzoni 2013-01-28 22:51 ` Jason Gunthorpe 2013-01-28 22:51 ` Jason Gunthorpe 2013-01-29 10:01 ` Thomas Petazzoni 2013-01-29 10:01 ` Thomas Petazzoni 2013-01-29 17:42 ` Jason Gunthorpe 2013-01-29 17:42 ` Jason Gunthorpe 2013-01-29 17:43 ` Thomas Petazzoni 2013-01-29 17:43 ` Thomas Petazzoni 2013-01-29 2:40 ` Bjorn Helgaas 2013-01-29 2:40 ` Bjorn Helgaas 2013-01-29 6:16 ` Jason Gunthorpe 2013-01-29 6:16 ` Jason Gunthorpe 2013-01-28 22:09 ` Thomas Petazzoni 2013-01-28 22:09 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 08/27] pci: implement an emulated PCI-to-PCI bridge Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 19:35 ` Jason Gunthorpe 2013-01-28 19:35 ` Jason Gunthorpe 2013-01-28 19:39 ` Thomas Petazzoni 2013-01-28 19:39 ` Thomas Petazzoni 2013-01-28 19:55 ` Jason Gunthorpe 2013-01-28 19:55 ` Jason Gunthorpe 2013-01-28 22:06 ` Stephen Warren 2013-01-28 22:06 ` Stephen Warren 2013-01-28 22:16 ` Jason Gunthorpe 2013-01-28 22:16 ` Jason Gunthorpe 2013-01-29 22:35 ` Bjorn Helgaas 2013-01-29 22:35 ` Bjorn Helgaas 2013-01-29 23:06 ` Arnd Bergmann 2013-01-29 23:06 ` Arnd Bergmann 2013-01-30 4:12 ` Jason Gunthorpe 2013-01-30 4:12 ` Jason Gunthorpe 2013-01-28 18:56 ` [PATCH v2 09/27] pci: infrastructure to add drivers in drivers/pci/host Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 10/27] arm: mvebu: fix address-cells in mpic DT node Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 11/27] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 22:08 ` Stephen Warren 2013-01-28 22:08 ` Stephen Warren 2013-01-28 22:21 ` Thomas Petazzoni 2013-01-28 22:21 ` Thomas Petazzoni 2013-01-28 22:27 ` Stephen Warren 2013-01-28 22:27 ` Stephen Warren 2013-01-28 22:44 ` Thomas Petazzoni 2013-01-28 22:44 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 12/27] clk: mvebu: add more PCIe clocks for Armada XP Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 13/27] arm: plat-orion: introduce WIN_CTRL_ENABLE in address mapping code Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 14/27] arm: plat-orion: refactor the orion_disable_wins() function Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 15/27] arm: plat-orion: introduce orion_{alloc,free}_cpu_win() functions Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 15/27] arm: plat-orion: introduce orion_{alloc, free}_cpu_win() functions Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 16/27] arm: mvebu: add functions to alloc/free PCIe decoding windows Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 17/27] arm: plat-orion: make common PCIe code usable on mvebu Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 18/27] arm: plat-orion: add more flexible PCI configuration space read/write functions Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 19:51 ` Jason Gunthorpe 2013-01-28 19:51 ` Jason Gunthorpe 2013-01-29 8:40 ` Thomas Petazzoni 2013-01-29 8:40 ` Thomas Petazzoni 2013-01-29 17:40 ` Jason Gunthorpe 2013-01-29 17:40 ` Jason Gunthorpe 2013-01-28 18:56 ` [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 22:21 ` Stephen Warren 2013-01-28 22:21 ` Stephen Warren 2013-01-29 8:41 ` Thomas Petazzoni 2013-01-29 8:41 ` Thomas Petazzoni 2013-01-29 9:20 ` Thierry Reding 2013-01-29 9:20 ` Thierry Reding 2013-01-29 9:21 ` Thomas Petazzoni 2013-01-29 9:21 ` Thomas Petazzoni 2013-02-07 10:24 ` Thomas Petazzoni 2013-02-07 10:24 ` Thomas Petazzoni 2013-02-07 15:46 ` Bjorn Helgaas 2013-02-07 15:46 ` Bjorn Helgaas 2013-02-07 16:00 ` Thomas Petazzoni 2013-02-07 16:00 ` Thomas Petazzoni 2013-02-07 18:08 ` Bjorn Helgaas 2013-02-07 18:08 ` Bjorn Helgaas 2013-02-07 18:15 ` Jason Gunthorpe 2013-02-07 18:15 ` Jason Gunthorpe 2013-02-07 18:30 ` Bjorn Helgaas 2013-02-07 18:30 ` Bjorn Helgaas 2013-02-07 18:43 ` Thierry Reding 2013-02-07 18:43 ` Thierry Reding 2013-01-29 19:47 ` Stephen Warren 2013-01-29 19:47 ` Stephen Warren 2013-01-29 3:29 ` Bjorn Helgaas 2013-01-29 3:29 ` Bjorn Helgaas 2013-01-29 5:55 ` Jason Gunthorpe 2013-01-29 5:55 ` Jason Gunthorpe 2013-01-29 8:00 ` Thomas Petazzoni 2013-01-29 8:00 ` Thomas Petazzoni 2013-01-29 17:47 ` Bjorn Helgaas 2013-01-29 17:47 ` Bjorn Helgaas 2013-01-29 18:14 ` Thomas Petazzoni 2013-01-29 18:14 ` Thomas Petazzoni 2013-01-29 18:41 ` Jason Gunthorpe 2013-01-29 18:41 ` Jason Gunthorpe 2013-01-29 19:07 ` Bjorn Helgaas 2013-01-29 19:07 ` Bjorn Helgaas 2013-01-29 19:18 ` Jason Gunthorpe 2013-01-29 19:18 ` Jason Gunthorpe 2013-01-29 19:38 ` Bjorn Helgaas 2013-01-29 19:38 ` Bjorn Helgaas 2013-01-29 22:27 ` Bjorn Helgaas 2013-01-29 22:27 ` Bjorn Helgaas 2013-01-30 4:24 ` Jason Gunthorpe 2013-01-30 4:24 ` Jason Gunthorpe 2013-01-30 9:35 ` Thomas Petazzoni 2013-01-30 9:35 ` Thomas Petazzoni 2013-01-30 18:52 ` Bjorn Helgaas 2013-01-30 18:52 ` Bjorn Helgaas 2013-01-30 22:28 ` Thomas Petazzoni 2013-01-30 22:28 ` Thomas Petazzoni 2013-01-30 23:10 ` Jason Gunthorpe 2013-01-30 23:10 ` Jason Gunthorpe 2013-01-30 23:48 ` Bjorn Helgaas 2013-01-30 23:48 ` Bjorn Helgaas 2013-01-31 16:04 ` Thomas Petazzoni 2013-01-31 16:04 ` Thomas Petazzoni 2013-01-31 16:30 ` Bjorn Helgaas 2013-01-31 16:30 ` Bjorn Helgaas 2013-01-31 16:33 ` Thomas Petazzoni 2013-01-31 16:33 ` Thomas Petazzoni 2013-01-31 17:03 ` Bjorn Helgaas 2013-01-31 17:03 ` Bjorn Helgaas 2013-01-31 16:42 ` Russell King - ARM Linux 2013-01-31 16:42 ` Russell King - ARM Linux 2013-01-29 13:22 ` Andrew Murray 2013-01-29 13:22 ` Andrew Murray 2013-01-29 13:45 ` Thomas Petazzoni 2013-01-29 13:45 ` Thomas Petazzoni 2013-01-29 14:05 ` Andrew Murray 2013-01-29 14:05 ` Andrew Murray 2013-01-29 14:20 ` Thierry Reding 2013-01-29 14:20 ` Thierry Reding 2013-01-29 14:29 ` Thomas Petazzoni 2013-01-29 14:29 ` Thomas Petazzoni 2013-01-29 15:02 ` Thierry Reding 2013-01-29 15:02 ` Thierry Reding 2013-01-29 15:08 ` Andrew Murray 2013-01-29 15:08 ` Andrew Murray 2013-01-29 15:10 ` Thomas Petazzoni 2013-01-29 15:10 ` Thomas Petazzoni 2013-02-07 14:37 ` Thomas Petazzoni 2013-02-07 14:37 ` Thomas Petazzoni 2013-02-07 15:51 ` Andrew Murray 2013-02-07 15:51 ` Andrew Murray 2013-02-07 16:19 ` Thomas Petazzoni 2013-02-07 16:19 ` Thomas Petazzoni 2013-02-07 16:40 ` Thomas Petazzoni 2013-02-07 16:40 ` Thomas Petazzoni 2013-02-07 16:53 ` Andrew Murray 2013-02-07 16:53 ` Andrew Murray 2013-02-07 17:14 ` Thomas Petazzoni 2013-02-07 17:14 ` Thomas Petazzoni 2013-02-07 17:29 ` Andrew Murray 2013-02-07 17:29 ` Andrew Murray 2013-02-07 17:37 ` Thomas Petazzoni 2013-02-07 17:37 ` Thomas Petazzoni 2013-02-07 18:21 ` Jason Gunthorpe 2013-02-07 18:21 ` Jason Gunthorpe 2013-02-07 23:25 ` Arnd Bergmann 2013-02-07 23:25 ` Arnd Bergmann 2013-02-08 0:44 ` Jason Gunthorpe 2013-02-08 0:44 ` Jason Gunthorpe 2013-02-09 22:23 ` Arnd Bergmann 2013-02-09 22:23 ` Arnd Bergmann 2013-02-12 19:26 ` Jason Gunthorpe 2013-02-12 19:26 ` Jason Gunthorpe 2013-02-07 18:30 ` Andrew Murray 2013-02-07 18:30 ` Andrew Murray 2013-02-07 23:27 ` Arnd Bergmann 2013-02-07 23:27 ` Arnd Bergmann 2013-01-30 11:32 ` Russell King - ARM Linux 2013-01-30 11:32 ` Russell King - ARM Linux 2013-01-30 11:37 ` Thomas Petazzoni 2013-01-30 11:37 ` Thomas Petazzoni 2013-01-30 12:03 ` Thierry Reding 2013-01-30 12:03 ` Thierry Reding 2013-01-30 13:07 ` Thomas Petazzoni 2013-01-30 13:07 ` Thomas Petazzoni 2013-01-30 15:08 ` Russell King - ARM Linux 2013-01-30 15:08 ` Russell King - ARM Linux 2013-01-30 15:19 ` Russell King - ARM Linux 2013-01-30 15:19 ` Russell King - ARM Linux 2013-01-30 15:36 ` Thomas Petazzoni 2013-01-30 15:36 ` Thomas Petazzoni 2013-01-30 15:46 ` Russell King - ARM Linux 2013-01-30 15:46 ` Russell King - ARM Linux 2013-01-31 14:30 ` Thomas Petazzoni 2013-01-31 14:30 ` Thomas Petazzoni 2013-01-31 14:50 ` Russell King - ARM Linux 2013-01-31 14:50 ` Russell King - ARM Linux 2013-01-31 14:57 ` Thomas Petazzoni 2013-01-31 14:57 ` Thomas Petazzoni 2013-01-31 15:08 ` Russell King - ARM Linux 2013-01-31 15:08 ` Russell King - ARM Linux 2013-01-31 15:22 ` Thomas Petazzoni 2013-01-31 15:22 ` Thomas Petazzoni 2013-01-31 15:36 ` Russell King - ARM Linux 2013-01-31 15:36 ` Russell King - ARM Linux 2013-01-31 15:47 ` Thomas Petazzoni 2013-01-31 15:47 ` Thomas Petazzoni 2013-01-31 15:48 ` Russell King - ARM Linux 2013-01-31 15:48 ` Russell King - ARM Linux 2013-01-31 16:18 ` Arnd Bergmann 2013-01-31 16:18 ` Arnd Bergmann 2013-01-31 18:02 ` Jason Gunthorpe 2013-01-31 18:02 ` Jason Gunthorpe 2013-01-31 20:46 ` Arnd Bergmann 2013-01-31 20:46 ` Arnd Bergmann 2013-01-31 22:44 ` Jason Gunthorpe 2013-01-31 22:44 ` Jason Gunthorpe 2013-02-01 11:30 ` Arnd Bergmann 2013-02-01 11:30 ` Arnd Bergmann 2013-02-01 19:52 ` Jason Gunthorpe 2013-02-01 19:52 ` Jason Gunthorpe 2013-02-06 16:51 ` Thomas Petazzoni 2013-02-06 16:51 ` Thomas Petazzoni 2013-02-06 17:09 ` Jason Gunthorpe 2013-02-06 17:09 ` Jason Gunthorpe 2013-02-06 17:18 ` Thomas Petazzoni 2013-02-06 17:18 ` Thomas Petazzoni 2013-02-06 17:50 ` Jason Gunthorpe 2013-02-06 17:50 ` Jason Gunthorpe 2013-02-06 18:02 ` Thomas Petazzoni 2013-02-06 18:02 ` Thomas Petazzoni 2013-02-06 18:22 ` Stephen Warren 2013-02-06 18:22 ` Stephen Warren 2013-02-06 18:39 ` Jason Gunthorpe 2013-02-06 18:39 ` Jason Gunthorpe 2013-02-06 18:42 ` Thomas Petazzoni 2013-02-06 18:42 ` Thomas Petazzoni 2013-02-06 22:04 ` Arnd Bergmann 2013-02-06 22:04 ` Arnd Bergmann 2013-02-07 15:50 ` Giving special alignment/size constraints to the Linux PCI core? Thomas Petazzoni 2013-02-07 23:33 ` Arnd Bergmann 2013-02-07 23:33 ` Arnd Bergmann 2013-02-08 4:21 ` Bjorn Helgaas 2013-02-08 4:21 ` Bjorn Helgaas 2013-02-08 8:14 ` Thomas Petazzoni 2013-02-08 8:14 ` Thomas Petazzoni 2013-02-12 16:00 ` Arnd Bergmann 2013-02-12 16:00 ` Arnd Bergmann 2013-02-12 18:41 ` Jason Gunthorpe 2013-02-12 18:41 ` Jason Gunthorpe 2013-02-12 19:02 ` Arnd Bergmann 2013-02-12 19:02 ` Arnd Bergmann 2013-02-12 19:38 ` Jason Gunthorpe 2013-02-12 19:38 ` Jason Gunthorpe 2013-02-12 23:05 ` Arnd Bergmann 2013-02-12 23:05 ` Arnd Bergmann 2013-02-13 0:32 ` Jason Gunthorpe 2013-02-13 0:32 ` Jason Gunthorpe 2013-02-13 18:53 ` Arnd Bergmann 2013-02-13 18:53 ` Arnd Bergmann 2013-02-13 19:12 ` Jason Gunthorpe 2013-02-13 19:12 ` Jason Gunthorpe 2013-02-13 19:51 ` Thomas Petazzoni 2013-02-13 19:51 ` Thomas Petazzoni 2013-02-13 21:10 ` Arnd Bergmann 2013-02-13 21:10 ` Arnd Bergmann 2013-02-13 21:20 ` Yinghai Lu 2013-02-13 21:20 ` Yinghai Lu 2013-02-13 22:24 ` Arnd Bergmann 2013-02-13 22:24 ` Arnd Bergmann 2013-02-13 21:02 ` Yinghai Lu 2013-02-13 21:02 ` Yinghai Lu 2013-01-31 7:10 ` [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems Thierry Reding 2013-01-31 7:10 ` Thierry Reding 2013-02-01 0:34 ` Stephen Warren 2013-02-01 0:34 ` Stephen Warren 2013-02-01 1:41 ` Jason Gunthorpe 2013-02-01 1:41 ` Jason Gunthorpe 2013-02-01 2:21 ` Stephen Warren 2013-02-01 2:21 ` Stephen Warren 2013-02-01 3:51 ` Jason Gunthorpe 2013-02-01 3:51 ` Jason Gunthorpe 2013-02-01 9:03 ` Thomas Petazzoni 2013-02-01 9:03 ` Thomas Petazzoni 2013-02-01 16:07 ` Arnd Bergmann 2013-02-01 16:07 ` Arnd Bergmann 2013-02-01 16:26 ` Russell King - ARM Linux 2013-02-01 16:26 ` Russell King - ARM Linux 2013-02-01 17:45 ` Arnd Bergmann 2013-02-01 17:45 ` Arnd Bergmann 2013-02-01 19:58 ` Jason Gunthorpe 2013-02-01 19:58 ` Jason Gunthorpe 2013-02-01 8:46 ` Thomas Petazzoni 2013-02-01 8:46 ` Thomas Petazzoni 2013-02-01 16:02 ` Arnd Bergmann 2013-02-01 16:02 ` Arnd Bergmann 2013-02-01 17:57 ` Stephen Warren 2013-02-01 17:57 ` Stephen Warren 2013-02-01 19:39 ` Jason Gunthorpe 2013-02-01 19:39 ` Jason Gunthorpe 2013-02-01 20:30 ` Stephen Warren 2013-02-01 20:30 ` Stephen Warren 2013-01-28 18:56 ` [PATCH v2 20/27] arm: mvebu: PCIe support is now available on mvebu Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 21/27] arm: mvebu: add PCIe Device Tree informations for Armada 370 Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 22/27] arm: mvebu: add PCIe Device Tree informations for Armada XP Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-02-06 22:41 ` Arnd Bergmann 2013-02-06 22:41 ` Arnd Bergmann 2013-02-06 23:07 ` Thomas Petazzoni 2013-02-06 23:07 ` Thomas Petazzoni 2013-02-07 8:04 ` Arnd Bergmann 2013-02-07 8:04 ` Arnd Bergmann 2013-02-07 8:45 ` Thomas Petazzoni 2013-02-07 8:45 ` Thomas Petazzoni 2013-02-07 9:09 ` Arnd Bergmann 2013-02-07 9:09 ` Arnd Bergmann 2013-02-07 1:05 ` Jason Gunthorpe [this message] 2013-02-07 1:05 ` Jason Gunthorpe 2013-02-07 7:28 ` Thierry Reding 2013-02-07 7:28 ` Thierry Reding 2013-02-07 17:49 ` Jason Gunthorpe 2013-02-07 17:49 ` Jason Gunthorpe 2013-02-07 8:24 ` Arnd Bergmann 2013-02-07 8:24 ` Arnd Bergmann 2013-02-07 17:00 ` Jason Gunthorpe 2013-02-07 17:00 ` Jason Gunthorpe 2013-02-07 23:44 ` Arnd Bergmann 2013-02-07 23:44 ` Arnd Bergmann 2013-01-28 18:56 ` [PATCH v2 23/27] arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 24/27] arm: mvebu: PCIe Device Tree informations for Armada XP DB Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 25/27] arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 26/27] arm: mvebu: PCIe Device Tree informations for Armada 370 DB Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni 2013-01-28 18:56 ` [PATCH v2 27/27] arm: mvebu: update defconfig with PCI and USB support Thomas Petazzoni 2013-01-28 18:56 ` Thomas Petazzoni
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