[v2 0/4] ARM: tegra: convert device tree files to use CLK defines

[v2 0/4] ARM: tegra: convert device tree files to use CLK defines

[Hiroshi Doyu]

Hi,

With new dtc+cpp feature, we can get rid of magic numbers in dts*
files. To get rid of Tegra clock magic number, the following patches
were created with a script run as below. This can be applied for
Tegra114 clock as well.

for x in 20 30; do
    cat drivers/clk/tegra/clk-tegra$x.c | enum2define.py \
    	> arch/arm/boot/dts/tegra$x-car.h 2>/tmp/tegra$x-car.sed
    sed -i -f /tmp/tegra$x-car.sed \
    	Documentation/devicetree/bindings/clock/nvidia\,tegra$x-car.txt \
	arch/arm/boot/dts/*
done

We plan to share those DT header files with kernel source later[1].

This series depends on:

  [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
  http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149613.html

v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149672.html

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149804.html

Hiroshi Doyu (4):
  ARM: tegra20: create a DT header defining CLK IDs
  ARM: tegra20: convert device tree files to use CLK defines
  ARM: tegra30: create a DT header defining CLK IDs
  ARM: tegra30: convert device tree files to use CLK defines

 .../bindings/clock/nvidia,tegra20-car.txt          |    2 +-
 .../bindings/clock/nvidia,tegra30-car.txt          |    2 +-
 arch/arm/boot/dts/tegra20-car.h                    |  114 +++++++++++++
 arch/arm/boot/dts/tegra20-paz00.dtsp               |    2 +-
 arch/arm/boot/dts/tegra20.dtsip                    |   85 +++++-----
 arch/arm/boot/dts/tegra30-car.h                    |  171 ++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsip                    |   87 +++++-----
 7 files changed, 375 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/tegra20-car.h
 create mode 100644 arch/arm/boot/dts/tegra30-car.h

--
1.7.9.5

[v2 0/4] ARM: tegra: convert device tree files to use CLK defines

[Hiroshi Doyu]

Hi,

With new dtc+cpp feature, we can get rid of magic numbers in dts*
files. To get rid of Tegra clock magic number, the following patches
were created with a script run as below. This can be applied for
Tegra114 clock as well.

for x in 20 30; do
    cat drivers/clk/tegra/clk-tegra$x.c | enum2define.py \
    	> arch/arm/boot/dts/tegra$x-car.h 2>/tmp/tegra$x-car.sed
    sed -i -f /tmp/tegra$x-car.sed \
    	Documentation/devicetree/bindings/clock/nvidia\,tegra$x-car.txt \
	arch/arm/boot/dts/*
done

We plan to share those DT header files with kernel source later[1].

This series depends on:

  [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
  http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149613.html

v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149672.html

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149804.html

Hiroshi Doyu (4):
  ARM: tegra20: create a DT header defining CLK IDs
  ARM: tegra20: convert device tree files to use CLK defines
  ARM: tegra30: create a DT header defining CLK IDs
  ARM: tegra30: convert device tree files to use CLK defines

 .../bindings/clock/nvidia,tegra20-car.txt          |    2 +-
 .../bindings/clock/nvidia,tegra30-car.txt          |    2 +-
 arch/arm/boot/dts/tegra20-car.h                    |  114 +++++++++++++
 arch/arm/boot/dts/tegra20-paz00.dtsp               |    2 +-
 arch/arm/boot/dts/tegra20.dtsip                    |   85 +++++-----
 arch/arm/boot/dts/tegra30-car.h                    |  171 ++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsip                    |   87 +++++-----
 7 files changed, 375 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/tegra20-car.h
 create mode 100644 arch/arm/boot/dts/tegra30-car.h

--
1.7.9.5

[v2 0/4] ARM: tegra: convert device tree files to use CLK defines

[Hiroshi Doyu]

Hi,

With new dtc+cpp feature, we can get rid of magic numbers in dts*
files. To get rid of Tegra clock magic number, the following patches
were created with a script run as below. This can be applied for
Tegra114 clock as well.

for x in 20 30; do
    cat drivers/clk/tegra/clk-tegra$x.c | enum2define.py \
    	> arch/arm/boot/dts/tegra$x-car.h 2>/tmp/tegra$x-car.sed
    sed -i -f /tmp/tegra$x-car.sed \
    	Documentation/devicetree/bindings/clock/nvidia\,tegra$x-car.txt \
	arch/arm/boot/dts/*
done

We plan to share those DT header files with kernel source later[1].

This series depends on:

  [PATCH 0/9] ARM: tegra: use new dtc+cpp feature
  http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149613.html

v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149672.html

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/149804.html

Hiroshi Doyu (4):
  ARM: tegra20: create a DT header defining CLK IDs
  ARM: tegra20: convert device tree files to use CLK defines
  ARM: tegra30: create a DT header defining CLK IDs
  ARM: tegra30: convert device tree files to use CLK defines

 .../bindings/clock/nvidia,tegra20-car.txt          |    2 +-
 .../bindings/clock/nvidia,tegra30-car.txt          |    2 +-
 arch/arm/boot/dts/tegra20-car.h                    |  114 +++++++++++++
 arch/arm/boot/dts/tegra20-paz00.dtsp               |    2 +-
 arch/arm/boot/dts/tegra20.dtsip                    |   85 +++++-----
 arch/arm/boot/dts/tegra30-car.h                    |  171 ++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsip                    |   87 +++++-----
 7 files changed, 375 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/tegra20-car.h
 create mode 100644 arch/arm/boot/dts/tegra30-car.h

--
1.7.9.5

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Hiroshi Doyu]

To replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra20-car.h |  114 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-car.h

diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
new file mode 100644
index 0000000..0659414
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-car.h
@@ -0,0 +1,114 @@
+#define CLK_CPU 0
+#define CLK_AC97 3
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_TWC 16
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_IDE 25
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+#define CLK_CACHE2 31
+#define CLK_MEM 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+#define CLK_KBC 36
+#define CLK_STAT_MON 37
+#define CLK_PMC 38
+#define CLK_FUSE 39
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SPI 43
+#define CLK_SBC2 44
+#define CLK_XIO 45
+#define CLK_SBC3 46
+#define CLK_DVC 47
+#define CLK_DSI 48
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PEX 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIE_XCLK 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 89
+#define CLK_CLK_D 90
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+#define CLK_UARTB 96
+#define CLK_VFIR 97
+#define CLK_SPDIF_IN 98
+#define CLK_SPDIF_OUT 99
+#define CLK_VI 100
+#define CLK_VI_SENSOR 101
+#define CLK_TVO 102
+#define CLK_CVE 103
+#define CLK_OSC 104
+#define CLK_CLK_32K 105
+#define CLK_CLK_M 106
+#define CLK_SCLK 107
+#define CLK_CCLK 108
+#define CLK_HCLK 109
+#define CLK_PCLK 110
+#define CLK_BLINK 111
+#define CLK_PLL_A 112
+#define CLK_PLL_A_OUT0 113
+#define CLK_PLL_C 114
+#define CLK_PLL_C_OUT1 115
+#define CLK_PLL_D 116
+#define CLK_PLL_D_OUT0 117
+#define CLK_PLL_E 118
+#define CLK_PLL_M 119
+#define CLK_PLL_M_OUT1 120
+#define CLK_PLL_P 121
+#define CLK_PLL_P_OUT1 122
+#define CLK_PLL_P_OUT2 123
+#define CLK_PLL_P_OUT3 124
+#define CLK_PLL_P_OUT4 125
+#define CLK_PLL_U 126
+#define CLK_PLL_X 127
+#define CLK_AUDIO 128
+#define CLK_PLL_REF 129
+#define CLK_TWD 130
+#define CLK_CLK_MAX 131
-- 
1.7.9.5

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Hiroshi Doyu]

To replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra20-car.h |  114 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra20-car.h

diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
new file mode 100644
index 0000000..0659414
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-car.h
@@ -0,0 +1,114 @@
+#define CLK_CPU 0
+#define CLK_AC97 3
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_TWC 16
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_IDE 25
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+#define CLK_CACHE2 31
+#define CLK_MEM 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+#define CLK_KBC 36
+#define CLK_STAT_MON 37
+#define CLK_PMC 38
+#define CLK_FUSE 39
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SPI 43
+#define CLK_SBC2 44
+#define CLK_XIO 45
+#define CLK_SBC3 46
+#define CLK_DVC 47
+#define CLK_DSI 48
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PEX 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIE_XCLK 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 89
+#define CLK_CLK_D 90
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+#define CLK_UARTB 96
+#define CLK_VFIR 97
+#define CLK_SPDIF_IN 98
+#define CLK_SPDIF_OUT 99
+#define CLK_VI 100
+#define CLK_VI_SENSOR 101
+#define CLK_TVO 102
+#define CLK_CVE 103
+#define CLK_OSC 104
+#define CLK_CLK_32K 105
+#define CLK_CLK_M 106
+#define CLK_SCLK 107
+#define CLK_CCLK 108
+#define CLK_HCLK 109
+#define CLK_PCLK 110
+#define CLK_BLINK 111
+#define CLK_PLL_A 112
+#define CLK_PLL_A_OUT0 113
+#define CLK_PLL_C 114
+#define CLK_PLL_C_OUT1 115
+#define CLK_PLL_D 116
+#define CLK_PLL_D_OUT0 117
+#define CLK_PLL_E 118
+#define CLK_PLL_M 119
+#define CLK_PLL_M_OUT1 120
+#define CLK_PLL_P 121
+#define CLK_PLL_P_OUT1 122
+#define CLK_PLL_P_OUT2 123
+#define CLK_PLL_P_OUT3 124
+#define CLK_PLL_P_OUT4 125
+#define CLK_PLL_U 126
+#define CLK_PLL_X 127
+#define CLK_AUDIO 128
+#define CLK_PLL_REF 129
+#define CLK_TWD 130
+#define CLK_CLK_MAX 131
-- 
1.7.9.5

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

> diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h

Sorry, forgot a couple small comments the last time around.

This file should probably have some header indicating which binding it
describes, rather like the GPIO header in my patch series.

> +#define CLK_CPU 0

I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
clock headers don't conflict. It's not too likely that more than one of
the /Tegra/ clock headers will be included at once, but it doesn't seem
that unlikely that a board file could end up having a Tegra clock header
included plus various other clock headers for some other chip that has
some clock outputs.

Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
the list of clocks.

BTW, I assume this patch includes the changes from my recent "clk:
tegra: fix driver to match DT binding" and anything else similar that's
in the most recent Tegra for-next?

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

> diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h

Sorry, forgot a couple small comments the last time around.

This file should probably have some header indicating which binding it
describes, rather like the GPIO header in my patch series.

> +#define CLK_CPU 0

I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
clock headers don't conflict. It's not too likely that more than one of
the /Tegra/ clock headers will be included at once, but it doesn't seem
that unlikely that a board file could end up having a Tegra clock header
included plus various other clock headers for some other chip that has
some clock outputs.

Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
the list of clocks.

BTW, I assume this patch includes the changes from my recent "clk:
tegra: fix driver to match DT binding" and anything else similar that's
in the most recent Tegra for-next?

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
> 
> -               clocks = <&tegra_car 28>;
> +               clocks = <&tegra_car CLK_HOST1X>;

> diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h

Sorry, forgot a couple small comments the last time around.

This file should probably have some header indicating which binding it
describes, rather like the GPIO header in my patch series.

> +#define CLK_CPU 0

I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
clock headers don't conflict. It's not too likely that more than one of
the /Tegra/ clock headers will be included at once, but it doesn't seem
that unlikely that a board file could end up having a Tegra clock header
included plus various other clock headers for some other chip that has
some clock outputs.

Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
the list of clocks.

BTW, I assume this patch includes the changes from my recent "clk:
tegra: fix driver to match DT binding" and anything else similar that's
in the most recent Tegra for-next?

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Hiroshi Doyu]

Stephen Warren <swarren@wwwdotorg.org> wrote @ Thu, 14 Feb 2013 21:15:28 +0100:

> Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
> the list of clocks.

Not yet removed. I think that this could be done with the patch which
allows kernel source to include DT header files.

> BTW, I assume this patch includes the changes from my recent "clk:
> tegra: fix driver to match DT binding" and anything else similar that's
> in the most recent Tegra for-next?

Of course not, that's a little bit too recent.

I'll rerun my script against the laste Tegra for-next and post them as
v3(inc. Tegra114)

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Hiroshi Doyu]

Stephen Warren <swarren@wwwdotorg.org> wrote @ Thu, 14 Feb 2013 21:15:28 +0100:

> Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
> the list of clocks.

Not yet removed. I think that this could be done with the patch which
allows kernel source to include DT header files.

> BTW, I assume this patch includes the changes from my recent "clk:
> tegra: fix driver to match DT binding" and anything else similar that's
> in the most recent Tegra for-next?

Of course not, that's a little bit too recent.

I'll rerun my script against the laste Tegra for-next and post them as
v3(inc. Tegra114)

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Hiroshi Doyu]

Stephen Warren <swarren@wwwdotorg.org> wrote @ Thu, 14 Feb 2013 21:15:28 +0100:

> Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
> the list of clocks.

Not yet removed. I think that this could be done with the patch which
allows kernel source to include DT header files.

> BTW, I assume this patch includes the changes from my recent "clk:
> tegra: fix driver to match DT binding" and anything else similar that's
> in the most recent Tegra for-next?

Of course not, that's a little bit too recent.

I'll rerun my script against the laste Tegra for-next and post them as
v3(inc. Tegra114)

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/14/2013 01:34 PM, Hiroshi Doyu wrote:
> Stephen Warren <swarren@wwwdotorg.org> wrote @ Thu, 14 Feb 2013 21:15:28 +0100:
> 
>> Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
>> the list of clocks.
> 
> Not yet removed. I think that this could be done with the patch which
> allows kernel source to include DT header files.

By defining the header file, you're really causing that header to be
part of the binding definition. I think we should move the code from the
binding .txt file to the header, rather than duplicating it and then
removing it. The kernel doesn't include the binding .txt file right now,
so I don't see any correlation with making it include the header vs.
when we remove the list from the binding document.

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/14/2013 01:34 PM, Hiroshi Doyu wrote:
> Stephen Warren <swarren@wwwdotorg.org> wrote @ Thu, 14 Feb 2013 21:15:28 +0100:
> 
>> Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
>> the list of clocks.
> 
> Not yet removed. I think that this could be done with the patch which
> allows kernel source to include DT header files.

By defining the header file, you're really causing that header to be
part of the binding definition. I think we should move the code from the
binding .txt file to the header, rather than duplicating it and then
removing it. The kernel doesn't include the binding .txt file right now,
so I don't see any correlation with making it include the header vs.
when we remove the list from the binding document.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/14/2013 01:34 PM, Hiroshi Doyu wrote:
> Stephen Warren <swarren@wwwdotorg.org> wrote @ Thu, 14 Feb 2013 21:15:28 +0100:
> 
>> Oh, and I don't think you updated e.g. nvidia,tegra20-car.txt to remove
>> the list of clocks.
> 
> Not yet removed. I think that this could be done with the patch which
> allows kernel source to include DT header files.

By defining the header file, you're really causing that header to be
part of the binding definition. I think we should move the code from the
binding .txt file to the header, rather than duplicating it and then
removing it. The kernel doesn't include the binding .txt file right now,
so I don't see any correlation with making it include the header vs.
when we remove the list from the binding document.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote:
> On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
> > To replace magic number in tegra_car:
> > 
> > -               clocks = <&tegra_car 28>;
> > +               clocks = <&tegra_car CLK_HOST1X>;
> 
> > diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
> 
> Sorry, forgot a couple small comments the last time around.
> 
> This file should probably have some header indicating which binding it
> describes, rather like the GPIO header in my patch series.
> 
> > +#define CLK_CPU 0
> 
> I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
> clock headers don't conflict. It's not too likely that more than one of
> the /Tegra/ clock headers will be included at once, but it doesn't seem
> that unlikely that a board file could end up having a Tegra clock header
> included plus various other clock headers for some other chip that has
> some clock outputs.
> 

I would suggest removing this clock. It's not actually implemented in the CCF
and rather useless. If you would gate the CPU clock from the CPU by writing to
this register, how would you ungate it? :) Note that this would gate the clock
to all CPUs.

Cheers,

Peter.

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote:
> On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
> > To replace magic number in tegra_car:
> > 
> > -               clocks = <&tegra_car 28>;
> > +               clocks = <&tegra_car CLK_HOST1X>;
> 
> > diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
> 
> Sorry, forgot a couple small comments the last time around.
> 
> This file should probably have some header indicating which binding it
> describes, rather like the GPIO header in my patch series.
> 
> > +#define CLK_CPU 0
> 
> I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
> clock headers don't conflict. It's not too likely that more than one of
> the /Tegra/ clock headers will be included at once, but it doesn't seem
> that unlikely that a board file could end up having a Tegra clock header
> included plus various other clock headers for some other chip that has
> some clock outputs.
> 

I would suggest removing this clock. It's not actually implemented in the CCF
and rather useless. If you would gate the CPU clock from the CPU by writing to
this register, how would you ungate it? :) Note that this would gate the clock
to all CPUs.

Cheers,

Peter.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote:
> On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
> > To replace magic number in tegra_car:
> > 
> > -               clocks = <&tegra_car 28>;
> > +               clocks = <&tegra_car CLK_HOST1X>;
> 
> > diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
> 
> Sorry, forgot a couple small comments the last time around.
> 
> This file should probably have some header indicating which binding it
> describes, rather like the GPIO header in my patch series.
> 
> > +#define CLK_CPU 0
> 
> I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
> clock headers don't conflict. It's not too likely that more than one of
> the /Tegra/ clock headers will be included at once, but it doesn't seem
> that unlikely that a board file could end up having a Tegra clock header
> included plus various other clock headers for some other chip that has
> some clock outputs.
> 

I would suggest removing this clock. It's not actually implemented in the CCF
and rather useless. If you would gate the CPU clock from the CPU by writing to
this register, how would you ungate it? :) Note that this would gate the clock
to all CPUs.

Cheers,

Peter.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/15/2013 02:24 AM, Peter De Schrijver wrote:
> On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote:
>> On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
>>> To replace magic number in tegra_car:
>>>
>>> -               clocks = <&tegra_car 28>;
>>> +               clocks = <&tegra_car CLK_HOST1X>;
>>
>>> diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
>>
>> Sorry, forgot a couple small comments the last time around.
>>
>> This file should probably have some header indicating which binding it
>> describes, rather like the GPIO header in my patch series.
>>
>>> +#define CLK_CPU 0
>>
>> I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
>> clock headers don't conflict. It's not too likely that more than one of
>> the /Tegra/ clock headers will be included at once, but it doesn't seem
>> that unlikely that a board file could end up having a Tegra clock header
>> included plus various other clock headers for some other chip that has
>> some clock outputs.
>>
> 
> I would suggest removing this clock. It's not actually implemented in the CCF
> and rather useless. If you would gate the CPU clock from the CPU by writing to
> this register, how would you ungate it? :) Note that this would gate the clock
> to all CPUs.

(Note that my comment was re: all clocks, not just that one clock)

Can't the PMC or flow-controller ungate the clock based on some event?
Either way, that clock definition exists in HW, right? So I don't think
there's actually any harm in including the definition in the binding
even if we never implement/use it.

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/15/2013 02:24 AM, Peter De Schrijver wrote:
> On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote:
>> On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
>>> To replace magic number in tegra_car:
>>>
>>> -               clocks = <&tegra_car 28>;
>>> +               clocks = <&tegra_car CLK_HOST1X>;
>>
>>> diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
>>
>> Sorry, forgot a couple small comments the last time around.
>>
>> This file should probably have some header indicating which binding it
>> describes, rather like the GPIO header in my patch series.
>>
>>> +#define CLK_CPU 0
>>
>> I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
>> clock headers don't conflict. It's not too likely that more than one of
>> the /Tegra/ clock headers will be included at once, but it doesn't seem
>> that unlikely that a board file could end up having a Tegra clock header
>> included plus various other clock headers for some other chip that has
>> some clock outputs.
>>
> 
> I would suggest removing this clock. It's not actually implemented in the CCF
> and rather useless. If you would gate the CPU clock from the CPU by writing to
> this register, how would you ungate it? :) Note that this would gate the clock
> to all CPUs.

(Note that my comment was re: all clocks, not just that one clock)

Can't the PMC or flow-controller ungate the clock based on some event?
Either way, that clock definition exists in HW, right? So I don't think
there's actually any harm in including the definition in the binding
even if we never implement/use it.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Stephen Warren]

On 02/15/2013 02:24 AM, Peter De Schrijver wrote:
> On Thu, Feb 14, 2013 at 09:15:28PM +0100, Stephen Warren wrote:
>> On 02/14/2013 11:59 AM, Hiroshi Doyu wrote:
>>> To replace magic number in tegra_car:
>>>
>>> -               clocks = <&tegra_car 28>;
>>> +               clocks = <&tegra_car CLK_HOST1X>;
>>
>>> diff --git a/arch/arm/boot/dts/tegra20-car.h b/arch/arm/boot/dts/tegra20-car.h
>>
>> Sorry, forgot a couple small comments the last time around.
>>
>> This file should probably have some header indicating which binding it
>> describes, rather like the GPIO header in my patch series.
>>
>>> +#define CLK_CPU 0
>>
>> I'd suggest naming that TEGRA20_CLK_CPU, so that the various different
>> clock headers don't conflict. It's not too likely that more than one of
>> the /Tegra/ clock headers will be included at once, but it doesn't seem
>> that unlikely that a board file could end up having a Tegra clock header
>> included plus various other clock headers for some other chip that has
>> some clock outputs.
>>
> 
> I would suggest removing this clock. It's not actually implemented in the CCF
> and rather useless. If you would gate the CPU clock from the CPU by writing to
> this register, how would you ungate it? :) Note that this would gate the clock
> to all CPUs.

(Note that my comment was re: all clocks, not just that one clock)

Can't the PMC or flow-controller ungate the clock based on some event?
Either way, that clock definition exists in HW, right? So I don't think
there's actually any harm in including the definition in the binding
even if we never implement/use it.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote:

...

> > I would suggest removing this clock. It's not actually implemented in the CCF
> > and rather useless. If you would gate the CPU clock from the CPU by writing to
> > this register, how would you ungate it? :) Note that this would gate the clock
> > to all CPUs.
> 
> (Note that my comment was re: all clocks, not just that one clock)
> 
> Can't the PMC or flow-controller ungate the clock based on some event?

I don't think the flow-controller controls this gate. The usual way of
clockgating a core is to execute a WFI instruction. That will trigger
clockgating the core, unless the flow-controller has been programmed to do
something else. The flow-controller will ungate the clock when there is an
interrupt.

> Either way, that clock definition exists in HW, right? So I don't think
> there's actually any harm in including the definition in the binding
> even if we never implement/use it.

The clock definition seems to exist in HW yes, the corresponding resetbit
however is marked as 'reserved' in the Tegra114 documentation.

Cheers,

Peter.

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote:

...

> > I would suggest removing this clock. It's not actually implemented in the CCF
> > and rather useless. If you would gate the CPU clock from the CPU by writing to
> > this register, how would you ungate it? :) Note that this would gate the clock
> > to all CPUs.
> 
> (Note that my comment was re: all clocks, not just that one clock)
> 
> Can't the PMC or flow-controller ungate the clock based on some event?

I don't think the flow-controller controls this gate. The usual way of
clockgating a core is to execute a WFI instruction. That will trigger
clockgating the core, unless the flow-controller has been programmed to do
something else. The flow-controller will ungate the clock when there is an
interrupt.

> Either way, that clock definition exists in HW, right? So I don't think
> there's actually any harm in including the definition in the binding
> even if we never implement/use it.

The clock definition seems to exist in HW yes, the corresponding resetbit
however is marked as 'reserved' in the Tegra114 documentation.

Cheers,

Peter.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote:

...

> > I would suggest removing this clock. It's not actually implemented in the CCF
> > and rather useless. If you would gate the CPU clock from the CPU by writing to
> > this register, how would you ungate it? :) Note that this would gate the clock
> > to all CPUs.
> 
> (Note that my comment was re: all clocks, not just that one clock)
> 
> Can't the PMC or flow-controller ungate the clock based on some event?

I don't think the flow-controller controls this gate. The usual way of
clockgating a core is to execute a WFI instruction. That will trigger
clockgating the core, unless the flow-controller has been programmed to do
something else. The flow-controller will ungate the clock when there is an
interrupt.

> Either way, that clock definition exists in HW, right? So I don't think
> there's actually any harm in including the definition in the binding
> even if we never implement/use it.

The clock definition seems to exist in HW yes, the corresponding resetbit
however is marked as 'reserved' in the Tegra114 documentation.

Cheers,

Peter.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Thu, Feb 21, 2013 at 01:25:36PM +0100, Peter De Schrijver wrote:
> On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote:
> 
> ...
> 
> > > I would suggest removing this clock. It's not actually implemented in the CCF
> > > and rather useless. If you would gate the CPU clock from the CPU by writing to
> > > this register, how would you ungate it? :) Note that this would gate the clock
> > > to all CPUs.
> > 
> > (Note that my comment was re: all clocks, not just that one clock)
> > 
> > Can't the PMC or flow-controller ungate the clock based on some event?
> 
> I don't think the flow-controller controls this gate. The usual way of
> clockgating a core is to execute a WFI instruction. That will trigger
> clockgating the core, unless the flow-controller has been programmed to do
> something else. The flow-controller will ungate the clock when there is an
> interrupt.
> 
> > Either way, that clock definition exists in HW, right? So I don't think
> > there's actually any harm in including the definition in the binding
> > even if we never implement/use it.
> 
> The clock definition seems to exist in HW yes, the corresponding resetbit
> however is marked as 'reserved' in the Tegra114 documentation.

Apparently from Tegra114 onwards, this bit no longer exists. In previous
chips, it is just turned by the bootloader running on the AVP and stays on
from there on. So at least for Tegra114 I think we remove this clock from
the DT binding.

Cheers,

Peter.

[v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Thu, Feb 21, 2013 at 01:25:36PM +0100, Peter De Schrijver wrote:
> On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote:
> 
> ...
> 
> > > I would suggest removing this clock. It's not actually implemented in the CCF
> > > and rather useless. If you would gate the CPU clock from the CPU by writing to
> > > this register, how would you ungate it? :) Note that this would gate the clock
> > > to all CPUs.
> > 
> > (Note that my comment was re: all clocks, not just that one clock)
> > 
> > Can't the PMC or flow-controller ungate the clock based on some event?
> 
> I don't think the flow-controller controls this gate. The usual way of
> clockgating a core is to execute a WFI instruction. That will trigger
> clockgating the core, unless the flow-controller has been programmed to do
> something else. The flow-controller will ungate the clock when there is an
> interrupt.
> 
> > Either way, that clock definition exists in HW, right? So I don't think
> > there's actually any harm in including the definition in the binding
> > even if we never implement/use it.
> 
> The clock definition seems to exist in HW yes, the corresponding resetbit
> however is marked as 'reserved' in the Tegra114 documentation.

Apparently from Tegra114 onwards, this bit no longer exists. In previous
chips, it is just turned by the bootloader running on the AVP and stays on
from there on. So at least for Tegra114 I think we remove this clock from
the DT binding.

Cheers,

Peter.

Re: [v2 1/4] ARM: tegra20: create a DT header defining CLK IDs

[Peter De Schrijver]

On Thu, Feb 21, 2013 at 01:25:36PM +0100, Peter De Schrijver wrote:
> On Fri, Feb 15, 2013 at 05:45:45PM +0100, Stephen Warren wrote:
> 
> ...
> 
> > > I would suggest removing this clock. It's not actually implemented in the CCF
> > > and rather useless. If you would gate the CPU clock from the CPU by writing to
> > > this register, how would you ungate it? :) Note that this would gate the clock
> > > to all CPUs.
> > 
> > (Note that my comment was re: all clocks, not just that one clock)
> > 
> > Can't the PMC or flow-controller ungate the clock based on some event?
> 
> I don't think the flow-controller controls this gate. The usual way of
> clockgating a core is to execute a WFI instruction. That will trigger
> clockgating the core, unless the flow-controller has been programmed to do
> something else. The flow-controller will ungate the clock when there is an
> interrupt.
> 
> > Either way, that clock definition exists in HW, right? So I don't think
> > there's actually any harm in including the definition in the binding
> > even if we never implement/use it.
> 
> The clock definition seems to exist in HW yes, the corresponding resetbit
> however is marked as 'reserved' in the Tegra114 documentation.

Apparently from Tegra114 onwards, this bit no longer exists. In previous
chips, it is just turned by the bootloader running on the AVP and stays on
from there on. So at least for Tegra114 I think we remove this clock from
the DT binding.

Cheers,

Peter.

[v2 2/4] ARM: tegra20: convert device tree files to use CLK defines

[Hiroshi Doyu]

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/clock/nvidia,tegra20-car.txt          |    2 +-
 arch/arm/boot/dts/tegra20-paz00.dtsp               |    2 +-
 arch/arm/boot/dts/tegra20.dtsip                    |   85 ++++++++++----------
 3 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac..8ceb8ce 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -172,7 +172,7 @@ Example SoC include file:
 	};
 
 	usb@c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
index e63473b..047ebda 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dtsp
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -277,7 +277,7 @@
 		clock-frequency = <80000>;
 		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C3>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 	};
 
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 7b05f53..df2ca9b 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,6 +1,7 @@
 #include "skeleton.dtsi"
 #include "tegra-gpio.h"
 #include "arm-gic.h"
+#include "tegra20-car.h"
 
 / {
 	compatible = "nvidia,tegra20";
@@ -19,7 +20,7 @@
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car 28>;
+		clocks = <&tegra_car CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -30,48 +31,48 @@
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 60>;
+			clocks = <&tegra_car CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 100>;
+			clocks = <&tegra_car CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 19>;
+			clocks = <&tegra_car CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 23>;
+			clocks = <&tegra_car CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 21>;
+			clocks = <&tegra_car CLK_GR2D>;
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car 24>;
+			clocks = <&tegra_car CLK_GR3D>;
 		};
 
 		dc@54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 27>, <&tegra_car 121>;
+			clocks = <&tegra_car CLK_DISP1>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp1", "parent";
 
 			rgb {
@@ -83,7 +84,7 @@
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 26>, <&tegra_car 121>;
+			clocks = <&tegra_car CLK_DISP2>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp2", "parent";
 
 			rgb {
@@ -95,7 +96,7 @@
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 51>, <&tegra_car 117>;
+			clocks = <&tegra_car CLK_HDMI>, <&tegra_car CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
@@ -104,14 +105,14 @@
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car 48>;
+			clocks = <&tegra_car CLK_DSI>;
 			status = "disabled";
 		};
 	};
@@ -174,7 +175,7 @@
 			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car CLK_APBDMA>;
 	};
 
 	ahb {
@@ -216,7 +217,7 @@
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
-		clocks = <&tegra_car 3>;
+		clocks = <&tegra_car CLK_AC97>;
 		status = "disabled";
 	};
 
@@ -225,7 +226,7 @@
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
-		clocks = <&tegra_car 11>;
+		clocks = <&tegra_car CLK_I2S1>;
 		status = "disabled";
 	};
 
@@ -234,7 +235,7 @@
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
-		clocks = <&tegra_car 18>;
+		clocks = <&tegra_car CLK_I2S2>;
 		status = "disabled";
 	};
 
@@ -252,7 +253,7 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car CLK_UARTA>;
 		status = "disabled";
 	};
 
@@ -263,7 +264,7 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		clocks = <&tegra_car 96>;
+		clocks = <&tegra_car CLK_UARTB>;
 		status = "disabled";
 	};
 
@@ -274,7 +275,7 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car CLK_UARTC>;
 		status = "disabled";
 	};
 
@@ -285,7 +286,7 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car CLK_UARTD>;
 		status = "disabled";
 	};
 
@@ -296,7 +297,7 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 20>;
-		clocks = <&tegra_car 66>;
+		clocks = <&tegra_car CLK_UARTE>;
 		status = "disabled";
 	};
 
@@ -304,7 +305,7 @@
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car CLK_PWM>;
 	};
 
 	rtc {
@@ -319,7 +320,7 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C1>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -331,7 +332,7 @@
 		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 43>;
+		clocks = <&tegra_car CLK_SPI>;
 		status = "disabled";
 	};
 
@@ -341,7 +342,7 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C2>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -352,7 +353,7 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C3>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -363,7 +364,7 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_DVC>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -375,7 +376,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car CLK_SBC1>;
 		status = "disabled";
 	};
 
@@ -386,7 +387,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car CLK_SBC2>;
 		status = "disabled";
 	};
 
@@ -397,7 +398,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car CLK_SBC3>;
 		status = "disabled";
 	};
 
@@ -408,7 +409,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car CLK_SBC4>;
 		status = "disabled";
 	};
 
@@ -416,7 +417,7 @@
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car CLK_KBC>;
 		status = "disabled";
 	};
 
@@ -451,7 +452,7 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
-		clocks = <&tegra_car 22>;
+		clocks = <&tegra_car CLK_USBD>;
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -462,7 +463,7 @@
 		reg = <0xc5000400 0x3c00>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
-		clocks = <&tegra_car 22>, <&tegra_car 127>;
+		clocks = <&tegra_car CLK_USBD>, <&tegra_car CLK_PLL_X>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -471,7 +472,7 @@
 		reg = <0xc5004000 0x4000>;
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
-		clocks = <&tegra_car 58>;
+		clocks = <&tegra_car CLK_USB2>;
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -480,7 +481,7 @@
 		compatible = "nvidia,tegra20-usb-phy";
 		reg = <0xc5004400 0x3c00>;
 		phy_type = "ulpi";
-		clocks = <&tegra_car 94>, <&tegra_car 127>;
+		clocks = <&tegra_car CLK_CDEV2>, <&tegra_car CLK_PLL_X>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -489,7 +490,7 @@
 		reg = <0xc5008000 0x4000>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
-		clocks = <&tegra_car 59>;
+		clocks = <&tegra_car CLK_USB3>;
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
@@ -498,7 +499,7 @@
 		compatible = "nvidia,tegra20-usb-phy";
 		reg = <0xc5008400 0x3c00>;
 		phy_type = "utmi";
-		clocks = <&tegra_car 22>, <&tegra_car 127>;
+		clocks = <&tegra_car CLK_USBD>, <&tegra_car CLK_PLL_X>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -506,7 +507,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car CLK_SDMMC1>;
 		status = "disabled";
 	};
 
@@ -514,7 +515,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car CLK_SDMMC2>;
 		status = "disabled";
 	};
 
@@ -522,7 +523,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car CLK_SDMMC3>;
 		status = "disabled";
 	};
 
@@ -530,7 +531,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car CLK_SDMMC4>;
 		status = "disabled";
 	};
 
-- 
1.7.9.5

[v2 2/4] ARM: tegra20: convert device tree files to use CLK defines

[Hiroshi Doyu]

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 .../bindings/clock/nvidia,tegra20-car.txt          |    2 +-
 arch/arm/boot/dts/tegra20-paz00.dtsp               |    2 +-
 arch/arm/boot/dts/tegra20.dtsip                    |   85 ++++++++++----------
 3 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac..8ceb8ce 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -172,7 +172,7 @@ Example SoC include file:
 	};
 
 	usb@c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/arch/arm/boot/dts/tegra20-paz00.dtsp b/arch/arm/boot/dts/tegra20-paz00.dtsp
index e63473b..047ebda 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dtsp
+++ b/arch/arm/boot/dts/tegra20-paz00.dtsp
@@ -277,7 +277,7 @@
 		clock-frequency = <80000>;
 		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C3>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 	};
 
diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip
index 7b05f53..df2ca9b 100644
--- a/arch/arm/boot/dts/tegra20.dtsip
+++ b/arch/arm/boot/dts/tegra20.dtsip
@@ -1,6 +1,7 @@
 #include "skeleton.dtsi"
 #include "tegra-gpio.h"
 #include "arm-gic.h"
+#include "tegra20-car.h"
 
 / {
 	compatible = "nvidia,tegra20";
@@ -19,7 +20,7 @@
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car 28>;
+		clocks = <&tegra_car CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -30,48 +31,48 @@
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 60>;
+			clocks = <&tegra_car CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 100>;
+			clocks = <&tegra_car CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 19>;
+			clocks = <&tegra_car CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 23>;
+			clocks = <&tegra_car CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 21>;
+			clocks = <&tegra_car CLK_GR2D>;
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car 24>;
+			clocks = <&tegra_car CLK_GR3D>;
 		};
 
 		dc@54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 27>, <&tegra_car 121>;
+			clocks = <&tegra_car CLK_DISP1>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp1", "parent";
 
 			rgb {
@@ -83,7 +84,7 @@
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 26>, <&tegra_car 121>;
+			clocks = <&tegra_car CLK_DISP2>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp2", "parent";
 
 			rgb {
@@ -95,7 +96,7 @@
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 51>, <&tegra_car 117>;
+			clocks = <&tegra_car CLK_HDMI>, <&tegra_car CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
@@ -104,14 +105,14 @@
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car 48>;
+			clocks = <&tegra_car CLK_DSI>;
 			status = "disabled";
 		};
 	};
@@ -174,7 +175,7 @@
 			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car CLK_APBDMA>;
 	};
 
 	ahb {
@@ -216,7 +217,7 @@
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
-		clocks = <&tegra_car 3>;
+		clocks = <&tegra_car CLK_AC97>;
 		status = "disabled";
 	};
 
@@ -225,7 +226,7 @@
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
-		clocks = <&tegra_car 11>;
+		clocks = <&tegra_car CLK_I2S1>;
 		status = "disabled";
 	};
 
@@ -234,7 +235,7 @@
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
-		clocks = <&tegra_car 18>;
+		clocks = <&tegra_car CLK_I2S2>;
 		status = "disabled";
 	};
 
@@ -252,7 +253,7 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car CLK_UARTA>;
 		status = "disabled";
 	};
 
@@ -263,7 +264,7 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		clocks = <&tegra_car 96>;
+		clocks = <&tegra_car CLK_UARTB>;
 		status = "disabled";
 	};
 
@@ -274,7 +275,7 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car CLK_UARTC>;
 		status = "disabled";
 	};
 
@@ -285,7 +286,7 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car CLK_UARTD>;
 		status = "disabled";
 	};
 
@@ -296,7 +297,7 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <216000000>;
 		nvidia,dma-request-selector = <&apbdma 20>;
-		clocks = <&tegra_car 66>;
+		clocks = <&tegra_car CLK_UARTE>;
 		status = "disabled";
 	};
 
@@ -304,7 +305,7 @@
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car CLK_PWM>;
 	};
 
 	rtc {
@@ -319,7 +320,7 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C1>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -331,7 +332,7 @@
 		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 43>;
+		clocks = <&tegra_car CLK_SPI>;
 		status = "disabled";
 	};
 
@@ -341,7 +342,7 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C2>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -352,7 +353,7 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_I2C3>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -363,7 +364,7 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>, <&tegra_car 124>;
+		clocks = <&tegra_car CLK_DVC>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -375,7 +376,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car CLK_SBC1>;
 		status = "disabled";
 	};
 
@@ -386,7 +387,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car CLK_SBC2>;
 		status = "disabled";
 	};
 
@@ -397,7 +398,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car CLK_SBC3>;
 		status = "disabled";
 	};
 
@@ -408,7 +409,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car CLK_SBC4>;
 		status = "disabled";
 	};
 
@@ -416,7 +417,7 @@
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car CLK_KBC>;
 		status = "disabled";
 	};
 
@@ -451,7 +452,7 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
-		clocks = <&tegra_car 22>;
+		clocks = <&tegra_car CLK_USBD>;
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -462,7 +463,7 @@
 		reg = <0xc5000400 0x3c00>;
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
-		clocks = <&tegra_car 22>, <&tegra_car 127>;
+		clocks = <&tegra_car CLK_USBD>, <&tegra_car CLK_PLL_X>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -471,7 +472,7 @@
 		reg = <0xc5004000 0x4000>;
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
-		clocks = <&tegra_car 58>;
+		clocks = <&tegra_car CLK_USB2>;
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -480,7 +481,7 @@
 		compatible = "nvidia,tegra20-usb-phy";
 		reg = <0xc5004400 0x3c00>;
 		phy_type = "ulpi";
-		clocks = <&tegra_car 94>, <&tegra_car 127>;
+		clocks = <&tegra_car CLK_CDEV2>, <&tegra_car CLK_PLL_X>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -489,7 +490,7 @@
 		reg = <0xc5008000 0x4000>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
-		clocks = <&tegra_car 59>;
+		clocks = <&tegra_car CLK_USB3>;
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
@@ -498,7 +499,7 @@
 		compatible = "nvidia,tegra20-usb-phy";
 		reg = <0xc5008400 0x3c00>;
 		phy_type = "utmi";
-		clocks = <&tegra_car 22>, <&tegra_car 127>;
+		clocks = <&tegra_car CLK_USBD>, <&tegra_car CLK_PLL_X>;
 		clock-names = "phy", "pll_u";
 	};
 
@@ -506,7 +507,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car CLK_SDMMC1>;
 		status = "disabled";
 	};
 
@@ -514,7 +515,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car CLK_SDMMC2>;
 		status = "disabled";
 	};
 
@@ -522,7 +523,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car CLK_SDMMC3>;
 		status = "disabled";
 	};
 
@@ -530,7 +531,7 @@
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car CLK_SDMMC4>;
 		status = "disabled";
 	};
 
-- 
1.7.9.5

[v2 4/4] ARM: tegra30: convert device tree files to use CLK defines

[Hiroshi Doyu]

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/clock/nvidia,tegra30-car.txt          |    2 +-
 arch/arm/boot/dts/tegra30.dtsip                    |   87 ++++++++++----------
 2 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index f3da3be..bc9660b 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -229,7 +229,7 @@ Example SoC include file:
 	};
 
 	usb@c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index 0148459..0483697 100644
--- a/arch/arm/boot/dts/tegra30.dtsip
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,6 +1,7 @@
 #include "skeleton.dtsi"
 #include "tegra-gpio.h"
 #include "arm-gic.h"
+#include "tegra30-car.h"
 
 / {
 	compatible = "nvidia,tegra30";
@@ -19,7 +20,7 @@
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car 28>;
+		clocks = <&tegra_car CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -30,35 +31,35 @@
 			compatible = "nvidia,tegra30-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 60>;
+			clocks = <&tegra_car CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra30-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 164>;
+			clocks = <&tegra_car CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra30-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 19>;
+			clocks = <&tegra_car CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra30-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 23>;
+			clocks = <&tegra_car CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 21>;
+			clocks = <&tegra_car CLK_GR2D>;
 		};
 
 		gr3d {
@@ -72,7 +73,7 @@
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 27>, <&tegra_car 179>;
+			clocks = <&tegra_car CLK_DISP1>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp1", "parent";
 
 			rgb {
@@ -84,7 +85,7 @@
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 26>, <&tegra_car 179>;
+			clocks = <&tegra_car CLK_DISP2>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp2", "parent";
 
 			rgb {
@@ -96,7 +97,7 @@
 			compatible = "nvidia,tegra30-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 51>, <&tegra_car 189>;
+			clocks = <&tegra_car CLK_HDMI>, <&tegra_car CLK_PLL_D2_OUT0>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
@@ -105,14 +106,14 @@
 			compatible = "nvidia,tegra30-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 169>;
+			clocks = <&tegra_car CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car 48>;
+			clocks = <&tegra_car CLK_DSIA>;
 			status = "disabled";
 		};
 	};
@@ -193,7 +194,7 @@
 			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car CLK_APBDMA>;
 	};
 
 	ahb: ahb {
@@ -239,7 +240,7 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <408000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car CLK_UARTA>;
 		status = "disabled";
 	};
 
@@ -250,7 +251,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		clocks = <&tegra_car 160>;
+		clocks = <&tegra_car CLK_UARTB>;
 		status = "disabled";
 	};
 
@@ -261,7 +262,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car CLK_UARTC>;
 		status = "disabled";
 	};
 
@@ -272,7 +273,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car CLK_UARTD>;
 		status = "disabled";
 	};
 
@@ -283,7 +284,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
-		clocks = <&tegra_car 66>;
+		clocks = <&tegra_car CLK_UARTE>;
 		status = "disabled";
 	};
 
@@ -291,7 +292,7 @@
 		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car CLK_PWM>;
 	};
 
 	rtc {
@@ -306,7 +307,7 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C1>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -317,7 +318,7 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C2>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -328,7 +329,7 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C3>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -339,7 +340,7 @@
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 103>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C4>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -350,7 +351,7 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C5>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -362,7 +363,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car CLK_SBC1>;
 		status = "disabled";
 	};
 
@@ -373,7 +374,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car CLK_SBC2>;
 		status = "disabled";
 	};
 
@@ -384,7 +385,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car CLK_SBC3>;
 		status = "disabled";
 	};
 
@@ -395,7 +396,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car CLK_SBC4>;
 		status = "disabled";
 	};
 
@@ -406,7 +407,7 @@
 		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 104>;
+		clocks = <&tegra_car CLK_SBC5>;
 		status = "disabled";
 	};
 
@@ -417,7 +418,7 @@
 		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 105>;
+		clocks = <&tegra_car CLK_SBC6>;
 		status = "disabled";
 	};
 
@@ -425,7 +426,7 @@
 		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car CLK_KBC>;
 		status = "disabled";
 	};
 
@@ -459,10 +460,10 @@
 		       0x70080200 0x100>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
-		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-			 <&tegra_car 110>, <&tegra_car 162>;
+		clocks = <&tegra_car CLK_D_AUDIO>, <&tegra_car CLK_APBIF>, <&tegra_car CLK_I2S0>,
+			 <&tegra_car CLK_I2S1>, <&tegra_car CLK_I2S2>, <&tegra_car CLK_I2S3>,
+			 <&tegra_car CLK_I2S4>, <&tegra_car CLK_DAM0>, <&tegra_car CLK_DAM1>,
+			 <&tegra_car CLK_DAM2>, <&tegra_car CLK_SPDIF_OUT>;
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in";
@@ -474,7 +475,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
-			clocks = <&tegra_car 30>;
+			clocks = <&tegra_car CLK_I2S0>;
 			status = "disabled";
 		};
 
@@ -482,7 +483,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
-			clocks = <&tegra_car 11>;
+			clocks = <&tegra_car CLK_I2S1>;
 			status = "disabled";
 		};
 
@@ -490,7 +491,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
-			clocks = <&tegra_car 18>;
+			clocks = <&tegra_car CLK_I2S2>;
 			status = "disabled";
 		};
 
@@ -498,7 +499,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
-			clocks = <&tegra_car 101>;
+			clocks = <&tegra_car CLK_I2S3>;
 			status = "disabled";
 		};
 
@@ -506,7 +507,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car CLK_I2S4>;
 			status = "disabled";
 		};
 	};
@@ -515,7 +516,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car CLK_SDMMC1>;
 		status = "disabled";
 	};
 
@@ -523,7 +524,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car CLK_SDMMC2>;
 		status = "disabled";
 	};
 
@@ -531,7 +532,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car CLK_SDMMC3>;
 		status = "disabled";
 	};
 
@@ -539,7 +540,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car CLK_SDMMC4>;
 		status = "disabled";
 	};
 
-- 
1.7.9.5

[v2 4/4] ARM: tegra30: convert device tree files to use CLK defines

[Hiroshi Doyu]

Replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 .../bindings/clock/nvidia,tegra30-car.txt          |    2 +-
 arch/arm/boot/dts/tegra30.dtsip                    |   87 ++++++++++----------
 2 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index f3da3be..bc9660b 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -229,7 +229,7 @@ Example SoC include file:
 	};
 
 	usb@c5004000 {
-		clocks = <&tegra_car 58>; /* usb2 */
+		clocks = <&tegra_car CLK_USB2>; /* usb2 */
 	};
 };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip
index 0148459..0483697 100644
--- a/arch/arm/boot/dts/tegra30.dtsip
+++ b/arch/arm/boot/dts/tegra30.dtsip
@@ -1,6 +1,7 @@
 #include "skeleton.dtsi"
 #include "tegra-gpio.h"
 #include "arm-gic.h"
+#include "tegra30-car.h"
 
 / {
 	compatible = "nvidia,tegra30";
@@ -19,7 +20,7 @@
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car 28>;
+		clocks = <&tegra_car CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -30,35 +31,35 @@
 			compatible = "nvidia,tegra30-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 60>;
+			clocks = <&tegra_car CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra30-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 164>;
+			clocks = <&tegra_car CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra30-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 19>;
+			clocks = <&tegra_car CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra30-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 23>;
+			clocks = <&tegra_car CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 21>;
+			clocks = <&tegra_car CLK_GR2D>;
 		};
 
 		gr3d {
@@ -72,7 +73,7 @@
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 27>, <&tegra_car 179>;
+			clocks = <&tegra_car CLK_DISP1>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp1", "parent";
 
 			rgb {
@@ -84,7 +85,7 @@
 			compatible = "nvidia,tegra30-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 26>, <&tegra_car 179>;
+			clocks = <&tegra_car CLK_DISP2>, <&tegra_car CLK_PLL_P>;
 			clock-names = "disp2", "parent";
 
 			rgb {
@@ -96,7 +97,7 @@
 			compatible = "nvidia,tegra30-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 51>, <&tegra_car 189>;
+			clocks = <&tegra_car CLK_HDMI>, <&tegra_car CLK_PLL_D2_OUT0>;
 			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
@@ -105,14 +106,14 @@
 			compatible = "nvidia,tegra30-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car 169>;
+			clocks = <&tegra_car CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car 48>;
+			clocks = <&tegra_car CLK_DSIA>;
 			status = "disabled";
 		};
 	};
@@ -193,7 +194,7 @@
 			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 34>;
+		clocks = <&tegra_car CLK_APBDMA>;
 	};
 
 	ahb: ahb {
@@ -239,7 +240,7 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		clock-frequency = <408000000>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		clocks = <&tegra_car 6>;
+		clocks = <&tegra_car CLK_UARTA>;
 		status = "disabled";
 	};
 
@@ -250,7 +251,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		clocks = <&tegra_car 160>;
+		clocks = <&tegra_car CLK_UARTB>;
 		status = "disabled";
 	};
 
@@ -261,7 +262,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		clocks = <&tegra_car 55>;
+		clocks = <&tegra_car CLK_UARTC>;
 		status = "disabled";
 	};
 
@@ -272,7 +273,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		clocks = <&tegra_car 65>;
+		clocks = <&tegra_car CLK_UARTD>;
 		status = "disabled";
 	};
 
@@ -283,7 +284,7 @@
 		clock-frequency = <408000000>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
-		clocks = <&tegra_car 66>;
+		clocks = <&tegra_car CLK_UARTE>;
 		status = "disabled";
 	};
 
@@ -291,7 +292,7 @@
 		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
-		clocks = <&tegra_car 17>;
+		clocks = <&tegra_car CLK_PWM>;
 	};
 
 	rtc {
@@ -306,7 +307,7 @@
 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 12>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C1>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -317,7 +318,7 @@
 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 54>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C2>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -328,7 +329,7 @@
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 67>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C3>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -339,7 +340,7 @@
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 103>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C4>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -350,7 +351,7 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 47>, <&tegra_car 182>;
+		clocks = <&tegra_car CLK_I2C5>, <&tegra_car CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -362,7 +363,7 @@
 		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 41>;
+		clocks = <&tegra_car CLK_SBC1>;
 		status = "disabled";
 	};
 
@@ -373,7 +374,7 @@
 		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 44>;
+		clocks = <&tegra_car CLK_SBC2>;
 		status = "disabled";
 	};
 
@@ -384,7 +385,7 @@
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 46>;
+		clocks = <&tegra_car CLK_SBC3>;
 		status = "disabled";
 	};
 
@@ -395,7 +396,7 @@
 		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 68>;
+		clocks = <&tegra_car CLK_SBC4>;
 		status = "disabled";
 	};
 
@@ -406,7 +407,7 @@
 		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 104>;
+		clocks = <&tegra_car CLK_SBC5>;
 		status = "disabled";
 	};
 
@@ -417,7 +418,7 @@
 		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car 105>;
+		clocks = <&tegra_car CLK_SBC6>;
 		status = "disabled";
 	};
 
@@ -425,7 +426,7 @@
 		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 36>;
+		clocks = <&tegra_car CLK_KBC>;
 		status = "disabled";
 	};
 
@@ -459,10 +460,10 @@
 		       0x70080200 0x100>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
-		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-			 <&tegra_car 110>, <&tegra_car 162>;
+		clocks = <&tegra_car CLK_D_AUDIO>, <&tegra_car CLK_APBIF>, <&tegra_car CLK_I2S0>,
+			 <&tegra_car CLK_I2S1>, <&tegra_car CLK_I2S2>, <&tegra_car CLK_I2S3>,
+			 <&tegra_car CLK_I2S4>, <&tegra_car CLK_DAM0>, <&tegra_car CLK_DAM1>,
+			 <&tegra_car CLK_DAM2>, <&tegra_car CLK_SPDIF_OUT>;
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in";
@@ -474,7 +475,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
-			clocks = <&tegra_car 30>;
+			clocks = <&tegra_car CLK_I2S0>;
 			status = "disabled";
 		};
 
@@ -482,7 +483,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
-			clocks = <&tegra_car 11>;
+			clocks = <&tegra_car CLK_I2S1>;
 			status = "disabled";
 		};
 
@@ -490,7 +491,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
-			clocks = <&tegra_car 18>;
+			clocks = <&tegra_car CLK_I2S2>;
 			status = "disabled";
 		};
 
@@ -498,7 +499,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
-			clocks = <&tegra_car 101>;
+			clocks = <&tegra_car CLK_I2S3>;
 			status = "disabled";
 		};
 
@@ -506,7 +507,7 @@
 			compatible = "nvidia,tegra30-i2s";
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
-			clocks = <&tegra_car 102>;
+			clocks = <&tegra_car CLK_I2S4>;
 			status = "disabled";
 		};
 	};
@@ -515,7 +516,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 14>;
+		clocks = <&tegra_car CLK_SDMMC1>;
 		status = "disabled";
 	};
 
@@ -523,7 +524,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 9>;
+		clocks = <&tegra_car CLK_SDMMC2>;
 		status = "disabled";
 	};
 
@@ -531,7 +532,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 69>;
+		clocks = <&tegra_car CLK_SDMMC3>;
 		status = "disabled";
 	};
 
@@ -539,7 +540,7 @@
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car 15>;
+		clocks = <&tegra_car CLK_SDMMC4>;
 		status = "disabled";
 	};
 
-- 
1.7.9.5

[v2 3/4] ARM: tegra30: create a DT header defining CLK IDs

[Hiroshi Doyu]

To replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra30-car.h |  171 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra30-car.h

diff --git a/arch/arm/boot/dts/tegra30-car.h b/arch/arm/boot/dts/tegra30-car.h
new file mode 100644
index 0000000..96af7b3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-car.h
@@ -0,0 +1,171 @@
+#define CLK_CPU 0
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+#define CLK_I2S0 30
+#define CLK_COP_CACHE 31
+#define CLK_MC 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+#define CLK_KBC 36
+#define CLK_STATMON 37
+#define CLK_PMC 38
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SBC2 44
+#define CLK_SBC3 46
+#define CLK_I2C5 47
+#define CLK_DSIA 48
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PCIE 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIEX 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+#define CLK_DTV 79
+#define CLK_NDSPEED 80
+#define CLK_I2C_SLOW 81
+#define CLK_DSIB 82
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 90
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+#define CLK_CPU_G 96
+#define CLK_CPU_LP 97
+#define CLK_GR3D2 98
+#define CLK_MSELECT 99
+#define CLK_TSENSOR 100
+#define CLK_I2S3 101
+#define CLK_I2S4 102
+#define CLK_I2C4 103
+#define CLK_SBC5 104
+#define CLK_SBC6 105
+#define CLK_D_AUDIO 106
+#define CLK_APBIF 107
+#define CLK_DAM0 108
+#define CLK_DAM1 109
+#define CLK_DAM2 110
+#define CLK_HDA2CODEC_2X 111
+#define CLK_ATOMICS 112
+#define CLK_AUDIO0_2X 113
+#define CLK_AUDIO1_2X 114
+#define CLK_AUDIO2_2X 115
+#define CLK_AUDIO3_2X 116
+#define CLK_AUDIO4_2X 117
+#define CLK_SPDIF_2X 118
+#define CLK_ACTMON 119
+#define CLK_EXTERN1 120
+#define CLK_EXTERN2 121
+#define CLK_EXTERN3 122
+#define CLK_SATA_OOB 123
+#define CLK_SATA 124
+#define CLK_HDA 125
+#define CLK_SE 127
+#define CLK_HDA2HDMI 128
+#define CLK_SATA_COLD 129
+#define CLK_UARTB 160
+#define CLK_VFIR 161
+#define CLK_SPDIF_OUT 162
+#define CLK_SPDIF_IN 163
+#define CLK_VI 164
+#define CLK_VI_SENSOR 165
+#define CLK_FUSE 166
+#define CLK_FUSE_BURN 167
+#define CLK_CVE 168
+#define CLK_TVO 169
+#define CLK_CLK_32K 170
+#define CLK_CLK_M 171
+#define CLK_CLK_M_DIV2 172
+#define CLK_CLK_M_DIV4 173
+#define CLK_PLL_REF 174
+#define CLK_PLL_C 175
+#define CLK_PLL_C_OUT1 176
+#define CLK_PLL_M 177
+#define CLK_PLL_M_OUT1 178
+#define CLK_PLL_P 179
+#define CLK_PLL_P_OUT1 180
+#define CLK_PLL_P_OUT2 181
+#define CLK_PLL_P_OUT3 182
+#define CLK_PLL_P_OUT4 183
+#define CLK_PLL_A 184
+#define CLK_PLL_A_OUT0 185
+#define CLK_PLL_D 186
+#define CLK_PLL_D_OUT0 187
+#define CLK_PLL_D2 188
+#define CLK_PLL_D2_OUT0 189
+#define CLK_PLL_U 190
+#define CLK_PLL_X 191
+#define CLK_PLL_X_OUT0 192
+#define CLK_PLL_E 193
+#define CLK_SPDIF_IN_SYNC 194
+#define CLK_I2S0_SYNC 195
+#define CLK_I2S1_SYNC 196
+#define CLK_I2S2_SYNC 197
+#define CLK_I2S3_SYNC 198
+#define CLK_I2S4_SYNC 199
+#define CLK_VIMCLK_SYNC 200
+#define CLK_AUDIO0 201
+#define CLK_AUDIO1 202
+#define CLK_AUDIO2 203
+#define CLK_AUDIO3 204
+#define CLK_AUDIO4 205
+#define CLK_SPDIF 206
+#define CLK_CLK_OUT_1 207
+#define CLK_CLK_OUT_2 208
+#define CLK_CLK_OUT_3 209
+#define CLK_SCLK 210
+#define CLK_BLINK 211
+#define CLK_CCLK_G 212
+#define CLK_CCLK_LP 213
+#define CLK_TWD 214
+#define CLK_CML0 215
+#define CLK_CML1 216
+#define CLK_I2CSLOW 217
+#define CLK_HCLK 218
+#define CLK_PCLK 219
+#define CLK_CLK_OUT_1_MUX 300
+#define CLK_CLK_MAX 301
-- 
1.7.9.5

[v2 3/4] ARM: tegra30: create a DT header defining CLK IDs

[Hiroshi Doyu]

To replace magic number in tegra_car:

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra30-car.h |  171 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra30-car.h

diff --git a/arch/arm/boot/dts/tegra30-car.h b/arch/arm/boot/dts/tegra30-car.h
new file mode 100644
index 0000000..96af7b3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-car.h
@@ -0,0 +1,171 @@
+#define CLK_CPU 0
+#define CLK_RTC 4
+#define CLK_TIMER 5
+#define CLK_UARTA 6
+#define CLK_GPIO 8
+#define CLK_SDMMC2 9
+#define CLK_I2S1 11
+#define CLK_I2C1 12
+#define CLK_NDFLASH 13
+#define CLK_SDMMC1 14
+#define CLK_SDMMC4 15
+#define CLK_PWM 17
+#define CLK_I2S2 18
+#define CLK_EPP 19
+#define CLK_GR2D 21
+#define CLK_USBD 22
+#define CLK_ISP 23
+#define CLK_GR3D 24
+#define CLK_DISP2 26
+#define CLK_DISP1 27
+#define CLK_HOST1X 28
+#define CLK_VCP 29
+#define CLK_I2S0 30
+#define CLK_COP_CACHE 31
+#define CLK_MC 32
+#define CLK_AHBDMA 33
+#define CLK_APBDMA 34
+#define CLK_KBC 36
+#define CLK_STATMON 37
+#define CLK_PMC 38
+#define CLK_KFUSE 40
+#define CLK_SBC1 41
+#define CLK_NOR 42
+#define CLK_SBC2 44
+#define CLK_SBC3 46
+#define CLK_I2C5 47
+#define CLK_DSIA 48
+#define CLK_MIPI 50
+#define CLK_HDMI 51
+#define CLK_CSI 52
+#define CLK_TVDAC 53
+#define CLK_I2C2 54
+#define CLK_UARTC 55
+#define CLK_EMC 57
+#define CLK_USB2 58
+#define CLK_USB3 59
+#define CLK_MPE 60
+#define CLK_VDE 61
+#define CLK_BSEA 62
+#define CLK_BSEV 63
+#define CLK_SPEEDO 64
+#define CLK_UARTD 65
+#define CLK_UARTE 66
+#define CLK_I2C3 67
+#define CLK_SBC4 68
+#define CLK_SDMMC3 69
+#define CLK_PCIE 70
+#define CLK_OWR 71
+#define CLK_AFI 72
+#define CLK_CSITE 73
+#define CLK_PCIEX 74
+#define CLK_AVPUCQ 75
+#define CLK_LA 76
+#define CLK_DTV 79
+#define CLK_NDSPEED 80
+#define CLK_I2C_SLOW 81
+#define CLK_DSIB 82
+#define CLK_IRAMA 84
+#define CLK_IRAMB 85
+#define CLK_IRAMC 86
+#define CLK_IRAMD 87
+#define CLK_CRAM2 88
+#define CLK_AUDIO_2X 90
+#define CLK_CSUS 92
+#define CLK_CDEV1 93
+#define CLK_CDEV2 94
+#define CLK_CPU_G 96
+#define CLK_CPU_LP 97
+#define CLK_GR3D2 98
+#define CLK_MSELECT 99
+#define CLK_TSENSOR 100
+#define CLK_I2S3 101
+#define CLK_I2S4 102
+#define CLK_I2C4 103
+#define CLK_SBC5 104
+#define CLK_SBC6 105
+#define CLK_D_AUDIO 106
+#define CLK_APBIF 107
+#define CLK_DAM0 108
+#define CLK_DAM1 109
+#define CLK_DAM2 110
+#define CLK_HDA2CODEC_2X 111
+#define CLK_ATOMICS 112
+#define CLK_AUDIO0_2X 113
+#define CLK_AUDIO1_2X 114
+#define CLK_AUDIO2_2X 115
+#define CLK_AUDIO3_2X 116
+#define CLK_AUDIO4_2X 117
+#define CLK_SPDIF_2X 118
+#define CLK_ACTMON 119
+#define CLK_EXTERN1 120
+#define CLK_EXTERN2 121
+#define CLK_EXTERN3 122
+#define CLK_SATA_OOB 123
+#define CLK_SATA 124
+#define CLK_HDA 125
+#define CLK_SE 127
+#define CLK_HDA2HDMI 128
+#define CLK_SATA_COLD 129
+#define CLK_UARTB 160
+#define CLK_VFIR 161
+#define CLK_SPDIF_OUT 162
+#define CLK_SPDIF_IN 163
+#define CLK_VI 164
+#define CLK_VI_SENSOR 165
+#define CLK_FUSE 166
+#define CLK_FUSE_BURN 167
+#define CLK_CVE 168
+#define CLK_TVO 169
+#define CLK_CLK_32K 170
+#define CLK_CLK_M 171
+#define CLK_CLK_M_DIV2 172
+#define CLK_CLK_M_DIV4 173
+#define CLK_PLL_REF 174
+#define CLK_PLL_C 175
+#define CLK_PLL_C_OUT1 176
+#define CLK_PLL_M 177
+#define CLK_PLL_M_OUT1 178
+#define CLK_PLL_P 179
+#define CLK_PLL_P_OUT1 180
+#define CLK_PLL_P_OUT2 181
+#define CLK_PLL_P_OUT3 182
+#define CLK_PLL_P_OUT4 183
+#define CLK_PLL_A 184
+#define CLK_PLL_A_OUT0 185
+#define CLK_PLL_D 186
+#define CLK_PLL_D_OUT0 187
+#define CLK_PLL_D2 188
+#define CLK_PLL_D2_OUT0 189
+#define CLK_PLL_U 190
+#define CLK_PLL_X 191
+#define CLK_PLL_X_OUT0 192
+#define CLK_PLL_E 193
+#define CLK_SPDIF_IN_SYNC 194
+#define CLK_I2S0_SYNC 195
+#define CLK_I2S1_SYNC 196
+#define CLK_I2S2_SYNC 197
+#define CLK_I2S3_SYNC 198
+#define CLK_I2S4_SYNC 199
+#define CLK_VIMCLK_SYNC 200
+#define CLK_AUDIO0 201
+#define CLK_AUDIO1 202
+#define CLK_AUDIO2 203
+#define CLK_AUDIO3 204
+#define CLK_AUDIO4 205
+#define CLK_SPDIF 206
+#define CLK_CLK_OUT_1 207
+#define CLK_CLK_OUT_2 208
+#define CLK_CLK_OUT_3 209
+#define CLK_SCLK 210
+#define CLK_BLINK 211
+#define CLK_CCLK_G 212
+#define CLK_CCLK_LP 213
+#define CLK_TWD 214
+#define CLK_CML0 215
+#define CLK_CML1 216
+#define CLK_I2CSLOW 217
+#define CLK_HCLK 218
+#define CLK_PCLK 219
+#define CLK_CLK_OUT_1_MUX 300
+#define CLK_CLK_MAX 301
-- 
1.7.9.5