From: Wenyou Yang <wenyou.yang@atmel.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <grant.likely@secretlab.ca>, <nicolas.ferre@atmel.com>, <plagnioj@jcrosoft.com>, <richard.genoud@gmail.com>, <JM.Lin@atmel.com>, <wenyou.yang@atmel.com>, <spi-devel-general@lists.sourceforge.net>, <linux-kernel@vger.kernel.org> Subject: [PATCH Resend v5 03/16] spi/spi-atmel: add support transfer on CS1,2,3, not only on CS0 Date: Wed, 27 Feb 2013 08:39:34 +0800 [thread overview] Message-ID: <1361925574-12023-1-git-send-email-wenyou.yang@atmel.com> (raw) In-Reply-To: <1361925297-11854-1-git-send-email-wenyou.yang@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Cc: spi-devel-general@lists.sourceforge.net Cc: linux-kernel@vger.kernel.org --- drivers/spi/spi-atmel.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index a8e091b..9c8f2d5 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -256,11 +256,6 @@ static bool atmel_spi_is_v2(struct atmel_spi *as) * Master on Chip Select 0.") No workaround exists for that ... so for * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, * and (c) will trigger that first erratum in some cases. - * - * TODO: Test if the atmel_spi_is_v2() branch below works on - * AT91RM9200 if we use some other register than CSR0. However, don't - * do this unconditionally since AP7000 has an errata where the BITS - * field in CSR0 overrides all other CSRs. */ static void cs_activate(struct atmel_spi *as, struct spi_device *spi) @@ -270,18 +265,22 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi) u32 mr; if (atmel_spi_is_v2(as)) { - /* - * Always use CSR0. This ensures that the clock - * switches to the correct idle polarity before we - * toggle the CS. + spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); + /* For the low SPI version, there is a issue that PDC transfer + * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS */ spi_writel(as, CSR0, asd->csr); if (as->caps.has_wdrbt) { - spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(WDRBT) - | SPI_BIT(MODFDIS) | SPI_BIT(MSTR)); + spi_writel(as, MR, + SPI_BF(PCS, ~(0x01 << spi->chip_select)) + | SPI_BIT(WDRBT) + | SPI_BIT(MODFDIS) + | SPI_BIT(MSTR)); } else { - spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); + spi_writel(as, MR, + SPI_BF(PCS, ~(0x01 << spi->chip_select)) + | SPI_BIT(MODFDIS) + | SPI_BIT(MSTR)); } mr = spi_readl(as, MR); gpio_set_value(asd->npcs_pin, active); -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: wenyou.yang@atmel.com (Wenyou Yang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH Resend v5 03/16] spi/spi-atmel: add support transfer on CS1, 2, 3, not only on CS0 Date: Wed, 27 Feb 2013 08:39:34 +0800 [thread overview] Message-ID: <1361925574-12023-1-git-send-email-wenyou.yang@atmel.com> (raw) In-Reply-To: <1361925297-11854-1-git-send-email-wenyou.yang@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Cc: spi-devel-general at lists.sourceforge.net Cc: linux-kernel at vger.kernel.org --- drivers/spi/spi-atmel.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index a8e091b..9c8f2d5 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -256,11 +256,6 @@ static bool atmel_spi_is_v2(struct atmel_spi *as) * Master on Chip Select 0.") No workaround exists for that ... so for * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, * and (c) will trigger that first erratum in some cases. - * - * TODO: Test if the atmel_spi_is_v2() branch below works on - * AT91RM9200 if we use some other register than CSR0. However, don't - * do this unconditionally since AP7000 has an errata where the BITS - * field in CSR0 overrides all other CSRs. */ static void cs_activate(struct atmel_spi *as, struct spi_device *spi) @@ -270,18 +265,22 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi) u32 mr; if (atmel_spi_is_v2(as)) { - /* - * Always use CSR0. This ensures that the clock - * switches to the correct idle polarity before we - * toggle the CS. + spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); + /* For the low SPI version, there is a issue that PDC transfer + * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS */ spi_writel(as, CSR0, asd->csr); if (as->caps.has_wdrbt) { - spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(WDRBT) - | SPI_BIT(MODFDIS) | SPI_BIT(MSTR)); + spi_writel(as, MR, + SPI_BF(PCS, ~(0x01 << spi->chip_select)) + | SPI_BIT(WDRBT) + | SPI_BIT(MODFDIS) + | SPI_BIT(MSTR)); } else { - spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); + spi_writel(as, MR, + SPI_BF(PCS, ~(0x01 << spi->chip_select)) + | SPI_BIT(MODFDIS) + | SPI_BIT(MSTR)); } mr = spi_readl(as, MR); gpio_set_value(asd->npcs_pin, active); -- 1.7.9.5
next prev parent reply other threads:[~2013-02-27 0:41 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-02-27 0:34 [PATCH Resend v5 00/16] spi/spi-atmel: add dmaengine support for atmel spi controller and to test the device tree support Wenyou Yang 2013-02-27 0:37 ` [PATCH Resend v5 01/16] spi/spi-atmel: fix master->num_chipselect wrongly set Wenyou Yang 2013-02-27 0:37 ` Wenyou Yang 2013-02-27 0:38 ` [PATCH Resend v5 02/16] spi/spi-atmel: detect the capabilities of SPI core by reading the VERSION register Wenyou Yang 2013-02-27 0:38 ` Wenyou Yang 2013-02-27 0:38 ` Wenyou Yang 2013-02-27 19:41 ` Joachim Eastwood 2013-02-27 19:41 ` Joachim Eastwood 2013-02-28 2:29 ` Yang, Wenyou 2013-02-28 2:29 ` Yang, Wenyou 2013-02-27 0:39 ` Wenyou Yang [this message] 2013-02-27 0:39 ` [PATCH Resend v5 03/16] spi/spi-atmel: add support transfer on CS1, 2, 3, not only on CS0 Wenyou Yang 2013-02-27 0:40 ` [PATCH Resend v5 04/16] spi/spi-atmel: add physical base address Wenyou Yang 2013-02-27 0:40 ` Wenyou Yang 2013-02-27 0:41 ` [PATCH Resend v5 05/16] spi/spi-atmel: call unmapping on transfers buffers Wenyou Yang 2013-02-27 0:41 ` Wenyou Yang 2013-02-27 0:42 ` [PATCH Resend v5 06/16] spi/spi-atmel: status information passed through controller data Wenyou Yang 2013-02-27 0:42 ` Wenyou Yang 2013-02-27 0:42 ` [PATCH Resend v5 07/16] spi/spi-atmel: add flag to controller data for lock operations Wenyou Yang 2013-02-27 0:42 ` Wenyou Yang 2013-02-27 0:43 ` [PATCH Resend v5 08/16] spi/spi-atmel: add dmaengine support Wenyou Yang 2013-02-27 0:43 ` Wenyou Yang 2013-02-27 0:44 ` [PATCH Resend v5 09/16] spi/spi-atmel: fix spi-atmel driver to adapt to slave_config changes Wenyou Yang 2013-02-27 0:44 ` Wenyou Yang 2013-02-27 0:45 ` [PATCH Resend v5 10/16] spi/spi-atmel: correct 16 bits transfers using PIO Wenyou Yang 2013-02-27 0:45 ` Wenyou Yang 2013-02-27 0:46 ` [PATCH Resend v5 11/16] spi/spi-atmel: correct 16 bits transfers with DMA Wenyou Yang 2013-02-27 0:46 ` Wenyou Yang 2013-02-27 0:47 ` [PATCH Resend v5 12/16] spi/spi-atmel: add pinctrl support for atmel spi Wenyou Yang 2013-02-27 0:47 ` Wenyou Yang 2013-02-27 19:26 ` Joachim Eastwood 2013-02-27 19:26 ` Joachim Eastwood 2013-02-27 0:47 ` [PATCH Resend v5 13/16] ARM: at91: add clocks for spi dt entries Wenyou Yang 2013-02-27 0:47 ` Wenyou Yang 2013-02-27 0:48 ` [PATCH Resend v5 14/16] ARM: dts: add spi nodes for atmel SoC Wenyou Yang 2013-02-27 0:48 ` Wenyou Yang 2013-02-27 0:49 ` [PATCH Resend v5 15/16] ARM: dts: add spi nodes for the atmel boards Wenyou Yang 2013-02-27 0:49 ` Wenyou Yang 2013-02-27 0:49 ` [PATCH Resend v5 16/16] ARM: dts: add pinctrl property for spi node for atmel SoC Wenyou Yang 2013-02-27 0:49 ` Wenyou Yang 2013-02-27 17:51 ` [PATCH Resend v5 00/16] spi/spi-atmel: add dmaengine support for atmel spi controller and to test the device tree support Robert Nelson 2013-02-28 2:16 ` Yang, Wenyou 2013-03-18 15:15 ` Douglas Gilbert 2013-02-27 19:47 ` Joachim Eastwood
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