* [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub
@ 2013-07-07 18:25 Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type Andreas Färber
` (42 more replies)
0 siblings, 43 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Green, Blue Swirl, Max Filippov,
Michael Walle, Jan Kiszka, Anthony Liguori, Paolo Bonzini,
Guan Xuetao, Andreas Färber, Aurélien Jarno,
Richard Henderson
Hello,
This series cleans up gdbstub by changing all its internal CPU state to CPUState
and by moving most target-specific code into the target directories.
Support for m68k, moxie and unicore32 to set the PC via gdbstub is added.
Lightweight subclasses for XtensaCPU are introduced, keeping the XtensaConfig
mechanisms, to stop xtensa from deviating at gdbstub level wrt register count.
I still wonder whether there would be interest in adding a "program-counter"
dynamic property to the CPU, given that a setter has been factored out here?
v2 replaces uint64_t with a new vaddr type, fixes xtensa breakage, adds a patch
replacing GDB_CORE_XML and attempts to make the read/write_register changes
better reviewable. More details below.
Available for testing at:
git://github.com/afaerber/qemu-cpu.git qom-cpu-11.v2
https://github.com/afaerber/qemu-cpu/commits/qom-cpu-11.v2
Regards,
Andreas
v1 -> v2:
* Applied some patches.
* Introduced new vaddr type, name courtesy of PMM.
* Avoided making the TranslationBlock typedef generally available.
* Rebased to avoid env/cpu field in alpha DisasContext (rth).
* Added missing ppc_cpu_get_phys_page_debug assignment.
* Converted two more cpu_get_phys_page_debug()s breaking xtensa (Max).
* Simplified xtensa subclasses by keeping CPUXtensaState::config for now (Max).
* Split up cpu_gdb_{read,write}_register() conversion (rth).
* Appended patch to drop GDB_CORE_XML.
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Aurélien Jarno <aurelien@aurel32.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Jan Kiszka <jan.kiszka@web.de> (gdbstub)
Cc: Anthony Green <green@moxielogic.com> (moxie)
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> (unicore32)
Cc: Max Filippov <jcmvbkbc@gmail.com> (xtensa)
Cc: Richard Henderson <rth@twiddle.net>
Cc: Michael Walle <michael@walle.cc> (lm32)
Cc: Peter Maydell <peter.maydell@linaro.org> (vaddr)
Andreas Färber (42):
cpu: Introduce vaddr type
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
target-m68k: Implement CPUClass::set_pc()
target-moxie: Implement CPUClass::set_pc()
target-unicore32: Implement CPUClass::set_pc()
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style
cpu: Change cpu_single_step() argument to CPUState
kvm: Change kvm_{insert,remove}_breakpoint() argument to CPUState
gdbstub: Change syscall callback argument to CPUState
gdbstub: Change gdb_handlesig() argument to CPUState
gdbstub: Change GDBState::c_cpu to CPUState
gdbstub: Change gdb_{read,write}_register() argument to CPUState
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
exec: Change cpu_memory_rw_debug() argument to CPUState
cpu: Introduce CPUClass::memory_rw_debug() for
target_memory_rw_debug()
gdbstub: Change GDBState::g_cpu to CPUState
cpu: Move gdb_regs field from CPU_COMMON to CPUState
gdbstub: Change gdb_register_coprocessor() argument to CPUState
target-xtensa: Introduce XtensaCPU subclasses
gdbstub: Fix cpu_gdb_{read,write}_register() Coding Style
gdbstub: Drop dead code in cpu_gdb_{read,write}_register()
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
target-i386: Move cpu_gdb_{read,write}_register()
target-ppc: Move cpu_gdb_{read,write}_register()
target-sparc: Move cpu_gdb_{read,write}_register()
target-arm: Move cpu_gdb_{read,write}_register()
target-m68k: Move cpu_gdb_{read,write}_register()
target-mips: Move cpu_gdb_{read,write}_register()
target-openrisc: Move cpu_gdb_{read,write}_register()
target-sh4: Move cpu_gdb_{read,write}_register()
target-microblaze: Move cpu_gdb_{read,write}_register()
target-cris: Move cpu_gdb_{read,write}_register()
target-alpha: Move cpu_gdb_{read,write}_register()
target-s390x: Move cpu_gdb_{read,write}_register()
target-lm32: Move cpu_gdb_{read,write}_register()
target-xtensa: Move cpu_gdb_{read,write}_register()
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
cpu: Introduce CPUClass::gdb_{read,write}_register()
target-cris: Factor out CPUClass::gdb_read_register() hook for v10
cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
bsd-user/main.c | 10 +-
cpu-exec.c | 10 +-
cpus.c | 6 +-
disas.c | 4 +-
exec.c | 36 +-
gdbstub.c | 1616 ++++-----------------------------------
hw/i386/kvmvapic.c | 78 +-
hw/xtensa/xtensa_lx60.c | 8 +-
hw/xtensa/xtensa_sim.c | 10 +-
include/exec/cpu-all.h | 14 +-
include/exec/cpu-defs.h | 3 -
include/exec/gdbstub.h | 51 +-
include/exec/softmmu-semi.h | 18 +-
include/qom/cpu.h | 122 +--
include/sysemu/kvm.h | 4 +-
kvm-all.c | 12 +-
kvm-stub.c | 4 +-
linux-user/main.c | 35 +-
linux-user/signal.c | 3 +-
monitor.c | 2 +-
qom/cpu.c | 22 +
stubs/Makefile.objs | 1 +
stubs/gdbstub.c | 5 +
target-alpha/Makefile.objs | 1 +
target-alpha/cpu-qom.h | 3 +
target-alpha/cpu.c | 18 +-
target-alpha/cpu.h | 5 -
target-alpha/gdbstub.c | 93 +++
target-alpha/helper.c | 5 +-
target-alpha/translate.c | 3 +-
target-arm/Makefile.objs | 1 +
target-arm/arm-semi.c | 10 +-
target-arm/cpu-qom.h | 5 +
target-arm/cpu.c | 17 +-
target-arm/cpu.h | 5 -
target-arm/gdbstub.c | 102 +++
target-arm/helper.c | 15 +-
target-arm/translate.c | 7 +-
target-cris/Makefile.objs | 1 +
target-cris/cpu-qom.h | 6 +
target-cris/cpu.c | 19 +
target-cris/cpu.h | 4 -
target-cris/gdbstub.c | 130 ++++
target-cris/helper.c | 7 +-
target-cris/translate.c | 7 +-
target-i386/Makefile.objs | 1 +
target-i386/cpu-qom.h | 5 +
target-i386/cpu.c | 22 +-
target-i386/cpu.h | 5 -
target-i386/gdbstub.c | 231 ++++++
target-i386/helper.c | 12 +-
target-i386/kvm.c | 20 +-
target-i386/translate.c | 5 +-
target-lm32/Makefile.objs | 1 +
target-lm32/cpu-qom.h | 3 +
target-lm32/cpu.c | 16 +-
target-lm32/cpu.h | 5 -
target-lm32/gdbstub.c | 92 +++
target-lm32/helper.c | 6 +-
target-lm32/translate.c | 7 +-
target-m68k/Makefile.objs | 1 +
target-m68k/cpu-qom.h | 3 +
target-m68k/cpu.c | 15 +
target-m68k/cpu.h | 5 -
target-m68k/gdbstub.c | 75 ++
target-m68k/helper.c | 5 +-
target-m68k/m68k-semi.c | 5 +-
target-m68k/translate.c | 7 +-
target-microblaze/Makefile.objs | 1 +
target-microblaze/cpu-qom.h | 3 +
target-microblaze/cpu.c | 16 +-
target-microblaze/cpu.h | 5 -
target-microblaze/gdbstub.c | 56 ++
target-microblaze/helper.c | 4 +-
target-microblaze/translate.c | 8 +-
target-mips/Makefile.objs | 1 +
target-mips/cpu-qom.h | 3 +
target-mips/cpu.c | 34 +-
target-mips/cpu.h | 7 -
target-mips/gdbstub.c | 155 ++++
target-mips/helper.c | 7 +-
target-mips/translate.c | 11 +-
target-moxie/cpu.c | 13 +-
target-moxie/cpu.h | 6 +-
target-moxie/helper.c | 11 +-
target-moxie/translate.c | 5 +-
target-openrisc/Makefile.objs | 1 +
target-openrisc/cpu.c | 16 +-
target-openrisc/cpu.h | 8 +-
target-openrisc/gdbstub.c | 83 ++
target-openrisc/mmu.c | 5 +-
target-openrisc/translate.c | 7 +-
target-ppc/Makefile.objs | 1 +
target-ppc/cpu-qom.h | 3 +
target-ppc/cpu.h | 5 -
target-ppc/gdbstub.c | 131 ++++
target-ppc/mmu_helper.c | 4 +-
target-ppc/translate.c | 8 +-
target-ppc/translate_init.c | 35 +-
target-s390x/Makefile.objs | 1 +
target-s390x/cpu-qom.h | 3 +
target-s390x/cpu.c | 14 +
target-s390x/cpu.h | 5 -
target-s390x/gdbstub.c | 88 +++
target-s390x/helper.c | 5 +-
target-s390x/translate.c | 5 +-
target-sh4/Makefile.objs | 1 +
target-sh4/cpu-qom.h | 3 +
target-sh4/cpu.c | 23 +
target-sh4/cpu.h | 6 -
target-sh4/gdbstub.c | 146 ++++
target-sh4/helper.c | 5 +-
target-sh4/translate.c | 8 +-
target-sparc/Makefile.objs | 1 +
target-sparc/cpu-qom.h | 3 +
target-sparc/cpu.c | 34 +-
target-sparc/cpu.h | 11 +-
target-sparc/gdbstub.c | 208 +++++
target-sparc/mmu_helper.c | 22 +-
target-sparc/translate.c | 3 +-
target-unicore32/cpu-qom.h | 1 +
target-unicore32/cpu.c | 11 +
target-unicore32/cpu.h | 5 -
target-unicore32/softmmu.c | 7 +-
target-unicore32/translate.c | 7 +-
target-xtensa/Makefile.objs | 1 +
target-xtensa/cpu-qom.h | 6 +
target-xtensa/cpu.c | 40 +-
target-xtensa/cpu.h | 5 -
target-xtensa/gdbstub.c | 109 +++
target-xtensa/helper.c | 47 +-
target-xtensa/translate.c | 7 +-
target-xtensa/xtensa-semi.c | 14 +-
133 files changed, 2701 insertions(+), 1892 deletions(-)
create mode 100644 stubs/gdbstub.c
create mode 100644 target-alpha/gdbstub.c
create mode 100644 target-arm/gdbstub.c
create mode 100644 target-cris/gdbstub.c
create mode 100644 target-i386/gdbstub.c
create mode 100644 target-lm32/gdbstub.c
create mode 100644 target-m68k/gdbstub.c
create mode 100644 target-microblaze/gdbstub.c
create mode 100644 target-mips/gdbstub.c
create mode 100644 target-openrisc/gdbstub.c
create mode 100644 target-ppc/gdbstub.c
create mode 100644 target-s390x/gdbstub.c
create mode 100644 target-sh4/gdbstub.c
create mode 100644 target-sparc/gdbstub.c
create mode 100644 target-xtensa/gdbstub.c
--
1.8.1.4
^ permalink raw reply [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-15 14:46 ` Peter Maydell
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() Andreas Färber
` (41 subsequent siblings)
42 siblings, 1 reply; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
vaddr is to target_ulong what uintmax_t is to unsigned int.
Its purpose is to allow turning per-target functions with target_ulong
arguments into CPUClass hooks.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
include/qom/cpu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 147c256..4fd12a0 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -29,6 +29,14 @@
typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque);
+typedef uint64_t vaddr;
+#define VADDR_PRId PRId64
+#define VADDR_PRIu PRIu64
+#define VADDR_PRIo PRIo64
+#define VADDR_PRIx PRIx64
+#define VADDR_PRIX PRIX64
+#define VADDR_MAX UINT64_MAX
+
/**
* SECTION:cpu
* @section_id: QEMU-cpu
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 03/42] target-m68k: Implement CPUClass::set_pc() Andreas Färber
` (40 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Alexander Graf, Blue Swirl, Max Filippov,
Michael Walle, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Andreas Färber, Aurelien Jarno, Richard Henderson
This moves setting the Program Counter from gdbstub into target code.
Use vaddr type as upper-bound replacement for target_ulong.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 39 ++++++---------------------------------
include/qom/cpu.h | 2 ++
target-alpha/cpu.c | 8 ++++++++
target-arm/cpu.c | 8 ++++++++
target-cris/cpu.c | 8 ++++++++
target-i386/cpu.c | 8 ++++++++
target-lm32/cpu.c | 8 ++++++++
target-microblaze/cpu.c | 8 ++++++++
target-mips/cpu.c | 14 ++++++++++++++
target-openrisc/cpu.c | 8 ++++++++
target-ppc/translate_init.c | 8 ++++++++
target-s390x/cpu.c | 8 ++++++++
target-sh4/cpu.c | 8 ++++++++
target-sparc/cpu.c | 9 +++++++++
target-xtensa/cpu.c | 8 ++++++++
15 files changed, 119 insertions(+), 33 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 39c8618..07838eb 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -2042,40 +2042,13 @@ static void gdb_breakpoint_remove_all(void)
static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
{
- cpu_synchronize_state(ENV_GET_CPU(s->c_cpu));
-#if defined(TARGET_I386)
- s->c_cpu->eip = pc;
-#elif defined (TARGET_PPC)
- s->c_cpu->nip = pc;
-#elif defined (TARGET_SPARC)
- s->c_cpu->pc = pc;
- s->c_cpu->npc = pc + 4;
-#elif defined (TARGET_ARM)
- s->c_cpu->regs[15] = pc;
-#elif defined (TARGET_SH4)
- s->c_cpu->pc = pc;
-#elif defined (TARGET_MIPS)
- s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
- if (pc & 1) {
- s->c_cpu->hflags |= MIPS_HFLAG_M16;
- } else {
- s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
+ CPUState *cpu = ENV_GET_CPU(s->c_cpu);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cpu_synchronize_state(cpu);
+ if (cc->set_pc) {
+ cc->set_pc(cpu, pc);
}
-#elif defined (TARGET_MICROBLAZE)
- s->c_cpu->sregs[SR_PC] = pc;
-#elif defined(TARGET_OPENRISC)
- s->c_cpu->pc = pc;
-#elif defined (TARGET_CRIS)
- s->c_cpu->pc = pc;
-#elif defined (TARGET_ALPHA)
- s->c_cpu->pc = pc;
-#elif defined (TARGET_S390X)
- s->c_cpu->psw.addr = pc;
-#elif defined (TARGET_LM32)
- s->c_cpu->pc = pc;
-#elif defined(TARGET_XTENSA)
- s->c_cpu->pc = pc;
-#endif
}
static CPUArchState *find_cpu(uint32_t thread_id)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 4fd12a0..e4c1ed9 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -69,6 +69,7 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings.
+ * @set_pc: Callback for setting the Program Counter register.
* @vmsd: State description for migration.
*
* Represents a CPU family or model.
@@ -92,6 +93,7 @@ typedef struct CPUClass {
bool (*get_paging_enabled)(const CPUState *cpu);
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ void (*set_pc)(CPUState *cpu, vaddr value);
const struct VMStateDescription *vmsd;
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 2670805..09bb7a8 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -24,6 +24,13 @@
#include "migration/vmstate.h"
+static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
@@ -264,6 +271,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = alpha_cpu_do_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access);
+ cc->set_pc = alpha_cpu_set_pc;
device_class_set_vmsd(dc, &vmstate_alpha_cpu);
}
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index be26acc..4809fd0 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -25,6 +25,13 @@
#endif
#include "sysemu/sysemu.h"
+static void arm_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ cpu->env.regs[15] = value;
+}
+
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
{
/* Reset a single ARMCPRegInfo register */
@@ -811,6 +818,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->do_interrupt = arm_cpu_do_interrupt;
cc->dump_state = arm_cpu_dump_state;
+ cc->set_pc = arm_cpu_set_pc;
cpu_class_set_vmsd(cc, &vmstate_arm_cpu);
}
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 2abb57f..b72fd98 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -26,6 +26,13 @@
#include "mmu.h"
+static void cris_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ CRISCPU *cpu = CRIS_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
/* CPUClass::reset() */
static void cris_cpu_reset(CPUState *s)
{
@@ -247,6 +254,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->do_interrupt = cris_cpu_do_interrupt;
cc->dump_state = cris_cpu_dump_state;
+ cc->set_pc = cris_cpu_set_pc;
}
static const TypeInfo cris_cpu_type_info = {
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index e3f75a8..67b095d 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2506,6 +2506,13 @@ static bool x86_cpu_get_paging_enabled(const CPUState *cs)
return cpu->env.cr[0] & CR0_PG_MASK;
}
+static void x86_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ cpu->env.eip = value;
+}
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -2522,6 +2529,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = x86_cpu_do_interrupt;
cc->dump_state = x86_cpu_dump_state;
+ cc->set_pc = x86_cpu_set_pc;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 04327ac..8aa28b5 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -22,6 +22,13 @@
#include "qemu-common.h"
+static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ LM32CPU *cpu = LM32_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
/* CPUClass::reset() */
static void lm32_cpu_reset(CPUState *s)
{
@@ -79,6 +86,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = lm32_cpu_do_interrupt;
cc->dump_state = lm32_cpu_dump_state;
+ cc->set_pc = lm32_cpu_set_pc;
cpu_class_set_vmsd(cc, &vmstate_lm32_cpu);
}
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index dce1c7e..0a9bcfa 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -26,6 +26,13 @@
#include "migration/vmstate.h"
+static void mb_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+ cpu->env.sregs[SR_PC] = value;
+}
+
/* CPUClass::reset() */
static void mb_cpu_reset(CPUState *s)
{
@@ -134,6 +141,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = mb_cpu_do_interrupt;
cc->dump_state = mb_cpu_dump_state;
cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access);
+ cc->set_pc = mb_cpu_set_pc;
dc->vmsd = &vmstate_mb_cpu;
dc->props = mb_properties;
}
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 60a3faf..6ec3d25 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -22,6 +22,19 @@
#include "qemu-common.h"
+static void mips_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ env->active_tc.PC = value & ~(target_ulong)1;
+ if (value & 1) {
+ env->hflags |= MIPS_HFLAG_M16;
+ } else {
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ }
+}
+
/* CPUClass::reset() */
static void mips_cpu_reset(CPUState *s)
{
@@ -76,6 +89,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access);
+ cc->set_pc = mips_cpu_set_pc;
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..27ee9f4 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -20,6 +20,13 @@
#include "cpu.h"
#include "qemu-common.h"
+static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
/* CPUClass::reset() */
static void openrisc_cpu_reset(CPUState *s)
{
@@ -146,6 +153,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->do_interrupt = openrisc_cpu_do_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
+ cc->set_pc = openrisc_cpu_set_pc;
device_class_set_vmsd(dc, &vmstate_openrisc_cpu);
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b62f04a..ec47bc8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8163,6 +8163,13 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
return cpu_list;
}
+static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ cpu->env.nip = value;
+}
+
/* CPUClass::reset() */
static void ppc_cpu_reset(CPUState *s)
{
@@ -8290,6 +8297,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = ppc_cpu_do_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
+ cc->set_pc = ppc_cpu_set_pc;
}
static const TypeInfo ppc_cpu_type_info = {
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 1ef2fc0..fe3cd8e 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -58,6 +58,13 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
}
#endif
+static void s390_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ S390CPU *cpu = S390_CPU(cs);
+
+ cpu->env.psw.addr = value;
+}
+
/* CPUClass::reset() */
static void s390_cpu_reset(CPUState *s)
{
@@ -165,6 +172,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = s390_cpu_do_interrupt;
cc->dump_state = s390_cpu_dump_state;
+ cc->set_pc = s390_cpu_set_pc;
dc->vmsd = &vmstate_s390_cpu;
}
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 03487eb..facbd18 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -24,6 +24,13 @@
#include "migration/vmstate.h"
+static void superh_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
/* CPUClass::reset() */
static void superh_cpu_reset(CPUState *s)
{
@@ -269,6 +276,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->do_interrupt = superh_cpu_do_interrupt;
cc->dump_state = superh_cpu_dump_state;
+ cc->set_pc = superh_cpu_set_pc;
dc->vmsd = &vmstate_sh_cpu;
}
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 87c3a50..88582c6 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -723,6 +723,14 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n");
}
+static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+
+ cpu->env.pc = value;
+ cpu->env.npc = value + 4;
+}
+
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
@@ -767,6 +775,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->dump_state = sparc_cpu_dump_state;
cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access);
+ cc->set_pc = sparc_cpu_set_pc;
}
static const TypeInfo sparc_cpu_type_info = {
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 0488984..e3d742a 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -33,6 +33,13 @@
#include "migration/vmstate.h"
+static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
/* CPUClass::reset() */
static void xtensa_cpu_reset(CPUState *s)
{
@@ -100,6 +107,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = xtensa_cpu_do_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
+ cc->set_pc = xtensa_cpu_set_pc;
dc->vmsd = &vmstate_xtensa_cpu;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 03/42] target-m68k: Implement CPUClass::set_pc()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 04/42] target-moxie: " Andreas Färber
` (39 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Paul Brook
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-m68k/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 1b6ef66..43011e7 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -23,6 +23,13 @@
#include "migration/vmstate.h"
+static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ M68kCPU *cpu = M68K_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
static void m68k_set_feature(CPUM68KState *env, int feature)
{
env->features |= (1u << feature);
@@ -182,6 +189,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->do_interrupt = m68k_cpu_do_interrupt;
cc->dump_state = m68k_cpu_dump_state;
+ cc->set_pc = m68k_cpu_set_pc;
dc->vmsd = &vmstate_m68k_cpu;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 04/42] target-moxie: Implement CPUClass::set_pc()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (2 preceding siblings ...)
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 03/42] target-m68k: Implement CPUClass::set_pc() Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 05/42] target-unicore32: " Andreas Färber
` (38 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Green, Andreas Färber
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-moxie/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 92ca594..91f6197 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -22,6 +22,13 @@
#include "migration/vmstate.h"
#include "machine.h"
+static void moxie_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ MoxieCPU *cpu = MOXIE_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
static void moxie_cpu_reset(CPUState *s)
{
MoxieCPU *cpu = MOXIE_CPU(s);
@@ -93,6 +100,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
+ cc->set_pc = moxie_cpu_set_pc;
cpu_class_set_vmsd(cc, &vmstate_moxie_cpu);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 05/42] target-unicore32: Implement CPUClass::set_pc()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (3 preceding siblings ...)
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 04/42] target-moxie: " Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 06/42] cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() Andreas Färber
` (37 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 6572f01..79f2292 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -16,6 +16,13 @@
#include "qemu-common.h"
#include "migration/vmstate.h"
+static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+
+ cpu->env.regs[31] = value;
+}
+
static inline void set_feature(CPUUniCore32State *env, int feature)
{
env->features |= feature;
@@ -131,6 +138,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->do_interrupt = uc32_cpu_do_interrupt;
cc->dump_state = uc32_cpu_dump_state;
+ cc->set_pc = uc32_cpu_set_pc;
dc->vmsd = &vmstate_uc32_cpu;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 06/42] cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (4 preceding siblings ...)
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 05/42] target-unicore32: " Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] " Andreas Färber
` (36 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf,
Blue Swirl, Max Filippov, Michael Walle, open list:PowerPC,
Paul Brook, Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 8 +++++++-
include/qom/cpu.h | 5 +++++
target-alpha/cpu.h | 5 -----
target-arm/cpu.h | 5 -----
target-cris/cpu.h | 4 ----
target-i386/cpu.c | 8 ++++++++
target-i386/cpu.h | 5 -----
target-lm32/cpu.h | 5 -----
target-m68k/cpu.h | 5 -----
target-microblaze/cpu.h | 5 -----
target-mips/cpu.c | 11 +++++++++++
target-mips/cpu.h | 7 -------
target-moxie/cpu.h | 5 -----
target-openrisc/cpu.h | 5 -----
target-ppc/cpu.h | 5 -----
target-s390x/cpu.h | 5 -----
target-sh4/cpu.c | 9 +++++++++
target-sh4/cpu.h | 6 ------
target-sparc/cpu.c | 9 +++++++++
target-sparc/cpu.h | 6 ------
target-unicore32/cpu.h | 5 -----
target-xtensa/cpu.h | 5 -----
22 files changed, 49 insertions(+), 84 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 6c784a7..3fccb86 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -59,8 +59,14 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
* counter hit zero); we must restore the guest PC to the address
* of the start of the TB.
*/
+ CPUClass *cc = CPU_GET_CLASS(cpu);
TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
- cpu_pc_from_tb(env, tb);
+ if (cc->synchronize_from_tb) {
+ cc->synchronize_from_tb(cpu, tb);
+ } else {
+ assert(cc->set_pc);
+ cc->set_pc(cpu, tb->pc);
+ }
}
if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
/* We were asked to stop executing TBs (probably a pending
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index e4c1ed9..152dad5 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -56,6 +56,8 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
bool is_write, bool is_exec, int opaque,
unsigned size);
+struct TranslationBlock;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -70,6 +72,8 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register.
+ * @synchronize_from_tb: Callback for synchronizing state from a TCG
+ * #TranslationBlock.
* @vmsd: State description for migration.
*
* Represents a CPU family or model.
@@ -94,6 +98,7 @@ typedef struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
+ void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
const struct VMStateDescription *vmsd;
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 066f032..c85dc6e 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -515,9 +515,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
#endif /* !defined (__CPU_ALPHA_H__) */
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1369604..0027492 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -796,11 +796,6 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
-{
- env->regs[15] = tb->pc;
-}
-
/* Load an instruction and return it in the standard little-endian order */
static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
bool do_swap)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index c12a8ca..4b9fc4c 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -279,8 +279,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 67b095d..b57ea4b 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2513,6 +2513,13 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.eip = value;
}
+static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ cpu->env.eip = tb->pc - tb->cs_base;
+}
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -2530,6 +2537,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = x86_cpu_do_interrupt;
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
+ cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 2d005b3..cedefdc 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1148,11 +1148,6 @@ static inline bool cpu_has_work(CPUState *cs)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb)
-{
- env->eip = tb->pc - tb->cs_base;
-}
-
static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 856bdc7..dbfe043 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -232,9 +232,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPULM32State *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
#endif
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 9fdf89e..cfd6846 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -260,9 +260,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUM68KState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
#endif
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 6c35475..7508cf5 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -365,9 +365,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb)
-{
- env->sregs[SR_PC] = tb->pc;
-}
-
#endif
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 6ec3d25..1581cd9 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -35,6 +35,16 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ env->active_tc.PC = tb->pc;
+ env->hflags &= ~MIPS_HFLAG_BMASK;
+ env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
+}
+
/* CPUClass::reset() */
static void mips_cpu_reset(CPUState *s)
{
@@ -90,6 +100,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = mips_cpu_dump_state;
cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access);
cc->set_pc = mips_cpu_set_pc;
+ cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7ffd2e3..a29c82f 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -732,13 +732,6 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
-{
- env->active_tc.PC = tb->pc;
- env->hflags &= ~MIPS_HFLAG_BMASK;
- env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
-}
-
static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 72d02c2..d5030a4 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -143,11 +143,6 @@ static inline int cpu_mmu_index(CPUMoxieState *env)
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUMoxieState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 0aff8f2..82bfd03 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -428,9 +428,4 @@ static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
return env->pc;
}
-static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
#endif /* CPU_OPENRISC_H */
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 7a7b1bf..6f51e1f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2144,11 +2144,6 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
-{
- env->nip = tb->pc;
-}
-
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
#endif /* !defined (__CPU_PPC_H__) */
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 6462688..65bef86 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1041,11 +1041,6 @@ static inline bool cpu_has_work(CPUState *cpu)
(env->psw.mask & PSW_MASK_EXT);
}
-static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
-{
- env->psw.addr = tb->pc;
-}
-
/* fpu_helper.c */
uint32_t set_cc_nz_f32(float32 v);
uint32_t set_cc_nz_f64(float64 v);
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index facbd18..03dedc1 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -31,6 +31,14 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+
+ cpu->env.pc = tb->pc;
+ cpu->env.flags = tb->flags;
+}
+
/* CPUClass::reset() */
static void superh_cpu_reset(CPUState *s)
{
@@ -277,6 +285,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = superh_cpu_do_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
+ cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
dc->vmsd = &vmstate_sh_cpu;
}
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index c8df18b..276d295 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -359,10 +359,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
- env->flags = tb->flags;
-}
-
#endif /* _CPU_SH4_H */
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 88582c6..a2deba5 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -731,6 +731,14 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.npc = value + 4;
}
+static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+
+ cpu->env.pc = tb->pc;
+ cpu->env.npc = tb->cs_base;
+}
+
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
@@ -776,6 +784,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = sparc_cpu_dump_state;
cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access);
cc->set_pc = sparc_cpu_set_pc;
+ cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
}
static const TypeInfo sparc_cpu_type_info = {
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 41b014a..0f35a22 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -759,10 +759,4 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUSPARCState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
- env->npc = tb->cs_base;
-}
-
#endif
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index d4be525..967511e 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -146,11 +146,6 @@ static inline int cpu_mmu_index(CPUUniCore32State *env)
#include "cpu-qom.h"
#include "exec/exec-all.h"
-static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
-{
- env->regs[31] = tb->pc;
-}
-
static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 6c9fc35..a8f02f6 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -522,9 +522,4 @@ static inline int cpu_has_work(CPUState *cpu)
return env->pending_irq_level;
}
-static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
#endif
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH qom-cpu v2 07/42] cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() Andreas Färber
` (41 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Andreas Färber, Gleb Natapov, Marcelo Tosatti,
Richard Henderson, Paul Brook, Peter Maydell, Edgar E. Iglesias,
Michael Walle, Aurelien Jarno, Anthony Green, Jia Liu,
Alexander Graf, Blue Swirl, Guan Xuetao, Max Filippov,
open list:Overall, open list:PowerPC
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 2 +-
cpus.c | 2 +-
exec.c | 10 ++++++----
include/exec/cpu-defs.h | 1 -
include/qom/cpu.h | 2 ++
kvm-all.c | 2 +-
target-alpha/translate.c | 3 ++-
target-arm/translate.c | 7 ++++---
target-cris/translate.c | 7 ++++---
target-i386/kvm.c | 6 ++++--
target-i386/translate.c | 5 +++--
target-lm32/translate.c | 7 ++++---
target-m68k/translate.c | 7 ++++---
target-microblaze/translate.c | 8 +++++---
target-mips/translate.c | 11 +++++++----
target-moxie/translate.c | 5 +++--
target-openrisc/translate.c | 7 ++++---
target-ppc/translate.c | 8 +++++---
target-s390x/translate.c | 5 +++--
target-sh4/translate.c | 8 +++++---
target-sparc/translate.c | 3 ++-
target-unicore32/translate.c | 7 ++++---
target-xtensa/translate.c | 7 ++++---
23 files changed, 78 insertions(+), 52 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 3fccb86..301be28 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -297,7 +297,7 @@ int cpu_exec(CPUArchState *env)
for(;;) {
interrupt_request = cpu->interrupt_request;
if (unlikely(interrupt_request)) {
- if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
+ if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
/* Mask out external interrupts for this step. */
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}
diff --git a/cpus.c b/cpus.c
index f141428..8a4f395 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1148,7 +1148,7 @@ static void tcg_exec_all(void)
CPUArchState *env = cpu->env_ptr;
qemu_clock_enable(vm_clock,
- (env->singlestep_enabled & SSTEP_NOTIMER) == 0);
+ (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
if (cpu_can_run(cpu)) {
r = tcg_cpu_exec(env);
diff --git a/exec.c b/exec.c
index f01e3b6..ae6eb24 100644
--- a/exec.c
+++ b/exec.c
@@ -588,11 +588,13 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
void cpu_single_step(CPUArchState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
- if (env->singlestep_enabled != enabled) {
- env->singlestep_enabled = enabled;
- if (kvm_enabled())
+ CPUState *cpu = ENV_GET_CPU(env);
+
+ if (cpu->singlestep_enabled != enabled) {
+ cpu->singlestep_enabled = enabled;
+ if (kvm_enabled()) {
kvm_update_guest_debug(env, 0);
- else {
+ } else {
/* must flush all the translated code to avoid inconsistencies */
/* XXX: only flush what is necessary */
tb_flush(env);
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 39094b3..12b1ca7 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -170,7 +170,6 @@ typedef struct CPUWatchpoint {
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
- int singlestep_enabled; \
\
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 152dad5..136482c 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -129,6 +129,7 @@ struct kvm_run;
* @stopped: Indicates the CPU has been artificially stopped.
* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
* CPU and return to its top level loop.
+ * @singlestep_enabled: Flags for single-stepping.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
* @next_cpu: Next CPU sharing TB cache.
@@ -161,6 +162,7 @@ struct CPUState {
volatile sig_atomic_t exit_request;
volatile sig_atomic_t tcg_exit_req;
uint32_t interrupt_request;
+ int singlestep_enabled;
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
diff --git a/kvm-all.c b/kvm-all.c
index c130705..0c16a44 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1893,7 +1893,7 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
data.dbg.control = reinject_trap;
- if (env->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
}
kvm_arch_update_guest_debug(cpu, &data.dbg);
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 698339d..fdfb23b 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3384,6 +3384,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUAlphaState *env = &cpu->env;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
@@ -3402,7 +3403,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
ctx.pc = pc_start;
ctx.mem_idx = cpu_mmu_index(env);
ctx.implver = env->implver;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
/* ??? Every TB begins with unset rounding mode, to be initialized on
the first fp insn of the TB. Alternately we could define a proper
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9310c58..19e3fb9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9800,6 +9800,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
CPUBreakpoint *bp;
@@ -9819,7 +9820,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->condjmp = 0;
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
@@ -9969,7 +9970,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* ensures prefetch aborts occur at the right place. */
num_insns ++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !cs->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -9986,7 +9987,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
gen_set_condexec(dc);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 1de9743..2a4beeb 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3165,6 +3165,7 @@ static inline void
gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUCRISState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
@@ -3197,7 +3198,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
dc->is_jmp = DISAS_NEXT;
dc->ppc = pc_start;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->flags_uptodate = 1;
dc->flagx_known = 1;
dc->flags_x = tb->flags & X_FLAG;
@@ -3337,7 +3338,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
/* If we are rexecuting a branch due to exceptions on
delay slots dont break. */
- if (!(tb->pc & 1) && env->singlestep_enabled) {
+ if (!(tb->pc & 1) && cs->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
@@ -3370,7 +3371,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
cris_evaluate_flags(dc);
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(env_pc, npc);
}
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 935ef63..1ec7b5b 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1597,6 +1597,7 @@ static int kvm_get_vcpu_events(X86CPU *cpu)
static int kvm_guest_debug_workarounds(X86CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int ret = 0;
unsigned long reinject_trap = 0;
@@ -1619,7 +1620,7 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu)
* reinject them via SET_GUEST_DEBUG.
*/
if (reinject_trap ||
- (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
+ (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
ret = kvm_update_guest_debug(env, reinject_trap);
}
return ret;
@@ -2045,13 +2046,14 @@ static CPUWatchpoint hw_watchpoint;
static int kvm_handle_debug(X86CPU *cpu,
struct kvm_debug_exit_arch *arch_info)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int ret = 0;
int n;
if (arch_info->exception == 1) {
if (arch_info->dr6 & (1 << 14)) {
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
ret = EXCP_DEBUG;
}
} else {
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6550c27..065a9d3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8255,6 +8255,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
@@ -8281,7 +8282,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->cs_base = cs_base;
@@ -8302,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
- dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
+ dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
|| (flags & HF_SOFTMMU_MASK)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index ed12f50..1247287 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1015,6 +1015,7 @@ static inline
void gen_intermediate_code_internal(LM32CPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPULM32State *env = &cpu->env;
struct DisasContext ctx, *dc = &ctx;
uint16_t *gen_opc_end;
@@ -1032,7 +1033,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->nr_nops = 0;
if (pc_start & 3) {
@@ -1077,7 +1078,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
} while (!dc->is_jmp
&& tcg_ctx.gen_opc_ptr < gen_opc_end
- && !env->singlestep_enabled
+ && !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1086,7 +1087,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
gen_io_end();
}
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 2d73af5..d562eeb 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2974,6 +2974,7 @@ static inline void
gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
uint16_t *gen_opc_end;
@@ -2995,7 +2996,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
dc->is_mem = 0;
@@ -3038,14 +3039,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
disas_m68k_insn(env, dc);
num_insns++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !cs->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
gen_flush_cc_op(dc);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index eba255b..cd43577 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1741,6 +1741,7 @@ static inline void
gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUMBState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
@@ -1766,7 +1767,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
dc->jmp = JMP_INDIRECT;
}
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->cpustate_changed = 0;
dc->abort_at_next_insn = 0;
dc->nr_nops = 0;
@@ -1859,8 +1860,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
break;
}
}
- if (env->singlestep_enabled)
+ if (cs->singlestep_enabled) {
break;
+ }
} while (!dc->is_jmp && !dc->cpustate_changed
&& tcg_ctx.gen_opc_ptr < gen_opc_end
&& !singlestep
@@ -1887,7 +1889,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
}
t_sync_flags(dc);
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
if (dc->is_jmp != DISAS_JUMP) {
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8246c20..877f8df 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15543,6 +15543,7 @@ static inline void
gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUMIPSState *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
@@ -15561,7 +15562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
ctx.pc = pc_start;
ctx.saved_pc = -1;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
ctx.tb = tb;
ctx.bstate = BS_NONE;
@@ -15637,8 +15638,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
+ if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
break;
+ }
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
@@ -15653,9 +15655,10 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
if (singlestep)
break;
}
- if (tb->cflags & CF_LAST_IO)
+ if (tb->cflags & CF_LAST_IO) {
gen_io_end();
- if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
+ }
+ if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
} else {
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index 664d359..8cc0bb7 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -824,6 +824,7 @@ static inline void
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
DisasContext ctx;
target_ulong pc_start;
uint16_t *gen_opc_end;
@@ -871,7 +872,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
ctx.pc += decode_opc(cpu, &ctx);
num_insns++;
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
break;
}
@@ -880,7 +881,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
}
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_tl(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index f222834..a6050ba 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1662,6 +1662,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
TranslationBlock *tb,
int search_pc)
{
+ CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint16_t *gen_opc_end;
uint32_t pc_start;
@@ -1681,7 +1682,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
dc->mem_idx = cpu_mmu_index(&cpu->env);
dc->synced_flags = dc->tb_flags = tb->flags;
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
- dc->singlestep_enabled = cpu->env.singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("-----------------------------------------\n");
log_cpu_state(CPU(cpu), 0);
@@ -1743,7 +1744,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
}
} while (!dc->is_jmp
&& tcg_ctx.gen_opc_ptr < gen_opc_end
- && !cpu->env.singlestep_enabled
+ && !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1755,7 +1756,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
dc->is_jmp = DISAS_UPDATE;
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
- if (unlikely(cpu->env.singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index eb96272..f07d70d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9730,6 +9730,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
@@ -9770,8 +9771,9 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.singlestep_enabled = 0;
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
- if (unlikely(env->singlestep_enabled))
+ if (unlikely(cs->singlestep_enabled)) {
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
+ }
#if defined (DO_SINGLE_STEP) && 0
/* Single step trace mode */
msr_se = 1;
@@ -9873,7 +9875,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.exception != POWERPC_EXCP_BRANCH)) {
gen_exception(ctxp, POWERPC_EXCP_TRACE);
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
- (env->singlestep_enabled) ||
+ (cs->singlestep_enabled) ||
singlestep ||
num_insns >= max_insns)) {
/* if we reach a page boundary or are single stepping, stop
@@ -9887,7 +9889,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
gen_debug_exception(ctxp);
}
/* Generate the return instruction */
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index cba7b87..1fb76c5 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -4740,6 +4740,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
DisasContext dc;
target_ulong pc_start;
@@ -4761,7 +4762,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
dc.tb = tb;
dc.pc = pc_start;
dc.cc_op = CC_OP_DYNAMIC;
- do_debug = dc.singlestep_enabled = env->singlestep_enabled;
+ do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
@@ -4818,7 +4819,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
|| tcg_ctx.gen_opc_ptr >= gen_opc_end
|| num_insns >= max_insns
|| singlestep
- || env->singlestep_enabled)) {
+ || cs->singlestep_enabled)) {
status = EXIT_PC_STALE;
}
} while (status == NO_EXIT);
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2fbe668..59f3d47 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1849,6 +1849,7 @@ static inline void
gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUSH4State *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
@@ -1868,7 +1869,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.features = env->features;
ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
@@ -1914,8 +1915,9 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
ctx.pc += 2;
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
- if (env->singlestep_enabled)
+ if (cs->singlestep_enabled) {
break;
+ }
if (num_insns >= max_insns)
break;
if (singlestep)
@@ -1923,7 +1925,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5e771e5..093e0e2 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5223,6 +5223,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
TranslationBlock *tb,
bool spc)
{
+ CPUState *cs = CPU(cpu);
CPUSPARCState *env = &cpu->env;
target_ulong pc_start, last_pc;
uint16_t *gen_opc_end;
@@ -5244,7 +5245,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
dc->def = env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
- dc->singlestep = (env->singlestep_enabled || singlestep);
+ dc->singlestep = (cs->singlestep_enabled || singlestep);
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
num_insns = 0;
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index d85185d..68be1c6 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1879,6 +1879,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUUniCore32State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
CPUBreakpoint *bp;
@@ -1900,7 +1901,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->condjmp = 0;
cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32();
@@ -1971,7 +1972,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
* ensures prefetch aborts occur at the right place. */
num_insns++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !cs->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -1988,7 +1989,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
if (dc->is_jmp == DISAS_SYSCALL) {
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index e4cf828..e692329 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2879,6 +2879,7 @@ static inline
void gen_intermediate_code_internal(XtensaCPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUXtensaState *env = &cpu->env;
DisasContext dc;
int insn_count = 0;
@@ -2894,7 +2895,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
}
dc.config = env->config;
- dc.singlestep_enabled = env->singlestep_enabled;
+ dc.singlestep_enabled = cs->singlestep_enabled;
dc.tb = tb;
dc.pc = pc_start;
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
@@ -2917,7 +2918,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
gen_tb_start();
- if (env->singlestep_enabled && env->exception_taken) {
+ if (cs->singlestep_enabled && env->exception_taken) {
env->exception_taken = 0;
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
@@ -2970,7 +2971,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
}
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
break;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 07/42] cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
@ 2013-07-07 18:25 ` Andreas Färber
0 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Gleb Natapov, Anthony Green,
Marcelo Tosatti, Alexander Graf, Blue Swirl, Max Filippov,
Michael Walle, open list:PowerPC, Paul Brook, open list:Overall,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 2 +-
cpus.c | 2 +-
exec.c | 10 ++++++----
include/exec/cpu-defs.h | 1 -
include/qom/cpu.h | 2 ++
kvm-all.c | 2 +-
target-alpha/translate.c | 3 ++-
target-arm/translate.c | 7 ++++---
target-cris/translate.c | 7 ++++---
target-i386/kvm.c | 6 ++++--
target-i386/translate.c | 5 +++--
target-lm32/translate.c | 7 ++++---
target-m68k/translate.c | 7 ++++---
target-microblaze/translate.c | 8 +++++---
target-mips/translate.c | 11 +++++++----
target-moxie/translate.c | 5 +++--
target-openrisc/translate.c | 7 ++++---
target-ppc/translate.c | 8 +++++---
target-s390x/translate.c | 5 +++--
target-sh4/translate.c | 8 +++++---
target-sparc/translate.c | 3 ++-
target-unicore32/translate.c | 7 ++++---
target-xtensa/translate.c | 7 ++++---
23 files changed, 78 insertions(+), 52 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 3fccb86..301be28 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -297,7 +297,7 @@ int cpu_exec(CPUArchState *env)
for(;;) {
interrupt_request = cpu->interrupt_request;
if (unlikely(interrupt_request)) {
- if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
+ if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
/* Mask out external interrupts for this step. */
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}
diff --git a/cpus.c b/cpus.c
index f141428..8a4f395 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1148,7 +1148,7 @@ static void tcg_exec_all(void)
CPUArchState *env = cpu->env_ptr;
qemu_clock_enable(vm_clock,
- (env->singlestep_enabled & SSTEP_NOTIMER) == 0);
+ (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
if (cpu_can_run(cpu)) {
r = tcg_cpu_exec(env);
diff --git a/exec.c b/exec.c
index f01e3b6..ae6eb24 100644
--- a/exec.c
+++ b/exec.c
@@ -588,11 +588,13 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
void cpu_single_step(CPUArchState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
- if (env->singlestep_enabled != enabled) {
- env->singlestep_enabled = enabled;
- if (kvm_enabled())
+ CPUState *cpu = ENV_GET_CPU(env);
+
+ if (cpu->singlestep_enabled != enabled) {
+ cpu->singlestep_enabled = enabled;
+ if (kvm_enabled()) {
kvm_update_guest_debug(env, 0);
- else {
+ } else {
/* must flush all the translated code to avoid inconsistencies */
/* XXX: only flush what is necessary */
tb_flush(env);
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 39094b3..12b1ca7 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -170,7 +170,6 @@ typedef struct CPUWatchpoint {
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
- int singlestep_enabled; \
\
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 152dad5..136482c 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -129,6 +129,7 @@ struct kvm_run;
* @stopped: Indicates the CPU has been artificially stopped.
* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
* CPU and return to its top level loop.
+ * @singlestep_enabled: Flags for single-stepping.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
* @next_cpu: Next CPU sharing TB cache.
@@ -161,6 +162,7 @@ struct CPUState {
volatile sig_atomic_t exit_request;
volatile sig_atomic_t tcg_exit_req;
uint32_t interrupt_request;
+ int singlestep_enabled;
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
diff --git a/kvm-all.c b/kvm-all.c
index c130705..0c16a44 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1893,7 +1893,7 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
data.dbg.control = reinject_trap;
- if (env->singlestep_enabled) {
+ if (cpu->singlestep_enabled) {
data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
}
kvm_arch_update_guest_debug(cpu, &data.dbg);
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 698339d..fdfb23b 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3384,6 +3384,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUAlphaState *env = &cpu->env;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
@@ -3402,7 +3403,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
ctx.pc = pc_start;
ctx.mem_idx = cpu_mmu_index(env);
ctx.implver = env->implver;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
/* ??? Every TB begins with unset rounding mode, to be initialized on
the first fp insn of the TB. Alternately we could define a proper
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9310c58..19e3fb9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9800,6 +9800,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
CPUBreakpoint *bp;
@@ -9819,7 +9820,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->condjmp = 0;
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
@@ -9969,7 +9970,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* ensures prefetch aborts occur at the right place. */
num_insns ++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !cs->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -9986,7 +9987,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
gen_set_condexec(dc);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 1de9743..2a4beeb 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3165,6 +3165,7 @@ static inline void
gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUCRISState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
@@ -3197,7 +3198,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
dc->is_jmp = DISAS_NEXT;
dc->ppc = pc_start;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->flags_uptodate = 1;
dc->flagx_known = 1;
dc->flags_x = tb->flags & X_FLAG;
@@ -3337,7 +3338,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
/* If we are rexecuting a branch due to exceptions on
delay slots dont break. */
- if (!(tb->pc & 1) && env->singlestep_enabled) {
+ if (!(tb->pc & 1) && cs->singlestep_enabled) {
break;
}
} while (!dc->is_jmp && !dc->cpustate_changed
@@ -3370,7 +3371,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
cris_evaluate_flags(dc);
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(env_pc, npc);
}
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 935ef63..1ec7b5b 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1597,6 +1597,7 @@ static int kvm_get_vcpu_events(X86CPU *cpu)
static int kvm_guest_debug_workarounds(X86CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int ret = 0;
unsigned long reinject_trap = 0;
@@ -1619,7 +1620,7 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu)
* reinject them via SET_GUEST_DEBUG.
*/
if (reinject_trap ||
- (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
+ (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
ret = kvm_update_guest_debug(env, reinject_trap);
}
return ret;
@@ -2045,13 +2046,14 @@ static CPUWatchpoint hw_watchpoint;
static int kvm_handle_debug(X86CPU *cpu,
struct kvm_debug_exit_arch *arch_info)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int ret = 0;
int n;
if (arch_info->exception == 1) {
if (arch_info->dr6 & (1 << 14)) {
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
ret = EXCP_DEBUG;
}
} else {
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6550c27..065a9d3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8255,6 +8255,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
@@ -8281,7 +8282,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->cs_base = cs_base;
@@ -8302,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
- dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
+ dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
|| (flags & HF_SOFTMMU_MASK)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index ed12f50..1247287 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1015,6 +1015,7 @@ static inline
void gen_intermediate_code_internal(LM32CPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPULM32State *env = &cpu->env;
struct DisasContext ctx, *dc = &ctx;
uint16_t *gen_opc_end;
@@ -1032,7 +1033,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->nr_nops = 0;
if (pc_start & 3) {
@@ -1077,7 +1078,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
} while (!dc->is_jmp
&& tcg_ctx.gen_opc_ptr < gen_opc_end
- && !env->singlestep_enabled
+ && !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1086,7 +1087,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
gen_io_end();
}
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 2d73af5..d562eeb 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2974,6 +2974,7 @@ static inline void
gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
uint16_t *gen_opc_end;
@@ -2995,7 +2996,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
dc->is_mem = 0;
@@ -3038,14 +3039,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
disas_m68k_insn(env, dc);
num_insns++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !cs->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
num_insns < max_insns);
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
gen_flush_cc_op(dc);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index eba255b..cd43577 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1741,6 +1741,7 @@ static inline void
gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUMBState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
@@ -1766,7 +1767,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
dc->jmp = JMP_INDIRECT;
}
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->cpustate_changed = 0;
dc->abort_at_next_insn = 0;
dc->nr_nops = 0;
@@ -1859,8 +1860,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
break;
}
}
- if (env->singlestep_enabled)
+ if (cs->singlestep_enabled) {
break;
+ }
} while (!dc->is_jmp && !dc->cpustate_changed
&& tcg_ctx.gen_opc_ptr < gen_opc_end
&& !singlestep
@@ -1887,7 +1889,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
}
t_sync_flags(dc);
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
if (dc->is_jmp != DISAS_JUMP) {
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8246c20..877f8df 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15543,6 +15543,7 @@ static inline void
gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUMIPSState *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
@@ -15561,7 +15562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
ctx.pc = pc_start;
ctx.saved_pc = -1;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
ctx.tb = tb;
ctx.bstate = BS_NONE;
@@ -15637,8 +15638,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
+ if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
break;
+ }
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
@@ -15653,9 +15655,10 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
if (singlestep)
break;
}
- if (tb->cflags & CF_LAST_IO)
+ if (tb->cflags & CF_LAST_IO) {
gen_io_end();
- if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
+ }
+ if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
} else {
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index 664d359..8cc0bb7 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -824,6 +824,7 @@ static inline void
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
DisasContext ctx;
target_ulong pc_start;
uint16_t *gen_opc_end;
@@ -871,7 +872,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
ctx.pc += decode_opc(cpu, &ctx);
num_insns++;
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
break;
}
@@ -880,7 +881,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
}
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_tl(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index f222834..a6050ba 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1662,6 +1662,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
TranslationBlock *tb,
int search_pc)
{
+ CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint16_t *gen_opc_end;
uint32_t pc_start;
@@ -1681,7 +1682,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
dc->mem_idx = cpu_mmu_index(&cpu->env);
dc->synced_flags = dc->tb_flags = tb->flags;
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
- dc->singlestep_enabled = cpu->env.singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("-----------------------------------------\n");
log_cpu_state(CPU(cpu), 0);
@@ -1743,7 +1744,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
}
} while (!dc->is_jmp
&& tcg_ctx.gen_opc_ptr < gen_opc_end
- && !cpu->env.singlestep_enabled
+ && !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1755,7 +1756,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
dc->is_jmp = DISAS_UPDATE;
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
- if (unlikely(cpu->env.singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index eb96272..f07d70d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9730,6 +9730,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
@@ -9770,8 +9771,9 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.singlestep_enabled = 0;
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
- if (unlikely(env->singlestep_enabled))
+ if (unlikely(cs->singlestep_enabled)) {
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
+ }
#if defined (DO_SINGLE_STEP) && 0
/* Single step trace mode */
msr_se = 1;
@@ -9873,7 +9875,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.exception != POWERPC_EXCP_BRANCH)) {
gen_exception(ctxp, POWERPC_EXCP_TRACE);
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
- (env->singlestep_enabled) ||
+ (cs->singlestep_enabled) ||
singlestep ||
num_insns >= max_insns)) {
/* if we reach a page boundary or are single stepping, stop
@@ -9887,7 +9889,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
gen_debug_exception(ctxp);
}
/* Generate the return instruction */
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index cba7b87..1fb76c5 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -4740,6 +4740,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
DisasContext dc;
target_ulong pc_start;
@@ -4761,7 +4762,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
dc.tb = tb;
dc.pc = pc_start;
dc.cc_op = CC_OP_DYNAMIC;
- do_debug = dc.singlestep_enabled = env->singlestep_enabled;
+ do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
@@ -4818,7 +4819,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
|| tcg_ctx.gen_opc_ptr >= gen_opc_end
|| num_insns >= max_insns
|| singlestep
- || env->singlestep_enabled)) {
+ || cs->singlestep_enabled)) {
status = EXIT_PC_STALE;
}
} while (status == NO_EXIT);
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2fbe668..59f3d47 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1849,6 +1849,7 @@ static inline void
gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUSH4State *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
@@ -1868,7 +1869,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.features = env->features;
ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
@@ -1914,8 +1915,9 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
ctx.pc += 2;
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
- if (env->singlestep_enabled)
+ if (cs->singlestep_enabled) {
break;
+ }
if (num_insns >= max_insns)
break;
if (singlestep)
@@ -1923,7 +1925,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
} else {
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5e771e5..093e0e2 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5223,6 +5223,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
TranslationBlock *tb,
bool spc)
{
+ CPUState *cs = CPU(cpu);
CPUSPARCState *env = &cpu->env;
target_ulong pc_start, last_pc;
uint16_t *gen_opc_end;
@@ -5244,7 +5245,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
dc->def = env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
- dc->singlestep = (env->singlestep_enabled || singlestep);
+ dc->singlestep = (cs->singlestep_enabled || singlestep);
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
num_insns = 0;
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index d85185d..68be1c6 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1879,6 +1879,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUUniCore32State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
CPUBreakpoint *bp;
@@ -1900,7 +1901,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->condjmp = 0;
cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32();
@@ -1971,7 +1972,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
* ensures prefetch aborts occur at the right place. */
num_insns++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !cs->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -1988,7 +1989,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
if (dc->is_jmp == DISAS_SYSCALL) {
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index e4cf828..e692329 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2879,6 +2879,7 @@ static inline
void gen_intermediate_code_internal(XtensaCPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPUXtensaState *env = &cpu->env;
DisasContext dc;
int insn_count = 0;
@@ -2894,7 +2895,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
}
dc.config = env->config;
- dc.singlestep_enabled = env->singlestep_enabled;
+ dc.singlestep_enabled = cs->singlestep_enabled;
dc.tb = tb;
dc.pc = pc_start;
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
@@ -2917,7 +2918,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
gen_tb_start();
- if (env->singlestep_enabled && env->exception_taken) {
+ if (cs->singlestep_enabled && env->exception_taken) {
env->exception_taken = 0;
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
@@ -2970,7 +2971,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
}
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
break;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 08/42] gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (6 preceding siblings ...)
2013-07-07 18:25 ` [Qemu-devel] " Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 09/42] cpu: Change cpu_single_step() argument to CPUState Andreas Färber
` (34 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
In particular reindent to 4 instead of 2 spaces.
Prepares for changing cpu_single_step() argument in gdb_handlesig().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 94 +++++++++++++++++++++++++++++++--------------------------------
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 07838eb..ede5cb1 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -2759,66 +2759,66 @@ gdb_queuesig (void)
}
int
-gdb_handlesig (CPUArchState *env, int sig)
+gdb_handlesig(CPUArchState *env, int sig)
{
- GDBState *s;
- char buf[256];
- int n;
+ GDBState *s;
+ char buf[256];
+ int n;
- s = gdbserver_state;
- if (gdbserver_fd < 0 || s->fd < 0)
- return sig;
+ s = gdbserver_state;
+ if (gdbserver_fd < 0 || s->fd < 0) {
+ return sig;
+ }
- /* disable single step if it was enabled */
- cpu_single_step(env, 0);
- tb_flush(env);
+ /* disable single step if it was enabled */
+ cpu_single_step(env, 0);
+ tb_flush(env);
- if (sig != 0)
- {
- snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
- put_packet(s, buf);
- }
- /* put_packet() might have detected that the peer terminated the
- connection. */
- if (s->fd < 0)
- return sig;
-
- sig = 0;
- s->state = RS_IDLE;
- s->running_state = 0;
- while (s->running_state == 0) {
- n = read (s->fd, buf, 256);
- if (n > 0)
- {
- int i;
+ if (sig != 0) {
+ snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb(sig));
+ put_packet(s, buf);
+ }
+ /* put_packet() might have detected that the peer terminated the
+ connection. */
+ if (s->fd < 0) {
+ return sig;
+ }
- for (i = 0; i < n; i++)
- gdb_read_byte (s, buf[i]);
- }
- else if (n == 0 || errno != EAGAIN)
- {
- /* XXX: Connection closed. Should probably wait for another
- connection before continuing. */
- return sig;
+ sig = 0;
+ s->state = RS_IDLE;
+ s->running_state = 0;
+ while (s->running_state == 0) {
+ n = read(s->fd, buf, 256);
+ if (n > 0) {
+ int i;
+
+ for (i = 0; i < n; i++) {
+ gdb_read_byte(s, buf[i]);
+ }
+ } else if (n == 0 || errno != EAGAIN) {
+ /* XXX: Connection closed. Should probably wait for another
+ connection before continuing. */
+ return sig;
}
- }
- sig = s->signal;
- s->signal = 0;
- return sig;
+ }
+ sig = s->signal;
+ s->signal = 0;
+ return sig;
}
/* Tell the remote gdb that the process has exited due to SIG. */
void gdb_signalled(CPUArchState *env, int sig)
{
- GDBState *s;
- char buf[4];
+ GDBState *s;
+ char buf[4];
- s = gdbserver_state;
- if (gdbserver_fd < 0 || s->fd < 0)
- return;
+ s = gdbserver_state;
+ if (gdbserver_fd < 0 || s->fd < 0) {
+ return;
+ }
- snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
- put_packet(s, buf);
+ snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb(sig));
+ put_packet(s, buf);
}
static void gdb_accept(void)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 09/42] cpu: Change cpu_single_step() argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (7 preceding siblings ...)
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 08/42] gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 10/42] kvm: Change kvm_{insert, remove}_breakpoint() " Andreas Färber
` (33 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Use CPUState::env_ptr for now.
Needed for GdbState::c_cpu.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 4 ++--
gdbstub.c | 9 +++++----
include/exec/cpu-all.h | 6 ------
include/qom/cpu.h | 13 +++++++++++++
4 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/exec.c b/exec.c
index ae6eb24..4c9e921 100644
--- a/exec.c
+++ b/exec.c
@@ -585,10 +585,10 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
-void cpu_single_step(CPUArchState *env, int enabled)
+void cpu_single_step(CPUState *cpu, int enabled)
{
#if defined(TARGET_HAS_ICE)
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
if (cpu->singlestep_enabled != enabled) {
cpu->singlestep_enabled = enabled;
diff --git a/gdbstub.c b/gdbstub.c
index ede5cb1..17da380 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -2153,7 +2153,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
s->c_cpu = env;
}
if (res == 's') {
- cpu_single_step(s->c_cpu, sstep_flags);
+ cpu_single_step(ENV_GET_CPU(s->c_cpu), sstep_flags);
}
s->signal = res_signal;
gdb_continue(s);
@@ -2181,7 +2181,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
addr = strtoull(p, (char **)&p, 16);
gdb_set_cpu_pc(s, addr);
}
- cpu_single_step(s->c_cpu, sstep_flags);
+ cpu_single_step(ENV_GET_CPU(s->c_cpu), sstep_flags);
gdb_continue(s);
return RS_IDLE;
case 'F':
@@ -2568,7 +2568,7 @@ send_packet:
put_packet(s, buf);
/* disable single step if it was enabled */
- cpu_single_step(env, 0);
+ cpu_single_step(cpu, 0);
}
#endif
@@ -2761,6 +2761,7 @@ gdb_queuesig (void)
int
gdb_handlesig(CPUArchState *env, int sig)
{
+ CPUState *cpu = ENV_GET_CPU(env);
GDBState *s;
char buf[256];
int n;
@@ -2771,7 +2772,7 @@ gdb_handlesig(CPUArchState *env, int sig)
}
/* disable single step if it was enabled */
- cpu_single_step(env, 0);
+ cpu_single_step(cpu, 0);
tb_flush(env);
if (sig != 0) {
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 6499cd0..1f3c002 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -428,12 +428,6 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
-#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
-#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
-#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
-
-void cpu_single_step(CPUArchState *env, int enabled);
-
#if !defined(CONFIG_USER_ONLY)
/* Return the physical page corresponding to a virtual one. Use it
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 136482c..641be1c 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -496,6 +496,19 @@ void cpu_resume(CPUState *cpu);
*/
void qemu_init_vcpu(CPUState *cpu);
+#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
+#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
+#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
+
+/**
+ * cpu_single_step:
+ * @cpu: CPU to the flags for.
+ * @enabled: Flags to enable.
+ *
+ * Enables or disables single-stepping for @cpu.
+ */
+void cpu_single_step(CPUState *cpu, int enabled);
+
#ifdef CONFIG_SOFTMMU
extern const struct VMStateDescription vmstate_cpu_common;
#else
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH qom-cpu v2 10/42] kvm: Change kvm_{insert,remove}_breakpoint() argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
@ 2013-07-07 18:25 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() Andreas Färber
` (41 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Andreas Färber, Gleb Natapov, Marcelo Tosatti, open list:Overall
CPUArchState is no longer directly used since converting CPU loops to
CPUState.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 12 ++++++++----
include/sysemu/kvm.h | 4 ++--
kvm-all.c | 10 ++++------
kvm-stub.c | 4 ++--
4 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 17da380..b77cd3e 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1954,8 +1954,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
CPUArchState *env;
int err = 0;
- if (kvm_enabled())
- return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
+ if (kvm_enabled()) {
+ return kvm_insert_breakpoint(ENV_GET_CPU(gdbserver_state->c_cpu),
+ addr, len, type);
+ }
switch (type) {
case GDB_BREAKPOINT_SW:
@@ -1991,8 +1993,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
CPUArchState *env;
int err = 0;
- if (kvm_enabled())
- return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
+ if (kvm_enabled()) {
+ return kvm_remove_breakpoint(ENV_GET_CPU(gdbserver_state->c_cpu),
+ addr, len, type);
+ }
switch (type) {
case GDB_BREAKPOINT_SW:
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 1e08a85..f8ac448 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -169,9 +169,9 @@ void *kvm_arch_ram_alloc(ram_addr_t size);
void kvm_setup_guest_memory(void *start, size_t size);
void kvm_flush_coalesced_mmio_buffer(void);
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type);
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type);
void kvm_remove_all_breakpoints(CPUState *cpu);
int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap);
diff --git a/kvm-all.c b/kvm-all.c
index 0c16a44..2263c48 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1903,10 +1903,9 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
return data.err;
}
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
- CPUState *cpu = ENV_GET_CPU(env);
struct kvm_sw_breakpoint *bp;
int err;
@@ -1949,10 +1948,9 @@ int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
return 0;
}
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
- CPUState *cpu = ENV_GET_CPU(env);
struct kvm_sw_breakpoint *bp;
int err;
@@ -2025,13 +2023,13 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
return -EINVAL;
}
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
diff --git a/kvm-stub.c b/kvm-stub.c
index 370c837..7b2233a 100644
--- a/kvm-stub.c
+++ b/kvm-stub.c
@@ -83,13 +83,13 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
return -ENOSYS;
}
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 10/42] kvm: Change kvm_{insert, remove}_breakpoint() argument to CPUState
@ 2013-07-07 18:25 ` Andreas Färber
0 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:25 UTC (permalink / raw)
To: qemu-devel
Cc: Marcelo Tosatti, Andreas Färber, Gleb Natapov, open list:Overall
CPUArchState is no longer directly used since converting CPU loops to
CPUState.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 12 ++++++++----
include/sysemu/kvm.h | 4 ++--
kvm-all.c | 10 ++++------
kvm-stub.c | 4 ++--
4 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 17da380..b77cd3e 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1954,8 +1954,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
CPUArchState *env;
int err = 0;
- if (kvm_enabled())
- return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
+ if (kvm_enabled()) {
+ return kvm_insert_breakpoint(ENV_GET_CPU(gdbserver_state->c_cpu),
+ addr, len, type);
+ }
switch (type) {
case GDB_BREAKPOINT_SW:
@@ -1991,8 +1993,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
CPUArchState *env;
int err = 0;
- if (kvm_enabled())
- return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
+ if (kvm_enabled()) {
+ return kvm_remove_breakpoint(ENV_GET_CPU(gdbserver_state->c_cpu),
+ addr, len, type);
+ }
switch (type) {
case GDB_BREAKPOINT_SW:
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 1e08a85..f8ac448 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -169,9 +169,9 @@ void *kvm_arch_ram_alloc(ram_addr_t size);
void kvm_setup_guest_memory(void *start, size_t size);
void kvm_flush_coalesced_mmio_buffer(void);
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type);
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type);
void kvm_remove_all_breakpoints(CPUState *cpu);
int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap);
diff --git a/kvm-all.c b/kvm-all.c
index 0c16a44..2263c48 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1903,10 +1903,9 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
return data.err;
}
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
- CPUState *cpu = ENV_GET_CPU(env);
struct kvm_sw_breakpoint *bp;
int err;
@@ -1949,10 +1948,9 @@ int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
return 0;
}
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
- CPUState *cpu = ENV_GET_CPU(env);
struct kvm_sw_breakpoint *bp;
int err;
@@ -2025,13 +2023,13 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
return -EINVAL;
}
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
diff --git a/kvm-stub.c b/kvm-stub.c
index 370c837..7b2233a 100644
--- a/kvm-stub.c
+++ b/kvm-stub.c
@@ -83,13 +83,13 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
return -ENOSYS;
}
-int kvm_insert_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-int kvm_remove_breakpoint(CPUArchState *env, target_ulong addr,
+int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 11/42] gdbstub: Change syscall callback argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (9 preceding siblings ...)
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 10/42] kvm: Change kvm_{insert, remove}_breakpoint() " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 12/42] gdbstub: Change gdb_handlesig() " Andreas Färber
` (31 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Callback implementations were specific to arm and m68k, so can easily
cast to ARMCPU and M68kCPU respectively.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 2 +-
include/exec/gdbstub.h | 2 +-
target-arm/arm-semi.c | 8 ++++++--
target-m68k/m68k-semi.c | 5 ++++-
4 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index b77cd3e..63ac5fe 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -2204,7 +2204,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
p++;
type = *p;
if (s->current_syscall_cb) {
- s->current_syscall_cb(s->c_cpu, ret, err);
+ s->current_syscall_cb(ENV_GET_CPU(s->c_cpu), ret, err);
s->current_syscall_cb = NULL;
}
if (type == 'C') {
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index ded4160..de0f4fb 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -11,7 +11,7 @@
#define GDB_WATCHPOINT_ACCESS 4
#ifdef NEED_CPU_H
-typedef void (*gdb_syscall_complete_cb)(CPUArchState *env,
+typedef void (*gdb_syscall_complete_cb)(CPUState *cpu,
target_ulong ret, target_ulong err);
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...);
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 5f01bca..4ecea65 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -122,8 +122,10 @@ static target_ulong arm_semi_syscall_len;
static target_ulong syscall_err;
#endif
-static void arm_semi_cb(CPUARMState *env, target_ulong ret, target_ulong err)
+static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
#ifdef CONFIG_USER_ONLY
TaskState *ts = env->opaque;
#endif
@@ -152,8 +154,10 @@ static void arm_semi_cb(CPUARMState *env, target_ulong ret, target_ulong err)
}
}
-static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong err)
+static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c
index 239fadb..94c4983 100644
--- a/target-m68k/m68k-semi.c
+++ b/target-m68k/m68k-semi.c
@@ -161,8 +161,11 @@ static void m68k_semi_return_u64(CPUM68KState *env, uint64_t ret, uint32_t err)
static int m68k_semi_is_fseek;
-static void m68k_semi_cb(CPUM68KState *env, target_ulong ret, target_ulong err)
+static void m68k_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (m68k_semi_is_fseek) {
/* FIXME: We've already lost the high bits of the fseek
return value. */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 12/42] gdbstub: Change gdb_handlesig() argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (10 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 11/42] gdbstub: Change syscall callback " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 13/42] gdbstub: Change GDBState::c_cpu " Andreas Färber
` (30 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Riku Voipio, Andreas Färber
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
bsd-user/main.c | 10 ++++++----
gdbstub.c | 6 +++---
include/exec/gdbstub.h | 2 +-
linux-user/main.c | 35 +++++++++++++++++++----------------
linux-user/signal.c | 3 ++-
5 files changed, 31 insertions(+), 25 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 1e92552..f9246aa 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -643,7 +643,7 @@ void cpu_loop(CPUSPARCState *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
#if 0
if (sig)
{
@@ -738,6 +738,7 @@ int main(int argc, char **argv)
struct image_info info1, *info = &info1;
TaskState ts1, *ts = &ts1;
CPUArchState *env;
+ CPUState *cpu;
int optind;
const char *r;
int gdbstub_port = 0;
@@ -912,10 +913,11 @@ int main(int argc, char **argv)
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ cpu = ENV_GET_CPU(env);
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
- cpu_reset(ENV_GET_CPU(env));
+ cpu_reset(cpu);
#endif
- thread_cpu = ENV_GET_CPU(env);
+ thread_cpu = cpu;
if (getenv("QEMU_STRACE")) {
do_strace = 1;
@@ -1134,7 +1136,7 @@ int main(int argc, char **argv)
if (gdbstub_port) {
gdbserver_start (gdbstub_port);
- gdb_handlesig(env, 0);
+ gdb_handlesig(cpu, 0);
}
cpu_loop(env);
/* never exits */
diff --git a/gdbstub.c b/gdbstub.c
index 63ac5fe..81a8941 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -2634,7 +2634,7 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
va_end(va);
#ifdef CONFIG_USER_ONLY
put_packet(s, s->syscall_buf);
- gdb_handlesig(s->c_cpu, 0);
+ gdb_handlesig(ENV_GET_CPU(s->c_cpu), 0);
#else
/* In this case wait to send the syscall packet until notification that
the CPU has stopped. This must be done because if the packet is sent
@@ -2763,9 +2763,9 @@ gdb_queuesig (void)
}
int
-gdb_handlesig(CPUArchState *env, int sig)
+gdb_handlesig(CPUState *cpu, int sig)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
GDBState *s;
char buf[256];
int n;
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index de0f4fb..0f1ad9a 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -20,7 +20,7 @@ void gdb_set_stop_cpu(CPUState *cpu);
void gdb_exit(CPUArchState *, int);
#ifdef CONFIG_USER_ONLY
int gdb_queuesig (void);
-int gdb_handlesig (CPUArchState *, int);
+int gdb_handlesig(CPUState *, int);
void gdb_signalled(CPUArchState *, int);
void gdbserver_fork(CPUArchState *);
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index 7f15d3d..27f8232 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -312,6 +312,7 @@ static void set_idt(int n, unsigned int dpl)
void cpu_loop(CPUX86State *env)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
int trapnr;
abi_ulong pc;
target_siginfo_t info;
@@ -443,7 +444,7 @@ void cpu_loop(CPUX86State *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -875,7 +876,7 @@ void cpu_loop(CPUARMState *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -966,7 +967,7 @@ void cpu_loop(CPUUniCore32State *env)
{
int sig;
- sig = gdb_handlesig(env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig) {
info.si_signo = sig;
info.si_errno = 0;
@@ -1233,7 +1234,7 @@ void cpu_loop (CPUSPARCState *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -1764,7 +1765,7 @@ void cpu_loop(CPUPPCState *env)
{
int sig;
- sig = gdb_handlesig(env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig) {
info.si_signo = sig;
info.si_errno = 0;
@@ -2315,7 +2316,7 @@ done_syscall:
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -2475,7 +2476,7 @@ void cpu_loop(CPUOpenRISCState *env)
break;
}
if (gdbsig) {
- gdb_handlesig(env, gdbsig);
+ gdb_handlesig(cs, gdbsig);
if (gdbsig != TARGET_SIGTRAP) {
exit(1);
}
@@ -2518,7 +2519,7 @@ void cpu_loop(CPUSH4State *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -2586,7 +2587,7 @@ void cpu_loop(CPUCRISState *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -2686,7 +2687,7 @@ void cpu_loop(CPUMBState *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -2779,7 +2780,7 @@ void cpu_loop(CPUM68KState *env)
{
int sig;
- sig = gdb_handlesig (env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig)
{
info.si_signo = sig;
@@ -3006,7 +3007,7 @@ void cpu_loop(CPUAlphaState *env)
}
break;
case EXCP_DEBUG:
- info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
+ info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
if (info.si_signo) {
env->lock_addr = -1;
info.si_errno = 0;
@@ -3059,7 +3060,7 @@ void cpu_loop(CPUS390XState *env)
break;
case EXCP_DEBUG:
- sig = gdb_handlesig(env, TARGET_SIGTRAP);
+ sig = gdb_handlesig(cs, TARGET_SIGTRAP);
if (sig) {
n = TARGET_TRAP_BRKPT;
goto do_signal_pc;
@@ -3541,6 +3542,7 @@ int main(int argc, char **argv, char **envp)
struct linux_binprm bprm;
TaskState *ts;
CPUArchState *env;
+ CPUState *cpu;
int optind;
char **target_environ, **wrk;
char **target_argv;
@@ -3637,11 +3639,12 @@ int main(int argc, char **argv, char **envp)
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ cpu = ENV_GET_CPU(env);
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
- cpu_reset(ENV_GET_CPU(env));
+ cpu_reset(cpu);
#endif
- thread_cpu = ENV_GET_CPU(env);
+ thread_cpu = cpu;
if (getenv("QEMU_STRACE")) {
do_strace = 1;
@@ -4076,7 +4079,7 @@ int main(int argc, char **argv, char **envp)
gdbstub_port);
exit(1);
}
- gdb_handlesig(env, 0);
+ gdb_handlesig(cpu, 0);
}
cpu_loop(env);
/* never exits */
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 42d8911..bba85c7 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -5386,6 +5386,7 @@ long do_rt_sigreturn(CPUArchState *env)
void process_pending_signals(CPUArchState *cpu_env)
{
+ CPUState *cpu = ENV_GET_CPU(cpu_env);
int sig;
abi_ulong handler;
sigset_t set, old_set;
@@ -5419,7 +5420,7 @@ void process_pending_signals(CPUArchState *cpu_env)
if (!k->first)
k->pending = 0;
- sig = gdb_handlesig (cpu_env, sig);
+ sig = gdb_handlesig(cpu, sig);
if (!sig) {
sa = NULL;
handler = TARGET_SIG_IGN;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 13/42] gdbstub: Change GDBState::c_cpu to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (11 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 12/42] gdbstub: Change gdb_handlesig() " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 14/42] gdbstub: Change gdb_{read, write}_register() argument " Andreas Färber
` (29 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Allows us to drop find_cpu().
Xtensa still needs env for its num_g_regs.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 68 +++++++++++++++++++++++++++++----------------------------------
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 81a8941..a8fafe2 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -287,7 +287,7 @@ enum RSState {
RS_CHKSUM2,
};
typedef struct GDBState {
- CPUArchState *c_cpu; /* current CPU for step/continue ops */
+ CPUState *c_cpu; /* current CPU for step/continue ops */
CPUArchState *g_cpu; /* current CPU for other ops */
CPUState *query_cpu; /* for q{f|s}ThreadInfo */
enum RSState state; /* parsing state */
@@ -1955,8 +1955,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
int err = 0;
if (kvm_enabled()) {
- return kvm_insert_breakpoint(ENV_GET_CPU(gdbserver_state->c_cpu),
- addr, len, type);
+ return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
}
switch (type) {
@@ -1994,8 +1993,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
int err = 0;
if (kvm_enabled()) {
- return kvm_remove_breakpoint(ENV_GET_CPU(gdbserver_state->c_cpu),
- addr, len, type);
+ return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
}
switch (type) {
@@ -2031,7 +2029,7 @@ static void gdb_breakpoint_remove_all(void)
CPUArchState *env;
if (kvm_enabled()) {
- kvm_remove_all_breakpoints(ENV_GET_CPU(gdbserver_state->c_cpu));
+ kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
return;
}
@@ -2046,7 +2044,7 @@ static void gdb_breakpoint_remove_all(void)
static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
{
- CPUState *cpu = ENV_GET_CPU(s->c_cpu);
+ CPUState *cpu = s->c_cpu;
CPUClass *cc = CPU_GET_CLASS(cpu);
cpu_synchronize_state(cpu);
@@ -2055,20 +2053,11 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
}
}
-static CPUArchState *find_cpu(uint32_t thread_id)
-{
- CPUState *cpu;
-
- cpu = qemu_get_cpu(thread_id);
- if (cpu == NULL) {
- return NULL;
- }
- return cpu->env_ptr;
-}
-
static int gdb_handle_packet(GDBState *s, const char *line_buf)
{
+#ifdef TARGET_XTENSA
CPUArchState *env;
+#endif
CPUState *cpu;
const char *p;
uint32_t thread;
@@ -2087,7 +2076,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
case '?':
/* TODO: Make this return the correct value for user-mode. */
snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
- cpu_index(ENV_GET_CPU(s->c_cpu)));
+ cpu_index(s->c_cpu));
put_packet(s, buf);
/* Remove all the breakpoints when this query is issued,
* because gdb is doing and initial connect and the state
@@ -2149,15 +2138,15 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
if (res) {
if (res_thread != -1 && res_thread != 0) {
- env = find_cpu(res_thread);
- if (env == NULL) {
+ cpu = qemu_get_cpu(res_thread);
+ if (cpu == NULL) {
put_packet(s, "E22");
break;
}
- s->c_cpu = env;
+ s->c_cpu = cpu;
}
if (res == 's') {
- cpu_single_step(ENV_GET_CPU(s->c_cpu), sstep_flags);
+ cpu_single_step(s->c_cpu, sstep_flags);
}
s->signal = res_signal;
gdb_continue(s);
@@ -2185,7 +2174,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
addr = strtoull(p, (char **)&p, 16);
gdb_set_cpu_pc(s, addr);
}
- cpu_single_step(ENV_GET_CPU(s->c_cpu), sstep_flags);
+ cpu_single_step(s->c_cpu, sstep_flags);
gdb_continue(s);
return RS_IDLE;
case 'F':
@@ -2204,7 +2193,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
p++;
type = *p;
if (s->current_syscall_cb) {
- s->current_syscall_cb(ENV_GET_CPU(s->c_cpu), ret, err);
+ s->current_syscall_cb(s->c_cpu, ret, err);
s->current_syscall_cb = NULL;
}
if (type == 'C') {
@@ -2216,7 +2205,9 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
break;
case 'g':
cpu_synchronize_state(ENV_GET_CPU(s->g_cpu));
+#ifdef TARGET_XTENSA
env = s->g_cpu;
+#endif
len = 0;
for (addr = 0; addr < num_g_regs; addr++) {
reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
@@ -2227,7 +2218,9 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
break;
case 'G':
cpu_synchronize_state(ENV_GET_CPU(s->g_cpu));
+#ifdef TARGET_XTENSA
env = s->g_cpu;
+#endif
registers = mem_buf;
len = strlen(p) / 2;
hextomem((uint8_t *)registers, p, len);
@@ -2317,18 +2310,18 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
put_packet(s, "OK");
break;
}
- env = find_cpu(thread);
- if (env == NULL) {
+ cpu = qemu_get_cpu(thread);
+ if (cpu == NULL) {
put_packet(s, "E22");
break;
}
switch (type) {
case 'c':
- s->c_cpu = env;
+ s->c_cpu = cpu;
put_packet(s, "OK");
break;
case 'g':
- s->g_cpu = env;
+ s->g_cpu = cpu->env_ptr;
put_packet(s, "OK");
break;
default:
@@ -2403,7 +2396,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
#ifdef CONFIG_USER_ONLY
else if (strncmp(p, "Offsets", 7) == 0) {
- TaskState *ts = s->c_cpu->opaque;
+ CPUArchState *env = s->c_cpu->env_ptr;
+ TaskState *ts = env->opaque;
snprintf(buf, sizeof(buf),
"Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
@@ -2495,7 +2489,7 @@ void gdb_set_stop_cpu(CPUState *cpu)
{
CPUArchState *env = cpu->env_ptr;
- gdbserver_state->c_cpu = env;
+ gdbserver_state->c_cpu = cpu;
gdbserver_state->g_cpu = env;
}
@@ -2503,8 +2497,8 @@ void gdb_set_stop_cpu(CPUState *cpu)
static void gdb_vm_state_change(void *opaque, int running, RunState state)
{
GDBState *s = gdbserver_state;
- CPUArchState *env = s->c_cpu;
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = s->c_cpu->env_ptr;
+ CPUState *cpu = s->c_cpu;
char buf[256];
const char *type;
int ret;
@@ -2634,7 +2628,7 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
va_end(va);
#ifdef CONFIG_USER_ONLY
put_packet(s, s->syscall_buf);
- gdb_handlesig(ENV_GET_CPU(s->c_cpu), 0);
+ gdb_handlesig(s->c_cpu, 0);
#else
/* In this case wait to send the syscall packet until notification that
the CPU has stopped. This must be done because if the packet is sent
@@ -2642,7 +2636,7 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
is still in the running state, which can cause packets to be dropped
and state transition 'T' packets to be sent while the syscall is still
being processed. */
- cpu_exit(ENV_GET_CPU(s->c_cpu));
+ cpu_exit(s->c_cpu);
#endif
}
@@ -2851,7 +2845,7 @@ static void gdb_accept(void)
socket_set_nodelay(fd);
s = g_malloc0(sizeof(GDBState));
- s->c_cpu = first_cpu->env_ptr;
+ s->c_cpu = first_cpu;
s->g_cpu = first_cpu->env_ptr;
s->fd = fd;
gdb_has_xml = 0;
@@ -3036,7 +3030,7 @@ int gdbserver_start(const char *device)
mon_chr = s->mon_chr;
memset(s, 0, sizeof(GDBState));
}
- s->c_cpu = first_cpu->env_ptr;
+ s->c_cpu = first_cpu;
s->g_cpu = first_cpu->env_ptr;
s->chr = chr;
s->state = chr ? RS_IDLE : RS_INACTIVE;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 14/42] gdbstub: Change gdb_{read, write}_register() argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (12 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 13/42] gdbstub: Change GDBState::c_cpu " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 15/42] cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook Andreas Färber
` (28 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Use CPUState::env_ptr for now.
Prepares for changing GDBState::g_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index a8fafe2..cee9c13 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1866,8 +1866,9 @@ static const char *get_feature_xml(const char *p, const char **newp)
}
#endif
-static int gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int reg)
+static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
+ CPUArchState *env = cpu->env_ptr;
GDBRegisterState *r;
if (reg < NUM_CORE_REGS)
@@ -1881,8 +1882,9 @@ static int gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int reg)
return 0;
}
-static int gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int reg)
+static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
+ CPUArchState *env = cpu->env_ptr;
GDBRegisterState *r;
if (reg < NUM_CORE_REGS)
@@ -2210,7 +2212,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
#endif
len = 0;
for (addr = 0; addr < num_g_regs; addr++) {
- reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
+ reg_size = gdb_read_register(ENV_GET_CPU(s->g_cpu),
+ mem_buf + len, addr);
len += reg_size;
}
memtohex(buf, mem_buf, len);
@@ -2225,7 +2228,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
len = strlen(p) / 2;
hextomem((uint8_t *)registers, p, len);
for (addr = 0; addr < num_g_regs && len > 0; addr++) {
- reg_size = gdb_write_register(s->g_cpu, registers, addr);
+ reg_size = gdb_write_register(ENV_GET_CPU(s->g_cpu), registers,
+ addr);
len -= reg_size;
registers += reg_size;
}
@@ -2264,7 +2268,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
if (!gdb_has_xml)
goto unknown_command;
addr = strtoull(p, (char **)&p, 16);
- reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
+ reg_size = gdb_read_register(ENV_GET_CPU(s->g_cpu), mem_buf, addr);
if (reg_size) {
memtohex(buf, mem_buf, reg_size);
put_packet(s, buf);
@@ -2280,7 +2284,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
p++;
reg_size = strlen(p) / 2;
hextomem(mem_buf, p, reg_size);
- gdb_write_register(s->g_cpu, mem_buf, addr);
+ gdb_write_register(ENV_GET_CPU(s->g_cpu), mem_buf, addr);
put_packet(s, "OK");
break;
case 'Z':
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 15/42] cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (13 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 14/42] gdbstub: Change gdb_{read, write}_register() argument " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] " Andreas Färber
` (27 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf,
Blue Swirl, Max Filippov, Michael Walle, open list:PowerPC,
Paul Brook, Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helpers
cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
Prepares for changing cpu_memory_rw_debug() argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 20 ++++++------
hw/i386/kvmvapic.c | 6 ++--
hw/xtensa/xtensa_lx60.c | 8 +++--
hw/xtensa/xtensa_sim.c | 10 +++---
include/exec/cpu-all.h | 5 ---
include/qom/cpu.h | 74 +++++++++++++--------------------------------
target-alpha/cpu-qom.h | 1 +
target-alpha/cpu.c | 7 +++--
target-alpha/helper.c | 5 +--
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 5 ++-
target-arm/helper.c | 8 +++--
target-cris/cpu-qom.h | 2 ++
target-cris/cpu.c | 3 ++
target-cris/helper.c | 7 +++--
target-i386/cpu-qom.h | 2 ++
target-i386/cpu.c | 3 +-
target-i386/helper.c | 4 ++-
target-lm32/cpu-qom.h | 1 +
target-lm32/cpu.c | 5 ++-
target-lm32/helper.c | 6 ++--
target-m68k/cpu-qom.h | 1 +
target-m68k/cpu.c | 3 ++
target-m68k/helper.c | 2 +-
target-microblaze/cpu-qom.h | 1 +
target-microblaze/cpu.c | 5 ++-
target-microblaze/helper.c | 4 ++-
target-mips/cpu-qom.h | 1 +
target-mips/cpu.c | 5 ++-
target-mips/helper.c | 7 +++--
target-moxie/cpu.c | 5 ++-
target-moxie/cpu.h | 1 +
target-moxie/helper.c | 11 +++----
target-openrisc/cpu.c | 5 ++-
target-openrisc/cpu.h | 1 +
target-openrisc/mmu.c | 5 ++-
target-ppc/cpu-qom.h | 1 +
target-ppc/mmu_helper.c | 4 ++-
target-ppc/translate_init.c | 3 ++
target-s390x/cpu-qom.h | 1 +
target-s390x/cpu.c | 3 ++
target-s390x/helper.c | 5 +--
target-sh4/cpu-qom.h | 1 +
target-sh4/cpu.c | 3 ++
target-sh4/helper.c | 5 +--
target-sparc/cpu-qom.h | 1 +
target-sparc/cpu.c | 5 ++-
target-sparc/mmu_helper.c | 11 ++++---
target-unicore32/cpu-qom.h | 1 +
target-unicore32/cpu.c | 3 ++
target-unicore32/softmmu.c | 7 +++--
target-xtensa/cpu-qom.h | 1 +
target-xtensa/cpu.c | 3 ++
target-xtensa/helper.c | 7 +++--
target-xtensa/xtensa-semi.c | 4 +--
55 files changed, 182 insertions(+), 128 deletions(-)
diff --git a/exec.c b/exec.c
index 4c9e921..a768aea 100644
--- a/exec.c
+++ b/exec.c
@@ -415,14 +415,14 @@ void cpu_exec_init(CPUArchState *env)
#if defined(TARGET_HAS_ICE)
#if defined(CONFIG_USER_ONLY)
-static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
+static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
-static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
+static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
- tb_invalidate_phys_addr(cpu_get_phys_page_debug(env, pc) |
+ tb_invalidate_phys_addr(cpu_get_phys_page_debug(cpu, pc) |
(pc & ~TARGET_PAGE_MASK));
}
#endif
@@ -525,15 +525,17 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
- if (flags & BP_GDB)
+ if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
- else
+ } else {
QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
+ }
- breakpoint_invalidate(env, pc);
+ breakpoint_invalidate(ENV_GET_CPU(env), pc);
- if (breakpoint)
+ if (breakpoint) {
*breakpoint = bp;
+ }
return 0;
#else
return -ENOSYS;
@@ -564,7 +566,7 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
#if defined(TARGET_HAS_ICE)
QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
- breakpoint_invalidate(env, breakpoint->pc);
+ breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc);
g_free(breakpoint);
#endif
@@ -2581,7 +2583,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
- phys_addr = cpu_get_phys_page_debug(env, page);
+ phys_addr = cpu_get_phys_page_debug(ENV_GET_CPU(env), page);
/* if no physical page mapped, return an error */
if (phys_addr == -1)
return -1;
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index ccd089a..224601f 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -146,6 +146,7 @@ static void update_guest_rom_state(VAPICROMState *s)
static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
hwaddr paddr;
target_ulong addr;
@@ -158,7 +159,7 @@ static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
* virtual address space for the APIC mapping.
*/
for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
- paddr = cpu_get_phys_page_debug(env, addr);
+ paddr = cpu_get_phys_page_debug(cs, addr);
if (paddr != APIC_DEFAULT_ADDRESS) {
continue;
}
@@ -271,6 +272,7 @@ instruction_ok:
static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
hwaddr paddr;
uint32_t rom_state_vaddr;
uint32_t pos, patch, offset;
@@ -287,7 +289,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong i
/* find out virtual address of the ROM */
rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
- paddr = cpu_get_phys_page_debug(env, rom_state_vaddr);
+ paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr);
if (paddr == -1) {
return -1;
}
diff --git a/hw/xtensa/xtensa_lx60.c b/hw/xtensa/xtensa_lx60.c
index 075daf1..1138666 100644
--- a/hw/xtensa/xtensa_lx60.c
+++ b/hw/xtensa/xtensa_lx60.c
@@ -144,9 +144,11 @@ static void lx60_net_init(MemoryRegion *address_space,
memory_region_add_subregion(address_space, buffers, ram);
}
-static uint64_t translate_phys_addr(void *env, uint64_t addr)
+static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
- return cpu_get_phys_page_debug(env, addr);
+ XtensaCPU *cpu = opaque;
+
+ return cpu_get_phys_page_debug(CPU(cpu), addr);
}
static void lx60_reset(void *opaque)
@@ -252,7 +254,7 @@ static void lx_init(const LxBoardDesc *board, QEMUMachineInitArgs *args)
}
uint64_t elf_entry;
uint64_t elf_lowaddr;
- int success = load_elf(kernel_filename, translate_phys_addr, env,
+ int success = load_elf(kernel_filename, translate_phys_addr, cpu,
&elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0);
if (success > 0) {
env->pc = elf_entry;
diff --git a/hw/xtensa/xtensa_sim.c b/hw/xtensa/xtensa_sim.c
index a88707e..ea91162 100644
--- a/hw/xtensa/xtensa_sim.c
+++ b/hw/xtensa/xtensa_sim.c
@@ -32,9 +32,11 @@
#include "exec/memory.h"
#include "exec/address-spaces.h"
-static uint64_t translate_phys_addr(void *env, uint64_t addr)
+static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
- return cpu_get_phys_page_debug(env, addr);
+ XtensaCPU *cpu = opaque;
+
+ return cpu_get_phys_page_debug(CPU(cpu), addr);
}
static void sim_reset(void *opaque)
@@ -88,10 +90,10 @@ static void xtensa_sim_init(QEMUMachineInitArgs *args)
uint64_t elf_entry;
uint64_t elf_lowaddr;
#ifdef TARGET_WORDS_BIGENDIAN
- int success = load_elf(kernel_filename, translate_phys_addr, env,
+ int success = load_elf(kernel_filename, translate_phys_addr, cpu,
&elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
#else
- int success = load_elf(kernel_filename, translate_phys_addr, env,
+ int success = load_elf(kernel_filename, translate_phys_addr, cpu,
&elf_entry, &elf_lowaddr, NULL, 0, ELF_MACHINE, 0);
#endif
if (success > 0) {
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 1f3c002..16eeb7a 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -430,11 +430,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
#if !defined(CONFIG_USER_ONLY)
-/* Return the physical page corresponding to a virtual one. Use it
- only for debugging because no protection checks are done. Return -1
- if no page found. */
-hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
-
/* memory API */
extern int phys_ram_fd;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 641be1c..fe82822 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -74,6 +74,7 @@ struct TranslationBlock;
* @set_pc: Callback for setting the Program Counter register.
* @synchronize_from_tb: Callback for synchronizing state from a TCG
* #TranslationBlock.
+ * @get_phys_page_debug: Callback for obtaining a physical address.
* @vmsd: State description for migration.
*
* Represents a CPU family or model.
@@ -99,6 +100,7 @@ typedef struct CPUClass {
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
const struct VMStateDescription *vmsd;
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
@@ -276,6 +278,25 @@ void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
+#ifndef CONFIG_USER_ONLY
+/**
+ * cpu_get_phys_page_debug:
+ * @cpu: The CPU to obtain the physical page address for.
+ * @addr: The virtual address.
+ *
+ * Obtains the physical page corresponding to a virtual one.
+ * Use it only for debugging because no protection checks are done.
+ *
+ * Returns: Corresponding physical page address or -1 if no page found.
+ */
+static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ return cc->get_phys_page_debug(cpu, addr);
+}
+#endif
+
/**
* cpu_reset:
* @cpu: The CPU whose state is to be reset.
@@ -294,59 +315,6 @@ void cpu_reset(CPUState *cpu);
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
/**
- * cpu_class_set_vmsd:
- * @cc: CPU class
- * @value: Value to set. Unused for %CONFIG_USER_ONLY.
- *
- * Sets #VMStateDescription for @cc.
- *
- * The @value argument is intentionally discarded for the non-softmmu targets
- * to avoid linker errors or excessive preprocessor usage. If this behavior
- * is undesired, you should assign #CPUClass.vmsd directly instead.
- */
-#ifndef CONFIG_USER_ONLY
-static inline void cpu_class_set_vmsd(CPUClass *cc,
- const struct VMStateDescription *value)
-{
- cc->vmsd = value;
-}
-#else
-#define cpu_class_set_vmsd(cc, value) ((cc)->vmsd = NULL)
-#endif
-
-#ifndef CONFIG_USER_ONLY
-static inline void cpu_class_set_do_unassigned_access(CPUClass *cc,
- CPUUnassignedAccess value)
-{
- cc->do_unassigned_access = value;
-}
-#else
-#define cpu_class_set_do_unassigned_access(cc, value) \
- ((cc)->do_unassigned_access = NULL)
-#endif
-
-/**
- * device_class_set_vmsd:
- * @dc: Device class
- * @value: Value to set. Unused for %CONFIG_USER_ONLY.
- *
- * Sets #VMStateDescription for @dc.
- *
- * The @value argument is intentionally discarded for the non-softmmu targets
- * to avoid linker errors or excessive preprocessor usage. If this behavior
- * is undesired, you should assign #DeviceClass.vmsd directly instead.
- */
-#ifndef CONFIG_USER_ONLY
-static inline void device_class_set_vmsd(DeviceClass *dc,
- const struct VMStateDescription *value)
-{
- dc->vmsd = value;
-}
-#else
-#define device_class_set_vmsd(dc, value) ((dc)->vmsd = NULL)
-#endif
-
-/**
* qemu_cpu_has_work:
* @cpu: The vCPU to check.
*
diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h
index 60125b1..b2eeba3 100644
--- a/target-alpha/cpu-qom.h
+++ b/target-alpha/cpu-qom.h
@@ -81,5 +81,6 @@ extern const struct VMStateDescription vmstate_alpha_cpu;
void alpha_cpu_do_interrupt(CPUState *cpu);
void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 09bb7a8..c8c8c2c 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -270,9 +270,12 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->do_interrupt = alpha_cpu_do_interrupt;
cc->dump_state = alpha_cpu_dump_state;
- cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access);
cc->set_pc = alpha_cpu_set_pc;
- device_class_set_vmsd(dc, &vmstate_alpha_cpu);
+#ifndef CONFIG_USER_ONLY
+ cc->do_unassigned_access = alpha_cpu_unassigned_access;
+ cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_alpha_cpu;
+#endif
}
static const TypeInfo alpha_cpu_type_info = {
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index ff57dd6..fc61bb0 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -315,12 +315,13 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
return ret;
}
-hwaddr cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr)
+hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
target_ulong phys;
int prot, fail;
- fail = get_physical_address(env, addr, 0, 0, &phys, &prot);
+ fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot);
return (fail >= 0 ? -1 : phys);
}
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 48ba605..02162c9 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -147,4 +147,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu);
void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4809fd0..90f6455 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -819,7 +819,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_cpu_do_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
- cpu_class_set_vmsd(cc, &vmstate_arm_cpu);
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
+ cc->vmsd = &vmstate_arm_cpu;
+#endif
}
static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5f639fd..2a2bb83 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2749,17 +2749,19 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
return 1;
}
-hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
+hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ ARMCPU *cpu = ARM_CPU(cs);
hwaddr phys_addr;
target_ulong page_size;
int prot;
int ret;
- ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
+ ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
- if (ret != 0)
+ if (ret != 0) {
return -1;
+ }
return phys_addr;
}
diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
index af7d14d..d7baf07 100644
--- a/target-cris/cpu-qom.h
+++ b/target-cris/cpu-qom.h
@@ -79,4 +79,6 @@ void crisv10_cpu_do_interrupt(CPUState *cpu);
void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
#endif
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index b72fd98..ba095e7 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -255,6 +255,9 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = cris_cpu_do_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
+#endif
}
static const TypeInfo cris_cpu_type_info = {
diff --git a/target-cris/helper.c b/target-cris/helper.c
index aba7537..d274b38 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -255,16 +255,17 @@ void cris_cpu_do_interrupt(CPUState *cs)
env->pregs[PR_ERP]);
}
-hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
+hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
uint32_t phy = addr;
struct cris_mmu_result res;
int miss;
- miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
+ miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
/* If D TLB misses, try I TLB. */
if (miss) {
- miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
+ miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
}
if (!miss) {
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 7e55e5f..d928562 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -104,4 +104,6 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b57ea4b..cd350cb 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2542,12 +2542,13 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
+ cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
+ cc->vmsd = &vmstate_x86_cpu;
#endif
- cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
}
static const TypeInfo x86_cpu_type_info = {
diff --git a/target-i386/helper.c b/target-i386/helper.c
index d6f43d7..2745292 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -884,8 +884,10 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
return 1;
}
-hwaddr cpu_get_phys_page_debug(CPUX86State *env, target_ulong addr)
+hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
target_ulong pde_addr, pte_addr;
uint64_t pte;
hwaddr paddr;
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index e3bb619..9e27329 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -78,5 +78,6 @@ extern const struct VMStateDescription vmstate_lm32_cpu;
void lm32_cpu_do_interrupt(CPUState *cpu);
void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 8aa28b5..ce55e48 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -87,7 +87,10 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = lm32_cpu_do_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
- cpu_class_set_vmsd(cc, &vmstate_lm32_cpu);
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
+ cc->vmsd = &vmstate_lm32_cpu;
+#endif
}
static const TypeInfo lm32_cpu_type_info = {
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 615b44e..15bc615 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -37,10 +37,12 @@ int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
return 0;
}
-hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
+hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ LM32CPU *cpu = LM32_CPU(cs);
+
addr &= TARGET_PAGE_MASK;
- if (env->flags & LM32_FLAG_IGNORE_MSB) {
+ if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
return addr & 0x7fffffff;
} else {
return addr;
diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h
index 858bf30..7115707 100644
--- a/target-m68k/cpu-qom.h
+++ b/target-m68k/cpu-qom.h
@@ -73,5 +73,6 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
void m68k_cpu_do_interrupt(CPUState *cpu);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 43011e7..988f476 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -190,6 +190,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->do_interrupt = m68k_cpu_do_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
+#endif
dc->vmsd = &vmstate_m68k_cpu;
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 54fa419..dcadfab 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -290,7 +290,7 @@ int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
/* MMU */
/* TODO: This will need fixing once the MMU is implemented. */
-hwaddr cpu_get_phys_page_debug(CPUM68KState *env, target_ulong addr)
+hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
return addr;
}
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index ec2b989..1318a36 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -74,5 +74,6 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
void mb_cpu_do_interrupt(CPUState *cs);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0a9bcfa..9f10c8c 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -140,8 +140,11 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = mb_cpu_do_interrupt;
cc->dump_state = mb_cpu_dump_state;
- cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access);
cc->set_pc = mb_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->do_unassigned_access = mb_cpu_unassigned_access;
+ cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
+#endif
dc->vmsd = &vmstate_mb_cpu;
dc->props = mb_properties;
}
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index c6c96d4..4fa9ce9 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -265,8 +265,10 @@ void mb_cpu_do_interrupt(CPUState *cs)
}
}
-hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
+hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
target_ulong vaddr, paddr = 0;
struct microblaze_mmu_lookup lu;
unsigned int hit;
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h
index 654744a..7c8e616 100644
--- a/target-mips/cpu-qom.h
+++ b/target-mips/cpu-qom.h
@@ -77,5 +77,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
void mips_cpu_do_interrupt(CPUState *cpu);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 1581cd9..4834c86 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -98,9 +98,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
- cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access);
cc->set_pc = mips_cpu_set_pc;
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
+#ifndef CONFIG_USER_ONLY
+ cc->do_unassigned_access = mips_cpu_unassigned_access;
+ cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
+#endif
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 6983b92..6feef7b 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -254,13 +254,16 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
}
#if !defined(CONFIG_USER_ONLY)
-hwaddr cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
+hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
hwaddr phys_addr;
int prot;
- if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
+ if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
+ ACCESS_INT) != 0) {
return -1;
+ }
return phys_addr;
}
#endif
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 91f6197..6550be5 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -101,7 +101,10 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
- cpu_class_set_vmsd(cc, &vmstate_moxie_cpu);
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
+ cc->vmsd = &vmstate_moxie_cpu;
+#endif
}
static void moxielite_initfn(Object *obj)
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index d5030a4..5ce14b5 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -118,6 +118,7 @@ int cpu_moxie_exec(CPUMoxieState *s);
void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr moxie_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void moxie_translate_init(void);
int cpu_moxie_signal_handler(int host_signum, void *pinfo,
void *puc);
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index ea0788f..b12e4ff 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -118,11 +118,6 @@ int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
return 1;
}
-hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
-{
- return addr;
-}
-
#else /* !CONFIG_USER_ONLY */
int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
@@ -162,12 +157,14 @@ void moxie_cpu_do_interrupt(CPUState *cs)
}
}
-hwaddr cpu_get_phys_page_debug(CPUMoxieState *env, target_ulong addr)
+hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ MoxieCPU *cpu = MOXIE_CPU(cs);
uint32_t phy = addr;
MoxieMMUResult res;
int miss;
- miss = moxie_mmu_translate(&res, env, addr, 0, 0);
+
+ miss = moxie_mmu_translate(&res, &cpu->env, addr, 0, 0);
if (!miss) {
phy = res.phy;
}
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 27ee9f4..3da5a7a 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -154,7 +154,10 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = openrisc_cpu_do_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
- device_class_set_vmsd(dc, &vmstate_openrisc_cpu);
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_openrisc_cpu;
+#endif
}
static void cpu_register(const OpenRISCCPUInfo *info)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 82bfd03..3ddb767 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -349,6 +349,7 @@ int cpu_openrisc_exec(CPUOpenRISCState *s);
void openrisc_cpu_do_interrupt(CPUState *cpu);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void openrisc_translate_init(void);
int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
target_ulong address,
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index d354e1f..57f5616 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -219,12 +219,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
#endif
#ifndef CONFIG_USER_ONLY
-hwaddr cpu_get_phys_page_debug(CPUOpenRISCState *env,
- target_ulong addr)
+hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
hwaddr phys_addr;
int prot;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
return -1;
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 7132599..3341c51 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -105,5 +105,6 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 77102c4..5dd4e05 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1409,8 +1409,10 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
return ret;
}
-hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
+hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
mmu_ctx_t ctx;
switch (env->mmu_model) {
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index ec47bc8..82fc463 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8298,6 +8298,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
+#endif
}
static const TypeInfo ppc_cpu_type_info = {
diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h
index 4c091e3..a4fe8fb 100644
--- a/target-s390x/cpu-qom.h
+++ b/target-s390x/cpu-qom.h
@@ -74,5 +74,6 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
void s390_cpu_do_interrupt(CPUState *cpu);
void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
+hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index fe3cd8e..cb89d1a 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -173,6 +173,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = s390_cpu_do_interrupt;
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
+#endif
dc->vmsd = &vmstate_s390_cpu;
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index b425054..61abfd7 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -417,9 +417,10 @@ int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
return 0;
}
-hwaddr cpu_get_phys_page_debug(CPUS390XState *env,
- target_ulong vaddr)
+hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
target_ulong raddr;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
int old_exc = env->exception_index;
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index c229a9a..7c9160b 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -86,5 +86,6 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
void superh_cpu_do_interrupt(CPUState *cpu);
void superh_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 03dedc1..51a7757 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -286,6 +286,9 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+#endif
dc->vmsd = &vmstate_sh_cpu;
}
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index cb6a2d2..9ac2825 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -508,12 +508,13 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
return 0;
}
-hwaddr cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
+hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
target_ulong physical;
int prot;
- get_physical_address(env, &physical, &prot, addr, 0, 0);
+ get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
return physical;
}
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
index 033a5b5..39d975b 100644
--- a/target-sparc/cpu-qom.h
+++ b/target-sparc/cpu-qom.h
@@ -78,5 +78,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
void sparc_cpu_do_interrupt(CPUState *cpu);
void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index a2deba5..12494cc 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -782,9 +782,12 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->dump_state = sparc_cpu_dump_state;
- cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access);
cc->set_pc = sparc_cpu_set_pc;
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
+#ifndef CONFIG_USER_ONLY
+ cc->do_unassigned_access = sparc_cpu_unassigned_access;
+ cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
+#endif
}
static const TypeInfo sparc_cpu_type_info = {
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 740cbe8..846d129 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -310,6 +310,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
target_ulong va, va1, va2;
unsigned int n, m, o;
hwaddr pde_ptr, pa;
@@ -322,20 +323,20 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
- pa = cpu_get_phys_page_debug(env, va);
+ pa = cpu_get_phys_page_debug(cs, va);
(*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
pde = mmu_probe(env, va1, 1);
if (pde) {
- pa = cpu_get_phys_page_debug(env, va1);
+ pa = cpu_get_phys_page_debug(cs, va1);
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
va1, pa, pde);
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
pde = mmu_probe(env, va2, 0);
if (pde) {
- pa = cpu_get_phys_page_debug(env, va2);
+ pa = cpu_get_phys_page_debug(cs, va2);
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
TARGET_FMT_plx " PTE: "
TARGET_FMT_lx "\n",
@@ -833,8 +834,10 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
}
#endif
-hwaddr cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
+hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
hwaddr phys_addr;
int mmu_idx = cpu_mmu_index(env);
MemoryRegionSection section;
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index 350d480..f727760 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -63,5 +63,6 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
void uc32_cpu_do_interrupt(CPUState *cpu);
void uc32_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 79f2292..46813e5 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -139,6 +139,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = uc32_cpu_do_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
+#endif
dc->vmsd = &vmstate_uc32_cpu;
}
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index eadaeb1..1e13a85 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -261,9 +261,10 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
return ret;
}
-hwaddr cpu_get_phys_page_debug(CPUUniCore32State *env,
- target_ulong addr)
+hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- cpu_abort(env, "%s not supported yet\n", __func__);
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+
+ cpu_abort(&cpu->env, "%s not supported yet\n", __func__);
return addr;
}
diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index 31e7498..b9896f2 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -83,5 +83,6 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
void xtensa_cpu_do_interrupt(CPUState *cpu);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
+hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index e3d742a..d2bcfc6 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -108,6 +108,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = xtensa_cpu_do_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
+#endif
dc->vmsd = &vmstate_xtensa_cpu;
}
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 6f613c66..de6cc3b 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -108,17 +108,18 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
}
}
-hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
+hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
uint32_t paddr;
uint32_t page_size;
unsigned access;
- if (xtensa_get_physical_addr(env, false, addr, 0, 0,
+ if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
&paddr, &page_size, &access) == 0) {
return paddr;
}
- if (xtensa_get_physical_addr(env, false, addr, 2, 0,
+ if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
&paddr, &page_size, &access) == 0) {
return paddr;
}
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
index 5fe0361..d9dd222 100644
--- a/target-xtensa/xtensa-semi.c
+++ b/target-xtensa/xtensa-semi.c
@@ -152,6 +152,7 @@ static uint32_t errno_h2g(int host_errno)
void HELPER(simcall)(CPUXtensaState *env)
{
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
uint32_t *regs = env->regs;
switch (regs[2]) {
@@ -169,8 +170,7 @@ void HELPER(simcall)(CPUXtensaState *env)
uint32_t len = regs[5];
while (len > 0) {
- hwaddr paddr =
- cpu_get_phys_page_debug(env, vaddr);
+ hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr);
uint32_t page_left =
TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
uint32_t io_sz = page_left < len ? page_left : len;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH qom-cpu v2 16/42] exec: Change cpu_memory_rw_debug() argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() Andreas Färber
` (41 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Andreas Färber, Luiz Capitulino, Paul Brook, Peter Maydell,
Gleb Natapov, Marcelo Tosatti, Blue Swirl, Max Filippov,
open list:X86
Propagate X86CPU in kvmvapic for simplicity.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpus.c | 4 +--
disas.c | 4 +--
exec.c | 6 ++--
gdbstub.c | 2 +-
hw/i386/kvmvapic.c | 72 +++++++++++++++++++++++----------------------
include/exec/cpu-all.h | 3 +-
include/exec/softmmu-semi.h | 18 +++++++-----
monitor.c | 2 +-
target-arm/arm-semi.c | 2 +-
target-i386/helper.c | 8 +++--
target-i386/kvm.c | 14 ++++-----
target-sparc/mmu_helper.c | 5 ++--
target-xtensa/xtensa-semi.c | 10 +++----
13 files changed, 77 insertions(+), 73 deletions(-)
diff --git a/cpus.c b/cpus.c
index 8a4f395..1ce6816 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1247,7 +1247,6 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
{
FILE *f;
uint32_t l;
- CPUArchState *env;
CPUState *cpu;
uint8_t buf[1024];
@@ -1261,7 +1260,6 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
"a CPU number");
return;
}
- env = cpu->env_ptr;
f = fopen(filename, "wb");
if (!f) {
@@ -1273,7 +1271,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
l = sizeof(buf);
if (l > size)
l = size;
- cpu_memory_rw_debug(env, addr, buf, l, 0);
+ cpu_memory_rw_debug(cpu, addr, buf, l, 0);
if (fwrite(buf, 1, l, f) != l) {
error_set(errp, QERR_IO_ERROR);
goto exit;
diff --git a/disas.c b/disas.c
index e51127e..71007fb 100644
--- a/disas.c
+++ b/disas.c
@@ -39,7 +39,7 @@ target_read_memory (bfd_vma memaddr,
{
CPUDebug *s = container_of(info, CPUDebug, info);
- cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0);
return 0;
}
@@ -392,7 +392,7 @@ monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
if (monitor_disas_is_physical) {
cpu_physical_memory_read(memaddr, myaddr, length);
} else {
- cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0);
}
return 0;
}
diff --git a/exec.c b/exec.c
index a768aea..f3fe6e6 100644
--- a/exec.c
+++ b/exec.c
@@ -1840,7 +1840,7 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l, flags;
@@ -2574,7 +2574,7 @@ void stq_be_phys(hwaddr addr, uint64_t val)
}
/* virtual memory access for debug (includes writing to ROM) */
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
@@ -2583,7 +2583,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
- phys_addr = cpu_get_phys_page_debug(ENV_GET_CPU(env), page);
+ phys_addr = cpu_get_phys_page_debug(cpu, page);
/* if no physical page mapped, return an error */
if (phys_addr == -1)
return -1;
diff --git a/gdbstub.c b/gdbstub.c
index cee9c13..43ecc0d 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -46,7 +46,7 @@
static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
- return cpu_memory_rw_debug(env, addr, buf, len, is_write);
+ return cpu_memory_rw_debug(ENV_GET_CPU(env), addr, buf, len, is_write);
}
#else
/* target_memory_rw_debug() defined in cpu.h */
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 224601f..035d0fe 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -188,9 +188,10 @@ static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
modrm_reg(opcode[1]) == instr->modrm_reg);
}
-static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
+static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
target_ulong *pip, TPRAccess access)
{
+ CPUState *cs = CPU(cpu);
const TPRInstruction *instr;
target_ulong ip = *pip;
uint8_t opcode[2];
@@ -211,7 +212,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
* RSP, used by the patched instruction, is zero, so the guest gets a
* double fault and dies.
*/
- if (env->regs[R_ESP] == 0) {
+ if (cpu->env.regs[R_ESP] == 0) {
return -1;
}
@@ -226,7 +227,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
if (instr->access != access) {
continue;
}
- if (cpu_memory_rw_debug(env, ip - instr->length, opcode,
+ if (cpu_memory_rw_debug(cs, ip - instr->length, opcode,
sizeof(opcode), 0) < 0) {
return -1;
}
@@ -237,7 +238,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
}
return -1;
} else {
- if (cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0) < 0) {
+ if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) {
return -1;
}
for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
@@ -254,7 +255,7 @@ instruction_ok:
* Grab the virtual TPR address from the instruction
* and update the cached values.
*/
- if (cpu_memory_rw_debug(env, ip + instr->addr_offset,
+ if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
(void *)&real_tpr_addr,
sizeof(real_tpr_addr), 0) < 0) {
return -1;
@@ -334,8 +335,9 @@ static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong i
* cannot be accessed or is considered invalid. This also ensures that we are
* not patching the wrong guest.
*/
-static int get_kpcr_number(CPUX86State *env)
+static int get_kpcr_number(X86CPU *cpu)
{
+ CPUX86State *env = &cpu->env;
struct kpcr {
uint8_t fill1[0x1c];
uint32_t self;
@@ -343,7 +345,7 @@ static int get_kpcr_number(CPUX86State *env)
uint8_t number;
} QEMU_PACKED kpcr;
- if (cpu_memory_rw_debug(env, env->segs[R_FS].base,
+ if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
(void *)&kpcr, sizeof(kpcr), 0) < 0 ||
kpcr.self != env->segs[R_FS].base) {
return -1;
@@ -351,9 +353,9 @@ static int get_kpcr_number(CPUX86State *env)
return kpcr.number;
}
-static int vapic_enable(VAPICROMState *s, CPUX86State *env)
+static int vapic_enable(VAPICROMState *s, X86CPU *cpu)
{
- int cpu_number = get_kpcr_number(env);
+ int cpu_number = get_kpcr_number(cpu);
hwaddr vapic_paddr;
static const uint8_t enabled = 1;
@@ -364,26 +366,26 @@ static int vapic_enable(VAPICROMState *s, CPUX86State *env)
(((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
(void *)&enabled, sizeof(enabled), 1);
- apic_enable_vapic(env->apic_state, vapic_paddr);
+ apic_enable_vapic(cpu->env.apic_state, vapic_paddr);
s->state = VAPIC_ACTIVE;
return 0;
}
-static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
+static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte)
{
- cpu_memory_rw_debug(env, addr, &byte, 1, 1);
+ cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1);
}
-static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
+static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
uint32_t target)
{
uint32_t offset;
offset = cpu_to_le32(target - ip - 5);
- patch_byte(env, ip, 0xe8); /* call near */
- cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
+ patch_byte(cpu, ip, 0xe8); /* call near */
+ cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1);
}
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
@@ -411,32 +413,32 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
pause_all_vcpus();
- cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0);
+ cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0);
switch (opcode[0]) {
case 0x89: /* mov r32 to r/m32 */
- patch_byte(env, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */
- patch_call(s, env, ip + 1, handlers->set_tpr);
+ patch_byte(cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */
+ patch_call(s, cpu, ip + 1, handlers->set_tpr);
break;
case 0x8b: /* mov r/m32 to r32 */
- patch_byte(env, ip, 0x90);
- patch_call(s, env, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
+ patch_byte(cpu, ip, 0x90);
+ patch_call(s, cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
break;
case 0xa1: /* mov abs to eax */
- patch_call(s, env, ip, handlers->get_tpr[0]);
+ patch_call(s, cpu, ip, handlers->get_tpr[0]);
break;
case 0xa3: /* mov eax to abs */
- patch_call(s, env, ip, handlers->set_tpr_eax);
+ patch_call(s, cpu, ip, handlers->set_tpr_eax);
break;
case 0xc7: /* mov imm32, r/m32 (c7/0) */
- patch_byte(env, ip, 0x68); /* push imm32 */
- cpu_memory_rw_debug(env, ip + 6, (void *)&imm32, sizeof(imm32), 0);
- cpu_memory_rw_debug(env, ip + 1, (void *)&imm32, sizeof(imm32), 1);
- patch_call(s, env, ip + 5, handlers->set_tpr);
+ patch_byte(cpu, ip, 0x68); /* push imm32 */
+ cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0);
+ cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1);
+ patch_call(s, cpu, ip + 5, handlers->set_tpr);
break;
case 0xff: /* push r/m32 */
- patch_byte(env, ip, 0x50); /* push eax */
- patch_call(s, env, ip + 1, handlers->get_tpr_stack);
+ patch_byte(cpu, ip, 0x50); /* push eax */
+ patch_call(s, cpu, ip + 1, handlers->get_tpr_stack);
break;
default:
abort();
@@ -460,16 +462,16 @@ void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
cpu_synchronize_state(cs);
- if (evaluate_tpr_instruction(s, env, &ip, access) < 0) {
+ if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) {
if (s->state == VAPIC_ACTIVE) {
- vapic_enable(s, env);
+ vapic_enable(s, cpu);
}
return;
}
if (update_rom_mapping(s, env, ip) < 0) {
return;
}
- if (vapic_enable(s, env) < 0) {
+ if (vapic_enable(s, cpu) < 0) {
return;
}
patch_instruction(s, cpu, ip);
@@ -669,8 +671,8 @@ static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
* accurate.
*/
pause_all_vcpus();
- patch_byte(env, env->eip - 2, 0x66);
- patch_byte(env, env->eip - 1, 0x90);
+ patch_byte(cpu, env->eip - 2, 0x66);
+ patch_byte(cpu, env->eip - 1, 0x90);
resume_all_vcpus();
}
@@ -683,7 +685,7 @@ static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
if (find_real_tpr_addr(s, env) < 0) {
break;
}
- vapic_enable(s, env);
+ vapic_enable(s, cpu);
break;
default:
case 4:
@@ -725,7 +727,7 @@ static void do_vapic_enable(void *data)
VAPICROMState *s = data;
X86CPU *cpu = X86_CPU(first_cpu);
- vapic_enable(s, &cpu->env);
+ vapic_enable(s, cpu);
}
static int vapic_post_load(void *opaque, int version_id)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 16eeb7a..928e93a 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"
+#include "qom/cpu.h"
/* some important defines:
*
@@ -484,7 +485,7 @@ void qemu_mutex_lock_ramlist(void);
void qemu_mutex_unlock_ramlist(void);
#endif /* !CONFIG_USER_ONLY */
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write);
#endif /* CPU_ALL_H */
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 93798b9..8401f7d 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -13,14 +13,14 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, uint32_t addr)
{
uint32_t val;
- cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
return tswap32(val);
}
static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)
{
uint8_t val;
- cpu_memory_rw_debug(env, addr, &val, 1, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
return val;
}
@@ -31,7 +31,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)
static inline void softmmu_tput32(CPUArchState *env, uint32_t addr, uint32_t val)
{
val = tswap32(val);
- cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
}
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
#define put_user_ual(arg, p) put_user_u32(arg, p)
@@ -42,8 +42,9 @@ static void *softmmu_lock_user(CPUArchState *env, uint32_t addr, uint32_t len,
uint8_t *p;
/* TODO: Make this something that isn't fixed size. */
p = malloc(len);
- if (p && copy)
- cpu_memory_rw_debug(env, addr, p, len, 0);
+ if (p && copy) {
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ }
return p;
}
#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
@@ -58,7 +59,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)
return NULL;
}
do {
- cpu_memory_rw_debug(env, addr, &c, 1, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
addr++;
*(p++) = c;
} while (c);
@@ -68,8 +69,9 @@ static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)
static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
target_ulong len)
{
- if (len)
- cpu_memory_rw_debug(env, addr, p, len, 1);
+ if (len) {
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ }
free(p);
}
#define unlock_user(s, args, len) softmmu_unlock_user(env, s, args, len)
diff --git a/monitor.c b/monitor.c
index 2ba7876..c0d0341 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1156,7 +1156,7 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize,
cpu_physical_memory_read(addr, buf, l);
} else {
env = mon_get_cpu();
- if (cpu_memory_rw_debug(env, addr, buf, l, 0) < 0) {
+ if (cpu_memory_rw_debug(ENV_GET_CPU(env), addr, buf, l, 0) < 0) {
monitor_printf(mon, " Cannot access memory\n");
break;
}
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 4ecea65..ee469c4 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -161,7 +161,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
- cpu_memory_rw_debug(env, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
+ cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
env->regs[0] = be32_to_cpu(size);
#ifdef CONFIG_USER_ONLY
((TaskState *)env->opaque)->swi_errno = err;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2745292..bf3e2ac 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -363,7 +363,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "Code=");
for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
- if (cpu_memory_rw_debug(env, base - offs + i, &code, 1, 0) == 0) {
+ if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
snprintf(codestr, sizeof(codestr), "%02x", code);
} else {
snprintf(codestr, sizeof(codestr), "??");
@@ -1260,6 +1260,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
target_ulong *base, unsigned int *limit,
unsigned int *flags)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
SegmentCache *dt;
target_ulong ptr;
uint32_t e1, e2;
@@ -1272,8 +1274,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
index = selector & ~7;
ptr = dt->base + index;
if ((index + 7) > dt->limit
- || cpu_memory_rw_debug(env, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
- || cpu_memory_rw_debug(env, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
+ || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
+ || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
return 0;
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 1ec7b5b..b689b22 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1935,25 +1935,23 @@ static int kvm_handle_tpr_access(X86CPU *cpu)
return 1;
}
-int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
+int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
- CPUX86State *env = &X86_CPU(cpu)->env;
static const uint8_t int3 = 0xcc;
- if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
- cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
+ cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
return -EINVAL;
}
return 0;
}
-int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
+int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
- CPUX86State *env = &X86_CPU(cpu)->env;
uint8_t int3;
- if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
- cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
+ cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
return -EINVAL;
}
return 0;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 846d129..45d08e4 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -356,6 +356,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
int i;
int len1;
int cwp = env->cwp;
@@ -390,7 +391,7 @@ int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
/* Handle access before this window. */
if (addr < fp) {
len1 = fp - addr;
- if (cpu_memory_rw_debug(env, addr, buf, len1, is_write) != 0) {
+ if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != 0) {
return -1;
}
addr += len1;
@@ -426,7 +427,7 @@ int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
}
}
}
- return cpu_memory_rw_debug(env, addr, buf, len, is_write);
+ return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
}
#else /* !TARGET_SPARC64 */
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
index d9dd222..424253d 100644
--- a/target-xtensa/xtensa-semi.c
+++ b/target-xtensa/xtensa-semi.c
@@ -204,8 +204,8 @@ void HELPER(simcall)(CPUXtensaState *env)
int i;
for (i = 0; i < ARRAY_SIZE(name); ++i) {
- rc = cpu_memory_rw_debug(
- env, regs[3] + i, (uint8_t *)name + i, 1, 0);
+ rc = cpu_memory_rw_debug(cs, regs[3] + i,
+ (uint8_t *)name + i, 1, 0);
if (rc != 0 || name[i] == 0) {
break;
}
@@ -249,7 +249,7 @@ void HELPER(simcall)(CPUXtensaState *env)
FD_SET(fd, &fdset);
if (target_tv) {
- cpu_memory_rw_debug(env, target_tv,
+ cpu_memory_rw_debug(cs, target_tv,
(uint8_t *)target_tvv, sizeof(target_tvv), 0);
tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
@@ -284,8 +284,8 @@ void HELPER(simcall)(CPUXtensaState *env)
};
argv.argptr[0] = tswap32(regs[3] + offsetof(struct Argv, text));
- cpu_memory_rw_debug(
- env, regs[3], (uint8_t *)&argv, sizeof(argv), 1);
+ cpu_memory_rw_debug(cs,
+ regs[3], (uint8_t *)&argv, sizeof(argv), 1);
}
break;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 16/42] exec: Change cpu_memory_rw_debug() argument to CPUState
@ 2013-07-07 18:26 ` Andreas Färber
0 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, open list:X86, Gleb Natapov, Marcelo Tosatti,
Luiz Capitulino, Blue Swirl, Max Filippov, Paul Brook,
Andreas Färber
Propagate X86CPU in kvmvapic for simplicity.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpus.c | 4 +--
disas.c | 4 +--
exec.c | 6 ++--
gdbstub.c | 2 +-
hw/i386/kvmvapic.c | 72 +++++++++++++++++++++++----------------------
include/exec/cpu-all.h | 3 +-
include/exec/softmmu-semi.h | 18 +++++++-----
monitor.c | 2 +-
target-arm/arm-semi.c | 2 +-
target-i386/helper.c | 8 +++--
target-i386/kvm.c | 14 ++++-----
target-sparc/mmu_helper.c | 5 ++--
target-xtensa/xtensa-semi.c | 10 +++----
13 files changed, 77 insertions(+), 73 deletions(-)
diff --git a/cpus.c b/cpus.c
index 8a4f395..1ce6816 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1247,7 +1247,6 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
{
FILE *f;
uint32_t l;
- CPUArchState *env;
CPUState *cpu;
uint8_t buf[1024];
@@ -1261,7 +1260,6 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
"a CPU number");
return;
}
- env = cpu->env_ptr;
f = fopen(filename, "wb");
if (!f) {
@@ -1273,7 +1271,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
l = sizeof(buf);
if (l > size)
l = size;
- cpu_memory_rw_debug(env, addr, buf, l, 0);
+ cpu_memory_rw_debug(cpu, addr, buf, l, 0);
if (fwrite(buf, 1, l, f) != l) {
error_set(errp, QERR_IO_ERROR);
goto exit;
diff --git a/disas.c b/disas.c
index e51127e..71007fb 100644
--- a/disas.c
+++ b/disas.c
@@ -39,7 +39,7 @@ target_read_memory (bfd_vma memaddr,
{
CPUDebug *s = container_of(info, CPUDebug, info);
- cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0);
return 0;
}
@@ -392,7 +392,7 @@ monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
if (monitor_disas_is_physical) {
cpu_physical_memory_read(memaddr, myaddr, length);
} else {
- cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0);
}
return 0;
}
diff --git a/exec.c b/exec.c
index a768aea..f3fe6e6 100644
--- a/exec.c
+++ b/exec.c
@@ -1840,7 +1840,7 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l, flags;
@@ -2574,7 +2574,7 @@ void stq_be_phys(hwaddr addr, uint64_t val)
}
/* virtual memory access for debug (includes writing to ROM) */
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
@@ -2583,7 +2583,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
- phys_addr = cpu_get_phys_page_debug(ENV_GET_CPU(env), page);
+ phys_addr = cpu_get_phys_page_debug(cpu, page);
/* if no physical page mapped, return an error */
if (phys_addr == -1)
return -1;
diff --git a/gdbstub.c b/gdbstub.c
index cee9c13..43ecc0d 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -46,7 +46,7 @@
static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
- return cpu_memory_rw_debug(env, addr, buf, len, is_write);
+ return cpu_memory_rw_debug(ENV_GET_CPU(env), addr, buf, len, is_write);
}
#else
/* target_memory_rw_debug() defined in cpu.h */
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 224601f..035d0fe 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -188,9 +188,10 @@ static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
modrm_reg(opcode[1]) == instr->modrm_reg);
}
-static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
+static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
target_ulong *pip, TPRAccess access)
{
+ CPUState *cs = CPU(cpu);
const TPRInstruction *instr;
target_ulong ip = *pip;
uint8_t opcode[2];
@@ -211,7 +212,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
* RSP, used by the patched instruction, is zero, so the guest gets a
* double fault and dies.
*/
- if (env->regs[R_ESP] == 0) {
+ if (cpu->env.regs[R_ESP] == 0) {
return -1;
}
@@ -226,7 +227,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
if (instr->access != access) {
continue;
}
- if (cpu_memory_rw_debug(env, ip - instr->length, opcode,
+ if (cpu_memory_rw_debug(cs, ip - instr->length, opcode,
sizeof(opcode), 0) < 0) {
return -1;
}
@@ -237,7 +238,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
}
return -1;
} else {
- if (cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0) < 0) {
+ if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) {
return -1;
}
for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
@@ -254,7 +255,7 @@ instruction_ok:
* Grab the virtual TPR address from the instruction
* and update the cached values.
*/
- if (cpu_memory_rw_debug(env, ip + instr->addr_offset,
+ if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
(void *)&real_tpr_addr,
sizeof(real_tpr_addr), 0) < 0) {
return -1;
@@ -334,8 +335,9 @@ static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong i
* cannot be accessed or is considered invalid. This also ensures that we are
* not patching the wrong guest.
*/
-static int get_kpcr_number(CPUX86State *env)
+static int get_kpcr_number(X86CPU *cpu)
{
+ CPUX86State *env = &cpu->env;
struct kpcr {
uint8_t fill1[0x1c];
uint32_t self;
@@ -343,7 +345,7 @@ static int get_kpcr_number(CPUX86State *env)
uint8_t number;
} QEMU_PACKED kpcr;
- if (cpu_memory_rw_debug(env, env->segs[R_FS].base,
+ if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
(void *)&kpcr, sizeof(kpcr), 0) < 0 ||
kpcr.self != env->segs[R_FS].base) {
return -1;
@@ -351,9 +353,9 @@ static int get_kpcr_number(CPUX86State *env)
return kpcr.number;
}
-static int vapic_enable(VAPICROMState *s, CPUX86State *env)
+static int vapic_enable(VAPICROMState *s, X86CPU *cpu)
{
- int cpu_number = get_kpcr_number(env);
+ int cpu_number = get_kpcr_number(cpu);
hwaddr vapic_paddr;
static const uint8_t enabled = 1;
@@ -364,26 +366,26 @@ static int vapic_enable(VAPICROMState *s, CPUX86State *env)
(((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
(void *)&enabled, sizeof(enabled), 1);
- apic_enable_vapic(env->apic_state, vapic_paddr);
+ apic_enable_vapic(cpu->env.apic_state, vapic_paddr);
s->state = VAPIC_ACTIVE;
return 0;
}
-static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
+static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte)
{
- cpu_memory_rw_debug(env, addr, &byte, 1, 1);
+ cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1);
}
-static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
+static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
uint32_t target)
{
uint32_t offset;
offset = cpu_to_le32(target - ip - 5);
- patch_byte(env, ip, 0xe8); /* call near */
- cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
+ patch_byte(cpu, ip, 0xe8); /* call near */
+ cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1);
}
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
@@ -411,32 +413,32 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
pause_all_vcpus();
- cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0);
+ cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0);
switch (opcode[0]) {
case 0x89: /* mov r32 to r/m32 */
- patch_byte(env, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */
- patch_call(s, env, ip + 1, handlers->set_tpr);
+ patch_byte(cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */
+ patch_call(s, cpu, ip + 1, handlers->set_tpr);
break;
case 0x8b: /* mov r/m32 to r32 */
- patch_byte(env, ip, 0x90);
- patch_call(s, env, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
+ patch_byte(cpu, ip, 0x90);
+ patch_call(s, cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
break;
case 0xa1: /* mov abs to eax */
- patch_call(s, env, ip, handlers->get_tpr[0]);
+ patch_call(s, cpu, ip, handlers->get_tpr[0]);
break;
case 0xa3: /* mov eax to abs */
- patch_call(s, env, ip, handlers->set_tpr_eax);
+ patch_call(s, cpu, ip, handlers->set_tpr_eax);
break;
case 0xc7: /* mov imm32, r/m32 (c7/0) */
- patch_byte(env, ip, 0x68); /* push imm32 */
- cpu_memory_rw_debug(env, ip + 6, (void *)&imm32, sizeof(imm32), 0);
- cpu_memory_rw_debug(env, ip + 1, (void *)&imm32, sizeof(imm32), 1);
- patch_call(s, env, ip + 5, handlers->set_tpr);
+ patch_byte(cpu, ip, 0x68); /* push imm32 */
+ cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0);
+ cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1);
+ patch_call(s, cpu, ip + 5, handlers->set_tpr);
break;
case 0xff: /* push r/m32 */
- patch_byte(env, ip, 0x50); /* push eax */
- patch_call(s, env, ip + 1, handlers->get_tpr_stack);
+ patch_byte(cpu, ip, 0x50); /* push eax */
+ patch_call(s, cpu, ip + 1, handlers->get_tpr_stack);
break;
default:
abort();
@@ -460,16 +462,16 @@ void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
cpu_synchronize_state(cs);
- if (evaluate_tpr_instruction(s, env, &ip, access) < 0) {
+ if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) {
if (s->state == VAPIC_ACTIVE) {
- vapic_enable(s, env);
+ vapic_enable(s, cpu);
}
return;
}
if (update_rom_mapping(s, env, ip) < 0) {
return;
}
- if (vapic_enable(s, env) < 0) {
+ if (vapic_enable(s, cpu) < 0) {
return;
}
patch_instruction(s, cpu, ip);
@@ -669,8 +671,8 @@ static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
* accurate.
*/
pause_all_vcpus();
- patch_byte(env, env->eip - 2, 0x66);
- patch_byte(env, env->eip - 1, 0x90);
+ patch_byte(cpu, env->eip - 2, 0x66);
+ patch_byte(cpu, env->eip - 1, 0x90);
resume_all_vcpus();
}
@@ -683,7 +685,7 @@ static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
if (find_real_tpr_addr(s, env) < 0) {
break;
}
- vapic_enable(s, env);
+ vapic_enable(s, cpu);
break;
default:
case 4:
@@ -725,7 +727,7 @@ static void do_vapic_enable(void *data)
VAPICROMState *s = data;
X86CPU *cpu = X86_CPU(first_cpu);
- vapic_enable(s, &cpu->env);
+ vapic_enable(s, cpu);
}
static int vapic_post_load(void *opaque, int version_id)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 16eeb7a..928e93a 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"
+#include "qom/cpu.h"
/* some important defines:
*
@@ -484,7 +485,7 @@ void qemu_mutex_lock_ramlist(void);
void qemu_mutex_unlock_ramlist(void);
#endif /* !CONFIG_USER_ONLY */
-int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write);
#endif /* CPU_ALL_H */
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 93798b9..8401f7d 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -13,14 +13,14 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, uint32_t addr)
{
uint32_t val;
- cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
return tswap32(val);
}
static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)
{
uint8_t val;
- cpu_memory_rw_debug(env, addr, &val, 1, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
return val;
}
@@ -31,7 +31,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)
static inline void softmmu_tput32(CPUArchState *env, uint32_t addr, uint32_t val)
{
val = tswap32(val);
- cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
}
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
#define put_user_ual(arg, p) put_user_u32(arg, p)
@@ -42,8 +42,9 @@ static void *softmmu_lock_user(CPUArchState *env, uint32_t addr, uint32_t len,
uint8_t *p;
/* TODO: Make this something that isn't fixed size. */
p = malloc(len);
- if (p && copy)
- cpu_memory_rw_debug(env, addr, p, len, 0);
+ if (p && copy) {
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ }
return p;
}
#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
@@ -58,7 +59,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)
return NULL;
}
do {
- cpu_memory_rw_debug(env, addr, &c, 1, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
addr++;
*(p++) = c;
} while (c);
@@ -68,8 +69,9 @@ static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)
static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
target_ulong len)
{
- if (len)
- cpu_memory_rw_debug(env, addr, p, len, 1);
+ if (len) {
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ }
free(p);
}
#define unlock_user(s, args, len) softmmu_unlock_user(env, s, args, len)
diff --git a/monitor.c b/monitor.c
index 2ba7876..c0d0341 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1156,7 +1156,7 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize,
cpu_physical_memory_read(addr, buf, l);
} else {
env = mon_get_cpu();
- if (cpu_memory_rw_debug(env, addr, buf, l, 0) < 0) {
+ if (cpu_memory_rw_debug(ENV_GET_CPU(env), addr, buf, l, 0) < 0) {
monitor_printf(mon, " Cannot access memory\n");
break;
}
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 4ecea65..ee469c4 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -161,7 +161,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
- cpu_memory_rw_debug(env, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
+ cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
env->regs[0] = be32_to_cpu(size);
#ifdef CONFIG_USER_ONLY
((TaskState *)env->opaque)->swi_errno = err;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2745292..bf3e2ac 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -363,7 +363,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "Code=");
for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
- if (cpu_memory_rw_debug(env, base - offs + i, &code, 1, 0) == 0) {
+ if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
snprintf(codestr, sizeof(codestr), "%02x", code);
} else {
snprintf(codestr, sizeof(codestr), "??");
@@ -1260,6 +1260,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
target_ulong *base, unsigned int *limit,
unsigned int *flags)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
SegmentCache *dt;
target_ulong ptr;
uint32_t e1, e2;
@@ -1272,8 +1274,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
index = selector & ~7;
ptr = dt->base + index;
if ((index + 7) > dt->limit
- || cpu_memory_rw_debug(env, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
- || cpu_memory_rw_debug(env, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
+ || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
+ || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
return 0;
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 1ec7b5b..b689b22 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1935,25 +1935,23 @@ static int kvm_handle_tpr_access(X86CPU *cpu)
return 1;
}
-int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
+int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
- CPUX86State *env = &X86_CPU(cpu)->env;
static const uint8_t int3 = 0xcc;
- if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
- cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
+ cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
return -EINVAL;
}
return 0;
}
-int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
+int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
- CPUX86State *env = &X86_CPU(cpu)->env;
uint8_t int3;
- if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
- cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
+ cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
return -EINVAL;
}
return 0;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 846d129..45d08e4 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -356,6 +356,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
int i;
int len1;
int cwp = env->cwp;
@@ -390,7 +391,7 @@ int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
/* Handle access before this window. */
if (addr < fp) {
len1 = fp - addr;
- if (cpu_memory_rw_debug(env, addr, buf, len1, is_write) != 0) {
+ if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != 0) {
return -1;
}
addr += len1;
@@ -426,7 +427,7 @@ int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
}
}
}
- return cpu_memory_rw_debug(env, addr, buf, len, is_write);
+ return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
}
#else /* !TARGET_SPARC64 */
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
index d9dd222..424253d 100644
--- a/target-xtensa/xtensa-semi.c
+++ b/target-xtensa/xtensa-semi.c
@@ -204,8 +204,8 @@ void HELPER(simcall)(CPUXtensaState *env)
int i;
for (i = 0; i < ARRAY_SIZE(name); ++i) {
- rc = cpu_memory_rw_debug(
- env, regs[3] + i, (uint8_t *)name + i, 1, 0);
+ rc = cpu_memory_rw_debug(cs, regs[3] + i,
+ (uint8_t *)name + i, 1, 0);
if (rc != 0 || name[i] == 0) {
break;
}
@@ -249,7 +249,7 @@ void HELPER(simcall)(CPUXtensaState *env)
FD_SET(fd, &fdset);
if (target_tv) {
- cpu_memory_rw_debug(env, target_tv,
+ cpu_memory_rw_debug(cs, target_tv,
(uint8_t *)target_tvv, sizeof(target_tvv), 0);
tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
@@ -284,8 +284,8 @@ void HELPER(simcall)(CPUXtensaState *env)
};
argv.argptr[0] = tswap32(regs[3] + offsetof(struct Argv, text));
- cpu_memory_rw_debug(
- env, regs[3], (uint8_t *)&argv, sizeof(argv), 1);
+ cpu_memory_rw_debug(cs,
+ regs[3], (uint8_t *)&argv, sizeof(argv), 1);
}
break;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 17/42] cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (15 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 18/42] gdbstub: Change GDBState::g_cpu to CPUState Andreas Färber
` (25 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Andreas Färber
Make inline target_memory_rw_debug() always available and change its
argument to CPUState. Let it check if CPUClass::memory_rw_debug provides
a specialized callback and fall back to cpu_memory_rw_debug() otherwise.
The only overriding implementation is for 32-bit sparc.
This prepares for changing GDBState::g_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 21 ++++++++++++---------
include/qom/cpu.h | 3 +++
target-sparc/cpu.c | 3 +++
target-sparc/cpu.h | 5 ++---
target-sparc/mmu_helper.c | 8 +++++---
5 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 43ecc0d..fa44550 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -42,15 +42,16 @@
#include "sysemu/kvm.h"
#include "qemu/bitops.h"
-#ifndef TARGET_CPU_MEMORY_RW_DEBUG
-static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
- uint8_t *buf, int len, int is_write)
+static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
+ uint8_t *buf, int len, bool is_write)
{
- return cpu_memory_rw_debug(ENV_GET_CPU(env), addr, buf, len, is_write);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->memory_rw_debug) {
+ return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+ return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
}
-#else
-/* target_memory_rw_debug() defined in cpu.h */
-#endif
enum {
GDB_SIGNAL_0 = 0,
@@ -2240,7 +2241,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
if (*p == ',')
p++;
len = strtoull(p, NULL, 16);
- if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
+ if (target_memory_rw_debug(ENV_GET_CPU(s->g_cpu), addr, mem_buf, len,
+ false) != 0) {
put_packet (s, "E14");
} else {
memtohex(buf, mem_buf, len);
@@ -2255,7 +2257,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
if (*p == ':')
p++;
hextomem(mem_buf, p, len);
- if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) {
+ if (target_memory_rw_debug(ENV_GET_CPU(s->g_cpu), addr, mem_buf, len,
+ true) != 0) {
put_packet(s, "E14");
} else {
put_packet(s, "OK");
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index fe82822..ba4fde1 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -66,6 +66,7 @@ struct TranslationBlock;
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @do_interrupt: Callback for interrupt handling.
* @do_unassigned_access: Callback for unassigned access handling.
+ * @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
@@ -90,6 +91,8 @@ typedef struct CPUClass {
int reset_dump_flags;
void (*do_interrupt)(CPUState *cpu);
CPUUnassignedAccess do_unassigned_access;
+ int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
+ uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
void (*dump_statistics)(CPUState *cpu, FILE *f,
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 12494cc..d1d0339 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -782,6 +782,9 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->dump_state = sparc_cpu_dump_state;
+#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
+ cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
+#endif
cc->set_pc = sparc_cpu_set_pc;
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
#ifndef CONFIG_USER_ONLY
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 0f35a22..41194ec 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -526,9 +526,8 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
-int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
- uint8_t *buf, int len, int is_write);
-#define TARGET_CPU_MEMORY_RW_DEBUG
+int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
+ uint8_t *buf, int len, bool is_write);
#endif
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 45d08e4..ef12a0a 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -353,10 +353,12 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
* reads (and only reads) in stack frames as if windows were flushed. We assume
* that the sparc ABI is followed.
*/
-int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
- uint8_t *buf, int len, int is_write)
+int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
+ uint8_t *buf, int len, bool is_write)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+ target_ulong addr = address;
int i;
int len1;
int cwp = env->cwp;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 18/42] gdbstub: Change GDBState::g_cpu to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (16 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 17/42] cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug() Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 19/42] cpu: Move gdb_regs field from CPU_COMMON " Andreas Färber
` (24 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Use CPUState::env_ptr for Xtensa.
This removes the last user of CPUArchState from gdb_set_stop_cpu().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 35 +++++++++++++++--------------------
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index fa44550..7be2342 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -289,7 +289,7 @@ enum RSState {
};
typedef struct GDBState {
CPUState *c_cpu; /* current CPU for step/continue ops */
- CPUArchState *g_cpu; /* current CPU for other ops */
+ CPUState *g_cpu; /* current CPU for other ops */
CPUState *query_cpu; /* for q{f|s}ThreadInfo */
enum RSState state; /* parsing state */
char line_buf[MAX_PACKET_LENGTH];
@@ -2207,30 +2207,28 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
break;
case 'g':
- cpu_synchronize_state(ENV_GET_CPU(s->g_cpu));
+ cpu_synchronize_state(s->g_cpu);
#ifdef TARGET_XTENSA
- env = s->g_cpu;
+ env = s->g_cpu->env_ptr;
#endif
len = 0;
for (addr = 0; addr < num_g_regs; addr++) {
- reg_size = gdb_read_register(ENV_GET_CPU(s->g_cpu),
- mem_buf + len, addr);
+ reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
len += reg_size;
}
memtohex(buf, mem_buf, len);
put_packet(s, buf);
break;
case 'G':
- cpu_synchronize_state(ENV_GET_CPU(s->g_cpu));
+ cpu_synchronize_state(s->g_cpu);
#ifdef TARGET_XTENSA
- env = s->g_cpu;
+ env = s->g_cpu->env_ptr;
#endif
registers = mem_buf;
len = strlen(p) / 2;
hextomem((uint8_t *)registers, p, len);
for (addr = 0; addr < num_g_regs && len > 0; addr++) {
- reg_size = gdb_write_register(ENV_GET_CPU(s->g_cpu), registers,
- addr);
+ reg_size = gdb_write_register(s->g_cpu, registers, addr);
len -= reg_size;
registers += reg_size;
}
@@ -2241,8 +2239,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
if (*p == ',')
p++;
len = strtoull(p, NULL, 16);
- if (target_memory_rw_debug(ENV_GET_CPU(s->g_cpu), addr, mem_buf, len,
- false) != 0) {
+ if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, false) != 0) {
put_packet (s, "E14");
} else {
memtohex(buf, mem_buf, len);
@@ -2257,7 +2254,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
if (*p == ':')
p++;
hextomem(mem_buf, p, len);
- if (target_memory_rw_debug(ENV_GET_CPU(s->g_cpu), addr, mem_buf, len,
+ if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len,
true) != 0) {
put_packet(s, "E14");
} else {
@@ -2271,7 +2268,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
if (!gdb_has_xml)
goto unknown_command;
addr = strtoull(p, (char **)&p, 16);
- reg_size = gdb_read_register(ENV_GET_CPU(s->g_cpu), mem_buf, addr);
+ reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
if (reg_size) {
memtohex(buf, mem_buf, reg_size);
put_packet(s, buf);
@@ -2287,7 +2284,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
p++;
reg_size = strlen(p) / 2;
hextomem(mem_buf, p, reg_size);
- gdb_write_register(ENV_GET_CPU(s->g_cpu), mem_buf, addr);
+ gdb_write_register(s->g_cpu, mem_buf, addr);
put_packet(s, "OK");
break;
case 'Z':
@@ -2328,7 +2325,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
put_packet(s, "OK");
break;
case 'g':
- s->g_cpu = cpu->env_ptr;
+ s->g_cpu = cpu;
put_packet(s, "OK");
break;
default:
@@ -2494,10 +2491,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
void gdb_set_stop_cpu(CPUState *cpu)
{
- CPUArchState *env = cpu->env_ptr;
-
gdbserver_state->c_cpu = cpu;
- gdbserver_state->g_cpu = env;
+ gdbserver_state->g_cpu = cpu;
}
#ifndef CONFIG_USER_ONLY
@@ -2853,7 +2848,7 @@ static void gdb_accept(void)
s = g_malloc0(sizeof(GDBState));
s->c_cpu = first_cpu;
- s->g_cpu = first_cpu->env_ptr;
+ s->g_cpu = first_cpu;
s->fd = fd;
gdb_has_xml = 0;
@@ -3038,7 +3033,7 @@ int gdbserver_start(const char *device)
memset(s, 0, sizeof(GDBState));
}
s->c_cpu = first_cpu;
- s->g_cpu = first_cpu->env_ptr;
+ s->g_cpu = first_cpu;
s->chr = chr;
s->state = chr ? RS_IDLE : RS_INACTIVE;
s->mon_chr = mon_chr;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 19/42] cpu: Move gdb_regs field from CPU_COMMON to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (17 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 18/42] gdbstub: Change GDBState::g_cpu to CPUState Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 20/42] gdbstub: Change gdb_register_coprocessor() argument " Andreas Färber
` (23 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Prepares for changing gdb_register_coprocessor() argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 11 ++++++-----
include/exec/cpu-defs.h | 2 --
include/qom/cpu.h | 2 ++
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 7be2342..d862cca 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1840,7 +1840,7 @@ static const char *get_feature_xml(const char *p, const char **newp)
/* Generate the XML description for this CPU. */
if (!target_xml[0]) {
GDBRegisterState *r;
- CPUArchState *env = first_cpu->env_ptr;
+ CPUState *cpu = first_cpu;
snprintf(target_xml, sizeof(target_xml),
"<?xml version=\"1.0\"?>"
@@ -1849,7 +1849,7 @@ static const char *get_feature_xml(const char *p, const char **newp)
"<xi:include href=\"%s\"/>",
GDB_CORE_XML);
- for (r = env->gdb_regs; r; r = r->next) {
+ for (r = cpu->gdb_regs; r; r = r->next) {
pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
pstrcat(target_xml, sizeof(target_xml), r->xml);
pstrcat(target_xml, sizeof(target_xml), "\"/>");
@@ -1875,7 +1875,7 @@ static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
if (reg < NUM_CORE_REGS)
return cpu_gdb_read_register(env, mem_buf, reg);
- for (r = env->gdb_regs; r; r = r->next) {
+ for (r = cpu->gdb_regs; r; r = r->next) {
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
return r->get_reg(env, mem_buf, reg - r->base_reg);
}
@@ -1891,7 +1891,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
if (reg < NUM_CORE_REGS)
return cpu_gdb_write_register(env, mem_buf, reg);
- for (r = env->gdb_regs; r; r = r->next) {
+ for (r = cpu->gdb_regs; r; r = r->next) {
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
return r->set_reg(env, mem_buf, reg - r->base_reg);
}
@@ -1910,11 +1910,12 @@ void gdb_register_coprocessor(CPUArchState * env,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos)
{
+ CPUState *cpu = ENV_GET_CPU(env);
GDBRegisterState *s;
GDBRegisterState **p;
static int last_reg = NUM_CORE_REGS;
- p = &env->gdb_regs;
+ p = &cpu->gdb_regs;
while (*p) {
/* Check for duplicates. */
if (strcmp((*p)->xml, xml) == 0)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 12b1ca7..b5b93db 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -174,8 +174,6 @@ typedef struct CPUWatchpoint {
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
\
- struct GDBRegisterState *gdb_regs; \
- \
/* Core interrupt code */ \
sigjmp_buf jmp_env; \
int exception_index; \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index ba4fde1..d33afac 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -137,6 +137,7 @@ struct kvm_run;
* @singlestep_enabled: Flags for single-stepping.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
+ * @gdb_regs: Additional GDB registers.
* @next_cpu: Next CPU sharing TB cache.
* @kvm_fd: vCPU file descriptor for KVM.
*
@@ -171,6 +172,7 @@ struct CPUState {
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
+ struct GDBRegisterState *gdb_regs;
CPUState *next_cpu;
int kvm_fd;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 20/42] gdbstub: Change gdb_register_coprocessor() argument to CPUState
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (18 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 19/42] cpu: Move gdb_regs field from CPU_COMMON " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 21/42] target-xtensa: Introduce XtensaCPU subclasses Andreas Färber
` (22 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Alexander Graf, open list:PowerPC,
Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 7 +++----
include/exec/gdbstub.h | 2 +-
target-arm/helper.c | 7 ++++---
target-m68k/helper.c | 3 ++-
target-ppc/translate_init.c | 15 ++++++++-------
5 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index d862cca..4ebe9e0 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1906,11 +1906,10 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
*/
-void gdb_register_coprocessor(CPUArchState * env,
- gdb_reg_cb get_reg, gdb_reg_cb set_reg,
- int num_regs, const char *xml, int g_pos)
+void gdb_register_coprocessor(CPUState *cpu,
+ gdb_reg_cb get_reg, gdb_reg_cb set_reg,
+ int num_regs, const char *xml, int g_pos)
{
- CPUState *cpu = ENV_GET_CPU(env);
GDBRegisterState *s;
GDBRegisterState **p;
static int last_reg = NUM_CORE_REGS;
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 0f1ad9a..1bd00ae 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -26,7 +26,7 @@ void gdbserver_fork(CPUArchState *);
#endif
/* Get or set a register. Returns the size of the register. */
typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
-void gdb_register_coprocessor(CPUArchState *env,
+void gdb_register_coprocessor(CPUState *cpu,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2a2bb83..c234372 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1502,16 +1502,17 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_NEON)) {
- gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP3)) {
- gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP)) {
- gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index dcadfab..00a7a08 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -121,10 +121,11 @@ M68kCPU *cpu_m68k_init(const char *cpu_model)
void m68k_cpu_init_gdb(M68kCPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
- gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg,
+ gdb_register_coprocessor(cs, fpu_gdb_get_reg, fpu_gdb_set_reg,
11, "cf-fp.xml", 18);
}
/* TODO: Add [E]MAC registers. */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 82fc463..36bff09 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7645,8 +7645,8 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu)
static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
{
+ CPUState *cs = CPU(dev);
PowerPCCPU *cpu = POWERPC_CPU(dev);
- CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
Error *local_err = NULL;
#if !defined(CONFIG_USER_ONLY)
@@ -7690,15 +7690,15 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
init_ppc_proc(cpu);
if (pcc->insns_flags & PPC_FLOAT) {
- gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
+ gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
33, "power-fpu.xml", 0);
}
if (pcc->insns_flags & PPC_ALTIVEC) {
- gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
+ gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
34, "power-altivec.xml", 0);
}
if (pcc->insns_flags & PPC_SPE) {
- gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
+ gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
34, "power-spe.xml", 0);
}
@@ -7706,6 +7706,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
#if defined(PPC_DUMP_CPU)
{
+ CPUPPCState *env = &cpu->env;
const char *mmu_model, *excp_model, *bus_model;
switch (env->mmu_model) {
case POWERPC_MMU_32B:
@@ -7857,10 +7858,10 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
printf(" none\n");
printf(" Time-base/decrementer clock source: %s\n",
env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
+ dump_ppc_insns(env);
+ dump_ppc_sprs(env);
+ fflush(stdout);
}
- dump_ppc_insns(env);
- dump_ppc_sprs(env);
- fflush(stdout);
#endif
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 21/42] target-xtensa: Introduce XtensaCPU subclasses
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (19 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 20/42] gdbstub: Change gdb_register_coprocessor() argument " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 22/42] gdbstub: Fix cpu_gdb_{read, write}_register() Coding Style Andreas Färber
` (21 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov, Andreas Färber
Register a CPU type per core registered. Save the XtensaConfig in
XtensaCPUClass and copy it from there to CPUXtensaState, to avoid
touching every env->config access for now.
Prepares for storing per-class GDB register count.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-xtensa/cpu-qom.h | 3 +++
target-xtensa/cpu.c | 24 +++++++++++++++++++++++-
target-xtensa/helper.c | 32 +++++++++++++++++++++-----------
3 files changed, 47 insertions(+), 12 deletions(-)
diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index b9896f2..1b9479e 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -45,6 +45,7 @@
* XtensaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
+ * @config: The CPU core configuration.
*
* An Xtensa CPU model.
*/
@@ -55,6 +56,8 @@ typedef struct XtensaCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+
+ const XtensaConfig *config;
} XtensaCPUClass;
/**
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index d2bcfc6..5a39971 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -64,6 +64,25 @@ static void xtensa_cpu_reset(CPUState *s)
reset_mmu(env);
}
+static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc;
+ char *typename;
+
+ if (cpu_model == NULL) {
+ return NULL;
+ }
+
+ typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
+ object_class_is_abstract(oc)) {
+ return NULL;
+ }
+ return oc;
+}
+
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
{
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
@@ -75,10 +94,12 @@ static void xtensa_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
XtensaCPU *cpu = XTENSA_CPU(obj);
+ XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
CPUXtensaState *env = &cpu->env;
static bool tcg_inited;
cs->env_ptr = env;
+ env->config = xcc->config;
cpu_exec_init(env);
if (tcg_enabled() && !tcg_inited) {
@@ -105,6 +126,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
xcc->parent_reset = cc->reset;
cc->reset = xtensa_cpu_reset;
+ cc->class_by_name = xtensa_cpu_class_by_name;
cc->do_interrupt = xtensa_cpu_do_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
@@ -119,7 +141,7 @@ static const TypeInfo xtensa_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(XtensaCPU),
.instance_init = xtensa_cpu_initfn,
- .abstract = false,
+ .abstract = true,
.class_size = sizeof(XtensaCPUClass),
.class_init = xtensa_cpu_class_init,
};
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index de6cc3b..e309879 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -35,10 +35,27 @@
static struct XtensaConfigList *xtensa_cores;
+static void xtensa_core_class_init(ObjectClass *oc, void *data)
+{
+ XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
+ const XtensaConfig *config = data;
+
+ xcc->config = config;
+}
+
void xtensa_register_core(XtensaConfigList *node)
{
+ TypeInfo type = {
+ .parent = TYPE_XTENSA_CPU,
+ .class_init = xtensa_core_class_init,
+ .class_data = (void *)node->config,
+ };
+
node->next = xtensa_cores;
xtensa_cores = node;
+ type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
+ type_register(&type);
+ g_free((gpointer)type.name);
}
static uint32_t check_hw_breakpoints(CPUXtensaState *env)
@@ -72,24 +89,17 @@ void xtensa_breakpoint_handler(CPUXtensaState *env)
XtensaCPU *cpu_xtensa_init(const char *cpu_model)
{
+ ObjectClass *oc;
XtensaCPU *cpu;
CPUXtensaState *env;
- const XtensaConfig *config = NULL;
- XtensaConfigList *core = xtensa_cores;
-
- for (; core; core = core->next)
- if (strcmp(core->config->name, cpu_model) == 0) {
- config = core->config;
- break;
- }
- if (config == NULL) {
+ oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
+ if (oc == NULL) {
return NULL;
}
- cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU));
+ cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
- env->config = config;
xtensa_irq_init(env);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 22/42] gdbstub: Fix cpu_gdb_{read, write}_register() Coding Style
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (20 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 21/42] target-xtensa: Introduce XtensaCPU subclasses Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 23/42] gdbstub: Drop dead code in cpu_gdb_{read, write}_register() Andreas Färber
` (20 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Add braces, replace tabs, remove trailing whitespace, drop space before
parenthesis and place break etc. below case statements.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 446 ++++++++++++++++++++++++++++++++++++++++----------------------
1 file changed, 292 insertions(+), 154 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 4ebe9e0..4f5c876 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -571,26 +571,42 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
} else {
GET_REG32(env->eip);
}
- case IDX_FLAGS_REG: GET_REG32(env->eflags);
-
- case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
- case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
- case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
- case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
- case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
- case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
+ case IDX_FLAGS_REG:
+ GET_REG32(env->eflags);
+
+ case IDX_SEG_REGS:
+ GET_REG32(env->segs[R_CS].selector);
+ case IDX_SEG_REGS + 1:
+ GET_REG32(env->segs[R_SS].selector);
+ case IDX_SEG_REGS + 2:
+ GET_REG32(env->segs[R_DS].selector);
+ case IDX_SEG_REGS + 3:
+ GET_REG32(env->segs[R_ES].selector);
+ case IDX_SEG_REGS + 4:
+ GET_REG32(env->segs[R_FS].selector);
+ case IDX_SEG_REGS + 5:
+ GET_REG32(env->segs[R_GS].selector);
- case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
- case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
- (env->fpstt & 0x7) << 11);
- case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
- case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
- case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
- case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
- case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
- case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
+ case IDX_FP_REGS + 8:
+ GET_REG32(env->fpuc);
+ case IDX_FP_REGS + 9:
+ GET_REG32((env->fpus & ~0x3800) |
+ (env->fpstt & 0x7) << 11);
+ case IDX_FP_REGS + 10:
+ GET_REG32(0); /* ftag */
+ case IDX_FP_REGS + 11:
+ GET_REG32(0); /* fiseg */
+ case IDX_FP_REGS + 12:
+ GET_REG32(0); /* fioff */
+ case IDX_FP_REGS + 13:
+ GET_REG32(0); /* foseg */
+ case IDX_FP_REGS + 14:
+ GET_REG32(0); /* fooff */
+ case IDX_FP_REGS + 15:
+ GET_REG32(0); /* fop */
- case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
+ case IDX_MXCSR_REG:
+ GET_REG32(env->mxcsr);
}
}
return 0;
@@ -612,8 +628,10 @@ static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
limit = 0xffff;
flags = 0;
} else {
- if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
+ if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
+ &flags)) {
return 4;
+ }
}
cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
#endif
@@ -664,12 +682,18 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
env->eflags = ldl_p(mem_buf);
return 4;
- case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
- case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
- case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
- case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
- case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
- case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
+ case IDX_SEG_REGS:
+ return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
+ case IDX_SEG_REGS + 1:
+ return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
+ case IDX_SEG_REGS + 2:
+ return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
+ case IDX_SEG_REGS + 3:
+ return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
+ case IDX_SEG_REGS + 4:
+ return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
+ case IDX_SEG_REGS + 5:
+ return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
case IDX_FP_REGS + 8:
env->fpuc = ldl_p(mem_buf);
@@ -679,12 +703,18 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
env->fpstt = (tmp >> 11) & 7;
env->fpus = tmp & ~0x3800;
return 4;
- case IDX_FP_REGS + 10: /* ftag */ return 4;
- case IDX_FP_REGS + 11: /* fiseg */ return 4;
- case IDX_FP_REGS + 12: /* fioff */ return 4;
- case IDX_FP_REGS + 13: /* foseg */ return 4;
- case IDX_FP_REGS + 14: /* fooff */ return 4;
- case IDX_FP_REGS + 15: /* fop */ return 4;
+ case IDX_FP_REGS + 10: /* ftag */
+ return 4;
+ case IDX_FP_REGS + 11: /* fiseg */
+ return 4;
+ case IDX_FP_REGS + 12: /* fioff */
+ return 4;
+ case IDX_FP_REGS + 13: /* foseg */
+ return 4;
+ case IDX_FP_REGS + 14: /* fooff */
+ return 4;
+ case IDX_FP_REGS + 15: /* fop */
+ return 4;
case IDX_MXCSR_REG:
env->mxcsr = ldl_p(mem_buf);
@@ -716,29 +746,37 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
GET_REGL(env->gpr[n]);
} else if (n < 64) {
/* fprs */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
stfq_p(mem_buf, env->fpr[n-32]);
return 8;
} else {
switch (n) {
- case 64: GET_REGL(env->nip);
- case 65: GET_REGL(env->msr);
+ case 64:
+ GET_REGL(env->nip);
+ case 65:
+ GET_REGL(env->msr);
case 66:
{
uint32_t cr = 0;
int i;
- for (i = 0; i < 8; i++)
+ for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
+ }
GET_REG32(cr);
}
- case 67: GET_REGL(env->lr);
- case 68: GET_REGL(env->ctr);
- case 69: GET_REGL(env->xer);
+ case 67:
+ GET_REGL(env->lr);
+ case 68:
+ GET_REGL(env->ctr);
+ case 69:
+ GET_REGL(env->xer);
case 70:
{
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
GET_REG32(env->fpscr);
}
}
@@ -754,8 +792,9 @@ static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
return sizeof(target_ulong);
} else if (n < 64) {
/* fprs */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
env->fpr[n-32] = ldfq_p(mem_buf);
return 8;
} else {
@@ -770,8 +809,9 @@ static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
uint32_t cr = ldl_p(mem_buf);
int i;
- for (i = 0; i < 8; i++)
+ for (i = 0; i < 8; i++) {
env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
+ }
return 4;
}
case 67:
@@ -785,8 +825,9 @@ static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
return sizeof(target_ulong);
case 70:
/* fpscr */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
return sizeof(target_ulong);
}
@@ -829,15 +870,24 @@ static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
}
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
switch (n) {
- case 64: GET_REGA(env->y);
- case 65: GET_REGA(cpu_get_psr(env));
- case 66: GET_REGA(env->wim);
- case 67: GET_REGA(env->tbr);
- case 68: GET_REGA(env->pc);
- case 69: GET_REGA(env->npc);
- case 70: GET_REGA(env->fsr);
- case 71: GET_REGA(0); /* csr */
- default: GET_REGA(0);
+ case 64:
+ GET_REGA(env->y);
+ case 65:
+ GET_REGA(cpu_get_psr(env));
+ case 66:
+ GET_REGA(env->wim);
+ case 67:
+ GET_REGA(env->tbr);
+ case 68:
+ GET_REGA(env->pc);
+ case 69:
+ GET_REGA(env->npc);
+ case 70:
+ GET_REGA(env->fsr);
+ case 71:
+ GET_REGA(0); /* csr */
+ default:
+ GET_REGA(0);
}
#else
if (n < 64) {
@@ -853,15 +903,21 @@ static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
GET_REG64(env->fpr[(n - 32) / 2].ll);
}
switch (n) {
- case 80: GET_REGL(env->pc);
- case 81: GET_REGL(env->npc);
- case 82: GET_REGL((cpu_get_ccr(env) << 32) |
- ((env->asi & 0xff) << 24) |
- ((env->pstate & 0xfff) << 8) |
- cpu_get_cwp64(env));
- case 83: GET_REGL(env->fsr);
- case 84: GET_REGL(env->fprs);
- case 85: GET_REGL(env->y);
+ case 80:
+ GET_REGL(env->pc);
+ case 81:
+ GET_REGL(env->npc);
+ case 82:
+ GET_REGL((cpu_get_ccr(env) << 32) |
+ ((env->asi & 0xff) << 24) |
+ ((env->pstate & 0xfff) << 8) |
+ cpu_get_cwp64(env));
+ case 83:
+ GET_REGL(env->fsr);
+ case 84:
+ GET_REGL(env->fprs);
+ case 85:
+ GET_REGL(env->y);
}
#endif
return 0;
@@ -898,14 +954,29 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
} else {
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
switch (n) {
- case 64: env->y = tmp; break;
- case 65: cpu_put_psr(env, tmp); break;
- case 66: env->wim = tmp; break;
- case 67: env->tbr = tmp; break;
- case 68: env->pc = tmp; break;
- case 69: env->npc = tmp; break;
- case 70: env->fsr = tmp; break;
- default: return 0;
+ case 64:
+ env->y = tmp;
+ break;
+ case 65:
+ cpu_put_psr(env, tmp);
+ break;
+ case 66:
+ env->wim = tmp;
+ break;
+ case 67:
+ env->tbr = tmp;
+ break;
+ case 68:
+ env->pc = tmp;
+ break;
+ case 69:
+ env->npc = tmp;
+ break;
+ case 70:
+ env->fsr = tmp;
+ break;
+ default:
+ return 0;
}
}
return 4;
@@ -924,18 +995,29 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
env->fpr[(n - 32) / 2].ll = tmp;
} else {
switch (n) {
- case 80: env->pc = tmp; break;
- case 81: env->npc = tmp; break;
+ case 80:
+ env->pc = tmp;
+ break;
+ case 81:
+ env->npc = tmp;
+ break;
case 82:
cpu_put_ccr(env, tmp >> 32);
- env->asi = (tmp >> 24) & 0xff;
- env->pstate = (tmp >> 8) & 0xfff;
+ env->asi = (tmp >> 24) & 0xff;
+ env->pstate = (tmp >> 8) & 0xfff;
cpu_put_cwp64(env, tmp & 0xff);
- break;
- case 83: env->fsr = tmp; break;
- case 84: env->fprs = tmp; break;
- case 85: env->y = tmp; break;
- default: return 0;
+ break;
+ case 83:
+ env->fsr = tmp;
+ break;
+ case 84:
+ env->fprs = tmp;
+ break;
+ case 85:
+ env->y = tmp;
+ break;
+ default:
+ return 0;
}
}
return 8;
@@ -959,16 +1041,18 @@ static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
}
if (n < 24) {
/* FPA registers. */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
memset(mem_buf, 0, 12);
return 12;
}
switch (n) {
case 24:
/* FPA status register. */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
GET_REG32(0);
case 25:
/* CPSR */
@@ -986,8 +1070,9 @@ static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
/* Mask out low bit of PC to workaround gdb bugs. This will probably
cause problems if we ever implement the Jazelle DBX extensions. */
- if (n == 15)
+ if (n == 15) {
tmp &= ~1;
+ }
if (n < 16) {
/* Core integer register. */
@@ -996,19 +1081,21 @@ static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
}
if (n < 24) { /* 16-23 */
/* FPA registers (ignored). */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
return 12;
}
switch (n) {
case 24:
/* FPA status register (ignored). */
- if (gdb_has_xml)
+ if (gdb_has_xml) {
return 0;
+ }
return 4;
case 25:
/* CPSR */
- cpsr_write (env, tmp, 0xffffffff);
+ cpsr_write(env, tmp, 0xffffffff);
return 4;
}
/* Unknown register. */
@@ -1030,9 +1117,11 @@ static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
/* A0-A7 */
GET_REG32(env->aregs[n - 8]);
} else {
- switch (n) {
- case 16: GET_REG32(env->sr);
- case 17: GET_REG32(env->pc);
+ switch (n) {
+ case 16:
+ GET_REG32(env->sr);
+ case 17:
+ GET_REG32(env->pc);
}
}
/* FP registers not included here because they vary between
@@ -1054,9 +1143,14 @@ static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
env->aregs[n - 8] = tmp;
} else {
switch (n) {
- case 16: env->sr = tmp; break;
- case 17: env->pc = tmp; break;
- default: return 0;
+ case 16:
+ env->sr = tmp;
+ break;
+ case 17:
+ env->pc = tmp;
+ break;
+ default:
+ return 0;
}
}
return 4;
@@ -1072,44 +1166,55 @@ static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
}
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
if (n >= 38 && n < 70) {
- if (env->CP0_Status & (1 << CP0St_FR))
- GET_REGL(env->active_fpu.fpr[n - 38].d);
- else
- GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ GET_REGL(env->active_fpu.fpr[n - 38].d);
+ } else {
+ GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
+ }
}
switch (n) {
- case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
- case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
+ case 70:
+ GET_REGL((int32_t)env->active_fpu.fcr31);
+ case 71:
+ GET_REGL((int32_t)env->active_fpu.fcr0);
}
}
switch (n) {
- case 32: GET_REGL((int32_t)env->CP0_Status);
- case 33: GET_REGL(env->active_tc.LO[0]);
- case 34: GET_REGL(env->active_tc.HI[0]);
- case 35: GET_REGL(env->CP0_BadVAddr);
- case 36: GET_REGL((int32_t)env->CP0_Cause);
- case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
- case 72: GET_REGL(0); /* fp */
- case 89: GET_REGL((int32_t)env->CP0_PRid);
+ case 32:
+ GET_REGL((int32_t)env->CP0_Status);
+ case 33:
+ GET_REGL(env->active_tc.LO[0]);
+ case 34:
+ GET_REGL(env->active_tc.HI[0]);
+ case 35:
+ GET_REGL(env->CP0_BadVAddr);
+ case 36:
+ GET_REGL((int32_t)env->CP0_Cause);
+ case 37:
+ GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
+ case 72:
+ GET_REGL(0); /* fp */
+ case 89:
+ GET_REGL((int32_t)env->CP0_PRid);
}
if (n >= 73 && n <= 88) {
- /* 16 embedded regs. */
- GET_REGL(0);
+ /* 16 embedded regs. */
+ GET_REGL(0);
}
return 0;
}
/* convert MIPS rounding mode in FCR31 to IEEE library */
-static unsigned int ieee_rm[] =
- {
+static unsigned int ieee_rm[] = {
float_round_nearest_even,
float_round_to_zero,
float_round_up,
float_round_down
- };
+};
#define RESTORE_ROUNDING_MODE \
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
+ &env->active_fpu.fp_status)
static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
@@ -1124,10 +1229,11 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
if (env->CP0_Config1 & (1 << CP0C1_FP)
&& n >= 38 && n < 73) {
if (n < 70) {
- if (env->CP0_Status & (1 << CP0St_FR))
- env->active_fpu.fpr[n - 38].d = tmp;
- else
- env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ env->active_fpu.fpr[n - 38].d = tmp;
+ } else {
+ env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
+ }
}
switch (n) {
case 70:
@@ -1135,16 +1241,28 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
/* set rounding mode */
RESTORE_ROUNDING_MODE;
break;
- case 71: env->active_fpu.fcr0 = tmp; break;
+ case 71:
+ env->active_fpu.fcr0 = tmp;
+ break;
}
return sizeof(target_ulong);
}
switch (n) {
- case 32: env->CP0_Status = tmp; break;
- case 33: env->active_tc.LO[0] = tmp; break;
- case 34: env->active_tc.HI[0] = tmp; break;
- case 35: env->CP0_BadVAddr = tmp; break;
- case 36: env->CP0_Cause = tmp; break;
+ case 32:
+ env->CP0_Status = tmp;
+ break;
+ case 33:
+ env->active_tc.LO[0] = tmp;
+ break;
+ case 34:
+ env->active_tc.HI[0] = tmp;
+ break;
+ case 35:
+ env->CP0_BadVAddr = tmp;
+ break;
+ case 36:
+ env->CP0_Cause = tmp;
+ break;
case 37:
env->active_tc.PC = tmp & ~(target_ulong)1;
if (tmp & 1) {
@@ -1153,12 +1271,14 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
env->hflags &= ~(MIPS_HFLAG_M16);
}
break;
- case 72: /* fp, ignored */ break;
- default:
- if (n > 89)
- return 0;
- /* Other registers are readonly. Ignore writes. */
- break;
+ case 72: /* fp, ignored */
+ break;
+ default:
+ if (n > 89) {
+ return 0;
+ }
+ /* Other registers are readonly. Ignore writes. */
+ break;
}
return sizeof(target_ulong);
@@ -1340,7 +1460,8 @@ static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
case 51 ... 58:
env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
break;
- default: return 0;
+ default:
+ return 0;
}
return 4;
@@ -1352,9 +1473,9 @@ static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- GET_REG32(env->regs[n]);
+ GET_REG32(env->regs[n]);
} else {
- GET_REG32(env->sregs[n - 32]);
+ GET_REG32(env->sregs[n - 32]);
}
return 0;
}
@@ -1363,15 +1484,16 @@ static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
- if (n > NUM_CORE_REGS)
- return 0;
+ if (n > NUM_CORE_REGS) {
+ return 0;
+ }
tmp = ldl_p(mem_buf);
if (n < 32) {
- env->regs[n] = tmp;
+ env->regs[n] = tmp;
} else {
- env->sregs[n - 32] = tmp;
+ env->sregs[n - 32] = tmp;
}
return 4;
}
@@ -1416,27 +1538,34 @@ static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint8_t srs;
- if (env->pregs[PR_VR] < 32)
+ if (env->pregs[PR_VR] < 32) {
return read_register_crisv10(env, mem_buf, n);
+ }
srs = env->pregs[PR_SRS];
if (n < 16) {
- GET_REG32(env->regs[n]);
+ GET_REG32(env->regs[n]);
}
if (n >= 21 && n < 32) {
- GET_REG32(env->pregs[n - 16]);
+ GET_REG32(env->pregs[n - 16]);
}
if (n >= 33 && n < 49) {
- GET_REG32(env->sregs[srs][n - 33]);
+ GET_REG32(env->sregs[srs][n - 33]);
}
switch (n) {
- case 16: GET_REG8(env->pregs[0]);
- case 17: GET_REG8(env->pregs[1]);
- case 18: GET_REG32(env->pregs[2]);
- case 19: GET_REG8(srs);
- case 20: GET_REG16(env->pregs[4]);
- case 32: GET_REG32(env->pc);
+ case 16:
+ GET_REG8(env->pregs[0]);
+ case 17:
+ GET_REG8(env->pregs[1]);
+ case 18:
+ GET_REG32(env->pregs[2]);
+ case 19:
+ GET_REG8(srs);
+ case 20:
+ GET_REG16(env->pregs[4]);
+ case 32:
+ GET_REG32(env->pc);
}
return 0;
@@ -1446,27 +1575,36 @@ static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
- if (n > 49)
- return 0;
+ if (n > 49) {
+ return 0;
+ }
tmp = ldl_p(mem_buf);
if (n < 16) {
- env->regs[n] = tmp;
+ env->regs[n] = tmp;
}
if (n >= 21 && n < 32) {
- env->pregs[n - 16] = tmp;
+ env->pregs[n - 16] = tmp;
}
/* FIXME: Should support function regs be writable? */
switch (n) {
- case 16: return 1;
- case 17: return 1;
- case 18: env->pregs[PR_PID] = tmp; break;
- case 19: return 1;
- case 20: return 2;
- case 32: env->pc = tmp; break;
+ case 16:
+ return 1;
+ case 17:
+ return 1;
+ case 18:
+ env->pregs[PR_PID] = tmp;
+ break;
+ case 19:
+ return 1;
+ case 20:
+ return 2;
+ case 32:
+ env->pc = tmp;
+ break;
}
return 4;
@@ -1731,7 +1869,7 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
default:
qemu_log("%s from reg %d of unsupported type %d\n",
- __func__, n, reg->type);
+ __func__, n, reg->type);
return 0;
}
}
@@ -1775,7 +1913,7 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
default:
qemu_log("%s to reg %d of unsupported type %d\n",
- __func__, n, reg->type);
+ __func__, n, reg->type);
return 0;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 23/42] gdbstub: Drop dead code in cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (21 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 22/42] gdbstub: Fix cpu_gdb_{read, write}_register() Coding Style Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 24/42] cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs Andreas Färber
` (19 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
GET_REG*() macros include a return statement, thus no need for break.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 4f5c876..d7cf7ab 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1295,15 +1295,12 @@ static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
switch (n) {
case 32: /* PPC */
GET_REG32(env->ppc);
- break;
case 33: /* NPC */
GET_REG32(env->npc);
- break;
case 34: /* SR */
GET_REG32(env->sr);
- break;
default:
break;
@@ -1516,14 +1513,11 @@ read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
switch (n) {
case 16:
GET_REG8(env->pregs[n - 16]);
- break;
case 17:
GET_REG8(env->pregs[n - 16]);
- break;
case 20:
case 21:
GET_REG16(env->pregs[n - 16]);
- break;
default:
if (n >= 23) {
GET_REG32(env->pregs[n - 16]);
@@ -1693,22 +1687,16 @@ static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
val = deposit64(env->psw.mask, 44, 2, cc_op);
GET_REGL(val);
- break;
case S390_PSWA_REGNUM:
GET_REGL(env->psw.addr);
- break;
case S390_R0_REGNUM ... S390_R15_REGNUM:
GET_REGL(env->regs[n-S390_R0_REGNUM]);
- break;
case S390_A0_REGNUM ... S390_A15_REGNUM:
GET_REG32(env->aregs[n-S390_A0_REGNUM]);
- break;
case S390_FPC_REGNUM:
GET_REG32(env->fpc);
- break;
case S390_F0_REGNUM ... S390_F15_REGNUM:
GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
- break;
}
return 0;
@@ -1762,26 +1750,19 @@ static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
switch (n) {
case 32:
GET_REG32(env->pc);
- break;
/* FIXME: put in right exception ID */
case 33:
GET_REG32(0);
- break;
case 34:
GET_REG32(env->eba);
- break;
case 35:
GET_REG32(env->deba);
- break;
case 36:
GET_REG32(env->ie);
- break;
case 37:
GET_REG32(lm32_pic_get_im(env->pic_state));
- break;
case 38:
GET_REG32(lm32_pic_get_ip(env->pic_state));
- break;
}
}
return 0;
@@ -1844,28 +1825,22 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
switch (reg->type) {
case 9: /*pc*/
GET_REG32(env->pc);
- break;
case 1: /*ar*/
xtensa_sync_phys_from_window(env);
GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
- break;
case 2: /*SR*/
GET_REG32(env->sregs[reg->targno & 0xff]);
- break;
case 3: /*UR*/
GET_REG32(env->uregs[reg->targno & 0xff]);
- break;
case 4: /*f*/
GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
- break;
case 8: /*a*/
GET_REG32(env->regs[reg->targno & 0x0f]);
- break;
default:
qemu_log("%s from reg %d of unsupported type %d\n",
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 24/42] cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (22 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 23/42] gdbstub: Drop dead code in cpu_gdb_{read, write}_register() Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 25/42] target-i386: Move cpu_gdb_{read, write}_register() Andreas Färber
` (18 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Alexander Graf, Blue Swirl, Max Filippov,
Michael Walle, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Andreas Färber, Aurelien Jarno, Richard Henderson
CPUState::gdb_num_regs replaces num_g_regs.
CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 83 +++++++++++----------------------------------
include/qom/cpu.h | 7 +++-
qom/cpu.c | 9 +++++
target-alpha/cpu.c | 1 +
target-arm/cpu.c | 1 +
target-cris/cpu.c | 2 ++
target-i386/cpu.c | 1 +
target-lm32/cpu.c | 1 +
target-m68k/cpu.c | 1 +
target-microblaze/cpu.c | 1 +
target-mips/cpu.c | 2 ++
target-openrisc/cpu.c | 1 +
target-ppc/translate_init.c | 2 ++
target-s390x/cpu.c | 1 +
target-sh4/cpu.c | 1 +
target-sparc/cpu.c | 6 ++++
target-xtensa/cpu.c | 3 ++
target-xtensa/helper.c | 8 +++++
18 files changed, 66 insertions(+), 65 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index d7cf7ab..b6c1dbe 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -530,8 +530,6 @@ static const int gpr_map[16] = {
#endif
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
-
#define IDX_IP_REG CPU_NB_REGS
#define IDX_FLAGS_REG (IDX_IP_REG + 1)
#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
@@ -732,7 +730,6 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
historical mishap the FP registers appear in between core integer
regs and PC, MSR, CR, and so forth. We hack round this by giving the
FP regs zero size when talking to a newer gdb. */
-#define NUM_CORE_REGS 71
#if defined (TARGET_PPC64)
#define GDB_CORE_XML "power64-core.xml"
#else
@@ -837,12 +834,6 @@ static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
#elif defined (TARGET_SPARC)
-#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
-#define NUM_CORE_REGS 86
-#else
-#define NUM_CORE_REGS 72
-#endif
-
#ifdef TARGET_ABI32
#define GET_REGA(val) GET_REG32(val)
#else
@@ -1030,7 +1021,6 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
the FPA registers appear in between core integer regs and the CPSR.
We hack round this by giving the FPA regs zero size when talking to a
newer gdb. */
-#define NUM_CORE_REGS 26
#define GDB_CORE_XML "arm-core.xml"
static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
@@ -1104,8 +1094,6 @@ static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
#elif defined (TARGET_M68K)
-#define NUM_CORE_REGS 18
-
#define GDB_CORE_XML "cf-core.xml"
static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
@@ -1157,8 +1145,6 @@ static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
}
#elif defined (TARGET_MIPS)
-#define NUM_CORE_REGS 73
-
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
@@ -1285,8 +1271,6 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
}
#elif defined(TARGET_OPENRISC)
-#define NUM_CORE_REGS (32 + 3)
-
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
@@ -1312,9 +1296,11 @@ static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUOpenRISCState *env,
uint8_t *mem_buf, int n)
{
+ OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
uint32_t tmp;
- if (n > NUM_CORE_REGS) {
+ if (n > cc->gdb_num_core_regs) {
return 0;
}
@@ -1347,8 +1333,6 @@ static int cpu_gdb_write_register(CPUOpenRISCState *env,
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
/* FIXME: We should use XML for this. */
-#define NUM_CORE_REGS 59
-
static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
switch (n) {
@@ -1465,8 +1449,6 @@ static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
}
#elif defined (TARGET_MICROBLAZE)
-#define NUM_CORE_REGS (32 + 5)
-
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
@@ -1479,9 +1461,11 @@ static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
uint32_t tmp;
- if (n > NUM_CORE_REGS) {
+ if (n > cc->gdb_num_core_regs) {
return 0;
}
@@ -1496,8 +1480,6 @@ static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
}
#elif defined (TARGET_CRIS)
-#define NUM_CORE_REGS 49
-
static int
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
{
@@ -1605,8 +1587,6 @@ static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
}
#elif defined (TARGET_ALPHA)
-#define NUM_CORE_REGS 67
-
static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
uint64_t val;
@@ -1675,8 +1655,6 @@ static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
}
#elif defined (TARGET_S390X)
-#define NUM_CORE_REGS S390_NUM_REGS
-
static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
uint64_t val;
@@ -1740,7 +1718,6 @@ static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
#elif defined (TARGET_LM32)
#include "hw/lm32/lm32_pic.h"
-#define NUM_CORE_REGS (32 + 7)
static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
@@ -1770,9 +1747,11 @@ static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
+ LM32CPU *cpu = lm32_env_get_cpu(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
uint32_t tmp;
- if (n > NUM_CORE_REGS) {
+ if (n > cc->gdb_num_core_regs) {
return 0;
}
@@ -1806,14 +1785,6 @@ static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
}
#elif defined(TARGET_XTENSA)
-/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
- * Use num_regs to see all registers. gdb modification is required for that:
- * reset bit 0 in the 'flags' field of the registers definitions in the
- * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
- */
-#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
-#define num_g_regs NUM_CORE_REGS
-
static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
@@ -1896,8 +1867,6 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
}
#else
-#define NUM_CORE_REGS 0
-
static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
{
return 0;
@@ -1910,10 +1879,6 @@ static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
#endif
-#if !defined(TARGET_XTENSA)
-static int num_g_regs = NUM_CORE_REGS;
-#endif
-
#ifdef GDB_CORE_XML
/* Encode data using the encoding for 'x' packets. */
static int memtox(char *buf, const char *mem, int len)
@@ -1982,11 +1947,13 @@ static const char *get_feature_xml(const char *p, const char **newp)
static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchState *env = cpu->env_ptr;
GDBRegisterState *r;
- if (reg < NUM_CORE_REGS)
+ if (reg < cc->gdb_num_core_regs) {
return cpu_gdb_read_register(env, mem_buf, reg);
+ }
for (r = cpu->gdb_regs; r; r = r->next) {
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
@@ -1998,11 +1965,13 @@ static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchState *env = cpu->env_ptr;
GDBRegisterState *r;
- if (reg < NUM_CORE_REGS)
+ if (reg < cc->gdb_num_core_regs) {
return cpu_gdb_write_register(env, mem_buf, reg);
+ }
for (r = cpu->gdb_regs; r; r = r->next) {
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
@@ -2012,7 +1981,6 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
return 0;
}
-#if !defined(TARGET_XTENSA)
/* Register a supplemental set of CPU registers. If g_pos is nonzero it
specifies the first register number and these registers are included in
a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
@@ -2025,7 +1993,6 @@ void gdb_register_coprocessor(CPUState *cpu,
{
GDBRegisterState *s;
GDBRegisterState **p;
- static int last_reg = NUM_CORE_REGS;
p = &cpu->gdb_regs;
while (*p) {
@@ -2036,25 +2003,22 @@ void gdb_register_coprocessor(CPUState *cpu,
}
s = g_new0(GDBRegisterState, 1);
- s->base_reg = last_reg;
+ s->base_reg = cpu->gdb_num_regs;
s->num_regs = num_regs;
s->get_reg = get_reg;
s->set_reg = set_reg;
s->xml = xml;
/* Add to end of list. */
- last_reg += num_regs;
+ cpu->gdb_num_regs += num_regs;
*p = s;
if (g_pos) {
if (g_pos != s->base_reg) {
fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
"Expected %d got %d\n", xml, g_pos, s->base_reg);
- } else {
- num_g_regs = last_reg;
}
}
}
-#endif
#ifndef CONFIG_USER_ONLY
static const int xlat_gdb_type[] = {
@@ -2171,9 +2135,6 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
static int gdb_handle_packet(GDBState *s, const char *line_buf)
{
-#ifdef TARGET_XTENSA
- CPUArchState *env;
-#endif
CPUState *cpu;
const char *p;
uint32_t thread;
@@ -2321,11 +2282,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
break;
case 'g':
cpu_synchronize_state(s->g_cpu);
-#ifdef TARGET_XTENSA
- env = s->g_cpu->env_ptr;
-#endif
len = 0;
- for (addr = 0; addr < num_g_regs; addr++) {
+ for (addr = 0; addr < s->g_cpu->gdb_num_regs; addr++) {
reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
len += reg_size;
}
@@ -2334,13 +2292,10 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
break;
case 'G':
cpu_synchronize_state(s->g_cpu);
-#ifdef TARGET_XTENSA
- env = s->g_cpu->env_ptr;
-#endif
registers = mem_buf;
len = strlen(p) / 2;
hextomem((uint8_t *)registers, p, len);
- for (addr = 0; addr < num_g_regs && len > 0; addr++) {
+ for (addr = 0; addr < s->g_cpu->gdb_num_regs && len > 0; addr++) {
reg_size = gdb_write_register(s->g_cpu, registers, addr);
len -= reg_size;
registers += reg_size;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index d33afac..7b953c0 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -77,6 +77,7 @@ struct TranslationBlock;
* #TranslationBlock.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @vmsd: State description for migration.
+ * @gdb_num_core_regs: Number of core registers accessible to GDB.
*
* Represents a CPU family or model.
*/
@@ -105,7 +106,6 @@ typedef struct CPUClass {
void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- const struct VMStateDescription *vmsd;
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
@@ -114,6 +114,9 @@ typedef struct CPUClass {
int cpuid, void *opaque);
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
+
+ const struct VMStateDescription *vmsd;
+ int gdb_num_core_regs;
} CPUClass;
struct KVMState;
@@ -138,6 +141,7 @@ struct kvm_run;
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
* @gdb_regs: Additional GDB registers.
+ * @gdb_num_regs: Number of total registers accessible to GDB.
* @next_cpu: Next CPU sharing TB cache.
* @kvm_fd: vCPU file descriptor for KVM.
*
@@ -173,6 +177,7 @@ struct CPUState {
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
struct GDBRegisterState *gdb_regs;
+ int gdb_num_regs;
CPUState *next_cpu;
int kvm_fd;
diff --git a/qom/cpu.c b/qom/cpu.c
index 5c45ab5..2839ddf 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -226,6 +226,14 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
}
}
+static void cpu_common_initfn(Object *obj)
+{
+ CPUState *cpu = CPU(obj);
+ CPUClass *cc = CPU_GET_CLASS(obj);
+
+ cpu->gdb_num_regs = cc->gdb_num_core_regs;
+}
+
static int64_t cpu_common_get_arch_id(CPUState *cpu)
{
return cpu->cpu_index;
@@ -253,6 +261,7 @@ static const TypeInfo cpu_type_info = {
.name = TYPE_CPU,
.parent = TYPE_DEVICE,
.instance_size = sizeof(CPUState),
+ .instance_init = cpu_common_initfn,
.abstract = true,
.class_size = sizeof(CPUClass),
.class_init = cpu_class_init,
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index c8c8c2c..cc0f69a 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -276,6 +276,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
+ cc->gdb_num_core_regs = 67;
}
static const TypeInfo alpha_cpu_type_info = {
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 90f6455..cbb0c9e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -823,6 +823,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_arm_cpu;
#endif
+ cc->gdb_num_core_regs = 26;
}
static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index ba095e7..31eeddf 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -258,6 +258,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
#endif
+
+ cc->gdb_num_core_regs = 49;
}
static const TypeInfo cris_cpu_type_info = {
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index cd350cb..df9832e 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2549,6 +2549,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
#endif
+ cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
}
static const TypeInfo x86_cpu_type_info = {
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index ce55e48..aa52696 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -91,6 +91,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
#endif
+ cc->gdb_num_core_regs = 32 + 7;
}
static const TypeInfo lm32_cpu_type_info = {
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 988f476..93200d9 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -194,6 +194,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_m68k_cpu;
+ cc->gdb_num_core_regs = 18;
}
static void register_cpu_type(const M68kCPUInfo *info)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 9f10c8c..758b0cb 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -147,6 +147,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#endif
dc->vmsd = &vmstate_mb_cpu;
dc->props = mb_properties;
+ cc->gdb_num_core_regs = 32 + 5;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 4834c86..e667fb7 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -104,6 +104,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->do_unassigned_access = mips_cpu_unassigned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
#endif
+
+ cc->gdb_num_core_regs = 73;
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 3da5a7a..b814e46 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -158,6 +158,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
#endif
+ cc->gdb_num_core_regs = 32 + 3;
}
static void cpu_register(const OpenRISCCPUInfo *info)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 36bff09..795225a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8302,6 +8302,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
#endif
+
+ cc->gdb_num_core_regs = 71;
}
static const TypeInfo ppc_cpu_type_info = {
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index cb89d1a..8f99d7c 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -177,6 +177,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_s390_cpu;
+ cc->gdb_num_core_regs = S390_NUM_REGS;
}
static const TypeInfo s390_cpu_type_info = {
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 51a7757..35f0535 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -290,6 +290,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_sh_cpu;
+ cc->gdb_num_core_regs = 59;
}
static const TypeInfo superh_cpu_type_info = {
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index d1d0339..388a632 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -791,6 +791,12 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_unassigned_access = sparc_cpu_unassigned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
#endif
+
+#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
+ cc->gdb_num_core_regs = 86;
+#else
+ cc->gdb_num_core_regs = 72;
+#endif
}
static const TypeInfo sparc_cpu_type_info = {
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 5a39971..560fa0c 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -85,8 +85,11 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
{
+ CPUState *cs = CPU(dev);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
+ cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
+
xcc->parent_realize(dev, errp);
}
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index e309879..a0f9993 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -37,10 +37,18 @@ static struct XtensaConfigList *xtensa_cores;
static void xtensa_core_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
const XtensaConfig *config = data;
xcc->config = config;
+
+ /* Use num_core_regs to see only non-privileged registers in an unmodified
+ * gdb. Use num_regs to see all registers. gdb modification is required
+ * for that: reset bit 0 in the 'flags' field of the registers definitions
+ * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
+ */
+ cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
}
void xtensa_register_core(XtensaConfigList *node)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 25/42] target-i386: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (23 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 24/42] cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 26/42] target-ppc: " Andreas Färber
` (17 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 203 +--------------------------------------------
target-i386/gdbstub.c | 222 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 223 insertions(+), 202 deletions(-)
create mode 100644 target-i386/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index b6c1dbe..01aaa18 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -520,208 +520,7 @@ static int put_packet(GDBState *s, const char *buf)
#if defined(TARGET_I386)
-#ifdef TARGET_X86_64
-static const int gpr_map[16] = {
- R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
- 8, 9, 10, 11, 12, 13, 14, 15
-};
-#else
-#define gpr_map gpr_map32
-#endif
-static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-
-#define IDX_IP_REG CPU_NB_REGS
-#define IDX_FLAGS_REG (IDX_IP_REG + 1)
-#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
-#define IDX_FP_REGS (IDX_SEG_REGS + 6)
-#define IDX_XMM_REGS (IDX_FP_REGS + 16)
-#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
-
-static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
-{
- if (n < CPU_NB_REGS) {
- if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
- GET_REG64(env->regs[gpr_map[n]]);
- } else if (n < CPU_NB_REGS32) {
- GET_REG32(env->regs[gpr_map32[n]]);
- }
- } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
-#ifdef USE_X86LDOUBLE
- /* FIXME: byteswap float values - after fixing fpregs layout. */
- memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
-#else
- memset(mem_buf, 0, 10);
-#endif
- return 10;
- } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
- n -= IDX_XMM_REGS;
- if (n < CPU_NB_REGS32 ||
- (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
- stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
- stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
- return 16;
- }
- } else {
- switch (n) {
- case IDX_IP_REG:
- if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
- GET_REG64(env->eip);
- } else {
- GET_REG32(env->eip);
- }
- case IDX_FLAGS_REG:
- GET_REG32(env->eflags);
-
- case IDX_SEG_REGS:
- GET_REG32(env->segs[R_CS].selector);
- case IDX_SEG_REGS + 1:
- GET_REG32(env->segs[R_SS].selector);
- case IDX_SEG_REGS + 2:
- GET_REG32(env->segs[R_DS].selector);
- case IDX_SEG_REGS + 3:
- GET_REG32(env->segs[R_ES].selector);
- case IDX_SEG_REGS + 4:
- GET_REG32(env->segs[R_FS].selector);
- case IDX_SEG_REGS + 5:
- GET_REG32(env->segs[R_GS].selector);
-
- case IDX_FP_REGS + 8:
- GET_REG32(env->fpuc);
- case IDX_FP_REGS + 9:
- GET_REG32((env->fpus & ~0x3800) |
- (env->fpstt & 0x7) << 11);
- case IDX_FP_REGS + 10:
- GET_REG32(0); /* ftag */
- case IDX_FP_REGS + 11:
- GET_REG32(0); /* fiseg */
- case IDX_FP_REGS + 12:
- GET_REG32(0); /* fioff */
- case IDX_FP_REGS + 13:
- GET_REG32(0); /* foseg */
- case IDX_FP_REGS + 14:
- GET_REG32(0); /* fooff */
- case IDX_FP_REGS + 15:
- GET_REG32(0); /* fop */
-
- case IDX_MXCSR_REG:
- GET_REG32(env->mxcsr);
- }
- }
- return 0;
-}
-
-static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
-{
- uint16_t selector = ldl_p(mem_buf);
-
- if (selector != env->segs[sreg].selector) {
-#if defined(CONFIG_USER_ONLY)
- cpu_x86_load_seg(env, sreg, selector);
-#else
- unsigned int limit, flags;
- target_ulong base;
-
- if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
- base = selector << 4;
- limit = 0xffff;
- flags = 0;
- } else {
- if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
- &flags)) {
- return 4;
- }
- }
- cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
-#endif
- }
- return 4;
-}
-
-static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
-{
- uint32_t tmp;
-
- if (n < CPU_NB_REGS) {
- if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
- env->regs[gpr_map[n]] = ldtul_p(mem_buf);
- return sizeof(target_ulong);
- } else if (n < CPU_NB_REGS32) {
- n = gpr_map32[n];
- env->regs[n] &= ~0xffffffffUL;
- env->regs[n] |= (uint32_t)ldl_p(mem_buf);
- return 4;
- }
- } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
-#ifdef USE_X86LDOUBLE
- /* FIXME: byteswap float values - after fixing fpregs layout. */
- memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
-#endif
- return 10;
- } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
- n -= IDX_XMM_REGS;
- if (n < CPU_NB_REGS32 ||
- (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
- env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
- env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
- return 16;
- }
- } else {
- switch (n) {
- case IDX_IP_REG:
- if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
- env->eip = ldq_p(mem_buf);
- return 8;
- } else {
- env->eip &= ~0xffffffffUL;
- env->eip |= (uint32_t)ldl_p(mem_buf);
- return 4;
- }
- case IDX_FLAGS_REG:
- env->eflags = ldl_p(mem_buf);
- return 4;
-
- case IDX_SEG_REGS:
- return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
- case IDX_SEG_REGS + 1:
- return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
- case IDX_SEG_REGS + 2:
- return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
- case IDX_SEG_REGS + 3:
- return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
- case IDX_SEG_REGS + 4:
- return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
- case IDX_SEG_REGS + 5:
- return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
-
- case IDX_FP_REGS + 8:
- env->fpuc = ldl_p(mem_buf);
- return 4;
- case IDX_FP_REGS + 9:
- tmp = ldl_p(mem_buf);
- env->fpstt = (tmp >> 11) & 7;
- env->fpus = tmp & ~0x3800;
- return 4;
- case IDX_FP_REGS + 10: /* ftag */
- return 4;
- case IDX_FP_REGS + 11: /* fiseg */
- return 4;
- case IDX_FP_REGS + 12: /* fioff */
- return 4;
- case IDX_FP_REGS + 13: /* foseg */
- return 4;
- case IDX_FP_REGS + 14: /* fooff */
- return 4;
- case IDX_FP_REGS + 15: /* fop */
- return 4;
-
- case IDX_MXCSR_REG:
- env->mxcsr = ldl_p(mem_buf);
- return 4;
- }
- }
- /* Unrecognised register. */
- return 0;
-}
+#include "target-i386/gdbstub.c"
#elif defined (TARGET_PPC)
diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c
new file mode 100644
index 0000000..974d8ad
--- /dev/null
+++ b/target-i386/gdbstub.c
@@ -0,0 +1,222 @@
+/*
+ * x86 gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef TARGET_X86_64
+static const int gpr_map[16] = {
+ R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
+ 8, 9, 10, 11, 12, 13, 14, 15
+};
+#else
+#define gpr_map gpr_map32
+#endif
+static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+#define IDX_IP_REG CPU_NB_REGS
+#define IDX_FLAGS_REG (IDX_IP_REG + 1)
+#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
+#define IDX_FP_REGS (IDX_SEG_REGS + 6)
+#define IDX_XMM_REGS (IDX_FP_REGS + 16)
+#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
+
+static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
+{
+ if (n < CPU_NB_REGS) {
+ if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
+ GET_REG64(env->regs[gpr_map[n]]);
+ } else if (n < CPU_NB_REGS32) {
+ GET_REG32(env->regs[gpr_map32[n]]);
+ }
+ } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
+#ifdef USE_X86LDOUBLE
+ /* FIXME: byteswap float values - after fixing fpregs layout. */
+ memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
+#else
+ memset(mem_buf, 0, 10);
+#endif
+ return 10;
+ } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
+ n -= IDX_XMM_REGS;
+ if (n < CPU_NB_REGS32 ||
+ (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
+ stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
+ stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
+ return 16;
+ }
+ } else {
+ switch (n) {
+ case IDX_IP_REG:
+ if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
+ GET_REG64(env->eip);
+ } else {
+ GET_REG32(env->eip);
+ }
+ case IDX_FLAGS_REG:
+ GET_REG32(env->eflags);
+
+ case IDX_SEG_REGS:
+ GET_REG32(env->segs[R_CS].selector);
+ case IDX_SEG_REGS + 1:
+ GET_REG32(env->segs[R_SS].selector);
+ case IDX_SEG_REGS + 2:
+ GET_REG32(env->segs[R_DS].selector);
+ case IDX_SEG_REGS + 3:
+ GET_REG32(env->segs[R_ES].selector);
+ case IDX_SEG_REGS + 4:
+ GET_REG32(env->segs[R_FS].selector);
+ case IDX_SEG_REGS + 5:
+ GET_REG32(env->segs[R_GS].selector);
+
+ case IDX_FP_REGS + 8:
+ GET_REG32(env->fpuc);
+ case IDX_FP_REGS + 9:
+ GET_REG32((env->fpus & ~0x3800) |
+ (env->fpstt & 0x7) << 11);
+ case IDX_FP_REGS + 10:
+ GET_REG32(0); /* ftag */
+ case IDX_FP_REGS + 11:
+ GET_REG32(0); /* fiseg */
+ case IDX_FP_REGS + 12:
+ GET_REG32(0); /* fioff */
+ case IDX_FP_REGS + 13:
+ GET_REG32(0); /* foseg */
+ case IDX_FP_REGS + 14:
+ GET_REG32(0); /* fooff */
+ case IDX_FP_REGS + 15:
+ GET_REG32(0); /* fop */
+
+ case IDX_MXCSR_REG:
+ GET_REG32(env->mxcsr);
+ }
+ }
+ return 0;
+}
+
+static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
+{
+ uint16_t selector = ldl_p(mem_buf);
+
+ if (selector != env->segs[sreg].selector) {
+#if defined(CONFIG_USER_ONLY)
+ cpu_x86_load_seg(env, sreg, selector);
+#else
+ unsigned int limit, flags;
+ target_ulong base;
+
+ if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
+ base = selector << 4;
+ limit = 0xffff;
+ flags = 0;
+ } else {
+ if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
+ &flags)) {
+ return 4;
+ }
+ }
+ cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
+#endif
+ }
+ return 4;
+}
+
+static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ if (n < CPU_NB_REGS) {
+ if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
+ env->regs[gpr_map[n]] = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n < CPU_NB_REGS32) {
+ n = gpr_map32[n];
+ env->regs[n] &= ~0xffffffffUL;
+ env->regs[n] |= (uint32_t)ldl_p(mem_buf);
+ return 4;
+ }
+ } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
+#ifdef USE_X86LDOUBLE
+ /* FIXME: byteswap float values - after fixing fpregs layout. */
+ memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
+#endif
+ return 10;
+ } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
+ n -= IDX_XMM_REGS;
+ if (n < CPU_NB_REGS32 ||
+ (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
+ env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
+ env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
+ return 16;
+ }
+ } else {
+ switch (n) {
+ case IDX_IP_REG:
+ if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
+ env->eip = ldq_p(mem_buf);
+ return 8;
+ } else {
+ env->eip &= ~0xffffffffUL;
+ env->eip |= (uint32_t)ldl_p(mem_buf);
+ return 4;
+ }
+ case IDX_FLAGS_REG:
+ env->eflags = ldl_p(mem_buf);
+ return 4;
+
+ case IDX_SEG_REGS:
+ return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
+ case IDX_SEG_REGS + 1:
+ return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
+ case IDX_SEG_REGS + 2:
+ return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
+ case IDX_SEG_REGS + 3:
+ return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
+ case IDX_SEG_REGS + 4:
+ return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
+ case IDX_SEG_REGS + 5:
+ return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
+
+ case IDX_FP_REGS + 8:
+ env->fpuc = ldl_p(mem_buf);
+ return 4;
+ case IDX_FP_REGS + 9:
+ tmp = ldl_p(mem_buf);
+ env->fpstt = (tmp >> 11) & 7;
+ env->fpus = tmp & ~0x3800;
+ return 4;
+ case IDX_FP_REGS + 10: /* ftag */
+ return 4;
+ case IDX_FP_REGS + 11: /* fiseg */
+ return 4;
+ case IDX_FP_REGS + 12: /* fioff */
+ return 4;
+ case IDX_FP_REGS + 13: /* foseg */
+ return 4;
+ case IDX_FP_REGS + 14: /* fooff */
+ return 4;
+ case IDX_FP_REGS + 15: /* fop */
+ return 4;
+
+ case IDX_MXCSR_REG:
+ env->mxcsr = ldl_p(mem_buf);
+ return 4;
+ }
+ }
+ /* Unrecognised register. */
+ return 0;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 26/42] target-ppc: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (24 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 25/42] target-i386: Move cpu_gdb_{read, write}_register() Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 27/42] target-sparc: " Andreas Färber
` (16 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: open list:PowerPC, Andreas Färber, Alexander Graf
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 101 +-----------------------------------------
target-ppc/gdbstub.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 123 insertions(+), 100 deletions(-)
create mode 100644 target-ppc/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 01aaa18..5acc496 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -524,112 +524,13 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_PPC)
-/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
- expects whatever the target description contains. Due to a
- historical mishap the FP registers appear in between core integer
- regs and PC, MSR, CR, and so forth. We hack round this by giving the
- FP regs zero size when talking to a newer gdb. */
#if defined (TARGET_PPC64)
#define GDB_CORE_XML "power64-core.xml"
#else
#define GDB_CORE_XML "power-core.xml"
#endif
-static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- /* gprs */
- GET_REGL(env->gpr[n]);
- } else if (n < 64) {
- /* fprs */
- if (gdb_has_xml) {
- return 0;
- }
- stfq_p(mem_buf, env->fpr[n-32]);
- return 8;
- } else {
- switch (n) {
- case 64:
- GET_REGL(env->nip);
- case 65:
- GET_REGL(env->msr);
- case 66:
- {
- uint32_t cr = 0;
- int i;
- for (i = 0; i < 8; i++) {
- cr |= env->crf[i] << (32 - ((i + 1) * 4));
- }
- GET_REG32(cr);
- }
- case 67:
- GET_REGL(env->lr);
- case 68:
- GET_REGL(env->ctr);
- case 69:
- GET_REGL(env->xer);
- case 70:
- {
- if (gdb_has_xml) {
- return 0;
- }
- GET_REG32(env->fpscr);
- }
- }
- }
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- /* gprs */
- env->gpr[n] = ldtul_p(mem_buf);
- return sizeof(target_ulong);
- } else if (n < 64) {
- /* fprs */
- if (gdb_has_xml) {
- return 0;
- }
- env->fpr[n-32] = ldfq_p(mem_buf);
- return 8;
- } else {
- switch (n) {
- case 64:
- env->nip = ldtul_p(mem_buf);
- return sizeof(target_ulong);
- case 65:
- ppc_store_msr(env, ldtul_p(mem_buf));
- return sizeof(target_ulong);
- case 66:
- {
- uint32_t cr = ldl_p(mem_buf);
- int i;
- for (i = 0; i < 8; i++) {
- env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
- }
- return 4;
- }
- case 67:
- env->lr = ldtul_p(mem_buf);
- return sizeof(target_ulong);
- case 68:
- env->ctr = ldtul_p(mem_buf);
- return sizeof(target_ulong);
- case 69:
- env->xer = ldtul_p(mem_buf);
- return sizeof(target_ulong);
- case 70:
- /* fpscr */
- if (gdb_has_xml) {
- return 0;
- }
- store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
- return sizeof(target_ulong);
- }
- }
- return 0;
-}
+#include "target-ppc/gdbstub.c"
#elif defined (TARGET_SPARC)
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
new file mode 100644
index 0000000..b834e60
--- /dev/null
+++ b/target-ppc/gdbstub.c
@@ -0,0 +1,122 @@
+/*
+ * PowerPC gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
+ * expects whatever the target description contains. Due to a
+ * historical mishap the FP registers appear in between core integer
+ * regs and PC, MSR, CR, and so forth. We hack round this by giving the
+ * FP regs zero size when talking to a newer gdb.
+ */
+
+static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ /* gprs */
+ GET_REGL(env->gpr[n]);
+ } else if (n < 64) {
+ /* fprs */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ stfq_p(mem_buf, env->fpr[n-32]);
+ return 8;
+ } else {
+ switch (n) {
+ case 64:
+ GET_REGL(env->nip);
+ case 65:
+ GET_REGL(env->msr);
+ case 66:
+ {
+ uint32_t cr = 0;
+ int i;
+ for (i = 0; i < 8; i++) {
+ cr |= env->crf[i] << (32 - ((i + 1) * 4));
+ }
+ GET_REG32(cr);
+ }
+ case 67:
+ GET_REGL(env->lr);
+ case 68:
+ GET_REGL(env->ctr);
+ case 69:
+ GET_REGL(env->xer);
+ case 70:
+ {
+ if (gdb_has_xml) {
+ return 0;
+ }
+ GET_REG32(env->fpscr);
+ }
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ /* gprs */
+ env->gpr[n] = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n < 64) {
+ /* fprs */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ env->fpr[n-32] = ldfq_p(mem_buf);
+ return 8;
+ } else {
+ switch (n) {
+ case 64:
+ env->nip = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ case 65:
+ ppc_store_msr(env, ldtul_p(mem_buf));
+ return sizeof(target_ulong);
+ case 66:
+ {
+ uint32_t cr = ldl_p(mem_buf);
+ int i;
+ for (i = 0; i < 8; i++) {
+ env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
+ }
+ return 4;
+ }
+ case 67:
+ env->lr = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ case 68:
+ env->ctr = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ case 69:
+ env->xer = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ case 70:
+ /* fpscr */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
+ return sizeof(target_ulong);
+ }
+ }
+ return 0;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 27/42] target-sparc: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (25 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 26/42] target-ppc: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 28/42] target-arm: " Andreas Färber
` (15 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 180 +-------------------------------------------
target-sparc/gdbstub.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 201 insertions(+), 179 deletions(-)
create mode 100644 target-sparc/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 5acc496..317c86d 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -534,186 +534,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_SPARC)
-#ifdef TARGET_ABI32
-#define GET_REGA(val) GET_REG32(val)
-#else
-#define GET_REGA(val) GET_REGL(val)
-#endif
+#include "target-sparc/gdbstub.c"
-static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 8) {
- /* g0..g7 */
- GET_REGA(env->gregs[n]);
- }
- if (n < 32) {
- /* register window */
- GET_REGA(env->regwptr[n - 8]);
- }
-#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
- if (n < 64) {
- /* fprs */
- if (n & 1) {
- GET_REG32(env->fpr[(n - 32) / 2].l.lower);
- } else {
- GET_REG32(env->fpr[(n - 32) / 2].l.upper);
- }
- }
- /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
- switch (n) {
- case 64:
- GET_REGA(env->y);
- case 65:
- GET_REGA(cpu_get_psr(env));
- case 66:
- GET_REGA(env->wim);
- case 67:
- GET_REGA(env->tbr);
- case 68:
- GET_REGA(env->pc);
- case 69:
- GET_REGA(env->npc);
- case 70:
- GET_REGA(env->fsr);
- case 71:
- GET_REGA(0); /* csr */
- default:
- GET_REGA(0);
- }
-#else
- if (n < 64) {
- /* f0-f31 */
- if (n & 1) {
- GET_REG32(env->fpr[(n - 32) / 2].l.lower);
- } else {
- GET_REG32(env->fpr[(n - 32) / 2].l.upper);
- }
- }
- if (n < 80) {
- /* f32-f62 (double width, even numbers only) */
- GET_REG64(env->fpr[(n - 32) / 2].ll);
- }
- switch (n) {
- case 80:
- GET_REGL(env->pc);
- case 81:
- GET_REGL(env->npc);
- case 82:
- GET_REGL((cpu_get_ccr(env) << 32) |
- ((env->asi & 0xff) << 24) |
- ((env->pstate & 0xfff) << 8) |
- cpu_get_cwp64(env));
- case 83:
- GET_REGL(env->fsr);
- case 84:
- GET_REGL(env->fprs);
- case 85:
- GET_REGL(env->y);
- }
-#endif
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
-{
-#if defined(TARGET_ABI32)
- abi_ulong tmp;
-
- tmp = ldl_p(mem_buf);
-#else
- target_ulong tmp;
-
- tmp = ldtul_p(mem_buf);
-#endif
-
- if (n < 8) {
- /* g0..g7 */
- env->gregs[n] = tmp;
- } else if (n < 32) {
- /* register window */
- env->regwptr[n - 8] = tmp;
- }
-#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
- else if (n < 64) {
- /* fprs */
- /* f0-f31 */
- if (n & 1) {
- env->fpr[(n - 32) / 2].l.lower = tmp;
- } else {
- env->fpr[(n - 32) / 2].l.upper = tmp;
- }
- } else {
- /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
- switch (n) {
- case 64:
- env->y = tmp;
- break;
- case 65:
- cpu_put_psr(env, tmp);
- break;
- case 66:
- env->wim = tmp;
- break;
- case 67:
- env->tbr = tmp;
- break;
- case 68:
- env->pc = tmp;
- break;
- case 69:
- env->npc = tmp;
- break;
- case 70:
- env->fsr = tmp;
- break;
- default:
- return 0;
- }
- }
- return 4;
-#else
- else if (n < 64) {
- /* f0-f31 */
- tmp = ldl_p(mem_buf);
- if (n & 1) {
- env->fpr[(n - 32) / 2].l.lower = tmp;
- } else {
- env->fpr[(n - 32) / 2].l.upper = tmp;
- }
- return 4;
- } else if (n < 80) {
- /* f32-f62 (double width, even numbers only) */
- env->fpr[(n - 32) / 2].ll = tmp;
- } else {
- switch (n) {
- case 80:
- env->pc = tmp;
- break;
- case 81:
- env->npc = tmp;
- break;
- case 82:
- cpu_put_ccr(env, tmp >> 32);
- env->asi = (tmp >> 24) & 0xff;
- env->pstate = (tmp >> 8) & 0xfff;
- cpu_put_cwp64(env, tmp & 0xff);
- break;
- case 83:
- env->fsr = tmp;
- break;
- case 84:
- env->fprs = tmp;
- break;
- case 85:
- env->y = tmp;
- break;
- default:
- return 0;
- }
- }
- return 8;
-#endif
-}
#elif defined (TARGET_ARM)
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
diff --git a/target-sparc/gdbstub.c b/target-sparc/gdbstub.c
new file mode 100644
index 0000000..914f586
--- /dev/null
+++ b/target-sparc/gdbstub.c
@@ -0,0 +1,200 @@
+/*
+ * SPARC gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef TARGET_ABI32
+#define GET_REGA(val) GET_REG32(val)
+#else
+#define GET_REGA(val) GET_REGL(val)
+#endif
+
+static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 8) {
+ /* g0..g7 */
+ GET_REGA(env->gregs[n]);
+ }
+ if (n < 32) {
+ /* register window */
+ GET_REGA(env->regwptr[n - 8]);
+ }
+#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
+ if (n < 64) {
+ /* fprs */
+ if (n & 1) {
+ GET_REG32(env->fpr[(n - 32) / 2].l.lower);
+ } else {
+ GET_REG32(env->fpr[(n - 32) / 2].l.upper);
+ }
+ }
+ /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
+ switch (n) {
+ case 64:
+ GET_REGA(env->y);
+ case 65:
+ GET_REGA(cpu_get_psr(env));
+ case 66:
+ GET_REGA(env->wim);
+ case 67:
+ GET_REGA(env->tbr);
+ case 68:
+ GET_REGA(env->pc);
+ case 69:
+ GET_REGA(env->npc);
+ case 70:
+ GET_REGA(env->fsr);
+ case 71:
+ GET_REGA(0); /* csr */
+ default:
+ GET_REGA(0);
+ }
+#else
+ if (n < 64) {
+ /* f0-f31 */
+ if (n & 1) {
+ GET_REG32(env->fpr[(n - 32) / 2].l.lower);
+ } else {
+ GET_REG32(env->fpr[(n - 32) / 2].l.upper);
+ }
+ }
+ if (n < 80) {
+ /* f32-f62 (double width, even numbers only) */
+ GET_REG64(env->fpr[(n - 32) / 2].ll);
+ }
+ switch (n) {
+ case 80:
+ GET_REGL(env->pc);
+ case 81:
+ GET_REGL(env->npc);
+ case 82:
+ GET_REGL((cpu_get_ccr(env) << 32) |
+ ((env->asi & 0xff) << 24) |
+ ((env->pstate & 0xfff) << 8) |
+ cpu_get_cwp64(env));
+ case 83:
+ GET_REGL(env->fsr);
+ case 84:
+ GET_REGL(env->fprs);
+ case 85:
+ GET_REGL(env->y);
+ }
+#endif
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
+{
+#if defined(TARGET_ABI32)
+ abi_ulong tmp;
+
+ tmp = ldl_p(mem_buf);
+#else
+ target_ulong tmp;
+
+ tmp = ldtul_p(mem_buf);
+#endif
+
+ if (n < 8) {
+ /* g0..g7 */
+ env->gregs[n] = tmp;
+ } else if (n < 32) {
+ /* register window */
+ env->regwptr[n - 8] = tmp;
+ }
+#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
+ else if (n < 64) {
+ /* fprs */
+ /* f0-f31 */
+ if (n & 1) {
+ env->fpr[(n - 32) / 2].l.lower = tmp;
+ } else {
+ env->fpr[(n - 32) / 2].l.upper = tmp;
+ }
+ } else {
+ /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
+ switch (n) {
+ case 64:
+ env->y = tmp;
+ break;
+ case 65:
+ cpu_put_psr(env, tmp);
+ break;
+ case 66:
+ env->wim = tmp;
+ break;
+ case 67:
+ env->tbr = tmp;
+ break;
+ case 68:
+ env->pc = tmp;
+ break;
+ case 69:
+ env->npc = tmp;
+ break;
+ case 70:
+ env->fsr = tmp;
+ break;
+ default:
+ return 0;
+ }
+ }
+ return 4;
+#else
+ else if (n < 64) {
+ /* f0-f31 */
+ tmp = ldl_p(mem_buf);
+ if (n & 1) {
+ env->fpr[(n - 32) / 2].l.lower = tmp;
+ } else {
+ env->fpr[(n - 32) / 2].l.upper = tmp;
+ }
+ return 4;
+ } else if (n < 80) {
+ /* f32-f62 (double width, even numbers only) */
+ env->fpr[(n - 32) / 2].ll = tmp;
+ } else {
+ switch (n) {
+ case 80:
+ env->pc = tmp;
+ break;
+ case 81:
+ env->npc = tmp;
+ break;
+ case 82:
+ cpu_put_ccr(env, tmp >> 32);
+ env->asi = (tmp >> 24) & 0xff;
+ env->pstate = (tmp >> 8) & 0xfff;
+ cpu_put_cwp64(env, tmp & 0xff);
+ break;
+ case 83:
+ env->fsr = tmp;
+ break;
+ case 84:
+ env->fprs = tmp;
+ break;
+ case 85:
+ env->y = tmp;
+ break;
+ default:
+ return 0;
+ }
+ }
+ return 8;
+#endif
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 28/42] target-arm: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (26 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 27/42] target-sparc: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 29/42] target-m68k: " Andreas Färber
` (14 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 74 +----------------------------------------
target-arm/gdbstub.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 95 insertions(+), 73 deletions(-)
create mode 100644 target-arm/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 317c86d..f2e0d73 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -538,81 +538,9 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_ARM)
-/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
- whatever the target description contains. Due to a historical mishap
- the FPA registers appear in between core integer regs and the CPSR.
- We hack round this by giving the FPA regs zero size when talking to a
- newer gdb. */
#define GDB_CORE_XML "arm-core.xml"
-static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
-{
- if (n < 16) {
- /* Core integer register. */
- GET_REG32(env->regs[n]);
- }
- if (n < 24) {
- /* FPA registers. */
- if (gdb_has_xml) {
- return 0;
- }
- memset(mem_buf, 0, 12);
- return 12;
- }
- switch (n) {
- case 24:
- /* FPA status register. */
- if (gdb_has_xml) {
- return 0;
- }
- GET_REG32(0);
- case 25:
- /* CPSR */
- GET_REG32(cpsr_read(env));
- }
- /* Unknown register. */
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
-{
- uint32_t tmp;
-
- tmp = ldl_p(mem_buf);
-
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
- cause problems if we ever implement the Jazelle DBX extensions. */
- if (n == 15) {
- tmp &= ~1;
- }
-
- if (n < 16) {
- /* Core integer register. */
- env->regs[n] = tmp;
- return 4;
- }
- if (n < 24) { /* 16-23 */
- /* FPA registers (ignored). */
- if (gdb_has_xml) {
- return 0;
- }
- return 12;
- }
- switch (n) {
- case 24:
- /* FPA status register (ignored). */
- if (gdb_has_xml) {
- return 0;
- }
- return 4;
- case 25:
- /* CPSR */
- cpsr_write(env, tmp, 0xffffffff);
- return 4;
- }
- /* Unknown register. */
- return 0;
-}
+#include "target-arm/gdbstub.c"
#elif defined (TARGET_M68K)
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
new file mode 100644
index 0000000..74903a3
--- /dev/null
+++ b/target-arm/gdbstub.c
@@ -0,0 +1,94 @@
+/*
+ * ARM gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
+ whatever the target description contains. Due to a historical mishap
+ the FPA registers appear in between core integer regs and the CPSR.
+ We hack round this by giving the FPA regs zero size when talking to a
+ newer gdb. */
+
+static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 16) {
+ /* Core integer register. */
+ GET_REG32(env->regs[n]);
+ }
+ if (n < 24) {
+ /* FPA registers. */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ memset(mem_buf, 0, 12);
+ return 12;
+ }
+ switch (n) {
+ case 24:
+ /* FPA status register. */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ GET_REG32(0);
+ case 25:
+ /* CPSR */
+ GET_REG32(cpsr_read(env));
+ }
+ /* Unknown register. */
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ tmp = ldl_p(mem_buf);
+
+ /* Mask out low bit of PC to workaround gdb bugs. This will probably
+ cause problems if we ever implement the Jazelle DBX extensions. */
+ if (n == 15) {
+ tmp &= ~1;
+ }
+
+ if (n < 16) {
+ /* Core integer register. */
+ env->regs[n] = tmp;
+ return 4;
+ }
+ if (n < 24) { /* 16-23 */
+ /* FPA registers (ignored). */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ return 12;
+ }
+ switch (n) {
+ case 24:
+ /* FPA status register (ignored). */
+ if (gdb_has_xml) {
+ return 0;
+ }
+ return 4;
+ case 25:
+ /* CPSR */
+ cpsr_write(env, tmp, 0xffffffff);
+ return 4;
+ }
+ /* Unknown register. */
+ return 0;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 29/42] target-m68k: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (27 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 28/42] target-arm: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 30/42] target-mips: " Andreas Färber
` (13 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 47 +-----------------------------------
target-m68k/gdbstub.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+), 46 deletions(-)
create mode 100644 target-m68k/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index f2e0d73..6f6f7b5 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -546,53 +546,8 @@ static int put_packet(GDBState *s, const char *buf)
#define GDB_CORE_XML "cf-core.xml"
-static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
-{
- if (n < 8) {
- /* D0-D7 */
- GET_REG32(env->dregs[n]);
- } else if (n < 16) {
- /* A0-A7 */
- GET_REG32(env->aregs[n - 8]);
- } else {
- switch (n) {
- case 16:
- GET_REG32(env->sr);
- case 17:
- GET_REG32(env->pc);
- }
- }
- /* FP registers not included here because they vary between
- ColdFire and m68k. Use XML bits for these. */
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
-{
- uint32_t tmp;
-
- tmp = ldl_p(mem_buf);
+#include "target-m68k/gdbstub.c"
- if (n < 8) {
- /* D0-D7 */
- env->dregs[n] = tmp;
- } else if (n < 16) {
- /* A0-A7 */
- env->aregs[n - 8] = tmp;
- } else {
- switch (n) {
- case 16:
- env->sr = tmp;
- break;
- case 17:
- env->pc = tmp;
- break;
- default:
- return 0;
- }
- }
- return 4;
-}
#elif defined (TARGET_MIPS)
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
diff --git a/target-m68k/gdbstub.c b/target-m68k/gdbstub.c
new file mode 100644
index 0000000..2eb4b98
--- /dev/null
+++ b/target-m68k/gdbstub.c
@@ -0,0 +1,67 @@
+/*
+ * m68k gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 8) {
+ /* D0-D7 */
+ GET_REG32(env->dregs[n]);
+ } else if (n < 16) {
+ /* A0-A7 */
+ GET_REG32(env->aregs[n - 8]);
+ } else {
+ switch (n) {
+ case 16:
+ GET_REG32(env->sr);
+ case 17:
+ GET_REG32(env->pc);
+ }
+ }
+ /* FP registers not included here because they vary between
+ ColdFire and m68k. Use XML bits for these. */
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 8) {
+ /* D0-D7 */
+ env->dregs[n] = tmp;
+ } else if (n < 16) {
+ /* A0-A7 */
+ env->aregs[n - 8] = tmp;
+ } else {
+ switch (n) {
+ case 16:
+ env->sr = tmp;
+ break;
+ case 17:
+ env->pc = tmp;
+ break;
+ default:
+ return 0;
+ }
+ }
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 30/42] target-mips: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (28 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 29/42] target-m68k: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 31/42] target-openrisc: " Andreas Färber
` (12 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 124 +------------------------------------------
target-mips/gdbstub.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 145 insertions(+), 123 deletions(-)
create mode 100644 target-mips/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 6f6f7b5..5018b34 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -550,130 +550,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_MIPS)
-static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- GET_REGL(env->active_tc.gpr[n]);
- }
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- if (n >= 38 && n < 70) {
- if (env->CP0_Status & (1 << CP0St_FR)) {
- GET_REGL(env->active_fpu.fpr[n - 38].d);
- } else {
- GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
- }
- }
- switch (n) {
- case 70:
- GET_REGL((int32_t)env->active_fpu.fcr31);
- case 71:
- GET_REGL((int32_t)env->active_fpu.fcr0);
- }
- }
- switch (n) {
- case 32:
- GET_REGL((int32_t)env->CP0_Status);
- case 33:
- GET_REGL(env->active_tc.LO[0]);
- case 34:
- GET_REGL(env->active_tc.HI[0]);
- case 35:
- GET_REGL(env->CP0_BadVAddr);
- case 36:
- GET_REGL((int32_t)env->CP0_Cause);
- case 37:
- GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
- case 72:
- GET_REGL(0); /* fp */
- case 89:
- GET_REGL((int32_t)env->CP0_PRid);
- }
- if (n >= 73 && n <= 88) {
- /* 16 embedded regs. */
- GET_REGL(0);
- }
-
- return 0;
-}
-
-/* convert MIPS rounding mode in FCR31 to IEEE library */
-static unsigned int ieee_rm[] = {
- float_round_nearest_even,
- float_round_to_zero,
- float_round_up,
- float_round_down
-};
-#define RESTORE_ROUNDING_MODE \
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
- &env->active_fpu.fp_status)
-
-static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
-{
- target_ulong tmp;
-
- tmp = ldtul_p(mem_buf);
-
- if (n < 32) {
- env->active_tc.gpr[n] = tmp;
- return sizeof(target_ulong);
- }
- if (env->CP0_Config1 & (1 << CP0C1_FP)
- && n >= 38 && n < 73) {
- if (n < 70) {
- if (env->CP0_Status & (1 << CP0St_FR)) {
- env->active_fpu.fpr[n - 38].d = tmp;
- } else {
- env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
- }
- }
- switch (n) {
- case 70:
- env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
- /* set rounding mode */
- RESTORE_ROUNDING_MODE;
- break;
- case 71:
- env->active_fpu.fcr0 = tmp;
- break;
- }
- return sizeof(target_ulong);
- }
- switch (n) {
- case 32:
- env->CP0_Status = tmp;
- break;
- case 33:
- env->active_tc.LO[0] = tmp;
- break;
- case 34:
- env->active_tc.HI[0] = tmp;
- break;
- case 35:
- env->CP0_BadVAddr = tmp;
- break;
- case 36:
- env->CP0_Cause = tmp;
- break;
- case 37:
- env->active_tc.PC = tmp & ~(target_ulong)1;
- if (tmp & 1) {
- env->hflags |= MIPS_HFLAG_M16;
- } else {
- env->hflags &= ~(MIPS_HFLAG_M16);
- }
- break;
- case 72: /* fp, ignored */
- break;
- default:
- if (n > 89) {
- return 0;
- }
- /* Other registers are readonly. Ignore writes. */
- break;
- }
+#include "target-mips/gdbstub.c"
- return sizeof(target_ulong);
-}
#elif defined(TARGET_OPENRISC)
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
new file mode 100644
index 0000000..15dc281
--- /dev/null
+++ b/target-mips/gdbstub.c
@@ -0,0 +1,144 @@
+/*
+ * MIPS gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ GET_REGL(env->active_tc.gpr[n]);
+ }
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ if (n >= 38 && n < 70) {
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ GET_REGL(env->active_fpu.fpr[n - 38].d);
+ } else {
+ GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
+ }
+ }
+ switch (n) {
+ case 70:
+ GET_REGL((int32_t)env->active_fpu.fcr31);
+ case 71:
+ GET_REGL((int32_t)env->active_fpu.fcr0);
+ }
+ }
+ switch (n) {
+ case 32:
+ GET_REGL((int32_t)env->CP0_Status);
+ case 33:
+ GET_REGL(env->active_tc.LO[0]);
+ case 34:
+ GET_REGL(env->active_tc.HI[0]);
+ case 35:
+ GET_REGL(env->CP0_BadVAddr);
+ case 36:
+ GET_REGL((int32_t)env->CP0_Cause);
+ case 37:
+ GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
+ case 72:
+ GET_REGL(0); /* fp */
+ case 89:
+ GET_REGL((int32_t)env->CP0_PRid);
+ }
+ if (n >= 73 && n <= 88) {
+ /* 16 embedded regs. */
+ GET_REGL(0);
+ }
+
+ return 0;
+}
+
+/* convert MIPS rounding mode in FCR31 to IEEE library */
+static unsigned int ieee_rm[] = {
+ float_round_nearest_even,
+ float_round_to_zero,
+ float_round_up,
+ float_round_down
+};
+#define RESTORE_ROUNDING_MODE \
+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
+ &env->active_fpu.fp_status)
+
+static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
+{
+ target_ulong tmp;
+
+ tmp = ldtul_p(mem_buf);
+
+ if (n < 32) {
+ env->active_tc.gpr[n] = tmp;
+ return sizeof(target_ulong);
+ }
+ if (env->CP0_Config1 & (1 << CP0C1_FP)
+ && n >= 38 && n < 73) {
+ if (n < 70) {
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ env->active_fpu.fpr[n - 38].d = tmp;
+ } else {
+ env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
+ }
+ }
+ switch (n) {
+ case 70:
+ env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
+ /* set rounding mode */
+ RESTORE_ROUNDING_MODE;
+ break;
+ case 71:
+ env->active_fpu.fcr0 = tmp;
+ break;
+ }
+ return sizeof(target_ulong);
+ }
+ switch (n) {
+ case 32:
+ env->CP0_Status = tmp;
+ break;
+ case 33:
+ env->active_tc.LO[0] = tmp;
+ break;
+ case 34:
+ env->active_tc.HI[0] = tmp;
+ break;
+ case 35:
+ env->CP0_BadVAddr = tmp;
+ break;
+ case 36:
+ env->CP0_Cause = tmp;
+ break;
+ case 37:
+ env->active_tc.PC = tmp & ~(target_ulong)1;
+ if (tmp & 1) {
+ env->hflags |= MIPS_HFLAG_M16;
+ } else {
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ }
+ break;
+ case 72: /* fp, ignored */
+ break;
+ default:
+ if (n > 89) {
+ return 0;
+ }
+ /* Other registers are readonly. Ignore writes. */
+ break;
+ }
+
+ return sizeof(target_ulong);
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 31/42] target-openrisc: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (29 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 30/42] target-mips: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 32/42] target-sh4: " Andreas Färber
` (11 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Jia Liu
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 57 +----------------------------------
target-openrisc/gdbstub.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+), 56 deletions(-)
create mode 100644 target-openrisc/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 5018b34..9ce7fab 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -554,63 +554,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined(TARGET_OPENRISC)
-static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- GET_REG32(env->gpr[n]);
- } else {
- switch (n) {
- case 32: /* PPC */
- GET_REG32(env->ppc);
-
- case 33: /* NPC */
- GET_REG32(env->npc);
-
- case 34: /* SR */
- GET_REG32(env->sr);
-
- default:
- break;
- }
- }
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUOpenRISCState *env,
- uint8_t *mem_buf, int n)
-{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
- uint32_t tmp;
-
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
- tmp = ldl_p(mem_buf);
-
- if (n < 32) {
- env->gpr[n] = tmp;
- } else {
- switch (n) {
- case 32: /* PPC */
- env->ppc = tmp;
- break;
+#include "target-openrisc/gdbstub.c"
- case 33: /* NPC */
- env->npc = tmp;
- break;
-
- case 34: /* SR */
- env->sr = tmp;
- break;
-
- default:
- break;
- }
- }
- return 4;
-}
#elif defined (TARGET_SH4)
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
new file mode 100644
index 0000000..fba096a
--- /dev/null
+++ b/target-openrisc/gdbstub.c
@@ -0,0 +1,77 @@
+/*
+ * OpenRISC gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ GET_REG32(env->gpr[n]);
+ } else {
+ switch (n) {
+ case 32: /* PPC */
+ GET_REG32(env->ppc);
+
+ case 33: /* NPC */
+ GET_REG32(env->npc);
+
+ case 34: /* SR */
+ GET_REG32(env->sr);
+
+ default:
+ break;
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUOpenRISCState *env,
+ uint8_t *mem_buf, int n)
+{
+ OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ uint32_t tmp;
+
+ if (n > cc->gdb_num_core_regs) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 32) {
+ env->gpr[n] = tmp;
+ } else {
+ switch (n) {
+ case 32: /* PPC */
+ env->ppc = tmp;
+ break;
+
+ case 33: /* NPC */
+ env->npc = tmp;
+ break;
+
+ case 34: /* SR */
+ env->sr = tmp;
+ break;
+
+ default:
+ break;
+ }
+ }
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 32/42] target-sh4: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (30 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 31/42] target-openrisc: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 33/42] target-microblaze: " Andreas Färber
` (10 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 117 +------------------------------------------
target-sh4/gdbstub.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 138 insertions(+), 116 deletions(-)
create mode 100644 target-sh4/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 9ce7fab..1e449f9 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -558,123 +558,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_SH4)
-/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
-/* FIXME: We should use XML for this. */
+#include "target-sh4/gdbstub.c"
-static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
-{
- switch (n) {
- case 0 ... 7:
- if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
- GET_REGL(env->gregs[n + 16]);
- } else {
- GET_REGL(env->gregs[n]);
- }
- case 8 ... 15:
- GET_REGL(env->gregs[n]);
- case 16:
- GET_REGL(env->pc);
- case 17:
- GET_REGL(env->pr);
- case 18:
- GET_REGL(env->gbr);
- case 19:
- GET_REGL(env->vbr);
- case 20:
- GET_REGL(env->mach);
- case 21:
- GET_REGL(env->macl);
- case 22:
- GET_REGL(env->sr);
- case 23:
- GET_REGL(env->fpul);
- case 24:
- GET_REGL(env->fpscr);
- case 25 ... 40:
- if (env->fpscr & FPSCR_FR) {
- stfl_p(mem_buf, env->fregs[n - 9]);
- } else {
- stfl_p(mem_buf, env->fregs[n - 25]);
- }
- return 4;
- case 41:
- GET_REGL(env->ssr);
- case 42:
- GET_REGL(env->spc);
- case 43 ... 50:
- GET_REGL(env->gregs[n - 43]);
- case 51 ... 58:
- GET_REGL(env->gregs[n - (51 - 16)]);
- }
-
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
-{
- switch (n) {
- case 0 ... 7:
- if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
- env->gregs[n + 16] = ldl_p(mem_buf);
- } else {
- env->gregs[n] = ldl_p(mem_buf);
- }
- break;
- case 8 ... 15:
- env->gregs[n] = ldl_p(mem_buf);
- break;
- case 16:
- env->pc = ldl_p(mem_buf);
- break;
- case 17:
- env->pr = ldl_p(mem_buf);
- break;
- case 18:
- env->gbr = ldl_p(mem_buf);
- break;
- case 19:
- env->vbr = ldl_p(mem_buf);
- break;
- case 20:
- env->mach = ldl_p(mem_buf);
- break;
- case 21:
- env->macl = ldl_p(mem_buf);
- break;
- case 22:
- env->sr = ldl_p(mem_buf);
- break;
- case 23:
- env->fpul = ldl_p(mem_buf);
- break;
- case 24:
- env->fpscr = ldl_p(mem_buf);
- break;
- case 25 ... 40:
- if (env->fpscr & FPSCR_FR) {
- env->fregs[n - 9] = ldfl_p(mem_buf);
- } else {
- env->fregs[n - 25] = ldfl_p(mem_buf);
- }
- break;
- case 41:
- env->ssr = ldl_p(mem_buf);
- break;
- case 42:
- env->spc = ldl_p(mem_buf);
- break;
- case 43 ... 50:
- env->gregs[n - 43] = ldl_p(mem_buf);
- break;
- case 51 ... 58:
- env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
- break;
- default:
- return 0;
- }
-
- return 4;
-}
#elif defined (TARGET_MICROBLAZE)
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
diff --git a/target-sh4/gdbstub.c b/target-sh4/gdbstub.c
new file mode 100644
index 0000000..38bc630
--- /dev/null
+++ b/target-sh4/gdbstub.c
@@ -0,0 +1,137 @@
+/*
+ * SuperH gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
+/* FIXME: We should use XML for this. */
+
+static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
+{
+ switch (n) {
+ case 0 ... 7:
+ if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
+ GET_REGL(env->gregs[n + 16]);
+ } else {
+ GET_REGL(env->gregs[n]);
+ }
+ case 8 ... 15:
+ GET_REGL(env->gregs[n]);
+ case 16:
+ GET_REGL(env->pc);
+ case 17:
+ GET_REGL(env->pr);
+ case 18:
+ GET_REGL(env->gbr);
+ case 19:
+ GET_REGL(env->vbr);
+ case 20:
+ GET_REGL(env->mach);
+ case 21:
+ GET_REGL(env->macl);
+ case 22:
+ GET_REGL(env->sr);
+ case 23:
+ GET_REGL(env->fpul);
+ case 24:
+ GET_REGL(env->fpscr);
+ case 25 ... 40:
+ if (env->fpscr & FPSCR_FR) {
+ stfl_p(mem_buf, env->fregs[n - 9]);
+ } else {
+ stfl_p(mem_buf, env->fregs[n - 25]);
+ }
+ return 4;
+ case 41:
+ GET_REGL(env->ssr);
+ case 42:
+ GET_REGL(env->spc);
+ case 43 ... 50:
+ GET_REGL(env->gregs[n - 43]);
+ case 51 ... 58:
+ GET_REGL(env->gregs[n - (51 - 16)]);
+ }
+
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
+{
+ switch (n) {
+ case 0 ... 7:
+ if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
+ env->gregs[n + 16] = ldl_p(mem_buf);
+ } else {
+ env->gregs[n] = ldl_p(mem_buf);
+ }
+ break;
+ case 8 ... 15:
+ env->gregs[n] = ldl_p(mem_buf);
+ break;
+ case 16:
+ env->pc = ldl_p(mem_buf);
+ break;
+ case 17:
+ env->pr = ldl_p(mem_buf);
+ break;
+ case 18:
+ env->gbr = ldl_p(mem_buf);
+ break;
+ case 19:
+ env->vbr = ldl_p(mem_buf);
+ break;
+ case 20:
+ env->mach = ldl_p(mem_buf);
+ break;
+ case 21:
+ env->macl = ldl_p(mem_buf);
+ break;
+ case 22:
+ env->sr = ldl_p(mem_buf);
+ break;
+ case 23:
+ env->fpul = ldl_p(mem_buf);
+ break;
+ case 24:
+ env->fpscr = ldl_p(mem_buf);
+ break;
+ case 25 ... 40:
+ if (env->fpscr & FPSCR_FR) {
+ env->fregs[n - 9] = ldfl_p(mem_buf);
+ } else {
+ env->fregs[n - 25] = ldfl_p(mem_buf);
+ }
+ break;
+ case 41:
+ env->ssr = ldl_p(mem_buf);
+ break;
+ case 42:
+ env->spc = ldl_p(mem_buf);
+ break;
+ case 43 ... 50:
+ env->gregs[n - 43] = ldl_p(mem_buf);
+ break;
+ case 51 ... 58:
+ env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
+ break;
+ default:
+ return 0;
+ }
+
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 33/42] target-microblaze: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (31 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 32/42] target-sh4: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 34/42] target-cris: " Andreas Färber
` (9 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 29 +--------------------------
target-microblaze/gdbstub.c | 49 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 28 deletions(-)
create mode 100644 target-microblaze/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 1e449f9..8fe149a 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -562,35 +562,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_MICROBLAZE)
-static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- GET_REG32(env->regs[n]);
- } else {
- GET_REG32(env->sregs[n - 32]);
- }
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
-{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
- uint32_t tmp;
+#include "target-microblaze/gdbstub.c"
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
- tmp = ldl_p(mem_buf);
-
- if (n < 32) {
- env->regs[n] = tmp;
- } else {
- env->sregs[n - 32] = tmp;
- }
- return 4;
-}
#elif defined (TARGET_CRIS)
static int
diff --git a/target-microblaze/gdbstub.c b/target-microblaze/gdbstub.c
new file mode 100644
index 0000000..96c4bc0
--- /dev/null
+++ b/target-microblaze/gdbstub.c
@@ -0,0 +1,49 @@
+/*
+ * MicroBlaze gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ GET_REG32(env->regs[n]);
+ } else {
+ GET_REG32(env->sregs[n - 32]);
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
+{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ uint32_t tmp;
+
+ if (n > cc->gdb_num_core_regs) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 32) {
+ env->regs[n] = tmp;
+ } else {
+ env->sregs[n - 32] = tmp;
+ }
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 34/42] target-cris: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (32 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 33/42] target-microblaze: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 35/42] target-alpha: " Andreas Färber
` (8 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 105 +-----------------------------------------
target-cris/gdbstub.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 126 insertions(+), 104 deletions(-)
create mode 100644 target-cris/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 8fe149a..1d4a881 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -566,111 +566,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_CRIS)
-static int
-read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
-{
- if (n < 15) {
- GET_REG32(env->regs[n]);
- }
-
- if (n == 15) {
- GET_REG32(env->pc);
- }
-
- if (n < 32) {
- switch (n) {
- case 16:
- GET_REG8(env->pregs[n - 16]);
- case 17:
- GET_REG8(env->pregs[n - 16]);
- case 20:
- case 21:
- GET_REG16(env->pregs[n - 16]);
- default:
- if (n >= 23) {
- GET_REG32(env->pregs[n - 16]);
- }
- break;
- }
- }
- return 0;
-}
-
-static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
-{
- uint8_t srs;
-
- if (env->pregs[PR_VR] < 32) {
- return read_register_crisv10(env, mem_buf, n);
- }
-
- srs = env->pregs[PR_SRS];
- if (n < 16) {
- GET_REG32(env->regs[n]);
- }
-
- if (n >= 21 && n < 32) {
- GET_REG32(env->pregs[n - 16]);
- }
- if (n >= 33 && n < 49) {
- GET_REG32(env->sregs[srs][n - 33]);
- }
- switch (n) {
- case 16:
- GET_REG8(env->pregs[0]);
- case 17:
- GET_REG8(env->pregs[1]);
- case 18:
- GET_REG32(env->pregs[2]);
- case 19:
- GET_REG8(srs);
- case 20:
- GET_REG16(env->pregs[4]);
- case 32:
- GET_REG32(env->pc);
- }
-
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
-{
- uint32_t tmp;
-
- if (n > 49) {
- return 0;
- }
-
- tmp = ldl_p(mem_buf);
-
- if (n < 16) {
- env->regs[n] = tmp;
- }
-
- if (n >= 21 && n < 32) {
- env->pregs[n - 16] = tmp;
- }
-
- /* FIXME: Should support function regs be writable? */
- switch (n) {
- case 16:
- return 1;
- case 17:
- return 1;
- case 18:
- env->pregs[PR_PID] = tmp;
- break;
- case 19:
- return 1;
- case 20:
- return 2;
- case 32:
- env->pc = tmp;
- break;
- }
+#include "target-cris/gdbstub.c"
- return 4;
-}
#elif defined (TARGET_ALPHA)
static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
diff --git a/target-cris/gdbstub.c b/target-cris/gdbstub.c
new file mode 100644
index 0000000..b48224a
--- /dev/null
+++ b/target-cris/gdbstub.c
@@ -0,0 +1,125 @@
+/*
+ * CRIS gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int
+read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 15) {
+ GET_REG32(env->regs[n]);
+ }
+
+ if (n == 15) {
+ GET_REG32(env->pc);
+ }
+
+ if (n < 32) {
+ switch (n) {
+ case 16:
+ GET_REG8(env->pregs[n - 16]);
+ case 17:
+ GET_REG8(env->pregs[n - 16]);
+ case 20:
+ case 21:
+ GET_REG16(env->pregs[n - 16]);
+ default:
+ if (n >= 23) {
+ GET_REG32(env->pregs[n - 16]);
+ }
+ break;
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
+{
+ uint8_t srs;
+
+ if (env->pregs[PR_VR] < 32) {
+ return read_register_crisv10(env, mem_buf, n);
+ }
+
+ srs = env->pregs[PR_SRS];
+ if (n < 16) {
+ GET_REG32(env->regs[n]);
+ }
+
+ if (n >= 21 && n < 32) {
+ GET_REG32(env->pregs[n - 16]);
+ }
+ if (n >= 33 && n < 49) {
+ GET_REG32(env->sregs[srs][n - 33]);
+ }
+ switch (n) {
+ case 16:
+ GET_REG8(env->pregs[0]);
+ case 17:
+ GET_REG8(env->pregs[1]);
+ case 18:
+ GET_REG32(env->pregs[2]);
+ case 19:
+ GET_REG8(srs);
+ case 20:
+ GET_REG16(env->pregs[4]);
+ case 32:
+ GET_REG32(env->pc);
+ }
+
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ if (n > 49) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 16) {
+ env->regs[n] = tmp;
+ }
+
+ if (n >= 21 && n < 32) {
+ env->pregs[n - 16] = tmp;
+ }
+
+ /* FIXME: Should support function regs be writable? */
+ switch (n) {
+ case 16:
+ return 1;
+ case 17:
+ return 1;
+ case 18:
+ env->pregs[PR_PID] = tmp;
+ break;
+ case 19:
+ return 1;
+ case 20:
+ return 2;
+ case 32:
+ env->pc = tmp;
+ break;
+ }
+
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 35/42] target-alpha: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (33 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 34/42] target-cris: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 36/42] target-s390x: " Andreas Färber
` (7 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 66 +-------------------------------------
target-alpha/gdbstub.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 87 insertions(+), 65 deletions(-)
create mode 100644 target-alpha/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 1d4a881..edff803 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -570,72 +570,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_ALPHA)
-static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
-{
- uint64_t val;
- CPU_DoubleU d;
-
- switch (n) {
- case 0 ... 30:
- val = env->ir[n];
- break;
- case 32 ... 62:
- d.d = env->fir[n - 32];
- val = d.ll;
- break;
- case 63:
- val = cpu_alpha_load_fpcr(env);
- break;
- case 64:
- val = env->pc;
- break;
- case 66:
- val = env->unique;
- break;
- case 31:
- case 65:
- /* 31 really is the zero register; 65 is unassigned in the
- gdb protocol, but is still required to occupy 8 bytes. */
- val = 0;
- break;
- default:
- return 0;
- }
- GET_REGL(val);
-}
+#include "target-alpha/gdbstub.c"
-static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
-{
- target_ulong tmp = ldtul_p(mem_buf);
- CPU_DoubleU d;
-
- switch (n) {
- case 0 ... 30:
- env->ir[n] = tmp;
- break;
- case 32 ... 62:
- d.ll = tmp;
- env->fir[n - 32] = d.d;
- break;
- case 63:
- cpu_alpha_store_fpcr(env, tmp);
- break;
- case 64:
- env->pc = tmp;
- break;
- case 66:
- env->unique = tmp;
- break;
- case 31:
- case 65:
- /* 31 really is the zero register; 65 is unassigned in the
- gdb protocol, but is still required to occupy 8 bytes. */
- break;
- default:
- return 0;
- }
- return 8;
-}
#elif defined (TARGET_S390X)
static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
diff --git a/target-alpha/gdbstub.c b/target-alpha/gdbstub.c
new file mode 100644
index 0000000..b23afe4
--- /dev/null
+++ b/target-alpha/gdbstub.c
@@ -0,0 +1,86 @@
+/*
+ * Alpha gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
+{
+ uint64_t val;
+ CPU_DoubleU d;
+
+ switch (n) {
+ case 0 ... 30:
+ val = env->ir[n];
+ break;
+ case 32 ... 62:
+ d.d = env->fir[n - 32];
+ val = d.ll;
+ break;
+ case 63:
+ val = cpu_alpha_load_fpcr(env);
+ break;
+ case 64:
+ val = env->pc;
+ break;
+ case 66:
+ val = env->unique;
+ break;
+ case 31:
+ case 65:
+ /* 31 really is the zero register; 65 is unassigned in the
+ gdb protocol, but is still required to occupy 8 bytes. */
+ val = 0;
+ break;
+ default:
+ return 0;
+ }
+ GET_REGL(val);
+}
+
+static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
+{
+ target_ulong tmp = ldtul_p(mem_buf);
+ CPU_DoubleU d;
+
+ switch (n) {
+ case 0 ... 30:
+ env->ir[n] = tmp;
+ break;
+ case 32 ... 62:
+ d.ll = tmp;
+ env->fir[n - 32] = d.d;
+ break;
+ case 63:
+ cpu_alpha_store_fpcr(env, tmp);
+ break;
+ case 64:
+ env->pc = tmp;
+ break;
+ case 66:
+ env->unique = tmp;
+ break;
+ case 31:
+ case 65:
+ /* 31 really is the zero register; 65 is unassigned in the
+ gdb protocol, but is still required to occupy 8 bytes. */
+ break;
+ default:
+ return 0;
+ }
+ return 8;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 36/42] target-s390x: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (34 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 35/42] target-alpha: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 37/42] target-lm32: " Andreas Färber
` (6 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf, Andreas Färber, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 60 +------------------------------------
target-s390x/gdbstub.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 81 insertions(+), 59 deletions(-)
create mode 100644 target-s390x/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index edff803..333f1a6 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -574,66 +574,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_S390X)
-static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
-{
- uint64_t val;
- int cc_op;
-
- switch (n) {
- case S390_PSWM_REGNUM:
- cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
- val = deposit64(env->psw.mask, 44, 2, cc_op);
- GET_REGL(val);
- case S390_PSWA_REGNUM:
- GET_REGL(env->psw.addr);
- case S390_R0_REGNUM ... S390_R15_REGNUM:
- GET_REGL(env->regs[n-S390_R0_REGNUM]);
- case S390_A0_REGNUM ... S390_A15_REGNUM:
- GET_REG32(env->aregs[n-S390_A0_REGNUM]);
- case S390_FPC_REGNUM:
- GET_REG32(env->fpc);
- case S390_F0_REGNUM ... S390_F15_REGNUM:
- GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
- }
-
- return 0;
-}
+#include "target-s390x/gdbstub.c"
-static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
-{
- target_ulong tmpl;
- uint32_t tmp32;
- int r = 8;
- tmpl = ldtul_p(mem_buf);
- tmp32 = ldl_p(mem_buf);
-
- switch (n) {
- case S390_PSWM_REGNUM:
- env->psw.mask = tmpl;
- env->cc_op = extract64(tmpl, 44, 2);
- break;
- case S390_PSWA_REGNUM:
- env->psw.addr = tmpl;
- break;
- case S390_R0_REGNUM ... S390_R15_REGNUM:
- env->regs[n-S390_R0_REGNUM] = tmpl;
- break;
- case S390_A0_REGNUM ... S390_A15_REGNUM:
- env->aregs[n-S390_A0_REGNUM] = tmp32;
- r = 4;
- break;
- case S390_FPC_REGNUM:
- env->fpc = tmp32;
- r = 4;
- break;
- case S390_F0_REGNUM ... S390_F15_REGNUM:
- env->fregs[n-S390_F0_REGNUM].ll = tmpl;
- break;
- default:
- return 0;
- }
- return r;
-}
#elif defined (TARGET_LM32)
#include "hw/lm32/lm32_pic.h"
diff --git a/target-s390x/gdbstub.c b/target-s390x/gdbstub.c
new file mode 100644
index 0000000..c966143
--- /dev/null
+++ b/target-s390x/gdbstub.c
@@ -0,0 +1,80 @@
+/*
+ * s390x gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
+{
+ uint64_t val;
+ int cc_op;
+
+ switch (n) {
+ case S390_PSWM_REGNUM:
+ cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
+ val = deposit64(env->psw.mask, 44, 2, cc_op);
+ GET_REGL(val);
+ case S390_PSWA_REGNUM:
+ GET_REGL(env->psw.addr);
+ case S390_R0_REGNUM ... S390_R15_REGNUM:
+ GET_REGL(env->regs[n-S390_R0_REGNUM]);
+ case S390_A0_REGNUM ... S390_A15_REGNUM:
+ GET_REG32(env->aregs[n-S390_A0_REGNUM]);
+ case S390_FPC_REGNUM:
+ GET_REG32(env->fpc);
+ case S390_F0_REGNUM ... S390_F15_REGNUM:
+ GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
+ }
+
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
+{
+ target_ulong tmpl;
+ uint32_t tmp32;
+ int r = 8;
+ tmpl = ldtul_p(mem_buf);
+ tmp32 = ldl_p(mem_buf);
+
+ switch (n) {
+ case S390_PSWM_REGNUM:
+ env->psw.mask = tmpl;
+ env->cc_op = extract64(tmpl, 44, 2);
+ break;
+ case S390_PSWA_REGNUM:
+ env->psw.addr = tmpl;
+ break;
+ case S390_R0_REGNUM ... S390_R15_REGNUM:
+ env->regs[n-S390_R0_REGNUM] = tmpl;
+ break;
+ case S390_A0_REGNUM ... S390_A15_REGNUM:
+ env->aregs[n-S390_A0_REGNUM] = tmp32;
+ r = 4;
+ break;
+ case S390_FPC_REGNUM:
+ env->fpc = tmp32;
+ r = 4;
+ break;
+ case S390_F0_REGNUM ... S390_F15_REGNUM:
+ env->fregs[n-S390_F0_REGNUM].ll = tmpl;
+ break;
+ default:
+ return 0;
+ }
+ return r;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 37/42] target-lm32: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (35 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 36/42] target-s390x: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 38/42] target-xtensa: " Andreas Färber
` (5 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Michael Walle, Andreas Färber
Acked-by: Michael Walle <michael@walle.cc>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 66 +--------------------------------------
target-lm32/gdbstub.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 86 insertions(+), 65 deletions(-)
create mode 100644 target-lm32/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 333f1a6..853f09d 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -578,72 +578,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined (TARGET_LM32)
-#include "hw/lm32/lm32_pic.h"
+#include "target-lm32/gdbstub.c"
-static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- GET_REG32(env->regs[n]);
- } else {
- switch (n) {
- case 32:
- GET_REG32(env->pc);
- /* FIXME: put in right exception ID */
- case 33:
- GET_REG32(0);
- case 34:
- GET_REG32(env->eba);
- case 35:
- GET_REG32(env->deba);
- case 36:
- GET_REG32(env->ie);
- case 37:
- GET_REG32(lm32_pic_get_im(env->pic_state));
- case 38:
- GET_REG32(lm32_pic_get_ip(env->pic_state));
- }
- }
- return 0;
-}
-
-static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
-{
- LM32CPU *cpu = lm32_env_get_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
- uint32_t tmp;
-
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
- tmp = ldl_p(mem_buf);
-
- if (n < 32) {
- env->regs[n] = tmp;
- } else {
- switch (n) {
- case 32:
- env->pc = tmp;
- break;
- case 34:
- env->eba = tmp;
- break;
- case 35:
- env->deba = tmp;
- break;
- case 36:
- env->ie = tmp;
- break;
- case 37:
- lm32_pic_set_im(env->pic_state, tmp);
- break;
- case 38:
- lm32_pic_set_ip(env->pic_state, tmp);
- break;
- }
- }
- return 4;
-}
#elif defined(TARGET_XTENSA)
static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
diff --git a/target-lm32/gdbstub.c b/target-lm32/gdbstub.c
new file mode 100644
index 0000000..732a633
--- /dev/null
+++ b/target-lm32/gdbstub.c
@@ -0,0 +1,85 @@
+/*
+ * LM32 gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "hw/lm32/lm32_pic.h"
+
+static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ GET_REG32(env->regs[n]);
+ } else {
+ switch (n) {
+ case 32:
+ GET_REG32(env->pc);
+ /* FIXME: put in right exception ID */
+ case 33:
+ GET_REG32(0);
+ case 34:
+ GET_REG32(env->eba);
+ case 35:
+ GET_REG32(env->deba);
+ case 36:
+ GET_REG32(env->ie);
+ case 37:
+ GET_REG32(lm32_pic_get_im(env->pic_state));
+ case 38:
+ GET_REG32(lm32_pic_get_ip(env->pic_state));
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
+{
+ LM32CPU *cpu = lm32_env_get_cpu(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ uint32_t tmp;
+
+ if (n > cc->gdb_num_core_regs) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 32) {
+ env->regs[n] = tmp;
+ } else {
+ switch (n) {
+ case 32:
+ env->pc = tmp;
+ break;
+ case 34:
+ env->eba = tmp;
+ break;
+ case 35:
+ env->deba = tmp;
+ break;
+ case 36:
+ env->ie = tmp;
+ break;
+ case 37:
+ lm32_pic_set_im(env->pic_state, tmp);
+ break;
+ case 38:
+ lm32_pic_set_ip(env->pic_state, tmp);
+ break;
+ }
+ }
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 38/42] target-xtensa: Move cpu_gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (36 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 37/42] target-lm32: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 39/42] gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions Andreas Färber
` (4 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 80 +-------------------------------------
target-xtensa/gdbstub.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 101 insertions(+), 79 deletions(-)
create mode 100644 target-xtensa/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 853f09d..9e12762 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -582,86 +582,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined(TARGET_XTENSA)
-static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
-{
- const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
-
- if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
- return 0;
- }
-
- switch (reg->type) {
- case 9: /*pc*/
- GET_REG32(env->pc);
-
- case 1: /*ar*/
- xtensa_sync_phys_from_window(env);
- GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
-
- case 2: /*SR*/
- GET_REG32(env->sregs[reg->targno & 0xff]);
-
- case 3: /*UR*/
- GET_REG32(env->uregs[reg->targno & 0xff]);
-
- case 4: /*f*/
- GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
-
- case 8: /*a*/
- GET_REG32(env->regs[reg->targno & 0x0f]);
-
- default:
- qemu_log("%s from reg %d of unsupported type %d\n",
- __func__, n, reg->type);
- return 0;
- }
-}
-
-static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
-{
- uint32_t tmp;
- const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
-
- if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
- return 0;
- }
-
- tmp = ldl_p(mem_buf);
-
- switch (reg->type) {
- case 9: /*pc*/
- env->pc = tmp;
- break;
-
- case 1: /*ar*/
- env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
- xtensa_sync_window_from_phys(env);
- break;
-
- case 2: /*SR*/
- env->sregs[reg->targno & 0xff] = tmp;
- break;
-
- case 3: /*UR*/
- env->uregs[reg->targno & 0xff] = tmp;
- break;
+#include "target-xtensa/gdbstub.c"
- case 4: /*f*/
- env->fregs[reg->targno & 0x0f] = make_float32(tmp);
- break;
-
- case 8: /*a*/
- env->regs[reg->targno & 0x0f] = tmp;
- break;
-
- default:
- qemu_log("%s to reg %d of unsupported type %d\n",
- __func__, n, reg->type);
- return 0;
- }
-
- return 4;
-}
#else
static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
diff --git a/target-xtensa/gdbstub.c b/target-xtensa/gdbstub.c
new file mode 100644
index 0000000..0880b7c
--- /dev/null
+++ b/target-xtensa/gdbstub.c
@@ -0,0 +1,100 @@
+/*
+ * Xtensa gdb server stub
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2013 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
+{
+ const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
+
+ if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
+ return 0;
+ }
+
+ switch (reg->type) {
+ case 9: /*pc*/
+ GET_REG32(env->pc);
+
+ case 1: /*ar*/
+ xtensa_sync_phys_from_window(env);
+ GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
+
+ case 2: /*SR*/
+ GET_REG32(env->sregs[reg->targno & 0xff]);
+
+ case 3: /*UR*/
+ GET_REG32(env->uregs[reg->targno & 0xff]);
+
+ case 4: /*f*/
+ GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
+
+ case 8: /*a*/
+ GET_REG32(env->regs[reg->targno & 0x0f]);
+
+ default:
+ qemu_log("%s from reg %d of unsupported type %d\n",
+ __func__, n, reg->type);
+ return 0;
+ }
+}
+
+static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+ const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
+
+ if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ switch (reg->type) {
+ case 9: /*pc*/
+ env->pc = tmp;
+ break;
+
+ case 1: /*ar*/
+ env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
+ xtensa_sync_window_from_phys(env);
+ break;
+
+ case 2: /*SR*/
+ env->sregs[reg->targno & 0xff] = tmp;
+ break;
+
+ case 3: /*UR*/
+ env->uregs[reg->targno & 0xff] = tmp;
+ break;
+
+ case 4: /*f*/
+ env->fregs[reg->targno & 0x0f] = make_float32(tmp);
+ break;
+
+ case 8: /*a*/
+ env->regs[reg->targno & 0x0f] = tmp;
+ break;
+
+ default:
+ qemu_log("%s to reg %d of unsupported type %d\n",
+ __func__, n, reg->type);
+ return 0;
+ }
+
+ return 4;
+}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 39/42] gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (37 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 38/42] target-xtensa: " Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 40/42] cpu: Introduce CPUClass::gdb_{read, write}_register() Andreas Färber
` (3 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Alexander Graf, Blue Swirl, Max Filippov,
Michael Walle, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Andreas Färber, Aurelien Jarno, Richard Henderson
This avoids polluting the global namespace with a non-prefixed macro and
makes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g.,
sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c
followed by manual tweaking for sparc's GET_REGA() and Coding Style.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 29 ------------------------
include/exec/gdbstub.h | 37 +++++++++++++++++++++++++++++++
target-alpha/gdbstub.c | 2 +-
target-arm/gdbstub.c | 6 ++---
target-cris/gdbstub.c | 30 ++++++++++++-------------
target-i386/gdbstub.c | 42 +++++++++++++++++------------------
target-lm32/gdbstub.c | 16 +++++++-------
target-m68k/gdbstub.c | 8 +++----
target-microblaze/gdbstub.c | 4 ++--
target-mips/gdbstub.c | 31 ++++++++++++++------------
target-openrisc/gdbstub.c | 8 +++----
target-ppc/gdbstub.c | 16 +++++++-------
target-s390x/gdbstub.c | 12 +++++-----
target-sh4/gdbstub.c | 32 +++++++++++++--------------
target-sparc/gdbstub.c | 54 ++++++++++++++++++++++-----------------------
target-xtensa/gdbstub.c | 14 +++++++-----
16 files changed, 177 insertions(+), 164 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 9e12762..c72ea5c 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -489,35 +489,6 @@ static int put_packet(GDBState *s, const char *buf)
return put_packet_binary(s, buf, strlen(buf));
}
-/* The GDB remote protocol transfers values in target byte order. This means
- we can use the raw memory access routines to access the value buffer.
- Conveniently, these also handle the case where the buffer is mis-aligned.
- */
-#define GET_REG8(val) do { \
- stb_p(mem_buf, val); \
- return 1; \
- } while(0)
-#define GET_REG16(val) do { \
- stw_p(mem_buf, val); \
- return 2; \
- } while(0)
-#define GET_REG32(val) do { \
- stl_p(mem_buf, val); \
- return 4; \
- } while(0)
-#define GET_REG64(val) do { \
- stq_p(mem_buf, val); \
- return 8; \
- } while(0)
-
-#if TARGET_LONG_BITS == 64
-#define GET_REGL(val) GET_REG64(val)
-#define ldtul_p(addr) ldq_p(addr)
-#else
-#define GET_REGL(val) GET_REG32(val)
-#define ldtul_p(addr) ldl_p(addr)
-#endif
-
#if defined(TARGET_I386)
#include "target-i386/gdbstub.c"
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 1bd00ae..5778b0e 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -39,6 +39,43 @@ static inline int cpu_index(CPUState *cpu)
#endif
}
+/* The GDB remote protocol transfers values in target byte order. This means
+ * we can use the raw memory access routines to access the value buffer.
+ * Conveniently, these also handle the case where the buffer is mis-aligned.
+ */
+
+static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val)
+{
+ stb_p(mem_buf, val);
+ return 1;
+}
+
+static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val)
+{
+ stw_p(mem_buf, val);
+ return 2;
+}
+
+static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val)
+{
+ stl_p(mem_buf, val);
+ return 4;
+}
+
+static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val)
+{
+ stq_p(mem_buf, val);
+ return 8;
+}
+
+#if TARGET_LONG_BITS == 64
+#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val)
+#define ldtul_p(addr) ldq_p(addr)
+#else
+#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val)
+#define ldtul_p(addr) ldl_p(addr)
+#endif
+
#endif
#ifdef CONFIG_USER_ONLY
diff --git a/target-alpha/gdbstub.c b/target-alpha/gdbstub.c
index b23afe4..1c18698 100644
--- a/target-alpha/gdbstub.c
+++ b/target-alpha/gdbstub.c
@@ -49,7 +49,7 @@ static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
default:
return 0;
}
- GET_REGL(val);
+ return gdb_get_regl(mem_buf, val);
}
static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index 74903a3..e1c7df4 100644
--- a/target-arm/gdbstub.c
+++ b/target-arm/gdbstub.c
@@ -28,7 +28,7 @@ static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
if (n < 16) {
/* Core integer register. */
- GET_REG32(env->regs[n]);
+ return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n < 24) {
/* FPA registers. */
@@ -44,10 +44,10 @@ static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
if (gdb_has_xml) {
return 0;
}
- GET_REG32(0);
+ return gdb_get_reg32(mem_buf, 0);
case 25:
/* CPSR */
- GET_REG32(cpsr_read(env));
+ return gdb_get_reg32(mem_buf, cpsr_read(env));
}
/* Unknown register. */
return 0;
diff --git a/target-cris/gdbstub.c b/target-cris/gdbstub.c
index b48224a..ed23966 100644
--- a/target-cris/gdbstub.c
+++ b/target-cris/gdbstub.c
@@ -22,25 +22,25 @@ static int
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
{
if (n < 15) {
- GET_REG32(env->regs[n]);
+ return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n == 15) {
- GET_REG32(env->pc);
+ return gdb_get_reg32(mem_buf, env->pc);
}
if (n < 32) {
switch (n) {
case 16:
- GET_REG8(env->pregs[n - 16]);
+ return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
case 17:
- GET_REG8(env->pregs[n - 16]);
+ return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
case 20:
case 21:
- GET_REG16(env->pregs[n - 16]);
+ return gdb_get_reg16(mem_buf, env->pregs[n - 16]);
default:
if (n >= 23) {
- GET_REG32(env->pregs[n - 16]);
+ return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
}
break;
}
@@ -58,28 +58,28 @@ static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
srs = env->pregs[PR_SRS];
if (n < 16) {
- GET_REG32(env->regs[n]);
+ return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n >= 21 && n < 32) {
- GET_REG32(env->pregs[n - 16]);
+ return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
}
if (n >= 33 && n < 49) {
- GET_REG32(env->sregs[srs][n - 33]);
+ return gdb_get_reg32(mem_buf, env->sregs[srs][n - 33]);
}
switch (n) {
case 16:
- GET_REG8(env->pregs[0]);
+ return gdb_get_reg8(mem_buf, env->pregs[0]);
case 17:
- GET_REG8(env->pregs[1]);
+ return gdb_get_reg8(mem_buf, env->pregs[1]);
case 18:
- GET_REG32(env->pregs[2]);
+ return gdb_get_reg32(mem_buf, env->pregs[2]);
case 19:
- GET_REG8(srs);
+ return gdb_get_reg8(mem_buf, srs);
case 20:
- GET_REG16(env->pregs[4]);
+ return gdb_get_reg16(mem_buf, env->pregs[4]);
case 32:
- GET_REG32(env->pc);
+ return gdb_get_reg32(mem_buf, env->pc);
}
return 0;
diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c
index 974d8ad..0a4d97d 100644
--- a/target-i386/gdbstub.c
+++ b/target-i386/gdbstub.c
@@ -39,9 +39,9 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
- GET_REG64(env->regs[gpr_map[n]]);
+ return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
} else if (n < CPU_NB_REGS32) {
- GET_REG32(env->regs[gpr_map32[n]]);
+ return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
}
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
@@ -63,46 +63,46 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
switch (n) {
case IDX_IP_REG:
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
- GET_REG64(env->eip);
+ return gdb_get_reg64(mem_buf, env->eip);
} else {
- GET_REG32(env->eip);
+ return gdb_get_reg32(mem_buf, env->eip);
}
case IDX_FLAGS_REG:
- GET_REG32(env->eflags);
+ return gdb_get_reg32(mem_buf, env->eflags);
case IDX_SEG_REGS:
- GET_REG32(env->segs[R_CS].selector);
+ return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
case IDX_SEG_REGS + 1:
- GET_REG32(env->segs[R_SS].selector);
+ return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
case IDX_SEG_REGS + 2:
- GET_REG32(env->segs[R_DS].selector);
+ return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
case IDX_SEG_REGS + 3:
- GET_REG32(env->segs[R_ES].selector);
+ return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
case IDX_SEG_REGS + 4:
- GET_REG32(env->segs[R_FS].selector);
+ return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
case IDX_SEG_REGS + 5:
- GET_REG32(env->segs[R_GS].selector);
+ return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
case IDX_FP_REGS + 8:
- GET_REG32(env->fpuc);
+ return gdb_get_reg32(mem_buf, env->fpuc);
case IDX_FP_REGS + 9:
- GET_REG32((env->fpus & ~0x3800) |
- (env->fpstt & 0x7) << 11);
+ return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
+ (env->fpstt & 0x7) << 11);
case IDX_FP_REGS + 10:
- GET_REG32(0); /* ftag */
+ return gdb_get_reg32(mem_buf, 0); /* ftag */
case IDX_FP_REGS + 11:
- GET_REG32(0); /* fiseg */
+ return gdb_get_reg32(mem_buf, 0); /* fiseg */
case IDX_FP_REGS + 12:
- GET_REG32(0); /* fioff */
+ return gdb_get_reg32(mem_buf, 0); /* fioff */
case IDX_FP_REGS + 13:
- GET_REG32(0); /* foseg */
+ return gdb_get_reg32(mem_buf, 0); /* foseg */
case IDX_FP_REGS + 14:
- GET_REG32(0); /* fooff */
+ return gdb_get_reg32(mem_buf, 0); /* fooff */
case IDX_FP_REGS + 15:
- GET_REG32(0); /* fop */
+ return gdb_get_reg32(mem_buf, 0); /* fop */
case IDX_MXCSR_REG:
- GET_REG32(env->mxcsr);
+ return gdb_get_reg32(mem_buf, env->mxcsr);
}
}
return 0;
diff --git a/target-lm32/gdbstub.c b/target-lm32/gdbstub.c
index 732a633..17f08f5 100644
--- a/target-lm32/gdbstub.c
+++ b/target-lm32/gdbstub.c
@@ -22,24 +22,24 @@
static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- GET_REG32(env->regs[n]);
+ return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
switch (n) {
case 32:
- GET_REG32(env->pc);
+ return gdb_get_reg32(mem_buf, env->pc);
/* FIXME: put in right exception ID */
case 33:
- GET_REG32(0);
+ return gdb_get_reg32(mem_buf, 0);
case 34:
- GET_REG32(env->eba);
+ return gdb_get_reg32(mem_buf, env->eba);
case 35:
- GET_REG32(env->deba);
+ return gdb_get_reg32(mem_buf, env->deba);
case 36:
- GET_REG32(env->ie);
+ return gdb_get_reg32(mem_buf, env->ie);
case 37:
- GET_REG32(lm32_pic_get_im(env->pic_state));
+ return gdb_get_reg32(mem_buf, lm32_pic_get_im(env->pic_state));
case 38:
- GET_REG32(lm32_pic_get_ip(env->pic_state));
+ return gdb_get_reg32(mem_buf, lm32_pic_get_ip(env->pic_state));
}
}
return 0;
diff --git a/target-m68k/gdbstub.c b/target-m68k/gdbstub.c
index 2eb4b98..9fa9fa6 100644
--- a/target-m68k/gdbstub.c
+++ b/target-m68k/gdbstub.c
@@ -22,16 +22,16 @@ static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* D0-D7 */
- GET_REG32(env->dregs[n]);
+ return gdb_get_reg32(mem_buf, env->dregs[n]);
} else if (n < 16) {
/* A0-A7 */
- GET_REG32(env->aregs[n - 8]);
+ return gdb_get_reg32(mem_buf, env->aregs[n - 8]);
} else {
switch (n) {
case 16:
- GET_REG32(env->sr);
+ return gdb_get_reg32(mem_buf, env->sr);
case 17:
- GET_REG32(env->pc);
+ return gdb_get_reg32(mem_buf, env->pc);
}
}
/* FP registers not included here because they vary between
diff --git a/target-microblaze/gdbstub.c b/target-microblaze/gdbstub.c
index 96c4bc0..678de21 100644
--- a/target-microblaze/gdbstub.c
+++ b/target-microblaze/gdbstub.c
@@ -21,9 +21,9 @@
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- GET_REG32(env->regs[n]);
+ return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
- GET_REG32(env->sregs[n - 32]);
+ return gdb_get_reg32(mem_buf, env->sregs[n - 32]);
}
return 0;
}
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index 15dc281..db826d8 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -21,44 +21,47 @@
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- GET_REGL(env->active_tc.gpr[n]);
+ return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
}
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
if (n >= 38 && n < 70) {
if (env->CP0_Status & (1 << CP0St_FR)) {
- GET_REGL(env->active_fpu.fpr[n - 38].d);
+ return gdb_get_regl(mem_buf,
+ env->active_fpu.fpr[n - 38].d);
} else {
- GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
+ return gdb_get_regl(mem_buf,
+ env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
}
}
switch (n) {
case 70:
- GET_REGL((int32_t)env->active_fpu.fcr31);
+ return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
case 71:
- GET_REGL((int32_t)env->active_fpu.fcr0);
+ return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
}
}
switch (n) {
case 32:
- GET_REGL((int32_t)env->CP0_Status);
+ return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
case 33:
- GET_REGL(env->active_tc.LO[0]);
+ return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
case 34:
- GET_REGL(env->active_tc.HI[0]);
+ return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
case 35:
- GET_REGL(env->CP0_BadVAddr);
+ return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
case 36:
- GET_REGL((int32_t)env->CP0_Cause);
+ return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
case 37:
- GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
+ return gdb_get_regl(mem_buf, env->active_tc.PC |
+ !!(env->hflags & MIPS_HFLAG_M16));
case 72:
- GET_REGL(0); /* fp */
+ return gdb_get_regl(mem_buf, 0); /* fp */
case 89:
- GET_REGL((int32_t)env->CP0_PRid);
+ return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
}
if (n >= 73 && n <= 88) {
/* 16 embedded regs. */
- GET_REGL(0);
+ return gdb_get_regl(mem_buf, 0);
}
return 0;
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
index fba096a..bdb8d2c 100644
--- a/target-openrisc/gdbstub.c
+++ b/target-openrisc/gdbstub.c
@@ -21,17 +21,17 @@
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- GET_REG32(env->gpr[n]);
+ return gdb_get_reg32(mem_buf, env->gpr[n]);
} else {
switch (n) {
case 32: /* PPC */
- GET_REG32(env->ppc);
+ return gdb_get_reg32(mem_buf, env->ppc);
case 33: /* NPC */
- GET_REG32(env->npc);
+ return gdb_get_reg32(mem_buf, env->npc);
case 34: /* SR */
- GET_REG32(env->sr);
+ return gdb_get_reg32(mem_buf, env->sr);
default:
break;
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index b834e60..40a9d7b 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -29,7 +29,7 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
- GET_REGL(env->gpr[n]);
+ return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n < 64) {
/* fprs */
if (gdb_has_xml) {
@@ -40,9 +40,9 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
} else {
switch (n) {
case 64:
- GET_REGL(env->nip);
+ return gdb_get_regl(mem_buf, env->nip);
case 65:
- GET_REGL(env->msr);
+ return gdb_get_regl(mem_buf, env->msr);
case 66:
{
uint32_t cr = 0;
@@ -50,20 +50,20 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
}
- GET_REG32(cr);
+ return gdb_get_reg32(mem_buf, cr);
}
case 67:
- GET_REGL(env->lr);
+ return gdb_get_regl(mem_buf, env->lr);
case 68:
- GET_REGL(env->ctr);
+ return gdb_get_regl(mem_buf, env->ctr);
case 69:
- GET_REGL(env->xer);
+ return gdb_get_regl(mem_buf, env->xer);
case 70:
{
if (gdb_has_xml) {
return 0;
}
- GET_REG32(env->fpscr);
+ return gdb_get_reg32(mem_buf, env->fpscr);
}
}
}
diff --git a/target-s390x/gdbstub.c b/target-s390x/gdbstub.c
index c966143..ee3e984 100644
--- a/target-s390x/gdbstub.c
+++ b/target-s390x/gdbstub.c
@@ -27,17 +27,17 @@ static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
case S390_PSWM_REGNUM:
cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
val = deposit64(env->psw.mask, 44, 2, cc_op);
- GET_REGL(val);
+ return gdb_get_regl(mem_buf, val);
case S390_PSWA_REGNUM:
- GET_REGL(env->psw.addr);
+ return gdb_get_regl(mem_buf, env->psw.addr);
case S390_R0_REGNUM ... S390_R15_REGNUM:
- GET_REGL(env->regs[n-S390_R0_REGNUM]);
+ return gdb_get_regl(mem_buf, env->regs[n-S390_R0_REGNUM]);
case S390_A0_REGNUM ... S390_A15_REGNUM:
- GET_REG32(env->aregs[n-S390_A0_REGNUM]);
+ return gdb_get_reg32(mem_buf, env->aregs[n-S390_A0_REGNUM]);
case S390_FPC_REGNUM:
- GET_REG32(env->fpc);
+ return gdb_get_reg32(mem_buf, env->fpc);
case S390_F0_REGNUM ... S390_F15_REGNUM:
- GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
+ return gdb_get_reg64(mem_buf, env->fregs[n-S390_F0_REGNUM].ll);
}
return 0;
diff --git a/target-sh4/gdbstub.c b/target-sh4/gdbstub.c
index 38bc630..fb85718 100644
--- a/target-sh4/gdbstub.c
+++ b/target-sh4/gdbstub.c
@@ -26,30 +26,30 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
switch (n) {
case 0 ... 7:
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
- GET_REGL(env->gregs[n + 16]);
+ return gdb_get_regl(mem_buf, env->gregs[n + 16]);
} else {
- GET_REGL(env->gregs[n]);
+ return gdb_get_regl(mem_buf, env->gregs[n]);
}
case 8 ... 15:
- GET_REGL(env->gregs[n]);
+ return gdb_get_regl(mem_buf, env->gregs[n]);
case 16:
- GET_REGL(env->pc);
+ return gdb_get_regl(mem_buf, env->pc);
case 17:
- GET_REGL(env->pr);
+ return gdb_get_regl(mem_buf, env->pr);
case 18:
- GET_REGL(env->gbr);
+ return gdb_get_regl(mem_buf, env->gbr);
case 19:
- GET_REGL(env->vbr);
+ return gdb_get_regl(mem_buf, env->vbr);
case 20:
- GET_REGL(env->mach);
+ return gdb_get_regl(mem_buf, env->mach);
case 21:
- GET_REGL(env->macl);
+ return gdb_get_regl(mem_buf, env->macl);
case 22:
- GET_REGL(env->sr);
+ return gdb_get_regl(mem_buf, env->sr);
case 23:
- GET_REGL(env->fpul);
+ return gdb_get_regl(mem_buf, env->fpul);
case 24:
- GET_REGL(env->fpscr);
+ return gdb_get_regl(mem_buf, env->fpscr);
case 25 ... 40:
if (env->fpscr & FPSCR_FR) {
stfl_p(mem_buf, env->fregs[n - 9]);
@@ -58,13 +58,13 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
}
return 4;
case 41:
- GET_REGL(env->ssr);
+ return gdb_get_regl(mem_buf, env->ssr);
case 42:
- GET_REGL(env->spc);
+ return gdb_get_regl(mem_buf, env->spc);
case 43 ... 50:
- GET_REGL(env->gregs[n - 43]);
+ return gdb_get_regl(mem_buf, env->gregs[n - 43]);
case 51 ... 58:
- GET_REGL(env->gregs[n - (51 - 16)]);
+ return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]);
}
return 0;
diff --git a/target-sparc/gdbstub.c b/target-sparc/gdbstub.c
index 914f586..460c0b7 100644
--- a/target-sparc/gdbstub.c
+++ b/target-sparc/gdbstub.c
@@ -19,80 +19,80 @@
*/
#ifdef TARGET_ABI32
-#define GET_REGA(val) GET_REG32(val)
+#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val)
#else
-#define GET_REGA(val) GET_REGL(val)
+#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
#endif
static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* g0..g7 */
- GET_REGA(env->gregs[n]);
+ return gdb_get_rega(mem_buf, env->gregs[n]);
}
if (n < 32) {
/* register window */
- GET_REGA(env->regwptr[n - 8]);
+ return gdb_get_rega(mem_buf, env->regwptr[n - 8]);
}
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
if (n < 64) {
/* fprs */
if (n & 1) {
- GET_REG32(env->fpr[(n - 32) / 2].l.lower);
+ return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
} else {
- GET_REG32(env->fpr[(n - 32) / 2].l.upper);
+ return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
}
}
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
switch (n) {
case 64:
- GET_REGA(env->y);
+ return gdb_get_rega(mem_buf, env->y);
case 65:
- GET_REGA(cpu_get_psr(env));
+ return gdb_get_rega(mem_buf, cpu_get_psr(env));
case 66:
- GET_REGA(env->wim);
+ return gdb_get_rega(mem_buf, env->wim);
case 67:
- GET_REGA(env->tbr);
+ return gdb_get_rega(mem_buf, env->tbr);
case 68:
- GET_REGA(env->pc);
+ return gdb_get_rega(mem_buf, env->pc);
case 69:
- GET_REGA(env->npc);
+ return gdb_get_rega(mem_buf, env->npc);
case 70:
- GET_REGA(env->fsr);
+ return gdb_get_rega(mem_buf, env->fsr);
case 71:
- GET_REGA(0); /* csr */
+ return gdb_get_rega(mem_buf, 0); /* csr */
default:
- GET_REGA(0);
+ return gdb_get_rega(mem_buf, 0);
}
#else
if (n < 64) {
/* f0-f31 */
if (n & 1) {
- GET_REG32(env->fpr[(n - 32) / 2].l.lower);
+ return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
} else {
- GET_REG32(env->fpr[(n - 32) / 2].l.upper);
+ return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
}
}
if (n < 80) {
/* f32-f62 (double width, even numbers only) */
- GET_REG64(env->fpr[(n - 32) / 2].ll);
+ return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
}
switch (n) {
case 80:
- GET_REGL(env->pc);
+ return gdb_get_regl(mem_buf, env->pc);
case 81:
- GET_REGL(env->npc);
+ return gdb_get_regl(mem_buf, env->npc);
case 82:
- GET_REGL((cpu_get_ccr(env) << 32) |
- ((env->asi & 0xff) << 24) |
- ((env->pstate & 0xfff) << 8) |
- cpu_get_cwp64(env));
+ return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) |
+ ((env->asi & 0xff) << 24) |
+ ((env->pstate & 0xfff) << 8) |
+ cpu_get_cwp64(env));
case 83:
- GET_REGL(env->fsr);
+ return gdb_get_regl(mem_buf, env->fsr);
case 84:
- GET_REGL(env->fprs);
+ return gdb_get_regl(mem_buf, env->fprs);
case 85:
- GET_REGL(env->y);
+ return gdb_get_regl(mem_buf, env->y);
}
#endif
return 0;
diff --git a/target-xtensa/gdbstub.c b/target-xtensa/gdbstub.c
index 0880b7c..c963563 100644
--- a/target-xtensa/gdbstub.c
+++ b/target-xtensa/gdbstub.c
@@ -28,23 +28,25 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
switch (reg->type) {
case 9: /*pc*/
- GET_REG32(env->pc);
+ return gdb_get_reg32(mem_buf, env->pc);
case 1: /*ar*/
xtensa_sync_phys_from_window(env);
- GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
+ return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
+ % env->config->nareg]);
case 2: /*SR*/
- GET_REG32(env->sregs[reg->targno & 0xff]);
+ return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
case 3: /*UR*/
- GET_REG32(env->uregs[reg->targno & 0xff]);
+ return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
case 4: /*f*/
- GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
+ return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno
+ & 0x0f]));
case 8: /*a*/
- GET_REG32(env->regs[reg->targno & 0x0f]);
+ return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
default:
qemu_log("%s from reg %d of unsupported type %d\n",
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 40/42] cpu: Introduce CPUClass::gdb_{read, write}_register()
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (38 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 39/42] gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 41/42] target-cris: Factor out CPUClass::gdb_read_register() hook for v10 Andreas Färber
` (2 subsequent siblings)
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Alexander Graf, Blue Swirl, Max Filippov,
Michael Walle, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Andreas Färber, Aurelien Jarno, Richard Henderson
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 80 ++++-------------------------------------
include/exec/gdbstub.h | 8 +++++
include/qom/cpu.h | 4 +++
qom/cpu.c | 13 +++++++
target-alpha/Makefile.objs | 1 +
target-alpha/cpu-qom.h | 2 ++
target-alpha/cpu.c | 2 ++
target-alpha/gdbstub.c | 11 ++++--
target-arm/Makefile.objs | 1 +
target-arm/cpu-qom.h | 3 ++
target-arm/cpu.c | 2 ++
target-arm/gdbstub.c | 12 +++++--
target-cris/Makefile.objs | 1 +
target-cris/cpu-qom.h | 3 ++
target-cris/cpu.c | 2 ++
target-cris/gdbstub.c | 11 ++++--
target-i386/Makefile.objs | 1 +
target-i386/cpu-qom.h | 3 ++
target-i386/cpu.c | 2 ++
target-i386/gdbstub.c | 27 +++++++++-----
target-lm32/Makefile.objs | 1 +
target-lm32/cpu-qom.h | 2 ++
target-lm32/cpu.c | 2 ++
target-lm32/gdbstub.c | 15 +++++---
target-m68k/Makefile.objs | 1 +
target-m68k/cpu-qom.h | 2 ++
target-m68k/cpu.c | 2 ++
target-m68k/gdbstub.c | 12 +++++--
target-microblaze/Makefile.objs | 1 +
target-microblaze/cpu-qom.h | 2 ++
target-microblaze/cpu.c | 2 ++
target-microblaze/gdbstub.c | 15 +++++---
target-mips/Makefile.objs | 1 +
target-mips/cpu-qom.h | 2 ++
target-mips/cpu.c | 2 ++
target-mips/gdbstub.c | 12 +++++--
target-openrisc/Makefile.objs | 1 +
target-openrisc/cpu.c | 2 ++
target-openrisc/cpu.h | 2 ++
target-openrisc/gdbstub.c | 16 ++++++---
target-ppc/Makefile.objs | 1 +
target-ppc/cpu-qom.h | 2 ++
target-ppc/gdbstub.c | 13 +++++--
target-ppc/translate_init.c | 2 ++
target-s390x/Makefile.objs | 1 +
target-s390x/cpu-qom.h | 2 ++
target-s390x/cpu.c | 2 ++
target-s390x/gdbstub.c | 12 +++++--
target-sh4/Makefile.objs | 1 +
target-sh4/cpu-qom.h | 2 ++
target-sh4/cpu.c | 2 ++
target-sh4/gdbstub.c | 13 +++++--
target-sparc/Makefile.objs | 1 +
target-sparc/cpu-qom.h | 2 ++
target-sparc/cpu.c | 2 ++
target-sparc/gdbstub.c | 12 +++++--
target-xtensa/Makefile.objs | 1 +
target-xtensa/cpu-qom.h | 2 ++
target-xtensa/cpu.c | 2 ++
target-xtensa/gdbstub.c | 11 ++++--
60 files changed, 255 insertions(+), 115 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index c72ea5c..1ec6d31 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -40,7 +40,6 @@
#include "cpu.h"
#include "qemu/sockets.h"
#include "sysemu/kvm.h"
-#include "qemu/bitops.h"
static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, bool is_write)
@@ -316,10 +315,7 @@ static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
static GDBState *gdbserver_state;
-/* This is an ugly hack to cope with both new and old gdb.
- If gdb sends qXfer:features:read then assume we're talking to a newish
- gdb that understands target descriptions. */
-static int gdb_has_xml;
+bool gdb_has_xml;
#ifdef CONFIG_USER_ONLY
/* XXX: This is not thread safe. Do we care? */
@@ -489,11 +485,7 @@ static int put_packet(GDBState *s, const char *buf)
return put_packet_binary(s, buf, strlen(buf));
}
-#if defined(TARGET_I386)
-
-#include "target-i386/gdbstub.c"
-
-#elif defined (TARGET_PPC)
+#if defined(TARGET_PPC)
#if defined (TARGET_PPC64)
#define GDB_CORE_XML "power64-core.xml"
@@ -501,72 +493,14 @@ static int put_packet(GDBState *s, const char *buf)
#define GDB_CORE_XML "power-core.xml"
#endif
-#include "target-ppc/gdbstub.c"
-
-#elif defined (TARGET_SPARC)
-
-#include "target-sparc/gdbstub.c"
-
#elif defined (TARGET_ARM)
#define GDB_CORE_XML "arm-core.xml"
-#include "target-arm/gdbstub.c"
-
#elif defined (TARGET_M68K)
#define GDB_CORE_XML "cf-core.xml"
-#include "target-m68k/gdbstub.c"
-
-#elif defined (TARGET_MIPS)
-
-#include "target-mips/gdbstub.c"
-
-#elif defined(TARGET_OPENRISC)
-
-#include "target-openrisc/gdbstub.c"
-
-#elif defined (TARGET_SH4)
-
-#include "target-sh4/gdbstub.c"
-
-#elif defined (TARGET_MICROBLAZE)
-
-#include "target-microblaze/gdbstub.c"
-
-#elif defined (TARGET_CRIS)
-
-#include "target-cris/gdbstub.c"
-
-#elif defined (TARGET_ALPHA)
-
-#include "target-alpha/gdbstub.c"
-
-#elif defined (TARGET_S390X)
-
-#include "target-s390x/gdbstub.c"
-
-#elif defined (TARGET_LM32)
-
-#include "target-lm32/gdbstub.c"
-
-#elif defined(TARGET_XTENSA)
-
-#include "target-xtensa/gdbstub.c"
-
-#else
-
-static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
-{
- return 0;
-}
-
-static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
-{
- return 0;
-}
-
#endif
#ifdef GDB_CORE_XML
@@ -642,7 +576,7 @@ static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
- return cpu_gdb_read_register(env, mem_buf, reg);
+ return cc->gdb_read_register(cpu, mem_buf, reg);
}
for (r = cpu->gdb_regs; r; r = r->next) {
@@ -660,7 +594,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
- return cpu_gdb_write_register(env, mem_buf, reg);
+ return cc->gdb_write_register(cpu, mem_buf, reg);
}
for (r = cpu->gdb_regs; r; r = r->next) {
@@ -1199,7 +1133,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
const char *xml;
target_ulong total_len;
- gdb_has_xml = 1;
+ gdb_has_xml = true;
p += 19;
xml = get_feature_xml(p, &p);
if (!xml) {
@@ -1608,7 +1542,7 @@ static void gdb_accept(void)
s->c_cpu = first_cpu;
s->g_cpu = first_cpu;
s->fd = fd;
- gdb_has_xml = 0;
+ gdb_has_xml = false;
gdbserver_state = s;
@@ -1694,7 +1628,7 @@ static void gdb_chr_event(void *opaque, int event)
switch (event) {
case CHR_EVENT_OPENED:
vm_stop(RUN_STATE_PAUSED);
- gdb_has_xml = 0;
+ gdb_has_xml = false;
break;
default:
break;
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 5778b0e..ba96bd4 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -84,6 +84,14 @@ int gdbserver_start(int);
int gdbserver_start(const char *port);
#endif
+/**
+ * gdb_has_xml:
+ * This is an ugly hack to cope with both new and old gdb.
+ * If gdb sends qXfer:features:read then assume we're talking to a newish
+ * gdb that understands target descriptions.
+ */
+extern bool gdb_has_xml;
+
/* in gdbstub-xml.c, generated by scripts/feature_to_c.sh */
extern const char *const xml_builtin[][2];
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7b953c0..68b9879 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -76,6 +76,8 @@ struct TranslationBlock;
* @synchronize_from_tb: Callback for synchronizing state from a TCG
* #TranslationBlock.
* @get_phys_page_debug: Callback for obtaining a physical address.
+ * @gdb_read_register: Callback for letting GDB read a register.
+ * @gdb_write_register: Callback for letting GDB write a register.
* @vmsd: State description for migration.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
*
@@ -105,6 +107,8 @@ typedef struct CPUClass {
void (*set_pc)(CPUState *cpu, vaddr value);
void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
+ int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/qom/cpu.c b/qom/cpu.c
index 2839ddf..dbc9fb6 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -157,6 +157,17 @@ static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
}
+static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
+{
+ return 0;
+}
+
+static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
+{
+ return 0;
+}
+
+
void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
@@ -253,6 +264,8 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf32_note = cpu_common_write_elf32_note;
k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
k->write_elf64_note = cpu_common_write_elf64_note;
+ k->gdb_read_register = cpu_common_gdb_read_register;
+ k->gdb_write_register = cpu_common_gdb_write_register;
dc->realize = cpu_common_realizefn;
dc->no_user = 1;
}
diff --git a/target-alpha/Makefile.objs b/target-alpha/Makefile.objs
index 590304c..b96c5da 100644
--- a/target-alpha/Makefile.objs
+++ b/target-alpha/Makefile.objs
@@ -1,3 +1,4 @@
obj-$(CONFIG_SOFTMMU) += machine.o
obj-y += translate.o helper.o cpu.o
obj-y += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
+obj-y += gdbstub.o
diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h
index b2eeba3..2ebc9bc 100644
--- a/target-alpha/cpu-qom.h
+++ b/target-alpha/cpu-qom.h
@@ -82,5 +82,7 @@ void alpha_cpu_do_interrupt(CPUState *cpu);
void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index cc0f69a..64c70bc 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -271,6 +271,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = alpha_cpu_do_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
+ cc->gdb_read_register = alpha_cpu_gdb_read_register;
+ cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->do_unassigned_access = alpha_cpu_unassigned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
diff --git a/target-alpha/gdbstub.c b/target-alpha/gdbstub.c
index 1c18698..980f140 100644
--- a/target-alpha/gdbstub.c
+++ b/target-alpha/gdbstub.c
@@ -17,9 +17,14 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
-static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
+int alpha_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
uint64_t val;
CPU_DoubleU d;
@@ -52,8 +57,10 @@ static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, val);
}
-static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
+int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
target_ulong tmp = ldtul_p(mem_buf);
CPU_DoubleU d;
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index 4a6e52e..2d9f77f 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -4,3 +4,4 @@ obj-$(CONFIG_KVM) += kvm.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += neon_helper.o iwmmxt_helper.o
+obj-y += gdbstub.o
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 02162c9..cf36587 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -149,4 +149,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index cbb0c9e..103a840 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -819,6 +819,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_cpu_do_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
+ cc->gdb_read_register = arm_cpu_gdb_read_register;
+ cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_arm_cpu;
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index e1c7df4..1c34396 100644
--- a/target-arm/gdbstub.c
+++ b/target-arm/gdbstub.c
@@ -17,6 +17,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
whatever the target description contains. Due to a historical mishap
@@ -24,8 +27,11 @@
We hack round this by giving the FPA regs zero size when talking to a
newer gdb. */
-static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
+int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
if (n < 16) {
/* Core integer register. */
return gdb_get_reg32(mem_buf, env->regs[n]);
@@ -53,8 +59,10 @@ static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
+int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
uint32_t tmp;
tmp = ldl_p(mem_buf);
diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
index afb87bc..7779227 100644
--- a/target-cris/Makefile.objs
+++ b/target-cris/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
index d7baf07..3e92ea0 100644
--- a/target-cris/cpu-qom.h
+++ b/target-cris/cpu-qom.h
@@ -81,4 +81,7 @@ void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+
#endif
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 31eeddf..8fcc95d 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -255,6 +255,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = cris_cpu_do_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
+ cc->gdb_read_register = cris_cpu_gdb_read_register;
+ cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
#endif
diff --git a/target-cris/gdbstub.c b/target-cris/gdbstub.c
index ed23966..958a370 100644
--- a/target-cris/gdbstub.c
+++ b/target-cris/gdbstub.c
@@ -17,6 +17,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
static int
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
@@ -48,8 +51,10 @@ read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
+int cris_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
uint8_t srs;
if (env->pregs[PR_VR] < 32) {
@@ -85,8 +90,10 @@ static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
+int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
uint32_t tmp;
if (n > 49) {
diff --git a/target-i386/Makefile.objs b/target-i386/Makefile.objs
index c1d4f05..3b629d4d 100644
--- a/target-i386/Makefile.objs
+++ b/target-i386/Makefile.objs
@@ -1,6 +1,7 @@
obj-y += translate.o helper.o cpu.o
obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o
obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o
+obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o
obj-$(CONFIG_KVM) += kvm.o hyperv.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index d928562..60d2b5d 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -106,4 +106,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index df9832e..2b59b7d 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2538,6 +2538,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->gdb_read_register = x86_cpu_gdb_read_register;
+ cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c
index 0a4d97d..15bebef 100644
--- a/target-i386/gdbstub.c
+++ b/target-i386/gdbstub.c
@@ -17,6 +17,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
#ifdef TARGET_X86_64
static const int gpr_map[16] = {
@@ -35,8 +38,11 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define IDX_XMM_REGS (IDX_FP_REGS + 16)
#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
-static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
+int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
@@ -108,8 +114,9 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
+static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
{
+ CPUX86State *env = &cpu->env;
uint16_t selector = ldl_p(mem_buf);
if (selector != env->segs[sreg].selector) {
@@ -135,8 +142,10 @@ static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
return 4;
}
-static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
+int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
uint32_t tmp;
if (n < CPU_NB_REGS) {
@@ -179,17 +188,17 @@ static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
return 4;
case IDX_SEG_REGS:
- return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
+ return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
case IDX_SEG_REGS + 1:
- return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
+ return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
case IDX_SEG_REGS + 2:
- return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
+ return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
case IDX_SEG_REGS + 3:
- return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
+ return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
case IDX_SEG_REGS + 4:
- return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
+ return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
case IDX_SEG_REGS + 5:
- return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
+ return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
case IDX_FP_REGS + 8:
env->fpuc = ldl_p(mem_buf);
diff --git a/target-lm32/Makefile.objs b/target-lm32/Makefile.objs
index ca20f21..4023687 100644
--- a/target-lm32/Makefile.objs
+++ b/target-lm32/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += machine.o
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index 9e27329..723f604 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -79,5 +79,7 @@ void lm32_cpu_do_interrupt(CPUState *cpu);
void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index aa52696..962d553 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -87,6 +87,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = lm32_cpu_do_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
+ cc->gdb_read_register = lm32_cpu_gdb_read_register;
+ cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
diff --git a/target-lm32/gdbstub.c b/target-lm32/gdbstub.c
index 17f08f5..4979a98 100644
--- a/target-lm32/gdbstub.c
+++ b/target-lm32/gdbstub.c
@@ -17,10 +17,16 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
#include "hw/lm32/lm32_pic.h"
-static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
+int lm32_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPULM32State *env = &cpu->env;
+
if (n < 32) {
return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
@@ -45,10 +51,11 @@ static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
+int lm32_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ CPULM32State *env = &cpu->env;
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
diff --git a/target-m68k/Makefile.objs b/target-m68k/Makefile.objs
index 2e2b850..02cf616 100644
--- a/target-m68k/Makefile.objs
+++ b/target-m68k/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += m68k-semi.o
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += gdbstub.o
diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h
index 7115707..7f388ed 100644
--- a/target-m68k/cpu-qom.h
+++ b/target-m68k/cpu-qom.h
@@ -74,5 +74,7 @@ void m68k_cpu_do_interrupt(CPUState *cpu);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 93200d9..01a70f1 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -190,6 +190,8 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->do_interrupt = m68k_cpu_do_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
+ cc->gdb_read_register = m68k_cpu_gdb_read_register;
+ cc->gdb_write_register = m68k_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
diff --git a/target-m68k/gdbstub.c b/target-m68k/gdbstub.c
index 9fa9fa6..ae8179c 100644
--- a/target-m68k/gdbstub.c
+++ b/target-m68k/gdbstub.c
@@ -17,9 +17,15 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
-static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
+int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (n < 8) {
/* D0-D7 */
return gdb_get_reg32(mem_buf, env->dregs[n]);
@@ -39,8 +45,10 @@ static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
+int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
uint32_t tmp;
tmp = ldl_p(mem_buf);
diff --git a/target-microblaze/Makefile.objs b/target-microblaze/Makefile.objs
index 985330e..f3d7b44 100644
--- a/target-microblaze/Makefile.objs
+++ b/target-microblaze/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += mmu.o
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index 1318a36..35a12b4 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -75,5 +75,7 @@ void mb_cpu_do_interrupt(CPUState *cs);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 758b0cb..c75d1bd 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -141,6 +141,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = mb_cpu_do_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
+ cc->gdb_read_register = mb_cpu_gdb_read_register;
+ cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->do_unassigned_access = mb_cpu_unassigned_access;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
diff --git a/target-microblaze/gdbstub.c b/target-microblaze/gdbstub.c
index 678de21..a70e2ee 100644
--- a/target-microblaze/gdbstub.c
+++ b/target-microblaze/gdbstub.c
@@ -17,9 +17,15 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
-static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
+int mb_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
if (n < 32) {
return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
@@ -28,10 +34,11 @@ static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
+int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ CPUMBState *env = &cpu->env;
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs
index 119c816..0277d56 100644
--- a/target-mips/Makefile.objs
+++ b/target-mips/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o
+obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += machine.o
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h
index 7c8e616..8877f81 100644
--- a/target-mips/cpu-qom.h
+++ b/target-mips/cpu-qom.h
@@ -78,5 +78,7 @@ void mips_cpu_do_interrupt(CPUState *cpu);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index e667fb7..f81f9e9 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -100,6 +100,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
+ cc->gdb_read_register = mips_cpu_gdb_read_register;
+ cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->do_unassigned_access = mips_cpu_unassigned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index db826d8..5b72d58 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -17,9 +17,15 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
-static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
+int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
if (n < 32) {
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
}
@@ -78,8 +84,10 @@ static unsigned int ieee_rm[] = {
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
&env->active_fpu.fp_status)
-static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
+int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
target_ulong tmp;
tmp = ldtul_p(mem_buf);
diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs
index 44dc539..397d016 100644
--- a/target-openrisc/Makefile.objs
+++ b/target-openrisc/Makefile.objs
@@ -2,3 +2,4 @@ obj-$(CONFIG_SOFTMMU) += machine.o
obj-y += cpu.o exception.o interrupt.o mmu.o translate.o
obj-y += exception_helper.o fpu_helper.o int_helper.o \
interrupt_helper.o mmu_helper.o sys_helper.o
+obj-y += gdbstub.o
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index b814e46..a526210 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -154,6 +154,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = openrisc_cpu_do_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
+ cc->gdb_read_register = openrisc_cpu_gdb_read_register;
+ cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 3ddb767..8fd0bc0 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -350,6 +350,8 @@ void openrisc_cpu_do_interrupt(CPUState *cpu);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
target_ulong address,
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
index bdb8d2c..18bcc46 100644
--- a/target-openrisc/gdbstub.c
+++ b/target-openrisc/gdbstub.c
@@ -17,9 +17,15 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
-static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
+int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ CPUOpenRISCState *env = &cpu->env;
+
if (n < 32) {
return gdb_get_reg32(mem_buf, env->gpr[n]);
} else {
@@ -40,11 +46,11 @@ static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUOpenRISCState *env,
- uint8_t *mem_buf, int n)
+int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ CPUOpenRISCState *env = &cpu->env;
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs
index 6e78cb3..f72e399 100644
--- a/target-ppc/Makefile.objs
+++ b/target-ppc/Makefile.objs
@@ -13,3 +13,4 @@ obj-y += timebase_helper.o
obj-y += misc_helper.o
obj-y += mem_helper.o
obj-$(CONFIG_USER_ONLY) += user_only_helper.o
+obj-y += gdbstub.o
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 3341c51..fc0d737 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -106,5 +106,7 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index 40a9d7b..1c91090 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -17,6 +17,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
* expects whatever the target description contains. Due to a
@@ -25,8 +28,11 @@
* FP regs zero size when talking to a newer gdb.
*/
-static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
+int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
/* gprs */
return gdb_get_regl(mem_buf, env->gpr[n]);
@@ -70,8 +76,11 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
+int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
if (n < 32) {
/* gprs */
env->gpr[n] = ldtul_p(mem_buf);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 795225a..1bd3eaf 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8299,6 +8299,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
+ cc->gdb_read_register = ppc_cpu_gdb_read_register;
+ cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
#endif
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 4e63417..ab938e7 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,4 +1,5 @@
obj-y += translate.o helper.o cpu.o interrupt.o
obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
+obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += ioinst.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h
index a4fe8fb..0d63b1c 100644
--- a/target-s390x/cpu-qom.h
+++ b/target-s390x/cpu-qom.h
@@ -75,5 +75,7 @@ void s390_cpu_do_interrupt(CPUState *cpu);
void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 8f99d7c..1d16da3 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -173,6 +173,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = s390_cpu_do_interrupt;
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
+ cc->gdb_read_register = s390_cpu_gdb_read_register;
+ cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
#endif
diff --git a/target-s390x/gdbstub.c b/target-s390x/gdbstub.c
index ee3e984..a129742 100644
--- a/target-s390x/gdbstub.c
+++ b/target-s390x/gdbstub.c
@@ -17,9 +17,15 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
+#include "qemu/bitops.h"
-static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
+int s390_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
uint64_t val;
int cc_op;
@@ -43,8 +49,10 @@ static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
+int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
target_ulong tmpl;
uint32_t tmp32;
int r = 8;
diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs
index cb448a8..a285358 100644
--- a/target-sh4/Makefile.objs
+++ b/target-sh4/Makefile.objs
@@ -1 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += gdbstub.o
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 7c9160b..c04e786 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -87,5 +87,7 @@ void superh_cpu_do_interrupt(CPUState *cpu);
void superh_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 35f0535..bda3c51 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -286,6 +286,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
+ cc->gdb_read_register = superh_cpu_gdb_read_register;
+ cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
diff --git a/target-sh4/gdbstub.c b/target-sh4/gdbstub.c
index fb85718..df4fa2a 100644
--- a/target-sh4/gdbstub.c
+++ b/target-sh4/gdbstub.c
@@ -17,12 +17,18 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
/* FIXME: We should use XML for this. */
-static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
+int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
switch (n) {
case 0 ... 7:
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
@@ -70,8 +76,11 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
+int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
switch (n) {
case 0 ... 7:
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
index 9fc42ea..1cd81cc 100644
--- a/target-sparc/Makefile.objs
+++ b/target-sparc/Makefile.objs
@@ -4,3 +4,4 @@ obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
obj-$(TARGET_SPARC) += int32_helper.o
obj-$(TARGET_SPARC64) += int64_helper.o
obj-$(TARGET_SPARC64) += vis_helper.o
+obj-y += gdbstub.o
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
index 39d975b..8e3e0de 100644
--- a/target-sparc/cpu-qom.h
+++ b/target-sparc/cpu-qom.h
@@ -79,5 +79,7 @@ void sparc_cpu_do_interrupt(CPUState *cpu);
void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 388a632..c7b4a90 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -787,6 +787,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->set_pc = sparc_cpu_set_pc;
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
+ cc->gdb_read_register = sparc_cpu_gdb_read_register;
+ cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->do_unassigned_access = sparc_cpu_unassigned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
diff --git a/target-sparc/gdbstub.c b/target-sparc/gdbstub.c
index 460c0b7..3de3242 100644
--- a/target-sparc/gdbstub.c
+++ b/target-sparc/gdbstub.c
@@ -17,6 +17,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
#ifdef TARGET_ABI32
#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val)
@@ -24,8 +27,11 @@
#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
#endif
-static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
+int sparc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
if (n < 8) {
/* g0..g7 */
return gdb_get_rega(mem_buf, env->gregs[n]);
@@ -98,8 +104,10 @@ static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
+int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
#if defined(TARGET_ABI32)
abi_ulong tmp;
diff --git a/target-xtensa/Makefile.objs b/target-xtensa/Makefile.objs
index 644b7f9..5c150a8 100644
--- a/target-xtensa/Makefile.objs
+++ b/target-xtensa/Makefile.objs
@@ -3,3 +3,4 @@ obj-y += core-dc232b.o
obj-y += core-dc233c.o
obj-y += core-fsf.o
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += gdbstub.o
diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index 1b9479e..c6cc2d9 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -87,5 +87,7 @@ void xtensa_cpu_do_interrupt(CPUState *cpu);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 560fa0c..e966aa0 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -133,6 +133,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = xtensa_cpu_do_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
+ cc->gdb_read_register = xtensa_cpu_gdb_read_register;
+ cc->gdb_write_register = xtensa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
diff --git a/target-xtensa/gdbstub.c b/target-xtensa/gdbstub.c
index c963563..9e13b20 100644
--- a/target-xtensa/gdbstub.c
+++ b/target-xtensa/gdbstub.c
@@ -17,9 +17,14 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
-static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
+int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
@@ -55,8 +60,10 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
}
}
-static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
+int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
uint32_t tmp;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 41/42] target-cris: Factor out CPUClass::gdb_read_register() hook for v10
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (39 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 40/42] cpu: Introduce CPUClass::gdb_{read, write}_register() Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 42/42] cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML Andreas Färber
2013-07-09 21:03 ` [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-cris/cpu-qom.h | 1 +
target-cris/cpu.c | 4 ++++
target-cris/gdbstub.c | 10 ++++------
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
index 3e92ea0..7559366 100644
--- a/target-cris/cpu-qom.h
+++ b/target-cris/cpu-qom.h
@@ -81,6 +81,7 @@ void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 8fcc95d..45f2d6b 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -175,6 +175,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 8;
cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->gdb_read_register = crisv10_cpu_gdb_read_register;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -184,6 +185,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 9;
cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->gdb_read_register = crisv10_cpu_gdb_read_register;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -193,6 +195,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 10;
cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->gdb_read_register = crisv10_cpu_gdb_read_register;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -202,6 +205,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 11;
cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->gdb_read_register = crisv10_cpu_gdb_read_register;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-cris/gdbstub.c b/target-cris/gdbstub.c
index 958a370..5db3683 100644
--- a/target-cris/gdbstub.c
+++ b/target-cris/gdbstub.c
@@ -21,9 +21,11 @@
#include "qemu-common.h"
#include "exec/gdbstub.h"
-static int
-read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
+int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
+
if (n < 15) {
return gdb_get_reg32(mem_buf, env->regs[n]);
}
@@ -57,10 +59,6 @@ int cris_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUCRISState *env = &cpu->env;
uint8_t srs;
- if (env->pregs[PR_VR] < 32) {
- return read_register_crisv10(env, mem_buf, n);
- }
-
srs = env->pregs[PR_SRS];
if (n < 16) {
return gdb_get_reg32(mem_buf, env->regs[n]);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 42/42] cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (40 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 41/42] target-cris: Factor out CPUClass::gdb_read_register() hook for v10 Andreas Färber
@ 2013-07-07 18:26 ` Andreas Färber
2013-07-09 21:03 ` [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-07 18:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Alexander Graf, open list:PowerPC,
Andreas Färber, Paul Brook
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field.
Use first_cpu for qSupported and qXfer:features:read: for now.
Add a stub for xml_builtin.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 42 ++++++++++++++----------------------------
include/qom/cpu.h | 2 ++
stubs/Makefile.objs | 1 +
stubs/gdbstub.c | 5 +++++
target-arm/cpu.c | 1 +
target-m68k/cpu.c | 1 +
target-ppc/translate_init.c | 5 +++++
7 files changed, 29 insertions(+), 28 deletions(-)
create mode 100644 stubs/gdbstub.c
diff --git a/gdbstub.c b/gdbstub.c
index 1ec6d31..eb1d12b 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -485,25 +485,6 @@ static int put_packet(GDBState *s, const char *buf)
return put_packet_binary(s, buf, strlen(buf));
}
-#if defined(TARGET_PPC)
-
-#if defined (TARGET_PPC64)
-#define GDB_CORE_XML "power64-core.xml"
-#else
-#define GDB_CORE_XML "power-core.xml"
-#endif
-
-#elif defined (TARGET_ARM)
-
-#define GDB_CORE_XML "arm-core.xml"
-
-#elif defined (TARGET_M68K)
-
-#define GDB_CORE_XML "cf-core.xml"
-
-#endif
-
-#ifdef GDB_CORE_XML
/* Encode data using the encoding for 'x' packets. */
static int memtox(char *buf, const char *mem, int len)
{
@@ -525,7 +506,8 @@ static int memtox(char *buf, const char *mem, int len)
return p - buf;
}
-static const char *get_feature_xml(const char *p, const char **newp)
+static const char *get_feature_xml(const char *p, const char **newp,
+ CPUClass *cc)
{
size_t len;
int i;
@@ -549,7 +531,7 @@ static const char *get_feature_xml(const char *p, const char **newp)
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target>"
"<xi:include href=\"%s\"/>",
- GDB_CORE_XML);
+ cc->gdb_core_xml_file);
for (r = cpu->gdb_regs; r; r = r->next) {
pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
@@ -567,7 +549,6 @@ static const char *get_feature_xml(const char *p, const char **newp)
}
return name ? xml_builtin[i][1] : NULL;
}
-#endif
static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
@@ -760,6 +741,7 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
static int gdb_handle_packet(GDBState *s, const char *line_buf)
{
CPUState *cpu;
+ CPUClass *cc;
const char *p;
uint32_t thread;
int ch, reg_size, type, res;
@@ -1122,20 +1104,25 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
#endif /* !CONFIG_USER_ONLY */
if (strncmp(p, "Supported", 9) == 0) {
snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
-#ifdef GDB_CORE_XML
- pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
-#endif
+ cc = CPU_GET_CLASS(first_cpu);
+ if (cc->gdb_core_xml_file != NULL) {
+ pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
+ }
put_packet(s, buf);
break;
}
-#ifdef GDB_CORE_XML
if (strncmp(p, "Xfer:features:read:", 19) == 0) {
const char *xml;
target_ulong total_len;
+ cc = CPU_GET_CLASS(first_cpu);
+ if (cc->gdb_core_xml_file == NULL) {
+ goto unknown_command;
+ }
+
gdb_has_xml = true;
p += 19;
- xml = get_feature_xml(p, &p);
+ xml = get_feature_xml(p, &p, cc);
if (!xml) {
snprintf(buf, sizeof(buf), "E00");
put_packet(s, buf);
@@ -1167,7 +1154,6 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
put_packet_binary(s, buf, len + 1);
break;
}
-#endif
/* Unrecognised 'q' command. */
goto unknown_command;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 68b9879..c3f25be 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -80,6 +80,7 @@ struct TranslationBlock;
* @gdb_write_register: Callback for letting GDB write a register.
* @vmsd: State description for migration.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
+ * @gdb_core_xml_file: File name for core registers GDB XML description.
*
* Represents a CPU family or model.
*/
@@ -121,6 +122,7 @@ typedef struct CPUClass {
const struct VMStateDescription *vmsd;
int gdb_num_core_regs;
+ const char *gdb_core_xml_file;
} CPUClass;
struct KVMState;
diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs
index 9b701b4..f306cba 100644
--- a/stubs/Makefile.objs
+++ b/stubs/Makefile.objs
@@ -7,6 +7,7 @@ stub-obj-y += fdset-add-fd.o
stub-obj-y += fdset-find-fd.o
stub-obj-y += fdset-get-fd.o
stub-obj-y += fdset-remove-fd.o
+stub-obj-y += gdbstub.o
stub-obj-y += get-fd.o
stub-obj-y += get-vm-name.o
stub-obj-y += iothread-lock.o
diff --git a/stubs/gdbstub.c b/stubs/gdbstub.c
new file mode 100644
index 0000000..c1dbfe7
--- /dev/null
+++ b/stubs/gdbstub.c
@@ -0,0 +1,5 @@
+#include "qemu-common.h"
+
+const char *const xml_builtin[][2] = {
+ { NULL, NULL }
+};
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 103a840..c145277 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -826,6 +826,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_arm_cpu;
#endif
cc->gdb_num_core_regs = 26;
+ cc->gdb_core_xml_file = "arm-core.xml";
}
static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 01a70f1..c0bcb0d 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -197,6 +197,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#endif
dc->vmsd = &vmstate_m68k_cpu;
cc->gdb_num_core_regs = 18;
+ cc->gdb_core_xml_file = "cf-core.xml";
}
static void register_cpu_type(const M68kCPUInfo *info)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1bd3eaf..a20a941 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8306,6 +8306,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 71;
+#if defined(TARGET_PPC64)
+ cc->gdb_core_xml_file = "power64-core.xml";
+#else
+ cc->gdb_core_xml_file = "power-core.xml";
+#endif
}
static const TypeInfo ppc_cpu_type_info = {
--
1.8.1.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
` (41 preceding siblings ...)
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 42/42] cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML Andreas Färber
@ 2013-07-09 21:03 ` Andreas Färber
42 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-09 21:03 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Green, Blue Swirl, Max Filippov,
Michael Walle, Jan Kiszka, Anthony Liguori, Paolo Bonzini,
Guan Xuetao, Aurélien Jarno, Richard Henderson
Am 07.07.2013 20:25, schrieb Andreas Färber:
> Hello,
>
> This series cleans up gdbstub by changing all its internal CPU state to CPUState
> and by moving most target-specific code into the target directories.
>
> Support for m68k, moxie and unicore32 to set the PC via gdbstub is added.
>
> Lightweight subclasses for XtensaCPU are introduced, keeping the XtensaConfig
> mechanisms, to stop xtensa from deviating at gdbstub level wrt register count.
>
> I still wonder whether there would be interest in adding a "program-counter"
> dynamic property to the CPU, given that a setter has been factored out here?
>
> v2 replaces uint64_t with a new vaddr type, fixes xtensa breakage, adds a patch
> replacing GDB_CORE_XML and attempts to make the read/write_register changes
> better reviewable. More details below.
Needs to be respun to keep find_cpu() around - any comments before I do?
Andreas
>
> Available for testing at:
> git://github.com/afaerber/qemu-cpu.git qom-cpu-11.v2
> https://github.com/afaerber/qemu-cpu/commits/qom-cpu-11.v2
>
> Regards,
> Andreas
>
> v1 -> v2:
> * Applied some patches.
> * Introduced new vaddr type, name courtesy of PMM.
> * Avoided making the TranslationBlock typedef generally available.
> * Rebased to avoid env/cpu field in alpha DisasContext (rth).
> * Added missing ppc_cpu_get_phys_page_debug assignment.
> * Converted two more cpu_get_phys_page_debug()s breaking xtensa (Max).
> * Simplified xtensa subclasses by keeping CPUXtensaState::config for now (Max).
> * Split up cpu_gdb_{read,write}_register() conversion (rth).
> * Appended patch to drop GDB_CORE_XML.
>
> Cc: Anthony Liguori <anthony@codemonkey.ws>
> Cc: Blue Swirl <blauwirbel@gmail.com>
> Cc: Aurélien Jarno <aurelien@aurel32.net>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Jan Kiszka <jan.kiszka@web.de> (gdbstub)
> Cc: Anthony Green <green@moxielogic.com> (moxie)
> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> (unicore32)
> Cc: Max Filippov <jcmvbkbc@gmail.com> (xtensa)
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Michael Walle <michael@walle.cc> (lm32)
> Cc: Peter Maydell <peter.maydell@linaro.org> (vaddr)
>
> Andreas Färber (42):
> cpu: Introduce vaddr type
> cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
> target-m68k: Implement CPUClass::set_pc()
> target-moxie: Implement CPUClass::set_pc()
> target-unicore32: Implement CPUClass::set_pc()
> cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
> cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
> gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style
> cpu: Change cpu_single_step() argument to CPUState
> kvm: Change kvm_{insert,remove}_breakpoint() argument to CPUState
> gdbstub: Change syscall callback argument to CPUState
> gdbstub: Change gdb_handlesig() argument to CPUState
> gdbstub: Change GDBState::c_cpu to CPUState
> gdbstub: Change gdb_{read,write}_register() argument to CPUState
> cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
> exec: Change cpu_memory_rw_debug() argument to CPUState
> cpu: Introduce CPUClass::memory_rw_debug() for
> target_memory_rw_debug()
> gdbstub: Change GDBState::g_cpu to CPUState
> cpu: Move gdb_regs field from CPU_COMMON to CPUState
> gdbstub: Change gdb_register_coprocessor() argument to CPUState
> target-xtensa: Introduce XtensaCPU subclasses
> gdbstub: Fix cpu_gdb_{read,write}_register() Coding Style
> gdbstub: Drop dead code in cpu_gdb_{read,write}_register()
> cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
> target-i386: Move cpu_gdb_{read,write}_register()
> target-ppc: Move cpu_gdb_{read,write}_register()
> target-sparc: Move cpu_gdb_{read,write}_register()
> target-arm: Move cpu_gdb_{read,write}_register()
> target-m68k: Move cpu_gdb_{read,write}_register()
> target-mips: Move cpu_gdb_{read,write}_register()
> target-openrisc: Move cpu_gdb_{read,write}_register()
> target-sh4: Move cpu_gdb_{read,write}_register()
> target-microblaze: Move cpu_gdb_{read,write}_register()
> target-cris: Move cpu_gdb_{read,write}_register()
> target-alpha: Move cpu_gdb_{read,write}_register()
> target-s390x: Move cpu_gdb_{read,write}_register()
> target-lm32: Move cpu_gdb_{read,write}_register()
> target-xtensa: Move cpu_gdb_{read,write}_register()
> gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
> cpu: Introduce CPUClass::gdb_{read,write}_register()
> target-cris: Factor out CPUClass::gdb_read_register() hook for v10
> cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
>
> bsd-user/main.c | 10 +-
> cpu-exec.c | 10 +-
> cpus.c | 6 +-
> disas.c | 4 +-
> exec.c | 36 +-
> gdbstub.c | 1616 ++++-----------------------------------
> hw/i386/kvmvapic.c | 78 +-
> hw/xtensa/xtensa_lx60.c | 8 +-
> hw/xtensa/xtensa_sim.c | 10 +-
> include/exec/cpu-all.h | 14 +-
> include/exec/cpu-defs.h | 3 -
> include/exec/gdbstub.h | 51 +-
> include/exec/softmmu-semi.h | 18 +-
> include/qom/cpu.h | 122 +--
> include/sysemu/kvm.h | 4 +-
> kvm-all.c | 12 +-
> kvm-stub.c | 4 +-
> linux-user/main.c | 35 +-
> linux-user/signal.c | 3 +-
> monitor.c | 2 +-
> qom/cpu.c | 22 +
> stubs/Makefile.objs | 1 +
> stubs/gdbstub.c | 5 +
> target-alpha/Makefile.objs | 1 +
> target-alpha/cpu-qom.h | 3 +
> target-alpha/cpu.c | 18 +-
> target-alpha/cpu.h | 5 -
> target-alpha/gdbstub.c | 93 +++
> target-alpha/helper.c | 5 +-
> target-alpha/translate.c | 3 +-
> target-arm/Makefile.objs | 1 +
> target-arm/arm-semi.c | 10 +-
> target-arm/cpu-qom.h | 5 +
> target-arm/cpu.c | 17 +-
> target-arm/cpu.h | 5 -
> target-arm/gdbstub.c | 102 +++
> target-arm/helper.c | 15 +-
> target-arm/translate.c | 7 +-
> target-cris/Makefile.objs | 1 +
> target-cris/cpu-qom.h | 6 +
> target-cris/cpu.c | 19 +
> target-cris/cpu.h | 4 -
> target-cris/gdbstub.c | 130 ++++
> target-cris/helper.c | 7 +-
> target-cris/translate.c | 7 +-
> target-i386/Makefile.objs | 1 +
> target-i386/cpu-qom.h | 5 +
> target-i386/cpu.c | 22 +-
> target-i386/cpu.h | 5 -
> target-i386/gdbstub.c | 231 ++++++
> target-i386/helper.c | 12 +-
> target-i386/kvm.c | 20 +-
> target-i386/translate.c | 5 +-
> target-lm32/Makefile.objs | 1 +
> target-lm32/cpu-qom.h | 3 +
> target-lm32/cpu.c | 16 +-
> target-lm32/cpu.h | 5 -
> target-lm32/gdbstub.c | 92 +++
> target-lm32/helper.c | 6 +-
> target-lm32/translate.c | 7 +-
> target-m68k/Makefile.objs | 1 +
> target-m68k/cpu-qom.h | 3 +
> target-m68k/cpu.c | 15 +
> target-m68k/cpu.h | 5 -
> target-m68k/gdbstub.c | 75 ++
> target-m68k/helper.c | 5 +-
> target-m68k/m68k-semi.c | 5 +-
> target-m68k/translate.c | 7 +-
> target-microblaze/Makefile.objs | 1 +
> target-microblaze/cpu-qom.h | 3 +
> target-microblaze/cpu.c | 16 +-
> target-microblaze/cpu.h | 5 -
> target-microblaze/gdbstub.c | 56 ++
> target-microblaze/helper.c | 4 +-
> target-microblaze/translate.c | 8 +-
> target-mips/Makefile.objs | 1 +
> target-mips/cpu-qom.h | 3 +
> target-mips/cpu.c | 34 +-
> target-mips/cpu.h | 7 -
> target-mips/gdbstub.c | 155 ++++
> target-mips/helper.c | 7 +-
> target-mips/translate.c | 11 +-
> target-moxie/cpu.c | 13 +-
> target-moxie/cpu.h | 6 +-
> target-moxie/helper.c | 11 +-
> target-moxie/translate.c | 5 +-
> target-openrisc/Makefile.objs | 1 +
> target-openrisc/cpu.c | 16 +-
> target-openrisc/cpu.h | 8 +-
> target-openrisc/gdbstub.c | 83 ++
> target-openrisc/mmu.c | 5 +-
> target-openrisc/translate.c | 7 +-
> target-ppc/Makefile.objs | 1 +
> target-ppc/cpu-qom.h | 3 +
> target-ppc/cpu.h | 5 -
> target-ppc/gdbstub.c | 131 ++++
> target-ppc/mmu_helper.c | 4 +-
> target-ppc/translate.c | 8 +-
> target-ppc/translate_init.c | 35 +-
> target-s390x/Makefile.objs | 1 +
> target-s390x/cpu-qom.h | 3 +
> target-s390x/cpu.c | 14 +
> target-s390x/cpu.h | 5 -
> target-s390x/gdbstub.c | 88 +++
> target-s390x/helper.c | 5 +-
> target-s390x/translate.c | 5 +-
> target-sh4/Makefile.objs | 1 +
> target-sh4/cpu-qom.h | 3 +
> target-sh4/cpu.c | 23 +
> target-sh4/cpu.h | 6 -
> target-sh4/gdbstub.c | 146 ++++
> target-sh4/helper.c | 5 +-
> target-sh4/translate.c | 8 +-
> target-sparc/Makefile.objs | 1 +
> target-sparc/cpu-qom.h | 3 +
> target-sparc/cpu.c | 34 +-
> target-sparc/cpu.h | 11 +-
> target-sparc/gdbstub.c | 208 +++++
> target-sparc/mmu_helper.c | 22 +-
> target-sparc/translate.c | 3 +-
> target-unicore32/cpu-qom.h | 1 +
> target-unicore32/cpu.c | 11 +
> target-unicore32/cpu.h | 5 -
> target-unicore32/softmmu.c | 7 +-
> target-unicore32/translate.c | 7 +-
> target-xtensa/Makefile.objs | 1 +
> target-xtensa/cpu-qom.h | 6 +
> target-xtensa/cpu.c | 40 +-
> target-xtensa/cpu.h | 5 -
> target-xtensa/gdbstub.c | 109 +++
> target-xtensa/helper.c | 47 +-
> target-xtensa/translate.c | 7 +-
> target-xtensa/xtensa-semi.c | 14 +-
> 133 files changed, 2701 insertions(+), 1892 deletions(-)
> create mode 100644 stubs/gdbstub.c
> create mode 100644 target-alpha/gdbstub.c
> create mode 100644 target-arm/gdbstub.c
> create mode 100644 target-cris/gdbstub.c
> create mode 100644 target-i386/gdbstub.c
> create mode 100644 target-lm32/gdbstub.c
> create mode 100644 target-m68k/gdbstub.c
> create mode 100644 target-microblaze/gdbstub.c
> create mode 100644 target-mips/gdbstub.c
> create mode 100644 target-openrisc/gdbstub.c
> create mode 100644 target-ppc/gdbstub.c
> create mode 100644 target-s390x/gdbstub.c
> create mode 100644 target-sh4/gdbstub.c
> create mode 100644 target-sparc/gdbstub.c
> create mode 100644 target-xtensa/gdbstub.c
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type Andreas Färber
@ 2013-07-15 14:46 ` Peter Maydell
2013-07-22 14:48 ` Andreas Färber
0 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2013-07-15 14:46 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 7 July 2013 19:25, Andreas Färber <afaerber@suse.de> wrote:
> vaddr is to target_ulong what uintmax_t is to unsigned int.
>
> Its purpose is to allow turning per-target functions with target_ulong
> arguments into CPUClass hooks.
>
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> include/qom/cpu.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 147c256..4fd12a0 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -29,6 +29,14 @@
>
> typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque);
>
> +typedef uint64_t vaddr;
> +#define VADDR_PRId PRId64
> +#define VADDR_PRIu PRIu64
> +#define VADDR_PRIo PRIo64
> +#define VADDR_PRIx PRIx64
> +#define VADDR_PRIX PRIX64
> +#define VADDR_MAX UINT64_MAX
> +
This looks OK, but I think it could use a brief comment above
the typedef explaining its purpose, and an update to HACKING
to say when to use vaddr and when target_ulong.
thanks
-- PMM
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type
2013-07-15 14:46 ` Peter Maydell
@ 2013-07-22 14:48 ` Andreas Färber
0 siblings, 0 replies; 49+ messages in thread
From: Andreas Färber @ 2013-07-22 14:48 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Am 15.07.2013 16:46, schrieb Peter Maydell:
> On 7 July 2013 19:25, Andreas Färber <afaerber@suse.de> wrote:
>> vaddr is to target_ulong what uintmax_t is to unsigned int.
>>
>> Its purpose is to allow turning per-target functions with target_ulong
>> arguments into CPUClass hooks.
>>
>> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>> ---
>> include/qom/cpu.h | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
>> index 147c256..4fd12a0 100644
>> --- a/include/qom/cpu.h
>> +++ b/include/qom/cpu.h
>> @@ -29,6 +29,14 @@
>>
>> typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque);
>>
>> +typedef uint64_t vaddr;
>> +#define VADDR_PRId PRId64
>> +#define VADDR_PRIu PRIu64
>> +#define VADDR_PRIo PRIo64
>> +#define VADDR_PRIx PRIx64
>> +#define VADDR_PRIX PRIX64
>> +#define VADDR_MAX UINT64_MAX
>> +
>
> This looks OK, but I think it could use a brief comment above
> the typedef explaining its purpose, and an update to HACKING
> to say when to use vaddr and when target_ulong.
I've added a gtk-doc comment. Not sure about HACKING, that can still be
done as fully reviewed follow-up.
(Note that v3 was identical to the above.)
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2013-07-22 14:48 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-07-07 18:25 [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 01/42] cpu: Introduce vaddr type Andreas Färber
2013-07-15 14:46 ` Peter Maydell
2013-07-22 14:48 ` Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 02/42] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 03/42] target-m68k: Implement CPUClass::set_pc() Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 04/42] target-moxie: " Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 05/42] target-unicore32: " Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 06/42] cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() Andreas Färber
2013-07-07 18:25 ` [PATCH qom-cpu v2 07/42] cpu: Move singlestep_enabled field from CPU_COMMON to CPUState Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] " Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 08/42] gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 09/42] cpu: Change cpu_single_step() argument to CPUState Andreas Färber
2013-07-07 18:25 ` [PATCH qom-cpu v2 10/42] kvm: Change kvm_{insert,remove}_breakpoint() " Andreas Färber
2013-07-07 18:25 ` [Qemu-devel] [PATCH qom-cpu v2 10/42] kvm: Change kvm_{insert, remove}_breakpoint() " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 11/42] gdbstub: Change syscall callback " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 12/42] gdbstub: Change gdb_handlesig() " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 13/42] gdbstub: Change GDBState::c_cpu " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 14/42] gdbstub: Change gdb_{read, write}_register() argument " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 15/42] cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook Andreas Färber
2013-07-07 18:26 ` [PATCH qom-cpu v2 16/42] exec: Change cpu_memory_rw_debug() argument to CPUState Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 17/42] cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug() Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 18/42] gdbstub: Change GDBState::g_cpu to CPUState Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 19/42] cpu: Move gdb_regs field from CPU_COMMON " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 20/42] gdbstub: Change gdb_register_coprocessor() argument " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 21/42] target-xtensa: Introduce XtensaCPU subclasses Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 22/42] gdbstub: Fix cpu_gdb_{read, write}_register() Coding Style Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 23/42] gdbstub: Drop dead code in cpu_gdb_{read, write}_register() Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 24/42] cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 25/42] target-i386: Move cpu_gdb_{read, write}_register() Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 26/42] target-ppc: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 27/42] target-sparc: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 28/42] target-arm: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 29/42] target-m68k: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 30/42] target-mips: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 31/42] target-openrisc: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 32/42] target-sh4: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 33/42] target-microblaze: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 34/42] target-cris: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 35/42] target-alpha: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 36/42] target-s390x: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 37/42] target-lm32: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 38/42] target-xtensa: " Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 39/42] gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 40/42] cpu: Introduce CPUClass::gdb_{read, write}_register() Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 41/42] target-cris: Factor out CPUClass::gdb_read_register() hook for v10 Andreas Färber
2013-07-07 18:26 ` [Qemu-devel] [PATCH qom-cpu v2 42/42] cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML Andreas Färber
2013-07-09 21:03 ` [Qemu-devel] [PATCH qom-cpu v2 00/42] QOM CPUState, part 11: GDB stub Andreas Färber
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