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From: Santosh Shilimkar <santosh.shilimkar@ti.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org, Vaibhav Bedia <vaibhav.bedia@ti.com>,
	Will Deacon <will.deacon@arm.com>,
	Russell King <linux@arm.linux.org.uk>,
	Santosh Shilimkar <santosh.shilimkar@ti.com>
Subject: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Date: Thu, 1 Aug 2013 14:17:13 -0400	[thread overview]
Message-ID: <1375381033-13220-1-git-send-email-santosh.shilimkar@ti.com> (raw)

From: Vaibhav Bedia <vaibhav.bedia@ti.com>

The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the SMP_ON_UP support, we need to additionally check the
number the cores in Cortex-A9 MPCore configuration. Without
such a check in place, the startup code tries to execute
ALT_SMP() set of instructions which lead to CPU faults.

The issue was spotted on TI's Aegis device and this patch
makes now the device work with omap2plus_defconfig which
enables SMP by default. The change is kept limited to only
Cortex-A9 MPCore detection code.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>

Acked-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/kernel/head.S |   18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 9cf6063..4924b11 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -486,7 +486,23 @@ __fixup_smp:
 	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
 	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
 	teq	r0, #0x80000000		@ not part of a uniprocessor system?
-	moveq	pc, lr			@ yes, assume SMP
+	bne    __fixup_smp_on_up	@ no, assume UP
+
+	@ Core indicates it is SMP.  Check for Aegis SOC where a single
+	@ Cortex-A9 CPU is present but SMP operations fault.
+	mov	r4, #0x41000000
+	orr	r4, r4, #0x0000c000
+	orr	r4, r4, #0x00000090
+	teq	r3, r4			@ Check for ARM Cortex-A9
+	movne	pc, lr			@ Not ARM Cortex-A9,
+
+	mrc	p15, 4, r0, c15, c0	@ get SCU base address
+	teq	r0, #0x0		@ '0' on actual UP A9 hardware
+	beq	__fixup_smp_on_up	@ So its an A9 UP
+	ldr	r0, [r0, #4]		@ read SCU Config
+	and	r0, r0, #0x3		@ number of CPUs
+	teq	r0, #0x0		@ is 1?
+	movne	pc, lr
 
 __fixup_smp_on_up:
 	adr	r0, 1f
-- 
1.7.9.5


WARNING: multiple messages have this Message-ID (diff)
From: santosh.shilimkar@ti.com (Santosh Shilimkar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Date: Thu, 1 Aug 2013 14:17:13 -0400	[thread overview]
Message-ID: <1375381033-13220-1-git-send-email-santosh.shilimkar@ti.com> (raw)

From: Vaibhav Bedia <vaibhav.bedia@ti.com>

The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the SMP_ON_UP support, we need to additionally check the
number the cores in Cortex-A9 MPCore configuration. Without
such a check in place, the startup code tries to execute
ALT_SMP() set of instructions which lead to CPU faults.

The issue was spotted on TI's Aegis device and this patch
makes now the device work with omap2plus_defconfig which
enables SMP by default. The change is kept limited to only
Cortex-A9 MPCore detection code.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>

Acked-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/kernel/head.S |   18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 9cf6063..4924b11 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -486,7 +486,23 @@ __fixup_smp:
 	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
 	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
 	teq	r0, #0x80000000		@ not part of a uniprocessor system?
-	moveq	pc, lr			@ yes, assume SMP
+	bne    __fixup_smp_on_up	@ no, assume UP
+
+	@ Core indicates it is SMP.  Check for Aegis SOC where a single
+	@ Cortex-A9 CPU is present but SMP operations fault.
+	mov	r4, #0x41000000
+	orr	r4, r4, #0x0000c000
+	orr	r4, r4, #0x00000090
+	teq	r3, r4			@ Check for ARM Cortex-A9
+	movne	pc, lr			@ Not ARM Cortex-A9,
+
+	mrc	p15, 4, r0, c15, c0	@ get SCU base address
+	teq	r0, #0x0		@ '0' on actual UP A9 hardware
+	beq	__fixup_smp_on_up	@ So its an A9 UP
+	ldr	r0, [r0, #4]		@ read SCU Config
+	and	r0, r0, #0x3		@ number of CPUs
+	teq	r0, #0x0		@ is 1?
+	movne	pc, lr
 
 __fixup_smp_on_up:
 	adr	r0, 1f
-- 
1.7.9.5

             reply	other threads:[~2013-08-01 18:17 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-01 18:17 Santosh Shilimkar [this message]
2013-08-01 18:17 ` [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices Santosh Shilimkar
2013-08-02  9:53 ` Will Deacon
2013-08-02  9:53   ` Will Deacon
2013-08-02 12:32   ` Santosh Shilimkar
2013-08-02 12:32     ` Santosh Shilimkar
2013-08-02 14:18 ` Dave Martin
2013-08-02 14:18   ` Dave Martin
2013-08-02 15:18   ` Santosh Shilimkar
2013-08-02 15:18     ` Santosh Shilimkar
2013-08-02 14:45 ` Sudeep KarkadaNagesha
2013-08-02 14:45   ` Sudeep KarkadaNagesha
2013-08-02 15:22   ` Santosh Shilimkar
2013-08-02 15:22     ` Santosh Shilimkar
2013-08-02 15:45     ` Sudeep KarkadaNagesha
2013-08-02 15:45       ` Sudeep KarkadaNagesha
2013-08-02 15:48       ` Will Deacon
2013-08-02 15:48         ` Will Deacon
2013-08-12 18:34         ` Santosh Shilimkar
2013-08-12 18:34           ` Santosh Shilimkar
2013-08-13 11:19           ` Will Deacon
2013-08-13 11:19             ` Will Deacon
2013-08-13 13:31             ` Santosh Shilimkar
2013-08-13 13:31               ` Santosh Shilimkar
2013-08-23 17:08               ` Sekhar Nori
2013-08-23 17:08                 ` Sekhar Nori
2013-08-23 17:17                 ` Santosh Shilimkar
2013-08-23 17:17                   ` Santosh Shilimkar
2013-08-23 17:41                   ` Sekhar Nori
2013-08-23 17:41                     ` Sekhar Nori
2013-09-24 17:08               ` Will Deacon
2013-09-24 17:08                 ` Will Deacon
2013-09-24 17:43                 ` Santosh Shilimkar
2013-09-24 17:43                   ` Santosh Shilimkar

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