From: Sekhar Nori <nsekhar@ti.com> To: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Will Deacon <will.deacon@arm.com>, Russell King <linux@arm.linux.org.uk>, Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>, "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>, Vaibhav Bedia <vaibhav.bedia@ti.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices Date: Fri, 23 Aug 2013 23:11:06 +0530 [thread overview] Message-ID: <52179EB2.2050800@ti.com> (raw) In-Reply-To: <52179927.1020906@ti.com> On 8/23/2013 10:47 PM, Santosh Shilimkar wrote: > On Friday 23 August 2013 01:08 PM, Sekhar Nori wrote: >> On 8/13/2013 7:01 PM, Santosh Shilimkar wrote: >>> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote: >>>> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote: >>>>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote: >>>>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as >>>>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE >>>>>> is zero. >>>>>> >>>>> What do we do here ? Should we document this in the code and proceed ? >>>>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but >>>>> I am open for any other alternative. >>>> >>>> The only other alternative I can think of is forcing people to have >>>> CONFIG_SMP=n, but that blows away single zImage for your platform. >>>> >>> Yep which surely we don't want considering after so much effort we >>> have it working first place. How about going ahead with assumption >>> that PERIPH_BASE = 0 case doesn't work. >> >> I must be missing something but why cannot we use the SCU configuration >> register "CPU number" field to determine that its a UP? I do not have an >> OMAP4 board, but on AM437x, it certainly indicates only CPU0 present. >> > Thats what patch does. Yes, you are missing the point of dicussion. Right, I see that now after actually reading the complete patch :) > On real UP Cortex-A9, the base address read will return '0' which is > treated as invalid address in the patch. Will D pointed out that one Is this something defined by spec for all UP Cortex-A9 or just an observation on AM437x implementation? It sounds like the later? Thanks, Sekhar
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From: nsekhar@ti.com (Sekhar Nori) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices Date: Fri, 23 Aug 2013 23:11:06 +0530 [thread overview] Message-ID: <52179EB2.2050800@ti.com> (raw) In-Reply-To: <52179927.1020906@ti.com> On 8/23/2013 10:47 PM, Santosh Shilimkar wrote: > On Friday 23 August 2013 01:08 PM, Sekhar Nori wrote: >> On 8/13/2013 7:01 PM, Santosh Shilimkar wrote: >>> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote: >>>> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote: >>>>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote: >>>>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as >>>>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE >>>>>> is zero. >>>>>> >>>>> What do we do here ? Should we document this in the code and proceed ? >>>>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but >>>>> I am open for any other alternative. >>>> >>>> The only other alternative I can think of is forcing people to have >>>> CONFIG_SMP=n, but that blows away single zImage for your platform. >>>> >>> Yep which surely we don't want considering after so much effort we >>> have it working first place. How about going ahead with assumption >>> that PERIPH_BASE = 0 case doesn't work. >> >> I must be missing something but why cannot we use the SCU configuration >> register "CPU number" field to determine that its a UP? I do not have an >> OMAP4 board, but on AM437x, it certainly indicates only CPU0 present. >> > Thats what patch does. Yes, you are missing the point of dicussion. Right, I see that now after actually reading the complete patch :) > On real UP Cortex-A9, the base address read will return '0' which is > treated as invalid address in the patch. Will D pointed out that one Is this something defined by spec for all UP Cortex-A9 or just an observation on AM437x implementation? It sounds like the later? Thanks, Sekhar
next prev parent reply other threads:[~2013-08-23 17:41 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-08-01 18:17 [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices Santosh Shilimkar 2013-08-01 18:17 ` Santosh Shilimkar 2013-08-02 9:53 ` Will Deacon 2013-08-02 9:53 ` Will Deacon 2013-08-02 12:32 ` Santosh Shilimkar 2013-08-02 12:32 ` Santosh Shilimkar 2013-08-02 14:18 ` Dave Martin 2013-08-02 14:18 ` Dave Martin 2013-08-02 15:18 ` Santosh Shilimkar 2013-08-02 15:18 ` Santosh Shilimkar 2013-08-02 14:45 ` Sudeep KarkadaNagesha 2013-08-02 14:45 ` Sudeep KarkadaNagesha 2013-08-02 15:22 ` Santosh Shilimkar 2013-08-02 15:22 ` Santosh Shilimkar 2013-08-02 15:45 ` Sudeep KarkadaNagesha 2013-08-02 15:45 ` Sudeep KarkadaNagesha 2013-08-02 15:48 ` Will Deacon 2013-08-02 15:48 ` Will Deacon 2013-08-12 18:34 ` Santosh Shilimkar 2013-08-12 18:34 ` Santosh Shilimkar 2013-08-13 11:19 ` Will Deacon 2013-08-13 11:19 ` Will Deacon 2013-08-13 13:31 ` Santosh Shilimkar 2013-08-13 13:31 ` Santosh Shilimkar 2013-08-23 17:08 ` Sekhar Nori 2013-08-23 17:08 ` Sekhar Nori 2013-08-23 17:17 ` Santosh Shilimkar 2013-08-23 17:17 ` Santosh Shilimkar 2013-08-23 17:41 ` Sekhar Nori [this message] 2013-08-23 17:41 ` Sekhar Nori 2013-09-24 17:08 ` Will Deacon 2013-09-24 17:08 ` Will Deacon 2013-09-24 17:43 ` Santosh Shilimkar 2013-09-24 17:43 ` Santosh Shilimkar
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