* [Qemu-devel] [PATCH 01/16] qemu-char: Allocate CharDriverState in qemu_chr_new_from_opts
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2014-01-23 13:32 ` Andreas Färber
2013-11-12 16:33 ` [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected Corey Minyard
` (14 subsequent siblings)
15 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This allocates the CharDriverState structure and passes it in to the
open routine. This allows a coming option to automatically attempt to
reconnect a chardev if the connection fails. The chardev has to be
kept around so a reconnect can be done on it.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
backends/baum.c | 6 +-
backends/msmouse.c | 5 +-
hw/misc/ivshmem.c | 11 ++-
include/sysemu/char.h | 9 +--
include/ui/console.h | 4 +-
include/ui/qemu-spice.h | 6 +-
qemu-char.c | 180 ++++++++++++++++++++++--------------------------
spice-qemu-char.c | 14 ++--
ui/console.c | 10 +--
9 files changed, 113 insertions(+), 132 deletions(-)
diff --git a/backends/baum.c b/backends/baum.c
index 1132899..9910a74 100644
--- a/backends/baum.c
+++ b/backends/baum.c
@@ -561,10 +561,9 @@ static void baum_close(struct CharDriverState *chr)
g_free(baum);
}
-CharDriverState *chr_baum_init(void)
+CharDriverState *chr_baum_init(CharDriverState *chr)
{
BaumDriverState *baum;
- CharDriverState *chr;
brlapi_handle_t *handle;
#ifdef CONFIG_SDL
SDL_SysWMinfo info;
@@ -572,7 +571,7 @@ CharDriverState *chr_baum_init(void)
int tty;
baum = g_malloc0(sizeof(BaumDriverState));
- baum->chr = chr = g_malloc0(sizeof(CharDriverState));
+ baum->chr = chr;
chr->opaque = baum;
chr->chr_write = baum_write;
@@ -618,7 +617,6 @@ fail:
brlapi__closeConnection(handle);
fail_handle:
g_free(handle);
- g_free(chr);
g_free(baum);
return NULL;
}
diff --git a/backends/msmouse.c b/backends/msmouse.c
index c0dbfcd..b4e7a23 100644
--- a/backends/msmouse.c
+++ b/backends/msmouse.c
@@ -63,11 +63,8 @@ static void msmouse_chr_close (struct CharDriverState *chr)
g_free (chr);
}
-CharDriverState *qemu_chr_open_msmouse(void)
+CharDriverState *qemu_chr_open_msmouse(CharDriverState *chr)
{
- CharDriverState *chr;
-
- chr = g_malloc0(sizeof(CharDriverState));
chr->chr_write = msmouse_chr_write;
chr->chr_close = msmouse_chr_close;
chr->explicit_be_open = true;
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 8d144ba..75e83c3 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -291,12 +291,17 @@ static CharDriverState* create_eventfd_chr_device(void * opaque, EventNotifier *
{
/* create a event character device based on the passed eventfd */
IVShmemState *s = opaque;
- CharDriverState * chr;
+ CharDriverState *chr, *newchr;
int eventfd = event_notifier_get_fd(n);
- chr = qemu_chr_open_eventfd(eventfd);
-
+ newchr = g_malloc0(sizeof(*chr));
+ if (newchr == NULL) {
+ fprintf(stderr, "creating eventfd for eventfd %d failed\n", eventfd);
+ exit(-1);
+ }
+ chr = qemu_chr_open_eventfd(newchr, eventfd);
if (chr == NULL) {
+ g_free(newchr);
fprintf(stderr, "creating eventfd for eventfd %d failed\n", eventfd);
exit(-1);
}
diff --git a/include/sysemu/char.h b/include/sysemu/char.h
index ad101d9..44baf0f 100644
--- a/include/sysemu/char.h
+++ b/include/sysemu/char.h
@@ -282,21 +282,22 @@ CharDriverState *qemu_chr_find(const char *name);
QemuOpts *qemu_chr_parse_compat(const char *label, const char *filename);
-void register_char_driver(const char *name, CharDriverState *(*open)(QemuOpts *));
+void register_char_driver(const char *name,
+ CharDriverState *(*open)(CharDriverState *, QemuOpts *));
void register_char_driver_qapi(const char *name, ChardevBackendKind kind,
void (*parse)(QemuOpts *opts, ChardevBackend *backend, Error **errp));
/* add an eventfd to the qemu devices that are polled */
-CharDriverState *qemu_chr_open_eventfd(int eventfd);
+CharDriverState *qemu_chr_open_eventfd(CharDriverState *chr, int eventfd);
extern int term_escape_char;
CharDriverState *qemu_char_get_next_serial(void);
/* msmouse */
-CharDriverState *qemu_chr_open_msmouse(void);
+CharDriverState *qemu_chr_open_msmouse(CharDriverState *chr);
/* baum.c */
-CharDriverState *chr_baum_init(void);
+CharDriverState *chr_baum_init(CharDriverState *chr);
#endif
diff --git a/include/ui/console.h b/include/ui/console.h
index 98edf41..5e5c74d 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -300,9 +300,9 @@ void qemu_console_copy(QemuConsole *con, int src_x, int src_y,
DisplaySurface *qemu_console_surface(QemuConsole *con);
DisplayState *qemu_console_displaystate(QemuConsole *console);
-typedef CharDriverState *(VcHandler)(ChardevVC *vc);
+typedef CharDriverState *(VcHandler)(CharDriverState *chr, ChardevVC *vc);
-CharDriverState *vc_init(ChardevVC *vc);
+CharDriverState *vc_init(CharDriverState *chr, ChardevVC *vc);
void register_vc_handler(VcHandler *handler);
/* sdl.c */
diff --git a/include/ui/qemu-spice.h b/include/ui/qemu-spice.h
index 86c75c7..eadb9c9 100644
--- a/include/ui/qemu-spice.h
+++ b/include/ui/qemu-spice.h
@@ -46,9 +46,11 @@ int qemu_spice_migrate_info(const char *hostname, int port, int tls_port,
void do_info_spice_print(Monitor *mon, const QObject *data);
void do_info_spice(Monitor *mon, QObject **ret_data);
-CharDriverState *qemu_chr_open_spice_vmc(const char *type);
+CharDriverState *qemu_chr_open_spice_vmc(CharDriverState *chr,
+ const char *type);
#if SPICE_SERVER_VERSION >= 0x000c02
-CharDriverState *qemu_chr_open_spice_port(const char *name);
+CharDriverState *qemu_chr_open_spice_port(CharDriverSTate *chr,
+ const char *name);
void qemu_spice_register_ports(void);
#else
static inline CharDriverState *qemu_chr_open_spice_port(const char *name)
diff --git a/qemu-char.c b/qemu-char.c
index e00f84c..dd04cc0 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -232,11 +232,8 @@ static int null_chr_write(CharDriverState *chr, const uint8_t *buf, int len)
return len;
}
-static CharDriverState *qemu_chr_open_null(void)
+static CharDriverState *qemu_chr_open_null(CharDriverState *chr)
{
- CharDriverState *chr;
-
- chr = g_malloc0(sizeof(CharDriverState));
chr->chr_write = null_chr_write;
chr->explicit_be_open = true;
return chr;
@@ -519,12 +516,11 @@ static Notifier muxes_realize_notify = {
.notify = muxes_realize_done,
};
-static CharDriverState *qemu_chr_open_mux(CharDriverState *drv)
+static CharDriverState *qemu_chr_open_mux(CharDriverState *chr,
+ CharDriverState *drv)
{
- CharDriverState *chr;
MuxDriver *d;
- chr = g_malloc0(sizeof(CharDriverState));
d = g_malloc0(sizeof(MuxDriver));
chr->opaque = d;
@@ -894,12 +890,11 @@ static void fd_chr_close(struct CharDriverState *chr)
}
/* open a character device to a unix fd */
-static CharDriverState *qemu_chr_open_fd(int fd_in, int fd_out)
+static CharDriverState *qemu_chr_open_fd(CharDriverState *chr,
+ int fd_in, int fd_out)
{
- CharDriverState *chr;
FDCharDriver *s;
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(FDCharDriver));
s->fd_in = io_channel_from_fd(fd_in);
s->fd_out = io_channel_from_fd(fd_out);
@@ -914,7 +909,8 @@ static CharDriverState *qemu_chr_open_fd(int fd_in, int fd_out)
return chr;
}
-static CharDriverState *qemu_chr_open_pipe(ChardevHostdev *opts)
+static CharDriverState *qemu_chr_open_pipe(CharDriverState *chr,
+ ChardevHostdev *opts)
{
int fd_in, fd_out;
char filename_in[256], filename_out[256];
@@ -939,7 +935,7 @@ static CharDriverState *qemu_chr_open_pipe(ChardevHostdev *opts)
return NULL;
}
}
- return qemu_chr_open_fd(fd_in, fd_out);
+ return qemu_chr_open_fd(chr, fd_in, fd_out);
}
/* init terminal so that we can grab keys */
@@ -980,10 +976,9 @@ static void qemu_chr_close_stdio(struct CharDriverState *chr)
fd_chr_close(chr);
}
-static CharDriverState *qemu_chr_open_stdio(ChardevStdio *opts)
+static CharDriverState *qemu_chr_open_stdio(CharDriverState *chr,
+ ChardevStdio *opts)
{
- CharDriverState *chr;
-
if (is_daemonized()) {
error_report("cannot use stdio with -daemonize");
return NULL;
@@ -993,7 +988,7 @@ static CharDriverState *qemu_chr_open_stdio(ChardevStdio *opts)
fcntl(0, F_SETFL, O_NONBLOCK);
atexit(term_exit);
- chr = qemu_chr_open_fd(0, 1);
+ qemu_chr_open_fd(chr, 0, 1);
chr->chr_close = qemu_chr_close_stdio;
chr->chr_set_echo = qemu_chr_set_echo_stdio;
if (opts->has_signal) {
@@ -1160,10 +1155,10 @@ static void pty_chr_close(struct CharDriverState *chr)
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
-static CharDriverState *qemu_chr_open_pty(const char *id,
+static CharDriverState *qemu_chr_open_pty(CharDriverState *chr,
+ const char *id,
ChardevReturn *ret)
{
- CharDriverState *chr;
PtyCharDriver *s;
int master_fd, slave_fd;
char pty_name[PATH_MAX];
@@ -1175,8 +1170,6 @@ static CharDriverState *qemu_chr_open_pty(const char *id,
close(slave_fd);
- chr = g_malloc0(sizeof(CharDriverState));
-
chr->filename = g_strdup_printf("pty:%s", pty_name);
ret->pty = g_strdup(pty_name);
ret->has_pty = true;
@@ -1398,12 +1391,10 @@ static void qemu_chr_close_tty(CharDriverState *chr)
}
}
-static CharDriverState *qemu_chr_open_tty_fd(int fd)
+static CharDriverState *qemu_chr_open_tty_fd(CharDriverState *chr, int fd)
{
- CharDriverState *chr;
-
tty_serial_init(fd, 115200, 'N', 8, 1);
- chr = qemu_chr_open_fd(fd, fd);
+ qemu_chr_open_fd(chr, fd, fd);
chr->chr_ioctl = tty_serial_ioctl;
chr->chr_close = qemu_chr_close_tty;
return chr;
@@ -1523,9 +1514,8 @@ static void pp_close(CharDriverState *chr)
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
-static CharDriverState *qemu_chr_open_pp_fd(int fd)
+static CharDriverState *qemu_chr_open_pp_fd(CharDriverState *chr, int fd)
{
- CharDriverState *chr;
ParallelCharDriver *drv;
if (ioctl(fd, PPCLAIM) < 0) {
@@ -1537,7 +1527,6 @@ static CharDriverState *qemu_chr_open_pp_fd(int fd)
drv->fd = fd;
drv->mode = IEEE1284_MODE_COMPAT;
- chr = g_malloc0(sizeof(CharDriverState));
chr->chr_write = null_chr_write;
chr->chr_ioctl = pp_ioctl;
chr->chr_close = pp_close;
@@ -1588,11 +1577,8 @@ static int pp_ioctl(CharDriverState *chr, int cmd, void *arg)
return 0;
}
-static CharDriverState *qemu_chr_open_pp_fd(int fd)
+static CharDriverState *qemu_chr_open_pp_fd(CharDriverState *chr, int fd)
{
- CharDriverState *chr;
-
- chr = g_malloc0(sizeof(CharDriverState));
chr->opaque = (void *)(intptr_t)fd;
chr->chr_write = null_chr_write;
chr->chr_ioctl = pp_ioctl;
@@ -1811,12 +1797,11 @@ static int win_chr_poll(void *opaque)
return 0;
}
-static CharDriverState *qemu_chr_open_win_path(const char *filename)
+static CharDriverState *qemu_chr_open_win_path(CharDriverState *chr,
+ const char *filename)
{
- CharDriverState *chr;
WinCharState *s;
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(WinCharState));
chr->opaque = s;
chr->chr_write = win_chr_write;
@@ -1824,7 +1809,6 @@ static CharDriverState *qemu_chr_open_win_path(const char *filename)
if (win_chr_init(chr, filename) < 0) {
g_free(s);
- g_free(chr);
return NULL;
}
return chr;
@@ -1909,13 +1893,12 @@ static int win_chr_pipe_init(CharDriverState *chr, const char *filename)
}
-static CharDriverState *qemu_chr_open_pipe(ChardevHostdev *opts)
+static CharDriverState *qemu_chr_open_pipe(CharDriverState *chr,
+ ChardevHostdev *opts)
{
const char *filename = opts->device;
- CharDriverState *chr;
WinCharState *s;
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(WinCharState));
chr->opaque = s;
chr->chr_write = win_chr_write;
@@ -1923,18 +1906,16 @@ static CharDriverState *qemu_chr_open_pipe(ChardevHostdev *opts)
if (win_chr_pipe_init(chr, filename) < 0) {
g_free(s);
- g_free(chr);
return NULL;
}
return chr;
}
-static CharDriverState *qemu_chr_open_win_file(HANDLE fd_out)
+static CharDriverState *qemu_chr_open_win_file(CharDriverState *chr,
+ HANDLE fd_out)
{
- CharDriverState *chr;
WinCharState *s;
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(WinCharState));
s->hcom = fd_out;
chr->opaque = s;
@@ -1942,9 +1923,9 @@ static CharDriverState *qemu_chr_open_win_file(HANDLE fd_out)
return chr;
}
-static CharDriverState *qemu_chr_open_win_con(void)
+static CharDriverState *qemu_chr_open_win_con(CharDriverState *chr)
{
- return qemu_chr_open_win_file(GetStdHandle(STD_OUTPUT_HANDLE));
+ return qemu_chr_open_win_file(chr, GetStdHandle(STD_OUTPUT_HANDLE));
}
static int win_stdio_write(CharDriverState *chr, const uint8_t *buf, int len)
@@ -2084,14 +2065,13 @@ static void win_stdio_close(CharDriverState *chr)
g_free(chr);
}
-static CharDriverState *qemu_chr_open_stdio(ChardevStdio *opts)
+static CharDriverState *qemu_chr_open_stdio(CharDriverState *chr,
+ ChardevStdio *opts)
{
- CharDriverState *chr;
WinStdioCharState *stdio;
DWORD dwMode;
int is_console = 0;
- chr = g_malloc0(sizeof(CharDriverState));
stdio = g_malloc0(sizeof(WinStdioCharState));
stdio->hStdIn = GetStdHandle(STD_INPUT_HANDLE);
@@ -2248,12 +2228,10 @@ static void udp_chr_close(CharDriverState *chr)
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
-static CharDriverState *qemu_chr_open_udp_fd(int fd)
+static CharDriverState *qemu_chr_open_udp_fd(CharDriverState *chr, int fd)
{
- CharDriverState *chr = NULL;
NetCharDriver *s = NULL;
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(NetCharDriver));
s->fd = fd;
@@ -2269,7 +2247,7 @@ static CharDriverState *qemu_chr_open_udp_fd(int fd)
return chr;
}
-static CharDriverState *qemu_chr_open_udp(QemuOpts *opts)
+static CharDriverState *qemu_chr_open_udp(CharDriverState *chr, QemuOpts *opts)
{
Error *local_err = NULL;
int fd = -1;
@@ -2280,7 +2258,7 @@ static CharDriverState *qemu_chr_open_udp(QemuOpts *opts)
error_free(local_err);
return NULL;
}
- return qemu_chr_open_udp_fd(fd);
+ return qemu_chr_open_udp_fd(chr, fd);
}
/***********************************************************/
@@ -2491,9 +2469,9 @@ static gboolean tcp_chr_read(GIOChannel *chan, GIOCondition cond, void *opaque)
}
#ifndef _WIN32
-CharDriverState *qemu_chr_open_eventfd(int eventfd)
+CharDriverState *qemu_chr_open_eventfd(CharDriverState *chr, int eventfd)
{
- return qemu_chr_open_fd(eventfd, eventfd);
+ return qemu_chr_open_fd(chr, eventfd, eventfd);
}
#endif
@@ -2608,12 +2586,12 @@ static void tcp_chr_close(CharDriverState *chr)
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
-static CharDriverState *qemu_chr_open_socket_fd(int fd, bool do_nodelay,
+static CharDriverState *qemu_chr_open_socket_fd(CharDriverState *chr,
+ int fd, bool do_nodelay,
bool is_listen, bool is_telnet,
bool is_waitconnect,
Error **errp)
{
- CharDriverState *chr = NULL;
TCPCharDriver *s = NULL;
char host[NI_MAXHOST], serv[NI_MAXSERV];
const char *left = "", *right = "";
@@ -2626,7 +2604,6 @@ static CharDriverState *qemu_chr_open_socket_fd(int fd, bool do_nodelay,
return NULL;
}
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(TCPCharDriver));
s->connected = 0;
@@ -2692,9 +2669,9 @@ static CharDriverState *qemu_chr_open_socket_fd(int fd, bool do_nodelay,
return chr;
}
-static CharDriverState *qemu_chr_open_socket(QemuOpts *opts)
+static CharDriverState *qemu_chr_open_socket(CharDriverState *chr,
+ QemuOpts *opts)
{
- CharDriverState *chr = NULL;
Error *local_err = NULL;
int fd = -1;
@@ -2724,8 +2701,8 @@ static CharDriverState *qemu_chr_open_socket(QemuOpts *opts)
if (!is_waitconnect)
qemu_set_nonblock(fd);
- chr = qemu_chr_open_socket_fd(fd, do_nodelay, is_listen, is_telnet,
- is_waitconnect, &local_err);
+ qemu_chr_open_socket_fd(chr, fd, do_nodelay, is_listen, is_telnet,
+ is_waitconnect, &local_err);
if (error_is_set(&local_err)) {
goto fail;
}
@@ -2742,7 +2719,6 @@ static CharDriverState *qemu_chr_open_socket(QemuOpts *opts)
}
if (chr) {
g_free(chr->opaque);
- g_free(chr);
}
return NULL;
}
@@ -2804,13 +2780,12 @@ static void ringbuf_chr_close(struct CharDriverState *chr)
chr->opaque = NULL;
}
-static CharDriverState *qemu_chr_open_ringbuf(ChardevRingbuf *opts,
+static CharDriverState *qemu_chr_open_ringbuf(struct CharDriverState *chr,
+ ChardevRingbuf *opts,
Error **errp)
{
- CharDriverState *chr;
RingBufCharDriver *d;
- chr = g_malloc0(sizeof(CharDriverState));
d = g_malloc(sizeof(*d));
d->size = opts->has_size ? opts->size : 65536;
@@ -2833,7 +2808,6 @@ static CharDriverState *qemu_chr_open_ringbuf(ChardevRingbuf *opts,
fail:
g_free(d);
- g_free(chr);
return NULL;
}
@@ -3156,7 +3130,7 @@ static void qemu_chr_parse_mux(QemuOpts *opts, ChardevBackend *backend,
typedef struct CharDriver {
const char *name;
/* old, pre qapi */
- CharDriverState *(*open)(QemuOpts *opts);
+ CharDriverState *(*open)(CharDriverState *chr, QemuOpts *opts);
/* new, qapi-based */
ChardevBackendKind kind;
void (*parse)(QemuOpts *opts, ChardevBackend *backend, Error **errp);
@@ -3164,7 +3138,8 @@ typedef struct CharDriver {
static GSList *backends;
-void register_char_driver(const char *name, CharDriverState *(*open)(QemuOpts *))
+void register_char_driver(const char *name,
+ CharDriverState *(*open)(CharDriverState*,QemuOpts *))
{
CharDriver *s;
@@ -3269,7 +3244,8 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
return chr;
}
- chr = cd->open(opts);
+ chr = g_malloc0(sizeof(CharDriverState));
+ chr = cd->open(chr, opts);
if (!chr) {
error_setg(errp, "chardev: opening backend \"%s\" failed",
qemu_opt_get(opts, "backend"));
@@ -3292,7 +3268,7 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
int len = strlen(qemu_opts_id(opts)) + 6;
base->label = g_malloc(len);
snprintf(base->label, len, "%s-base", qemu_opts_id(opts));
- chr = qemu_chr_open_mux(base);
+ chr = qemu_chr_open_mux(chr, base);
chr->filename = base->filename;
chr->avail_connections = MAX_MUX;
QTAILQ_INSERT_TAIL(&chardevs, chr, next);
@@ -3580,7 +3556,8 @@ static int qmp_chardev_open_file_source(char *src, int flags,
return fd;
}
-static CharDriverState *qmp_chardev_open_file(ChardevFile *file, Error **errp)
+static CharDriverState *qmp_chardev_open_file(CharDriverState *chr,
+ ChardevFile *file, Error **errp)
{
int flags, in = -1, out = -1;
@@ -3599,10 +3576,11 @@ static CharDriverState *qmp_chardev_open_file(ChardevFile *file, Error **errp)
}
}
- return qemu_chr_open_fd(in, out);
+ return qemu_chr_open_fd(chr, in, out);
}
-static CharDriverState *qmp_chardev_open_serial(ChardevHostdev *serial,
+static CharDriverState *qmp_chardev_open_serial(CharDriverState *chr,
+ ChardevHostdev *serial,
Error **errp)
{
#ifdef HAVE_CHARDEV_TTY
@@ -3613,14 +3591,15 @@ static CharDriverState *qmp_chardev_open_serial(ChardevHostdev *serial,
return NULL;
}
qemu_set_nonblock(fd);
- return qemu_chr_open_tty_fd(fd);
+ return qemu_chr_open_tty_fd(chr, fd);
#else
error_setg(errp, "character device backend type 'serial' not supported");
return NULL;
#endif
}
-static CharDriverState *qmp_chardev_open_parallel(ChardevHostdev *parallel,
+static CharDriverState *qmp_chardev_open_parallel(CharDriverState *chr,
+ ChardevHostdev *parallel,
Error **errp)
{
#ifdef HAVE_CHARDEV_PARPORT
@@ -3630,7 +3609,7 @@ static CharDriverState *qmp_chardev_open_parallel(ChardevHostdev *parallel,
if (error_is_set(errp)) {
return NULL;
}
- return qemu_chr_open_pp_fd(fd);
+ return qemu_chr_open_pp_fd(chr, fd);
#else
error_setg(errp, "character device backend type 'parallel' not supported");
return NULL;
@@ -3639,7 +3618,8 @@ static CharDriverState *qmp_chardev_open_parallel(ChardevHostdev *parallel,
#endif /* WIN32 */
-static CharDriverState *qmp_chardev_open_socket(ChardevSocket *sock,
+static CharDriverState *qmp_chardev_open_socket(CharDriverState *chr,
+ ChardevSocket *sock,
Error **errp)
{
SocketAddress *addr = sock->addr;
@@ -3657,11 +3637,12 @@ static CharDriverState *qmp_chardev_open_socket(ChardevSocket *sock,
if (error_is_set(errp)) {
return NULL;
}
- return qemu_chr_open_socket_fd(fd, do_nodelay, is_listen,
+ return qemu_chr_open_socket_fd(chr, fd, do_nodelay, is_listen,
is_telnet, is_waitconnect, errp);
}
-static CharDriverState *qmp_chardev_open_udp(ChardevUdp *udp,
+static CharDriverState *qmp_chardev_open_udp(CharDriverState *chr,
+ ChardevUdp *udp,
Error **errp)
{
int fd;
@@ -3670,14 +3651,14 @@ static CharDriverState *qmp_chardev_open_udp(ChardevUdp *udp,
if (error_is_set(errp)) {
return NULL;
}
- return qemu_chr_open_udp_fd(fd);
+ return qemu_chr_open_udp_fd(chr, fd);
}
ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend,
Error **errp)
{
ChardevReturn *ret = g_new0(ChardevReturn, 1);
- CharDriverState *base, *chr = NULL;
+ CharDriverState *base, *chr, *newchr;
chr = qemu_chr_find(id);
if (chr) {
@@ -3686,32 +3667,34 @@ ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend,
return NULL;
}
+ newchr = g_malloc0(sizeof(CharDriverState));
+
switch (backend->kind) {
case CHARDEV_BACKEND_KIND_FILE:
- chr = qmp_chardev_open_file(backend->file, errp);
+ chr = qmp_chardev_open_file(newchr, backend->file, errp);
break;
case CHARDEV_BACKEND_KIND_SERIAL:
- chr = qmp_chardev_open_serial(backend->serial, errp);
+ chr = qmp_chardev_open_serial(newchr, backend->serial, errp);
break;
case CHARDEV_BACKEND_KIND_PARALLEL:
- chr = qmp_chardev_open_parallel(backend->parallel, errp);
+ chr = qmp_chardev_open_parallel(newchr, backend->parallel, errp);
break;
case CHARDEV_BACKEND_KIND_PIPE:
- chr = qemu_chr_open_pipe(backend->pipe);
+ chr = qemu_chr_open_pipe(newchr, backend->pipe);
break;
case CHARDEV_BACKEND_KIND_SOCKET:
- chr = qmp_chardev_open_socket(backend->socket, errp);
+ chr = qmp_chardev_open_socket(newchr, backend->socket, errp);
break;
case CHARDEV_BACKEND_KIND_UDP:
- chr = qmp_chardev_open_udp(backend->udp, errp);
+ chr = qmp_chardev_open_udp(newchr, backend->udp, errp);
break;
#ifdef HAVE_CHARDEV_TTY
case CHARDEV_BACKEND_KIND_PTY:
- chr = qemu_chr_open_pty(id, ret);
+ chr = qemu_chr_open_pty(newchr, id, ret);
break;
#endif
case CHARDEV_BACKEND_KIND_NULL:
- chr = qemu_chr_open_null();
+ chr = qemu_chr_open_null(newchr);
break;
case CHARDEV_BACKEND_KIND_MUX:
base = qemu_chr_find(backend->mux->chardev);
@@ -3720,38 +3703,38 @@ ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend,
backend->mux->chardev);
break;
}
- chr = qemu_chr_open_mux(base);
+ chr = qemu_chr_open_mux(newchr, base);
break;
case CHARDEV_BACKEND_KIND_MSMOUSE:
- chr = qemu_chr_open_msmouse();
+ chr = qemu_chr_open_msmouse(newchr);
break;
#ifdef CONFIG_BRLAPI
case CHARDEV_BACKEND_KIND_BRAILLE:
- chr = chr_baum_init();
+ chr = chr_baum_init(newchr);
break;
#endif
case CHARDEV_BACKEND_KIND_STDIO:
- chr = qemu_chr_open_stdio(backend->stdio);
+ chr = qemu_chr_open_stdio(newchr, backend->stdio);
break;
#ifdef _WIN32
case CHARDEV_BACKEND_KIND_CONSOLE:
- chr = qemu_chr_open_win_con();
+ chr = qemu_chr_open_win_con(newchr);
break;
#endif
#ifdef CONFIG_SPICE
case CHARDEV_BACKEND_KIND_SPICEVMC:
- chr = qemu_chr_open_spice_vmc(backend->spicevmc->type);
+ chr = qemu_chr_open_spice_vmc(newchr, backend->spicevmc->type);
break;
case CHARDEV_BACKEND_KIND_SPICEPORT:
- chr = qemu_chr_open_spice_port(backend->spiceport->fqdn);
+ chr = qemu_chr_open_spice_port(newchr, backend->spiceport->fqdn);
break;
#endif
case CHARDEV_BACKEND_KIND_VC:
- chr = vc_init(backend->vc);
+ chr = vc_init(newchr, backend->vc);
break;
case CHARDEV_BACKEND_KIND_RINGBUF:
case CHARDEV_BACKEND_KIND_MEMORY:
- chr = qemu_chr_open_ringbuf(backend->ringbuf, errp);
+ chr = qemu_chr_open_ringbuf(newchr, backend->ringbuf, errp);
break;
default:
error_setg(errp, "unknown chardev backend (%d)", backend->kind);
@@ -3774,6 +3757,7 @@ ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend,
QTAILQ_INSERT_TAIL(&chardevs, chr, next);
return ret;
} else {
+ g_free(newchr);
g_free(ret);
return NULL;
}
diff --git a/spice-qemu-char.c b/spice-qemu-char.c
index 6d147a7..05564a9 100644
--- a/spice-qemu-char.c
+++ b/spice-qemu-char.c
@@ -240,12 +240,10 @@ static void print_allowed_subtypes(void)
fprintf(stderr, "\n");
}
-static CharDriverState *chr_open(const char *subtype)
+static CharDriverState *chr_open(CharDriverState *chr, const char *subtype)
{
- CharDriverState *chr;
SpiceCharDriver *s;
- chr = g_malloc0(sizeof(CharDriverState));
s = g_malloc0(sizeof(SpiceCharDriver));
s->chr = chr;
s->active = false;
@@ -262,7 +260,7 @@ static CharDriverState *chr_open(const char *subtype)
return chr;
}
-CharDriverState *qemu_chr_open_spice_vmc(const char *type)
+CharDriverState *qemu_chr_open_spice_vmc(CharDriverState *chr, const char *type)
{
const char **psubtype = spice_server_char_device_recognized_subtypes();
@@ -282,13 +280,13 @@ CharDriverState *qemu_chr_open_spice_vmc(const char *type)
return NULL;
}
- return chr_open(type);
+ return chr_open(chr, type);
}
#if SPICE_SERVER_VERSION >= 0x000c02
-CharDriverState *qemu_chr_open_spice_port(const char *name)
+CharDriverState *qemu_chr_open_spice_port(CharDriverState *chr,
+ const char *name)
{
- CharDriverState *chr;
SpiceCharDriver *s;
if (name == NULL) {
@@ -296,7 +294,7 @@ CharDriverState *qemu_chr_open_spice_port(const char *name)
return NULL;
}
- chr = chr_open("port");
+ chr_open(chr, "port");
s = chr->opaque;
s->sin.portname = g_strdup(name);
diff --git a/ui/console.c b/ui/console.c
index aad4fc9..6676352 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1761,15 +1761,12 @@ static void text_console_do_init(CharDriverState *chr, DisplayState *ds)
chr->init(chr);
}
-static CharDriverState *text_console_init(ChardevVC *vc)
+static CharDriverState *text_console_init(CharDriverState *chr, ChardevVC *vc)
{
- CharDriverState *chr;
QemuConsole *s;
unsigned width = 0;
unsigned height = 0;
- chr = g_malloc0(sizeof(CharDriverState));
-
if (vc->has_width) {
width = vc->width;
} else if (vc->has_cols) {
@@ -1791,7 +1788,6 @@ static CharDriverState *text_console_init(ChardevVC *vc)
}
if (!s) {
- g_free(chr);
return NULL;
}
@@ -1811,9 +1807,9 @@ static CharDriverState *text_console_init(ChardevVC *vc)
static VcHandler *vc_handler = text_console_init;
-CharDriverState *vc_init(ChardevVC *vc)
+CharDriverState *vc_init(CharDriverState *chr, ChardevVC *vc)
{
- return vc_handler(vc);
+ return vc_handler(chr, vc);
}
void register_vc_handler(VcHandler *handler)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 01/16] qemu-char: Allocate CharDriverState in qemu_chr_new_from_opts
2013-11-12 16:33 ` [Qemu-devel] [PATCH 01/16] qemu-char: Allocate CharDriverState in qemu_chr_new_from_opts Corey Minyard
@ 2014-01-23 13:32 ` Andreas Färber
2014-01-23 13:58 ` Andreas Färber
0 siblings, 1 reply; 42+ messages in thread
From: Andreas Färber @ 2014-01-23 13:32 UTC (permalink / raw)
To: Corey Minyard, qemu-devel; +Cc: Bret Ketchum, Corey Minyard, Michael S. Tsirkin
Am 12.11.2013 17:33, schrieb Corey Minyard:
> This allocates the CharDriverState structure and passes it in to the
> open routine. This allows a coming option to automatically attempt to
> reconnect a chardev if the connection fails. The chardev has to be
> kept around so a reconnect can be done on it.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
[...]
> diff --git a/include/ui/qemu-spice.h b/include/ui/qemu-spice.h
> index 86c75c7..eadb9c9 100644
> --- a/include/ui/qemu-spice.h
> +++ b/include/ui/qemu-spice.h
> @@ -46,9 +46,11 @@ int qemu_spice_migrate_info(const char *hostname, int port, int tls_port,
> void do_info_spice_print(Monitor *mon, const QObject *data);
> void do_info_spice(Monitor *mon, QObject **ret_data);
>
> -CharDriverState *qemu_chr_open_spice_vmc(const char *type);
> +CharDriverState *qemu_chr_open_spice_vmc(CharDriverState *chr,
> + const char *type);
> #if SPICE_SERVER_VERSION >= 0x000c02
> -CharDriverState *qemu_chr_open_spice_port(const char *name);
> +CharDriverState *qemu_chr_open_spice_port(CharDriverSTate *chr,
This needs to be CharDriverState.
> + const char *name);
> void qemu_spice_register_ports(void);
> #else
> static inline CharDriverState *qemu_chr_open_spice_port(const char *name)
[snip]
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 01/16] qemu-char: Allocate CharDriverState in qemu_chr_new_from_opts
2014-01-23 13:32 ` Andreas Färber
@ 2014-01-23 13:58 ` Andreas Färber
0 siblings, 0 replies; 42+ messages in thread
From: Andreas Färber @ 2014-01-23 13:58 UTC (permalink / raw)
To: Corey Minyard, qemu-devel; +Cc: Bret Ketchum, Corey Minyard, Michael S. Tsirkin
Am 23.01.2014 14:32, schrieb Andreas Färber:
> Am 12.11.2013 17:33, schrieb Corey Minyard:
>> This allocates the CharDriverState structure and passes it in to the
>> open routine. This allows a coming option to automatically attempt to
>> reconnect a chardev if the connection fails. The chardev has to be
>> kept around so a reconnect can be done on it.
>>
>> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> [...]
>> diff --git a/include/ui/qemu-spice.h b/include/ui/qemu-spice.h
>> index 86c75c7..eadb9c9 100644
>> --- a/include/ui/qemu-spice.h
>> +++ b/include/ui/qemu-spice.h
>> @@ -46,9 +46,11 @@ int qemu_spice_migrate_info(const char *hostname, int port, int tls_port,
>> void do_info_spice_print(Monitor *mon, const QObject *data);
>> void do_info_spice(Monitor *mon, QObject **ret_data);
>>
>> -CharDriverState *qemu_chr_open_spice_vmc(const char *type);
>> +CharDriverState *qemu_chr_open_spice_vmc(CharDriverState *chr,
>> + const char *type);
>> #if SPICE_SERVER_VERSION >= 0x000c02
>> -CharDriverState *qemu_chr_open_spice_port(const char *name);
>> +CharDriverState *qemu_chr_open_spice_port(CharDriverSTate *chr,
>
> This needs to be CharDriverState.
>
>> + const char *name);
>> void qemu_spice_register_ports(void);
>> #else
>> static inline CharDriverState *qemu_chr_open_spice_port(const char *name)
> [snip]
I also needed the following:
diff --git a/ui/gtk.c b/ui/gtk.c
index 6316f5b..c2210a2 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -1113,11 +1113,8 @@ static int gd_vc_chr_write(CharDriverState *chr,
const uint8_t *buf, int len)
static int nb_vcs;
static CharDriverState *vcs[MAX_VCS];
-static CharDriverState *gd_vc_handler(ChardevVC *unused)
+static CharDriverState *gd_vc_handler(CharDriverState *chr, ChardevVC
*unused)
{
- CharDriverState *chr;
-
- chr = g_malloc0(sizeof(*chr));
chr->chr_write = gd_vc_chr_write;
/* defer OPENED events until our vc is fully initialized */
chr->explicit_be_open = true;
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 01/16] qemu-char: Allocate CharDriverState in qemu_chr_new_from_opts Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:43 ` Eric Blake
2013-11-13 8:55 ` Gerd Hoffmann
2013-11-12 16:33 ` [Qemu-devel] [PATCH 03/16] qemu-char: remove free of chr from win_stdio_close Corey Minyard
` (13 subsequent siblings)
15 siblings, 2 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
Allow a socket that connects to reconnect on a periodic basis if it
fails to connect at startup or if the connection drops while in use.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
include/sysemu/char.h | 3 ++
qemu-char.c | 88 ++++++++++++++++++++++++++++++++++++++++++++-------
qemu-options.hx | 11 +++++--
3 files changed, 87 insertions(+), 15 deletions(-)
diff --git a/include/sysemu/char.h b/include/sysemu/char.h
index 44baf0f..3d21b5a 100644
--- a/include/sysemu/char.h
+++ b/include/sysemu/char.h
@@ -81,6 +81,9 @@ struct CharDriverState {
guint fd_in_tag;
QemuOpts *opts;
QTAILQ_ENTRY(CharDriverState) next;
+ GSList *backend;
+ QEMUTimer *recon_timer;
+ uint64_t recon_time;
};
/**
diff --git a/qemu-char.c b/qemu-char.c
index dd04cc0..23d7647 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -96,9 +96,22 @@ void qemu_chr_be_event(CharDriverState *s, int event)
/* Keep track if the char device is open */
switch (event) {
case CHR_EVENT_OPENED:
+ if (s->recon_timer) {
+ timer_del(s->recon_timer);
+ }
s->be_open = 1;
break;
case CHR_EVENT_CLOSED:
+ if (s->recon_timer) {
+ void (*chr_close)(struct CharDriverState *chr) = s->chr_close;
+ if (chr_close) {
+ s->chr_close = NULL;
+ chr_close(s);
+ }
+ timer_mod(s->recon_timer,
+ (get_clock() +
+ (s->recon_time * get_ticks_per_sec())));
+ }
s->be_open = 0;
break;
}
@@ -2583,6 +2596,7 @@ static void tcp_chr_close(CharDriverState *chr)
closesocket(s->listen_fd);
}
g_free(s);
+ chr->opaque = NULL;
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
@@ -2642,8 +2656,6 @@ static CharDriverState *qemu_chr_open_socket_fd(CharDriverState *chr,
chr->get_msgfd = tcp_get_msgfd;
chr->chr_add_client = tcp_chr_add_client;
chr->chr_add_watch = tcp_chr_add_watch;
- /* be isn't opened until we get a connection */
- chr->explicit_be_open = true;
if (is_listen) {
s->listen_fd = fd;
@@ -2681,6 +2693,9 @@ static CharDriverState *qemu_chr_open_socket(CharDriverState *chr,
bool do_nodelay = !qemu_opt_get_bool(opts, "delay", true);
bool is_unix = qemu_opt_get(opts, "path") != NULL;
+ /* be isn't opened until we get a connection */
+ chr->explicit_be_open = true;
+
if (is_unix) {
if (is_listen) {
fd = unix_listen_opts(opts, &local_err);
@@ -2717,8 +2732,9 @@ static CharDriverState *qemu_chr_open_socket(CharDriverState *chr,
if (fd >= 0) {
closesocket(fd);
}
- if (chr) {
+ if (chr && chr->opaque) {
g_free(chr->opaque);
+ chr->opaque = NULL;
}
return NULL;
}
@@ -3163,6 +3179,20 @@ void register_char_driver_qapi(const char *name, ChardevBackendKind kind,
backends = g_slist_append(backends, s);
}
+static void recon_timeout(void *opaque)
+{
+ CharDriverState *chr = opaque;
+ CharDriver *cd = chr->backend->data;
+
+ if (chr->be_open) {
+ return;
+ }
+
+ timer_mod(chr->recon_timer,
+ (get_clock() + (chr->recon_time * get_ticks_per_sec())));
+ cd->open(chr, chr->opts);
+}
+
CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
void (*init)(struct CharDriverState *s),
Error **errp)
@@ -3245,11 +3275,36 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
}
chr = g_malloc0(sizeof(CharDriverState));
- chr = cd->open(chr, opts);
- if (!chr) {
- error_setg(errp, "chardev: opening backend \"%s\" failed",
- qemu_opt_get(opts, "backend"));
- goto err;
+
+ chr->backend = i;
+ chr->recon_time = qemu_opt_get_number(opts, "reconnect", 0);
+ if (chr->recon_time) {
+ if (strcmp(qemu_opt_get(opts, "backend"), "socket") != 0) {
+ g_free(chr);
+ fprintf(stderr, "chardev: reconnect only supported on sockets\n");
+ return NULL;
+ }
+ if (qemu_opt_get_bool(opts, "server", 0)) {
+ g_free(chr);
+ fprintf(stderr, "chardev: server device cannot reconnect\n");
+ return NULL;
+ }
+ chr->opts = opts;
+ chr->recon_timer = timer_new(QEMU_CLOCK_REALTIME, SCALE_NS,
+ recon_timeout, chr);
+
+ /* Make sure it connects in time. */
+ timer_mod(chr->recon_timer,
+ (get_clock() + (chr->recon_time * get_ticks_per_sec())));
+ }
+
+ if (!cd->open(chr, opts)) {
+ if (!chr->recon_time) {
+ /* Reconnect is not enabled, give up */
+ fprintf(stderr, "chardev: opening backend \"%s\" failed\n",
+ qemu_opt_get(opts, "backend"));
+ return NULL;
+ }
}
if (!chr->filename)
@@ -3268,7 +3323,8 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
int len = strlen(qemu_opts_id(opts)) + 6;
base->label = g_malloc(len);
snprintf(base->label, len, "%s-base", qemu_opts_id(opts));
- chr = qemu_chr_open_mux(chr, base);
+ chr = g_malloc0(sizeof(CharDriverState));
+ qemu_chr_open_mux(chr, base);
chr->filename = base->filename;
chr->avail_connections = MAX_MUX;
QTAILQ_INSERT_TAIL(&chardevs, chr, next);
@@ -3276,7 +3332,6 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
chr->avail_connections = 1;
}
chr->label = g_strdup(qemu_opts_id(opts));
- chr->opts = opts;
return chr;
err:
@@ -3372,9 +3427,15 @@ void qemu_chr_fe_release(CharDriverState *s)
void qemu_chr_delete(CharDriverState *chr)
{
+ void (*chr_close)(struct CharDriverState *chr) = chr->chr_close;
+
QTAILQ_REMOVE(&chardevs, chr, next);
- if (chr->chr_close) {
- chr->chr_close(chr);
+ if (chr_close) {
+ chr->chr_close = NULL;
+ chr_close(chr);
+ }
+ if (chr->recon_timer) {
+ timer_free(chr->recon_timer);
}
g_free(chr->filename);
g_free(chr->label);
@@ -3490,6 +3551,9 @@ QemuOptsList qemu_chardev_opts = {
.name = "mux",
.type = QEMU_OPT_BOOL,
},{
+ .name = "reconnect",
+ .type = QEMU_OPT_NUMBER,
+ },{
.name = "signal",
.type = QEMU_OPT_BOOL,
},{
diff --git a/qemu-options.hx b/qemu-options.hx
index 5dc8b75..5bcfaa0 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1780,8 +1780,9 @@ ETEXI
DEF("chardev", HAS_ARG, QEMU_OPTION_chardev,
"-chardev null,id=id[,mux=on|off]\n"
"-chardev socket,id=id[,host=host],port=host[,to=to][,ipv4][,ipv6][,nodelay]\n"
- " [,server][,nowait][,telnet][,mux=on|off] (tcp)\n"
- "-chardev socket,id=id,path=path[,server][,nowait][,telnet],[mux=on|off] (unix)\n"
+ " [,server][,nowait][,telnet][,mux=on|off][,reconnect=seconds] (tcp)\n"
+ "-chardev socket,id=id,path=path[,server][,nowait][,telnet][,mux=on|off]\n"
+ " [,reconnect=seconds] (unix)\n"
"-chardev udp,id=id[,host=host],port=port[,localaddr=localaddr]\n"
" [,localport=localport][,ipv4][,ipv6][,mux=on|off]\n"
"-chardev msmouse,id=id[,mux=on|off]\n"
@@ -1853,7 +1854,7 @@ Options to each backend are described below.
A void device. This device will not emit any data, and will drop any data it
receives. The null backend does not take any options.
-@item -chardev socket ,id=@var{id} [@var{TCP options} or @var{unix options}] [,server] [,nowait] [,telnet]
+@item -chardev socket ,id=@var{id} [@var{TCP options} or @var{unix options}] [,server] [,nowait] [,telnet] [,reconnect=@var{seconds}]
Create a two-way stream socket, which can be either a TCP or a unix socket. A
unix socket will be created if @option{path} is specified. Behaviour is
@@ -1867,6 +1868,10 @@ connect to a listening socket.
@option{telnet} specifies that traffic on the socket should interpret telnet
escape sequences.
+@option{reconnect} specifies that if the socket does not come up at startup,
+or if the socket is closed for some reason (like the other end exited),
+wait the given number of seconds and attempt to reconnect.
+
TCP and unix socket options are given below:
@table @option
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-12 16:33 ` [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected Corey Minyard
@ 2013-11-12 16:43 ` Eric Blake
2013-11-12 17:08 ` Corey Minyard
2013-11-13 8:55 ` Gerd Hoffmann
1 sibling, 1 reply; 42+ messages in thread
From: Eric Blake @ 2013-11-12 16:43 UTC (permalink / raw)
To: Corey Minyard, qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
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On 11/12/2013 09:33 AM, Corey Minyard wrote:
> Allow a socket that connects to reconnect on a periodic basis if it
> fails to connect at startup or if the connection drops while in use.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> ---
> include/sysemu/char.h | 3 ++
> qemu-char.c | 88 ++++++++++++++++++++++++++++++++++++++++++++-------
> qemu-options.hx | 11 +++++--
> 3 files changed, 87 insertions(+), 15 deletions(-)
>
> +++ b/qemu-options.hx
> @@ -1780,8 +1780,9 @@ ETEXI
> DEF("chardev", HAS_ARG, QEMU_OPTION_chardev,
> "-chardev null,id=id[,mux=on|off]\n"
> "-chardev socket,id=id[,host=host],port=host[,to=to][,ipv4][,ipv6][,nodelay]\n"
> - " [,server][,nowait][,telnet][,mux=on|off] (tcp)\n"
> - "-chardev socket,id=id,path=path[,server][,nowait][,telnet],[mux=on|off] (unix)\n"
> + " [,server][,nowait][,telnet][,mux=on|off][,reconnect=seconds] (tcp)\n"
> + "-chardev socket,id=id,path=path[,server][,nowait][,telnet][,mux=on|off]\n"
> + " [,reconnect=seconds] (unix)\n"
> +@option{reconnect} specifies that if the socket does not come up at startup,
> +or if the socket is closed for some reason (like the other end exited),
> +wait the given number of seconds and attempt to reconnect.
Sounds cool. Are you planning on also adding the QMP counterpart for
specifying this option when doing hotplugs of a chardev? Does reconnect
make any sense when not using server mode?
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-12 16:43 ` Eric Blake
@ 2013-11-12 17:08 ` Corey Minyard
2013-11-14 7:32 ` Michael S. Tsirkin
0 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 17:08 UTC (permalink / raw)
To: Eric Blake, qemu-devel
Cc: Bret Ketchum, Andreas Färber, Michael S. Tsirkin
On 11/12/2013 10:43 AM, Eric Blake wrote:
> On 11/12/2013 09:33 AM, Corey Minyard wrote:
>> Allow a socket that connects to reconnect on a periodic basis if it
>> fails to connect at startup or if the connection drops while in use.
>>
>> Signed-off-by: Corey Minyard <cminyard@mvista.com>
>> ---
>> include/sysemu/char.h | 3 ++
>> qemu-char.c | 88 ++++++++++++++++++++++++++++++++++++++++++++-------
>> qemu-options.hx | 11 +++++--
>> 3 files changed, 87 insertions(+), 15 deletions(-)
>>
>> +++ b/qemu-options.hx
>> @@ -1780,8 +1780,9 @@ ETEXI
>> DEF("chardev", HAS_ARG, QEMU_OPTION_chardev,
>> "-chardev null,id=id[,mux=on|off]\n"
>> "-chardev socket,id=id[,host=host],port=host[,to=to][,ipv4][,ipv6][,nodelay]\n"
>> - " [,server][,nowait][,telnet][,mux=on|off] (tcp)\n"
>> - "-chardev socket,id=id,path=path[,server][,nowait][,telnet],[mux=on|off] (unix)\n"
>> + " [,server][,nowait][,telnet][,mux=on|off][,reconnect=seconds] (tcp)\n"
>> + "-chardev socket,id=id,path=path[,server][,nowait][,telnet][,mux=on|off]\n"
>> + " [,reconnect=seconds] (unix)\n"
>> +@option{reconnect} specifies that if the socket does not come up at startup,
>> +or if the socket is closed for some reason (like the other end exited),
>> +wait the given number of seconds and attempt to reconnect.
> Sounds cool. Are you planning on also adding the QMP counterpart for
> specifying this option when doing hotplugs of a chardev?
Yes, I need to add that.
> Does reconnect
> make any sense when not using server mode?
>
Actually, it only really makes sense when in client mode. The option
currently won't do anything in server mode. I can't see a use for it in
server mode, it doesn't know where to connect.
-corey
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-12 17:08 ` Corey Minyard
@ 2013-11-14 7:32 ` Michael S. Tsirkin
2013-11-14 13:29 ` Corey Minyard
0 siblings, 1 reply; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-14 7:32 UTC (permalink / raw)
To: Corey Minyard; +Cc: Bret Ketchum, qemu-devel, Andreas Färber
On Tue, Nov 12, 2013 at 11:08:07AM -0600, Corey Minyard wrote:
> On 11/12/2013 10:43 AM, Eric Blake wrote:
> > On 11/12/2013 09:33 AM, Corey Minyard wrote:
> >> Allow a socket that connects to reconnect on a periodic basis if it
> >> fails to connect at startup or if the connection drops while in use.
> >>
> >> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> >> ---
> >> include/sysemu/char.h | 3 ++
> >> qemu-char.c | 88 ++++++++++++++++++++++++++++++++++++++++++++-------
> >> qemu-options.hx | 11 +++++--
> >> 3 files changed, 87 insertions(+), 15 deletions(-)
> >>
> >> +++ b/qemu-options.hx
> >> @@ -1780,8 +1780,9 @@ ETEXI
> >> DEF("chardev", HAS_ARG, QEMU_OPTION_chardev,
> >> "-chardev null,id=id[,mux=on|off]\n"
> >> "-chardev socket,id=id[,host=host],port=host[,to=to][,ipv4][,ipv6][,nodelay]\n"
> >> - " [,server][,nowait][,telnet][,mux=on|off] (tcp)\n"
> >> - "-chardev socket,id=id,path=path[,server][,nowait][,telnet],[mux=on|off] (unix)\n"
> >> + " [,server][,nowait][,telnet][,mux=on|off][,reconnect=seconds] (tcp)\n"
> >> + "-chardev socket,id=id,path=path[,server][,nowait][,telnet][,mux=on|off]\n"
> >> + " [,reconnect=seconds] (unix)\n"
> >> +@option{reconnect} specifies that if the socket does not come up at startup,
> >> +or if the socket is closed for some reason (like the other end exited),
> >> +wait the given number of seconds and attempt to reconnect.
> > Sounds cool. Are you planning on also adding the QMP counterpart for
> > specifying this option when doing hotplugs of a chardev?
>
> Yes, I need to add that.
>
> > Does reconnect
> > make any sense when not using server mode?
> >
> Actually, it only really makes sense when in client mode. The option
> currently won't do anything in server mode. I can't see a use for it in
> server mode, it doesn't know where to connect.
>
> -corey
I guess it could mean "allow reconnect from a client"?
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-14 7:32 ` Michael S. Tsirkin
@ 2013-11-14 13:29 ` Corey Minyard
0 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-14 13:29 UTC (permalink / raw)
To: Michael S. Tsirkin, Corey Minyard
Cc: Bret Ketchum, qemu-devel, Andreas Färber
On 11/14/2013 01:32 AM, Michael S. Tsirkin wrote:
> On Tue, Nov 12, 2013 at 11:08:07AM -0600, Corey Minyard wrote:
>> On 11/12/2013 10:43 AM, Eric Blake wrote:
>>> On 11/12/2013 09:33 AM, Corey Minyard wrote:
>>>> Allow a socket that connects to reconnect on a periodic basis if it
>>>> fails to connect at startup or if the connection drops while in use.
>>>>
>>>> Signed-off-by: Corey Minyard <cminyard@mvista.com>
>>>> ---
>>>> include/sysemu/char.h | 3 ++
>>>> qemu-char.c | 88 ++++++++++++++++++++++++++++++++++++++++++++-------
>>>> qemu-options.hx | 11 +++++--
>>>> 3 files changed, 87 insertions(+), 15 deletions(-)
>>>>
>>>> +++ b/qemu-options.hx
>>>> @@ -1780,8 +1780,9 @@ ETEXI
>>>> DEF("chardev", HAS_ARG, QEMU_OPTION_chardev,
>>>> "-chardev null,id=id[,mux=on|off]\n"
>>>> "-chardev socket,id=id[,host=host],port=host[,to=to][,ipv4][,ipv6][,nodelay]\n"
>>>> - " [,server][,nowait][,telnet][,mux=on|off] (tcp)\n"
>>>> - "-chardev socket,id=id,path=path[,server][,nowait][,telnet],[mux=on|off] (unix)\n"
>>>> + " [,server][,nowait][,telnet][,mux=on|off][,reconnect=seconds] (tcp)\n"
>>>> + "-chardev socket,id=id,path=path[,server][,nowait][,telnet][,mux=on|off]\n"
>>>> + " [,reconnect=seconds] (unix)\n"
>>>> +@option{reconnect} specifies that if the socket does not come up at startup,
>>>> +or if the socket is closed for some reason (like the other end exited),
>>>> +wait the given number of seconds and attempt to reconnect.
>>> Sounds cool. Are you planning on also adding the QMP counterpart for
>>> specifying this option when doing hotplugs of a chardev?
>> Yes, I need to add that.
>>
>>> Does reconnect
>>> make any sense when not using server mode?
>>>
>> Actually, it only really makes sense when in client mode. The option
>> currently won't do anything in server mode. I can't see a use for it in
>> server mode, it doesn't know where to connect.
>>
>> -corey
> I guess it could mean "allow reconnect from a client"?
>
Yes, rephrasing that is definitely in order.
-corey
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-12 16:33 ` [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected Corey Minyard
2013-11-12 16:43 ` Eric Blake
@ 2013-11-13 8:55 ` Gerd Hoffmann
2013-11-13 20:51 ` Corey Minyard
1 sibling, 1 reply; 42+ messages in thread
From: Gerd Hoffmann @ 2013-11-13 8:55 UTC (permalink / raw)
To: Corey Minyard
Cc: Bret Ketchum, Corey Minyard, Michael S. Tsirkin, qemu-devel,
Andreas Färber
Hi,
> Allow a socket that connects to reconnect on a periodic basis if it
> fails to connect at startup or if the connection drops while in use.
> + chr->backend = i;
> + chr->recon_time = qemu_opt_get_number(opts, "reconnect", 0);
> + if (chr->recon_time) {
> + if (strcmp(qemu_opt_get(opts, "backend"), "socket") != 0) {
> + g_free(chr);
> + fprintf(stderr, "chardev: reconnect only supported on sockets\n");
> + return NULL;
> + }
I think it would work *much* better to just add a "chr_reconnect"
function pointer to CharDriverState. You don't need patch #1 then.
Also it avoids backend-specific bits in generic code. Generic code just
checks if chr->chr_reconnect exists to figure whenever reconnect is
supported or not. And the socket backend can set chr_reconnect for
client sockets only.
cheers,
Gerd
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-13 8:55 ` Gerd Hoffmann
@ 2013-11-13 20:51 ` Corey Minyard
2013-11-14 13:56 ` Michael S. Tsirkin
0 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-13 20:51 UTC (permalink / raw)
To: Gerd Hoffmann, Corey Minyard
Cc: Bret Ketchum, Michael S. Tsirkin, qemu-devel, Andreas Färber
On 11/13/2013 02:55 AM, Gerd Hoffmann wrote:
> Hi,
>
>> Allow a socket that connects to reconnect on a periodic basis if it
>> fails to connect at startup or if the connection drops while in use.
>> + chr->backend = i;
>> + chr->recon_time = qemu_opt_get_number(opts, "reconnect", 0);
>> + if (chr->recon_time) {
>> + if (strcmp(qemu_opt_get(opts, "backend"), "socket") != 0) {
>> + g_free(chr);
>> + fprintf(stderr, "chardev: reconnect only supported on sockets\n");
>> + return NULL;
>> + }
> I think it would work *much* better to just add a "chr_reconnect"
> function pointer to CharDriverState. You don't need patch #1 then.
> Also it avoids backend-specific bits in generic code. Generic code just
> checks if chr->chr_reconnect exists to figure whenever reconnect is
> supported or not. And the socket backend can set chr_reconnect for
> client sockets only.
I was trying for something more generic than one that just applies to
socket devices. It may not be good for server sockets, but it might be
useful for ptys and hotplug devices. Looking at the code, ptys already
has its own code that does something similar; that could be pulled out
and replaced with the generic code.
Also, IMHO allocating the chardev in each back end is not optimal. It
breaks layering. Plus patch #1 has a net reduction in lines of code
because it pulls out all the allocations and does it in one place.
Thanks,
-corey
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected
2013-11-13 20:51 ` Corey Minyard
@ 2013-11-14 13:56 ` Michael S. Tsirkin
0 siblings, 0 replies; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-14 13:56 UTC (permalink / raw)
To: Corey Minyard
Cc: Bret Ketchum, Andreas Färber, Gerd Hoffmann, Corey Minyard,
qemu-devel
On Wed, Nov 13, 2013 at 02:51:39PM -0600, Corey Minyard wrote:
> On 11/13/2013 02:55 AM, Gerd Hoffmann wrote:
> > Hi,
> >
> >> Allow a socket that connects to reconnect on a periodic basis if it
> >> fails to connect at startup or if the connection drops while in use.
> >> + chr->backend = i;
> >> + chr->recon_time = qemu_opt_get_number(opts, "reconnect", 0);
> >> + if (chr->recon_time) {
> >> + if (strcmp(qemu_opt_get(opts, "backend"), "socket") != 0) {
> >> + g_free(chr);
> >> + fprintf(stderr, "chardev: reconnect only supported on sockets\n");
> >> + return NULL;
> >> + }
> > I think it would work *much* better to just add a "chr_reconnect"
> > function pointer to CharDriverState. You don't need patch #1 then.
> > Also it avoids backend-specific bits in generic code. Generic code just
> > checks if chr->chr_reconnect exists to figure whenever reconnect is
> > supported or not. And the socket backend can set chr_reconnect for
> > client sockets only.
>
> I was trying for something more generic than one that just applies to
> socket devices. It may not be good for server sockets, but it might be
> useful for ptys and hotplug devices. Looking at the code, ptys already
> has its own code that does something similar; that could be pulled out
> and replaced with the generic code.
>
> Also, IMHO allocating the chardev in each back end is not optimal. It
> breaks layering. Plus patch #1 has a net reduction in lines of code
> because it pulls out all the allocations and does it in one place.
>
> Thanks,
>
> -corey
I guess this was just one suggestion.
What Gerd is asking for here is that we avoid
code like
strcmp(qemu_opt_get(opts, "backend"), "socket")
in generic code, instead making a backend report
reconnect support.
This sounds reasonable, does it not?
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 03/16] qemu-char: remove free of chr from win_stdio_close
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 01/16] qemu-char: Allocate CharDriverState in qemu_chr_new_from_opts Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 02/16] qemu-char: Allow a chardev to reconnect if disconnected Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 04/16] qemu-char: Close fd at end of file Corey Minyard
` (12 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This will result in a double free on close, because it's freed
in qemu_chr_delete() right after calling the close function.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
qemu-char.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/qemu-char.c b/qemu-char.c
index 23d7647..935066d 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -2075,7 +2075,6 @@ static void win_stdio_close(CharDriverState *chr)
}
g_free(chr->opaque);
- g_free(chr);
}
static CharDriverState *qemu_chr_open_stdio(CharDriverState *chr,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 04/16] qemu-char: Close fd at end of file
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (2 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 03/16] qemu-char: remove free of chr from win_stdio_close Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 05/16] Add a base IPMI interface Corey Minyard
` (11 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
The chardev backends that used qemu_chr_open_fd did not get their
file descriptors closed at end of file or when the chardev was closed.
This could result in a file descriptor leak.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
qemu-char.c | 35 +++++++++++++++++++++++++++++------
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index 935066d..08b29ac 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -820,6 +820,8 @@ typedef struct FDCharDriver {
GIOChannel *fd_in, *fd_out;
int max_size;
QTAILQ_ENTRY(FDCharDriver) node;
+ int close_fdin;
+ int close_fdout;
} FDCharDriver;
static int fd_chr_write(CharDriverState *chr, const uint8_t *buf, int len)
@@ -829,6 +831,18 @@ static int fd_chr_write(CharDriverState *chr, const uint8_t *buf, int len)
return io_channel_send(s->fd_out, buf, len);
}
+static void fd_close_fds(FDCharDriver *s)
+{
+ if ((s->close_fdin != s->close_fdout) && (s->close_fdout != -1)) {
+ close(s->close_fdout);
+ }
+ s->close_fdout = -1;
+ if (s->close_fdin != -1) {
+ close(s->close_fdin);
+ }
+ s->close_fdin = -1;
+}
+
static gboolean fd_chr_read(GIOChannel *chan, GIOCondition cond, void *opaque)
{
CharDriverState *chr = opaque;
@@ -850,6 +864,7 @@ static gboolean fd_chr_read(GIOChannel *chan, GIOCondition cond, void *opaque)
len, &bytes_read, NULL);
if (status == G_IO_STATUS_EOF) {
remove_fd_in_watch(chr);
+ fd_close_fds(s);
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
return FALSE;
}
@@ -898,19 +913,27 @@ static void fd_chr_close(struct CharDriverState *chr)
g_io_channel_unref(s->fd_out);
}
+ fd_close_fds(s);
g_free(s);
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
/* open a character device to a unix fd */
static CharDriverState *qemu_chr_open_fd(CharDriverState *chr,
- int fd_in, int fd_out)
+ int fd_in, int fd_out,
+ int close_fds_on_close)
{
FDCharDriver *s;
s = g_malloc0(sizeof(FDCharDriver));
s->fd_in = io_channel_from_fd(fd_in);
s->fd_out = io_channel_from_fd(fd_out);
+ if (close_fds_on_close) {
+ s->close_fdin = fd_in;
+ s->close_fdout = fd_out;
+ } else {
+ s->close_fdin = s->close_fdout = -1;
+ }
fcntl(fd_out, F_SETFL, O_NONBLOCK);
s->chr = chr;
chr->opaque = s;
@@ -948,7 +971,7 @@ static CharDriverState *qemu_chr_open_pipe(CharDriverState *chr,
return NULL;
}
}
- return qemu_chr_open_fd(chr, fd_in, fd_out);
+ return qemu_chr_open_fd(chr, fd_in, fd_out, TRUE);
}
/* init terminal so that we can grab keys */
@@ -1001,7 +1024,7 @@ static CharDriverState *qemu_chr_open_stdio(CharDriverState *chr,
fcntl(0, F_SETFL, O_NONBLOCK);
atexit(term_exit);
- qemu_chr_open_fd(chr, 0, 1);
+ qemu_chr_open_fd(chr, 0, 1, FALSE);
chr->chr_close = qemu_chr_close_stdio;
chr->chr_set_echo = qemu_chr_set_echo_stdio;
if (opts->has_signal) {
@@ -1407,7 +1430,7 @@ static void qemu_chr_close_tty(CharDriverState *chr)
static CharDriverState *qemu_chr_open_tty_fd(CharDriverState *chr, int fd)
{
tty_serial_init(fd, 115200, 'N', 8, 1);
- qemu_chr_open_fd(chr, fd, fd);
+ qemu_chr_open_fd(chr, fd, fd, TRUE);
chr->chr_ioctl = tty_serial_ioctl;
chr->chr_close = qemu_chr_close_tty;
return chr;
@@ -2483,7 +2506,7 @@ static gboolean tcp_chr_read(GIOChannel *chan, GIOCondition cond, void *opaque)
#ifndef _WIN32
CharDriverState *qemu_chr_open_eventfd(CharDriverState *chr, int eventfd)
{
- return qemu_chr_open_fd(chr, eventfd, eventfd);
+ return qemu_chr_open_fd(chr, eventfd, eventfd, FALSE);
}
#endif
@@ -3639,7 +3662,7 @@ static CharDriverState *qmp_chardev_open_file(CharDriverState *chr,
}
}
- return qemu_chr_open_fd(chr, in, out);
+ return qemu_chr_open_fd(chr, in, out, TRUE);
}
static CharDriverState *qmp_chardev_open_serial(CharDriverState *chr,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 05/16] Add a base IPMI interface
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (3 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 04/16] qemu-char: Close fd at end of file Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 06/16] ipmi: Add a PC ISA type structure Corey Minyard
` (10 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
Add the basic IPMI types and infrastructure to QEMU. Low-level
interfaces and simulation interfaces will register with this; it's
kind of the go-between to tie them together.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/Makefile.objs | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi.c | 167 +++++++++++++++++++++++++
hw/ipmi/ipmi.h | 241 +++++++++++++++++++++++++++++++++++++
qemu-doc.texi | 2 +
7 files changed, 414 insertions(+)
create mode 100644 hw/ipmi/Makefile.objs
create mode 100644 hw/ipmi/ipmi.c
create mode 100644 hw/ipmi/ipmi.h
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 37ef90f..89199fb 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -10,6 +10,7 @@ CONFIG_VGA_ISA=y
CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
+CONFIG_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 31bddce..154248a 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -10,6 +10,7 @@ CONFIG_VGA_ISA=y
CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
+CONFIG_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 0243d6a..eeeb3bd 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -12,6 +12,7 @@ devices-dirs-$(CONFIG_SOFTMMU) += i2c/
devices-dirs-$(CONFIG_SOFTMMU) += ide/
devices-dirs-$(CONFIG_SOFTMMU) += input/
devices-dirs-$(CONFIG_SOFTMMU) += intc/
+devices-dirs-$(CONFIG_SOFTMMU) += ipmi/
devices-dirs-$(CONFIG_SOFTMMU) += isa/
devices-dirs-$(CONFIG_SOFTMMU) += misc/
devices-dirs-$(CONFIG_SOFTMMU) += net/
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
new file mode 100644
index 0000000..65bde11
--- /dev/null
+++ b/hw/ipmi/Makefile.objs
@@ -0,0 +1 @@
+common-obj-$(CONFIG_IPMI) += ipmi.o
diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c
new file mode 100644
index 0000000..21560a9
--- /dev/null
+++ b/hw/ipmi/ipmi.c
@@ -0,0 +1,167 @@
+/*
+ * QEMU IPMI emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/hw.h"
+#include "ipmi.h"
+#include "sysemu/sysemu.h"
+#include "qmp-commands.h"
+
+#ifdef DO_IPMI_THREAD
+static void *ipmi_thread(void *opaque)
+{
+ IPMIInterface *s = opaque;
+ int64_t wait_until;
+
+ ipmi_lock(s);
+ for (;;) {
+ qemu_cond_wait(&s->waker, &s->lock);
+ wait_until = 0;
+ while (s->do_wake) {
+ s->do_wake = 0;
+ s->handle_if_event(s);
+ }
+ }
+ ipmi_unlock(s);
+ return NULL;
+}
+#endif
+
+static int ipmi_do_hw_op(IPMIInterface *s, enum ipmi_op op, int checkonly)
+{
+ switch (op) {
+ case IPMI_RESET_CHASSIS:
+ if (checkonly) {
+ return 0;
+ }
+ qemu_system_reset_request();
+ return 0;
+
+ case IPMI_POWEROFF_CHASSIS:
+ if (checkonly) {
+ return 0;
+ }
+ qemu_system_powerdown_request();
+ return 0;
+
+ case IPMI_SEND_NMI:
+ if (checkonly) {
+ return 0;
+ }
+ qemu_mutex_lock_iothread();
+ qmp_inject_nmi(NULL);
+ qemu_mutex_unlock_iothread();
+ return 0;
+
+ case IPMI_POWERCYCLE_CHASSIS:
+ case IPMI_PULSE_DIAG_IRQ:
+ case IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP:
+ case IPMI_POWERON_CHASSIS:
+ default:
+ return IPMI_CC_COMMAND_NOT_SUPPORTED;
+ }
+}
+
+static void ipmi_set_irq_enable(IPMIInterface *s, int val)
+{
+ s->irqs_enabled = val;
+}
+
+void ipmi_interface_reset(IPMIInterface *s)
+{
+ IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(s->bmc);
+
+ if (bk->handle_reset) {
+ bk->handle_reset(s->bmc);
+ }
+}
+
+int ipmi_interface_init(IPMIInterface *s)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ if (k->init) {
+ int rc = k->init(s);
+ if (rc) {
+ return rc;
+ }
+ }
+
+ if (!s->slave_addr) {
+ s->slave_addr = 0x20;
+ }
+
+#ifdef DO_IPMI_THREAD
+ qemu_mutex_init(&s->lock);
+ qemu_cond_init(&s->waker);
+ qemu_thread_create(&s->thread, ipmi_thread, s, 0);
+#endif
+
+ return 0;
+}
+
+static void ipmi_interface_class_init(ObjectClass *class, void *data)
+{
+ IPMIInterfaceClass *ik = IPMI_INTERFACE_CLASS(class);
+
+ ik->do_hw_op = ipmi_do_hw_op;
+ ik->set_irq_enable = ipmi_set_irq_enable;
+}
+
+static TypeInfo ipmi_interface_type_info = {
+ .name = TYPE_IPMI_INTERFACE,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(IPMIInterface),
+ .abstract = true,
+ .class_size = sizeof(IPMIInterfaceClass),
+ .class_init = ipmi_interface_class_init,
+};
+
+int ipmi_bmc_init(IPMIBmc *s)
+{
+ IPMIBmcClass *k = IPMI_BMC_GET_CLASS(s);
+
+ if (k->init) {
+ int rc = k->init(s);
+ if (rc) {
+ return rc;
+ }
+ }
+ return 0;
+}
+
+static TypeInfo ipmi_bmc_type_info = {
+ .name = TYPE_IPMI_BMC,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(IPMIBmc),
+ .abstract = true,
+ .class_size = sizeof(IPMIBmcClass),
+};
+
+static void ipmi_register_types(void)
+{
+ type_register_static(&ipmi_interface_type_info);
+ type_register_static(&ipmi_bmc_type_info);
+}
+
+type_init(ipmi_register_types)
diff --git a/hw/ipmi/ipmi.h b/hw/ipmi/ipmi.h
new file mode 100644
index 0000000..8838023
--- /dev/null
+++ b/hw/ipmi/ipmi.h
@@ -0,0 +1,241 @@
+/*
+ * IPMI base class
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_IPMI_H
+#define HW_IPMI_H
+
+#include "exec/memory.h"
+#include "qemu-common.h"
+#include "hw/qdev.h"
+
+/*
+ * Create a separate thread for the IPMI interface itself. This is a
+ * better simulation and lets the IPMI interface do things asynchronously
+ * if necessary.
+ */
+/* #define DO_IPMI_THREAD */
+
+#ifdef DO_IPMI_THREAD
+#include "qemu-thread.h"
+
+#define ipmi_lock(s) qemu_mutex_lock(&(s)->lock)
+#define ipmi_unlock(s) qemu_mutex_unlock(&(s)->lock)
+#define ipmi_signal(s) \
+do { \
+ (s)->do_wake = 1; \
+ qemu_cond_signal(&(s)->waker); \
+} while (0)
+
+#else
+#define ipmi_lock(s) ((s)->lockcount++)
+#define ipmi_unlock(s) ((s)->lockcount--)
+#define ipmi_signal(s) \
+do { \
+ (s)->do_wake = 1; \
+ while ((s)->do_wake) { \
+ (s)->do_wake = 0; \
+ (IPMI_INTERFACE_GET_CLASS(s))->handle_if_event(s); \
+ } \
+} while (0)
+#endif
+
+#define MAX_IPMI_MSG_SIZE 300
+
+enum ipmi_op {
+ IPMI_RESET_CHASSIS,
+ IPMI_POWEROFF_CHASSIS,
+ IPMI_POWERON_CHASSIS,
+ IPMI_POWERCYCLE_CHASSIS,
+ IPMI_PULSE_DIAG_IRQ,
+ IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP,
+ IPMI_SEND_NMI
+};
+
+#define IPMI_CC_INVALID_CMD 0xc1
+#define IPMI_CC_COMMAND_INVALID_FOR_LUN 0xc2
+#define IPMI_CC_TIMEOUT 0xc3
+#define IPMI_CC_OUT_OF_SPACE 0xc4
+#define IPMI_CC_INVALID_RESERVATION 0xc5
+#define IPMI_CC_REQUEST_DATA_TRUNCATED 0xc6
+#define IPMI_CC_REQUEST_DATA_LENGTH_INVALID 0xc7
+#define IPMI_CC_PARM_OUT_OF_RANGE 0xc9
+#define IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES 0xca
+#define IPMI_CC_REQ_ENTRY_NOT_PRESENT 0xcb
+#define IPMI_CC_INVALID_DATA_FIELD 0xcc
+#define IPMI_CC_BMC_INIT_IN_PROGRESS 0xd2
+#define IPMI_CC_COMMAND_NOT_SUPPORTED 0xd5
+
+#define IPMI_NETFN_APP 0x06
+
+#define IPMI_DEBUG 1
+
+/* Specified in the SMBIOS spec. */
+#define IPMI_SMBIOS_KCS 0x01
+#define IPMI_SMBIOS_SMIC 0x02
+#define IPMI_SMBIOS_BT 0x03
+#define IPMI_SMBIOS_SSIF 0x04
+
+/* IPMI Interface types (KCS, SMIC, BT) are prefixed with this */
+#define TYPE_IPMI_INTERFACE_PREFIX "ipmi-interface-"
+
+typedef struct IPMIBmc IPMIBmc;
+
+/*
+ * An IPMI Interface, the interface for talking between the target
+ * and the BMC.
+ */
+#define TYPE_IPMI_INTERFACE "ipmi-interface"
+#define IPMI_INTERFACE(obj) \
+ OBJECT_CHECK(IPMIInterface, (obj), TYPE_IPMI_INTERFACE)
+#define IPMI_INTERFACE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IPMIInterfaceClass, (klass), TYPE_IPMI_INTERFACE)
+#define IPMI_INTERFACE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IPMIInterfaceClass, (obj), TYPE_IPMI_INTERFACE)
+
+typedef struct IPMIInterface {
+ Object parent_obj;
+
+ IPMIBmc *bmc;
+
+#ifdef DO_IPMI_THREAD
+ QemuThread thread;
+ QemuCond waker;
+ QemuMutex lock;
+#else
+ int lockcount;
+#endif
+ bool do_wake;
+
+ qemu_irq irq;
+
+ unsigned long io_base;
+ unsigned long io_length;
+ MemoryRegion io;
+
+ unsigned char slave_addr;
+
+ bool obf_irq_set;
+ bool atn_irq_set;
+ bool use_irq;
+ bool irqs_enabled;
+
+ uint8_t outmsg[MAX_IPMI_MSG_SIZE];
+ uint32_t outpos;
+ uint32_t outlen;
+
+ uint8_t inmsg[MAX_IPMI_MSG_SIZE];
+ uint32_t inlen;
+ bool write_end;
+} IPMIInterface;
+
+typedef struct IPMIInterfaceClass {
+ ObjectClass parent_class;
+
+ unsigned int smbios_type;
+
+ int (*init)(struct IPMIInterface *s);
+
+ /*
+ * Perform various operations on the hardware. If checkonly is
+ * true, it will return if the operation can be performed, but it
+ * will not do the operation.
+ */
+ int (*do_hw_op)(struct IPMIInterface *s, enum ipmi_op op, int checkonly);
+
+ /*
+ * Enable/disable irqs on the interface when the BMC requests this.
+ */
+ void (*set_irq_enable)(struct IPMIInterface *s, int val);
+
+ /*
+ * Handle an event that occurred on the interface, generally the.
+ * target writing to a register.
+ */
+ void (*handle_if_event)(struct IPMIInterface *s);
+
+ /*
+ * The interfaces use this to perform certain ops
+ */
+ void (*set_atn)(struct IPMIInterface *s, int val, int irq);
+
+ /*
+ * Handle a response from the bmc. Must be called with ipmi_lock
+ * held.
+ */
+ void (*handle_rsp)(struct IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len);
+} IPMIInterfaceClass;
+
+int ipmi_interface_init(IPMIInterface *s);
+void ipmi_interface_reset(IPMIInterface *s);
+
+/*
+ * Define a BMC simulator (or perhaps a connection to a real BMC)
+ */
+#define TYPE_IPMI_BMC "ipmi-bmc"
+#define IPMI_BMC(obj) \
+ OBJECT_CHECK(IPMIBmc, (obj), TYPE_IPMI_BMC)
+#define IPMI_BMC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IPMIBmcClass, (klass), TYPE_IPMI_BMC)
+#define IPMI_BMC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IPMIBmcClass, (obj), TYPE_IPMI_BMC)
+
+#define TYPE_IPMI_BMC_EXTERN "ipmi-bmc-extern"
+#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim"
+
+struct IPMIBmc {
+ Object parent_obj;
+
+ IPMIInterface *intf;
+ CharDriverState *chr;
+};
+
+typedef struct IPMIBmcClass {
+ ObjectClass parent_class;
+
+ int (*init)(IPMIBmc *s);
+
+ /* Called when the system resets to report to the bmc. */
+ void (*handle_reset)(struct IPMIBmc *s);
+
+ /*
+ * Handle a command to the bmc. Must be called with ipmi_lock
+ * held.
+ */
+ void (*handle_command)(struct IPMIBmc *s,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id);
+} IPMIBmcClass;
+
+int ipmi_bmc_init(IPMIBmc *s);
+
+#ifdef IPMI_DEBUG
+#define ipmi_debug(fs, ...) \
+ fprintf(stderr, "IPMI (%s): " fs, __func__, ##__VA_ARGS__)
+#else
+#define ipmi_debug(fs, ...)
+#endif
+
+#endif
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 185dd47..afe50dd 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -195,6 +195,8 @@ PCI and ISA network adapters
@item
Serial ports
@item
+IPMI BMC, either and internal or external one
+@item
Creative SoundBlaster 16 sound card
@item
ENSONIQ AudioPCI ES1370 sound card
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 06/16] ipmi: Add a PC ISA type structure
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (4 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 05/16] Add a base IPMI interface Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2014-01-29 14:58 ` Andreas Färber
2013-11-12 16:33 ` [Qemu-devel] [PATCH 07/16] ipmi: Add a KCS low-level interface Corey Minyard
` (9 subsequent siblings)
15 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This provides the base infrastructure to tie IPMI low-level
interfaces into a PC ISA bus.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/isa_ipmi.c | 148 +++++++++++++++++++++++++++++++++++++
include/hw/nvram/fw_cfg.h | 11 ++-
5 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 hw/ipmi/isa_ipmi.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 89199fb..d5ee6c5 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
+CONFIG_ISA_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 154248a..0b700ae 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
+CONFIG_ISA_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 65bde11..3494b70 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -1 +1,2 @@
common-obj-$(CONFIG_IPMI) += ipmi.o
+common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
new file mode 100644
index 0000000..0242a41
--- /dev/null
+++ b/hw/ipmi/isa_ipmi.c
@@ -0,0 +1,148 @@
+/*
+ * QEMU ISA IPMI emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "hw/isa/isa.h"
+#include "hw/i386/pc.h"
+#include "qemu/timer.h"
+#include "sysemu/char.h"
+#include "sysemu/sysemu.h"
+#include "ipmi.h"
+
+/* This is the type the user specifies on the -device command line */
+#define TYPE_ISA_IPMI "isa-ipmi"
+#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), \
+ TYPE_ISA_IPMI)
+typedef struct ISAIPMIDevice {
+ ISADevice dev;
+ char *interface;
+ uint32_t iobase;
+ uint32_t isairq;
+ uint8_t slave_addr;
+ CharDriverState *chr;
+ IPMIInterface *intf;
+} ISAIPMIDevice;
+
+static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
+{
+ ISADevice *isadev = ISA_DEVICE(dev);
+ ISAIPMIDevice *isa = ISA_IPMI(dev);
+ char typename[20];
+ Object *intfobj;
+ IPMIInterface *intf;
+ Object *bmcobj;
+ IPMIBmc *bmc;
+ int rc;
+
+ if (!isa->interface) {
+ isa->interface = g_strdup("kcs");
+ }
+
+ if (isa->chr) {
+ bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
+ } else {
+ bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
+ }
+ bmc = IPMI_BMC(bmcobj);
+ bmc->chr = isa->chr;
+ snprintf(typename, sizeof(typename),
+ TYPE_IPMI_INTERFACE_PREFIX "%s", isa->interface);
+ intfobj = object_new(typename);
+ intf = IPMI_INTERFACE(intfobj);
+ bmc->intf = intf;
+ intf->bmc = bmc;
+ intf->io_base = isa->iobase;
+ intf->slave_addr = isa->slave_addr;
+ rc = ipmi_interface_init(intf);
+ if (rc) {
+ error_setg(errp, "Error initializing IPMI interface: %d\n", rc);
+ return;
+ }
+ rc = ipmi_bmc_init(bmc);
+ if (rc) {
+ error_setg(errp, "Error initializing BMC: %d\n", rc);
+ return;
+ }
+
+ /* These may be set by the interface. */
+ isa->iobase = intf->io_base;
+ isa->slave_addr = intf->slave_addr;
+
+ if (isa->isairq != 0) {
+ isa_init_irq(isadev, &intf->irq, isa->isairq);
+ intf->use_irq = 1;
+ }
+
+ isa->intf = intf;
+ object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
+ if (error_is_set(errp)) {
+ return;
+ }
+ object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
+ if (error_is_set(errp)) {
+ return;
+ }
+
+ qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
+
+ isa_register_ioport(isadev, &intf->io, intf->io_base);
+}
+
+static void ipmi_isa_reset(DeviceState *dev)
+{
+ ISAIPMIDevice *isa = ISA_IPMI(dev);
+
+ ipmi_interface_reset(isa->intf);
+}
+
+static Property ipmi_isa_properties[] = {
+ DEFINE_PROP_STRING("interface", ISAIPMIDevice, interface),
+ DEFINE_PROP_HEX32("iobase", ISAIPMIDevice, iobase, 0),
+ DEFINE_PROP_UINT32("irq", ISAIPMIDevice, isairq, 5),
+ DEFINE_PROP_UINT8("slave_addr", ISAIPMIDevice, slave_addr, 0),
+ DEFINE_PROP_CHR("chardev", ISAIPMIDevice, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = ipmi_isa_realizefn;
+ dc->reset = ipmi_isa_reset;
+ dc->props = ipmi_isa_properties;
+}
+
+static const TypeInfo ipmi_isa_info = {
+ .name = TYPE_ISA_IPMI,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(ISAIPMIDevice),
+ .class_init = ipmi_isa_class_initfn,
+};
+
+static void ipmi_register_types(void)
+{
+ type_register_static(&ipmi_isa_info);
+}
+
+type_init(ipmi_register_types)
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 72b1549..40ab84e 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -38,7 +38,16 @@
#define FW_CFG_FILE_FIRST 0x20
#define FW_CFG_FILE_SLOTS 0x10
-#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
+
+#define FW_CFG_IPMI_INTERFACE 0x30
+#define FW_CFG_IPMI_BASE_ADDR 0x31
+#define FW_CFG_IPMI_REG_SPACE 0x32
+#define FW_CFG_IPMI_REG_SPACING 0x33
+#define FW_CFG_IPMI_SLAVE_ADDR 0x34
+#define FW_CFG_IPMI_IRQ 0x35
+#define FW_CFG_IPMI_VERSION 0x36
+
+#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
#define FW_CFG_WRITE_CHANNEL 0x4000
#define FW_CFG_ARCH_LOCAL 0x8000
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 06/16] ipmi: Add a PC ISA type structure
2013-11-12 16:33 ` [Qemu-devel] [PATCH 06/16] ipmi: Add a PC ISA type structure Corey Minyard
@ 2014-01-29 14:58 ` Andreas Färber
0 siblings, 0 replies; 42+ messages in thread
From: Andreas Färber @ 2014-01-29 14:58 UTC (permalink / raw)
To: Corey Minyard, qemu-devel; +Cc: Bret Ketchum, Corey Minyard, Michael S. Tsirkin
Am 12.11.2013 17:33, schrieb Corey Minyard:
> This provides the base infrastructure to tie IPMI low-level
> interfaces into a PC ISA bus.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
[...]
> diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
> new file mode 100644
> index 0000000..0242a41
> --- /dev/null
> +++ b/hw/ipmi/isa_ipmi.c
> @@ -0,0 +1,148 @@
> +/*
> + * QEMU ISA IPMI emulation
> + *
> + * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "hw/hw.h"
> +#include "hw/isa/isa.h"
> +#include "hw/i386/pc.h"
> +#include "qemu/timer.h"
> +#include "sysemu/char.h"
> +#include "sysemu/sysemu.h"
> +#include "ipmi.h"
> +
> +/* This is the type the user specifies on the -device command line */
> +#define TYPE_ISA_IPMI "isa-ipmi"
> +#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), \
> + TYPE_ISA_IPMI)
> +typedef struct ISAIPMIDevice {
> + ISADevice dev;
> + char *interface;
> + uint32_t iobase;
> + uint32_t isairq;
> + uint8_t slave_addr;
> + CharDriverState *chr;
> + IPMIInterface *intf;
> +} ISAIPMIDevice;
> +
> +static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
> +{
> + ISADevice *isadev = ISA_DEVICE(dev);
> + ISAIPMIDevice *isa = ISA_IPMI(dev);
> + char typename[20];
> + Object *intfobj;
> + IPMIInterface *intf;
> + Object *bmcobj;
> + IPMIBmc *bmc;
> + int rc;
> +
> + if (!isa->interface) {
> + isa->interface = g_strdup("kcs");
> + }
> +
> + if (isa->chr) {
> + bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
> + } else {
> + bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
> + }
[snip]
This depends on types registered in patches 09 and 10.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 07/16] ipmi: Add a KCS low-level interface
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (5 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 06/16] ipmi: Add a PC ISA type structure Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 08/16] ipmi: Add a BT " Corey Minyard
` (8 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This provides the simulation of the KCS hardware interface.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_kcs.c | 345 +++++++++++++++++++++++++++++++++++++
4 files changed, 348 insertions(+)
create mode 100644 hw/ipmi/ipmi_kcs.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index d5ee6c5..e257954 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -12,6 +12,7 @@ CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
+CONFIG_IPMI_KCS=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 0b700ae..f3b2bf8 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -12,6 +12,7 @@ CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
+CONFIG_IPMI_KCS=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 3494b70..3c811ae 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -1,2 +1,3 @@
common-obj-$(CONFIG_IPMI) += ipmi.o
common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
+common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
diff --git a/hw/ipmi/ipmi_kcs.c b/hw/ipmi/ipmi_kcs.c
new file mode 100644
index 0000000..056a369
--- /dev/null
+++ b/hw/ipmi/ipmi_kcs.c
@@ -0,0 +1,345 @@
+/*
+ * QEMU IPMI KCS emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "ipmi.h"
+
+#define TYPE_IPMI_INTERFACE_KCS TYPE_IPMI_INTERFACE_PREFIX "kcs"
+#define IPMI_INTERFACE_KCS(obj) OBJECT_CHECK(IPMIKcsInterface, (obj), \
+ TYPE_IPMI_INTERFACE_KCS)
+
+#define IPMI_KCS_OBF_BIT 0
+#define IPMI_KCS_IBF_BIT 1
+#define IPMI_KCS_SMS_ATN_BIT 2
+#define IPMI_KCS_CD_BIT 3
+
+#define IPMI_KCS_OBF_MASK (1 << IPMI_KCS_OBF_BIT)
+#define IPMI_KCS_GET_OBF(d) (((d) >> IPMI_KCS_OBF_BIT) & 0x1)
+#define IPMI_KCS_SET_OBF(d, v) (d) = (((d) & ~IPMI_KCS_OBF_MASK) | \
+ (((v) & 1) << IPMI_KCS_OBF_BIT))
+#define IPMI_KCS_IBF_MASK (1 << IPMI_KCS_IBF_BIT)
+#define IPMI_KCS_GET_IBF(d) (((d) >> IPMI_KCS_IBF_BIT) & 0x1)
+#define IPMI_KCS_SET_IBF(d, v) (d) = (((d) & ~IPMI_KCS_IBF_MASK) | \
+ (((v) & 1) << IPMI_KCS_IBF_BIT))
+#define IPMI_KCS_SMS_ATN_MASK (1 << IPMI_KCS_SMS_ATN_BIT)
+#define IPMI_KCS_GET_SMS_ATN(d) (((d) >> IPMI_KCS_SMS_ATN_BIT) & 0x1)
+#define IPMI_KCS_SET_SMS_ATN(d, v) (d) = (((d) & ~IPMI_KCS_SMS_ATN_MASK) | \
+ (((v) & 1) << IPMI_KCS_SMS_ATN_BIT))
+#define IPMI_KCS_CD_MASK (1 << IPMI_KCS_CD_BIT)
+#define IPMI_KCS_GET_CD(d) (((d) >> IPMI_KCS_CD_BIT) & 0x1)
+#define IPMI_KCS_SET_CD(d, v) (d) = (((d) & ~IPMI_KCS_CD_MASK) | \
+ (((v) & 1) << IPMI_KCS_CD_BIT))
+
+#define IPMI_KCS_IDLE_STATE 0
+#define IPMI_KCS_READ_STATE 1
+#define IPMI_KCS_WRITE_STATE 2
+#define IPMI_KCS_ERROR_STATE 3
+
+#define IPMI_KCS_GET_STATE(d) (((d) >> 6) & 0x3)
+#define IPMI_KCS_SET_STATE(d, v) ((d) = ((d) & ~0xc0) | (((v) & 0x3) << 6))
+
+#define IPMI_KCS_ABORT_STATUS_CMD 0x60
+#define IPMI_KCS_WRITE_START_CMD 0x61
+#define IPMI_KCS_WRITE_END_CMD 0x62
+#define IPMI_KCS_READ_CMD 0x68
+
+#define IPMI_KCS_STATUS_NO_ERR 0x00
+#define IPMI_KCS_STATUS_ABORTED_ERR 0x01
+#define IPMI_KCS_STATUS_BAD_CC_ERR 0x02
+#define IPMI_KCS_STATUS_LENGTH_ERR 0x06
+
+typedef struct IPMIKcsInterface {
+ IPMIInterface intf;
+
+ uint8_t status_reg;
+ uint8_t data_out_reg;
+
+ int16_t data_in_reg; /* -1 means not written */
+ int16_t cmd_reg;
+
+ /*
+ * This is a response number that we send with the command to make
+ * sure that the response matches the command.
+ */
+ uint8_t waiting_rsp;
+} IPMIKcsInterface;
+
+#define SET_OBF() \
+ do { \
+ IPMI_KCS_SET_OBF(kcs->status_reg, 1); \
+ if (s->use_irq && s->irqs_enabled && !s->obf_irq_set) { \
+ s->obf_irq_set = 1; \
+ if (!s->atn_irq_set) { \
+ qemu_irq_raise(s->irq); \
+ } \
+ } \
+ } while (0)
+
+static void ipmi_kcs_handle_event(IPMIInterface *s)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ if (kcs->cmd_reg == IPMI_KCS_ABORT_STATUS_CMD) {
+ if (IPMI_KCS_GET_STATE(kcs->status_reg) != IPMI_KCS_ERROR_STATE) {
+ kcs->waiting_rsp++; /* Invalidate the message */
+ s->outmsg[0] = IPMI_KCS_STATUS_ABORTED_ERR;
+ s->outlen = 1;
+ s->outpos = 0;
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_ERROR_STATE);
+ SET_OBF();
+ }
+ goto out;
+ }
+
+ switch (IPMI_KCS_GET_STATE(kcs->status_reg)) {
+ case IPMI_KCS_IDLE_STATE:
+ if (kcs->cmd_reg == IPMI_KCS_WRITE_START_CMD) {
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_WRITE_STATE);
+ kcs->cmd_reg = -1;
+ s->write_end = 0;
+ s->inlen = 0;
+ SET_OBF();
+ }
+ break;
+
+ case IPMI_KCS_READ_STATE:
+ handle_read:
+ if (s->outpos >= s->outlen) {
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_IDLE_STATE);
+ SET_OBF();
+ } else if (kcs->data_in_reg == IPMI_KCS_READ_CMD) {
+ kcs->data_out_reg = s->outmsg[s->outpos];
+ s->outpos++;
+ SET_OBF();
+ } else {
+ s->outmsg[0] = IPMI_KCS_STATUS_BAD_CC_ERR;
+ s->outlen = 1;
+ s->outpos = 0;
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_ERROR_STATE);
+ SET_OBF();
+ goto out;
+ }
+ break;
+
+ case IPMI_KCS_WRITE_STATE:
+ if (kcs->data_in_reg != -1) {
+ /*
+ * Don't worry about input overrun here, that will be
+ * handled in the BMC.
+ */
+ if (s->inlen < sizeof(s->inmsg)) {
+ s->inmsg[s->inlen] = kcs->data_in_reg;
+ }
+ s->inlen++;
+ }
+ if (s->write_end) {
+ IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(s->bmc);
+ s->outlen = 0;
+ s->write_end = 0;
+ s->outpos = 0;
+ bk->handle_command(s->bmc, s->inmsg, s->inlen, sizeof(s->inmsg),
+ kcs->waiting_rsp);
+ goto out_noibf;
+ } else if (kcs->cmd_reg == IPMI_KCS_WRITE_END_CMD) {
+ kcs->cmd_reg = -1;
+ s->write_end = 1;
+ }
+ SET_OBF();
+ break;
+
+ case IPMI_KCS_ERROR_STATE:
+ if (kcs->data_in_reg != -1) {
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_READ_STATE);
+ kcs->data_in_reg = IPMI_KCS_READ_CMD;
+ goto handle_read;
+ }
+ break;
+ }
+
+ if (kcs->cmd_reg != -1) {
+ /* Got an invalid command */
+ s->outmsg[0] = IPMI_KCS_STATUS_BAD_CC_ERR;
+ s->outlen = 1;
+ s->outpos = 0;
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_ERROR_STATE);
+ }
+
+ out:
+ kcs->cmd_reg = -1;
+ kcs->data_in_reg = -1;
+ IPMI_KCS_SET_IBF(kcs->status_reg, 0);
+ out_noibf:
+ return;
+}
+
+static void ipmi_kcs_handle_rsp(IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ /* ipmi_lock is already claimed. */
+ if (kcs->waiting_rsp == msg_id) {
+ kcs->waiting_rsp++;
+ if (rsp_len > sizeof(s->outmsg)) {
+ s->outmsg[0] = rsp[0];
+ s->outmsg[1] = rsp[1];
+ s->outmsg[2] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
+ s->outlen = 3;
+ } else {
+ memcpy(s->outmsg, rsp, rsp_len);
+ s->outlen = rsp_len;
+ }
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_READ_STATE);
+ kcs->data_in_reg = IPMI_KCS_READ_CMD;
+ ipmi_signal(&kcs->intf);
+ }
+}
+
+
+static uint64_t ipmi_kcs_ioport_read(void *opaque, hwaddr addr, unsigned size)
+{
+ IPMIKcsInterface *kcs = opaque;
+ uint32_t ret;
+
+ ipmi_lock(&kcs->intf);
+ switch (addr & 1) {
+ case 0:
+ ret = kcs->data_out_reg;
+ IPMI_KCS_SET_OBF(kcs->status_reg, 0);
+ if (kcs->intf.obf_irq_set) {
+ kcs->intf.obf_irq_set = 0;
+ if (!kcs->intf.atn_irq_set) {
+ qemu_irq_lower(kcs->intf.irq);
+ }
+ }
+ break;
+ case 1:
+ ret = kcs->status_reg;
+ if (kcs->intf.atn_irq_set) {
+ kcs->intf.atn_irq_set = 0;
+ if (!kcs->intf.obf_irq_set) {
+ qemu_irq_lower(kcs->intf.irq);
+ }
+ }
+ break;
+ }
+ ipmi_unlock(&kcs->intf);
+ return ret;
+}
+
+static void ipmi_kcs_ioport_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ IPMIKcsInterface *kcs = opaque;
+ IPMIInterface *s = &kcs->intf;
+
+ if (IPMI_KCS_GET_IBF(kcs->status_reg)) {
+ return;
+ }
+
+ ipmi_lock(s);
+ switch (addr & 1) {
+ case 0:
+ kcs->data_in_reg = val;
+ break;
+
+ case 1:
+ kcs->cmd_reg = val;
+ break;
+ }
+ IPMI_KCS_SET_IBF(kcs->status_reg, 1);
+ ipmi_signal(s);
+ ipmi_unlock(s);
+}
+
+static const MemoryRegionOps ipmi_kcs_io_ops = {
+ .read = ipmi_kcs_ioport_read,
+ .write = ipmi_kcs_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ipmi_kcs_set_atn(IPMIInterface *s, int val, int irq)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ IPMI_KCS_SET_SMS_ATN(kcs->status_reg, val);
+ if (val) {
+ if (irq && !s->atn_irq_set && s->use_irq && s->irqs_enabled) {
+ s->atn_irq_set = 1;
+ if (!s->obf_irq_set) {
+ qemu_irq_raise(s->irq);
+ }
+ }
+ } else {
+ if (s->atn_irq_set) {
+ s->atn_irq_set = 0;
+ if (!s->obf_irq_set) {
+ qemu_irq_lower(s->irq);
+ }
+ }
+ }
+}
+
+static int ipmi_kcs_init(IPMIInterface *s)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ if (!s->io_base) {
+ s->io_base = 0xca2;
+ }
+ s->io_length = 2;
+
+ memory_region_init_io(&s->io, OBJECT(s), &ipmi_kcs_io_ops, kcs,
+ "ipmi-kcs", 2);
+
+ return 0;
+}
+
+static void ipmi_kcs_class_init(ObjectClass *class, void *data)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_CLASS(class);
+
+ k->init = ipmi_kcs_init;
+ k->smbios_type = IPMI_SMBIOS_KCS;
+ k->set_atn = ipmi_kcs_set_atn;
+ k->handle_rsp = ipmi_kcs_handle_rsp;
+ k->handle_if_event = ipmi_kcs_handle_event;
+}
+
+static const TypeInfo ipmi_kcs_type = {
+ .name = TYPE_IPMI_INTERFACE_KCS,
+ .parent = TYPE_IPMI_INTERFACE,
+ .instance_size = sizeof(IPMIKcsInterface),
+ .class_init = ipmi_kcs_class_init,
+};
+
+static void ipmi_kcs_register_types(void)
+{
+ type_register_static(&ipmi_kcs_type);
+}
+
+type_init(ipmi_kcs_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 08/16] ipmi: Add a BT low-level interface
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (6 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 07/16] ipmi: Add a KCS low-level interface Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 09/16] ipmi: Add a local BMC simulation Corey Minyard
` (7 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This provides the simulation of the BT hardware interface for
IPMI.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_bt.c | 367 +++++++++++++++++++++++++++++++++++++
4 files changed, 370 insertions(+)
create mode 100644 hw/ipmi/ipmi_bt.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index e257954..ea3a3b4 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -13,6 +13,7 @@ CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
+CONFIG_IPMI_BT=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index f3b2bf8..89efe84 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -13,6 +13,7 @@ CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
+CONFIG_IPMI_BT=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 3c811ae..a8cd463 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -1,3 +1,4 @@
common-obj-$(CONFIG_IPMI) += ipmi.o
common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
+common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
diff --git a/hw/ipmi/ipmi_bt.c b/hw/ipmi/ipmi_bt.c
new file mode 100644
index 0000000..ec256f4
--- /dev/null
+++ b/hw/ipmi/ipmi_bt.c
@@ -0,0 +1,367 @@
+/*
+ * QEMU IPMI BT emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "ipmi.h"
+
+#define TYPE_IPMI_INTERFACE_BT TYPE_IPMI_INTERFACE_PREFIX "bt"
+#define IPMI_INTERFACE_BT(obj) OBJECT_CHECK(IPMIBtInterface, (obj), \
+ TYPE_IPMI_INTERFACE_BT)
+
+/* Control register */
+#define IPMI_BT_CLR_WR_BIT 0
+#define IPMI_BT_CLR_RD_BIT 1
+#define IPMI_BT_H2B_ATN_BIT 2
+#define IPMI_BT_B2H_ATN_BIT 3
+#define IPMI_BT_SMS_ATN_BIT 4
+#define IPMI_BT_HBUSY_BIT 6
+#define IPMI_BT_BBUSY_BIT 7
+
+#define IPMI_BT_CLR_WR_MASK (1 << IPMI_BT_CLR_WR_BIT)
+#define IPMI_BT_GET_CLR_WR(d) (((d) >> IPMI_BT_CLR_WR_BIT) & 0x1)
+#define IPMI_BT_SET_CLR_WR(d, v) (d) = (((d) & ~IPMI_BT_CLR_WR_MASK) | \
+ (((v & 1) << IPMI_BT_CLR_WR_BIT)))
+
+#define IPMI_BT_CLR_RD_MASK (1 << IPMI_BT_CLR_RD_BIT)
+#define IPMI_BT_GET_CLR_RD(d) (((d) >> IPMI_BT_CLR_RD_BIT) & 0x1)
+#define IPMI_BT_SET_CLR_RD(d, v) (d) = (((d) & ~IPMI_BT_CLR_RD_MASK) | \
+ (((v & 1) << IPMI_BT_CLR_RD_BIT)))
+
+#define IPMI_BT_H2B_ATN_MASK (1 << IPMI_BT_H2B_ATN_BIT)
+#define IPMI_BT_GET_H2B_ATN(d) (((d) >> IPMI_BT_H2B_ATN_BIT) & 0x1)
+#define IPMI_BT_SET_H2B_ATN(d, v) (d) = (((d) & ~IPMI_BT_H2B_ATN_MASK) | \
+ (((v & 1) << IPMI_BT_H2B_ATN_BIT)))
+
+#define IPMI_BT_B2H_ATN_MASK (1 << IPMI_BT_B2H_ATN_BIT)
+#define IPMI_BT_GET_B2H_ATN(d) (((d) >> IPMI_BT_B2H_ATN_BIT) & 0x1)
+#define IPMI_BT_SET_B2H_ATN(d, v) (d) = (((d) & ~IPMI_BT_B2H_ATN_MASK) | \
+ (((v & 1) << IPMI_BT_B2H_ATN_BIT)))
+
+#define IPMI_BT_SMS_ATN_MASK (1 << IPMI_BT_SMS_ATN_BIT)
+#define IPMI_BT_GET_SMS_ATN(d) (((d) >> IPMI_BT_SMS_ATN_BIT) & 0x1)
+#define IPMI_BT_SET_SMS_ATN(d, v) (d) = (((d) & ~IPMI_BT_SMS_ATN_MASK) | \
+ (((v & 1) << IPMI_BT_SMS_ATN_BIT)))
+
+#define IPMI_BT_HBUSY_MASK (1 << IPMI_BT_HBUSY_BIT)
+#define IPMI_BT_GET_HBUSY(d) (((d) >> IPMI_BT_HBUSY_BIT) & 0x1)
+#define IPMI_BT_SET_HBUSY(d, v) (d) = (((d) & ~IPMI_BT_HBUSY_MASK) | \
+ (((v & 1) << IPMI_BT_HBUSY_BIT)))
+
+#define IPMI_BT_BBUSY_MASK (1 << IPMI_BT_BBUSY_BIT)
+#define IPMI_BT_GET_BBUSY(d) (((d) >> IPMI_BT_BBUSY_BIT) & 0x1)
+#define IPMI_BT_SET_BBUSY(d, v) (d) = (((d) & ~IPMI_BT_BBUSY_MASK) | \
+ (((v & 1) << IPMI_BT_BBUSY_BIT)))
+
+
+/* Mask register */
+#define IPMI_BT_B2H_IRQ_EN_BIT 0
+#define IPMI_BT_B2H_IRQ_BIT 1
+
+#define IPMI_BT_B2H_IRQ_EN_MASK (1 << IPMI_BT_B2H_IRQ_EN_BIT)
+#define IPMI_BT_GET_B2H_IRQ_EN(d) (((d) >> IPMI_BT_B2H_IRQ_EN_BIT) & 0x1)
+#define IPMI_BT_SET_B2H_IRQ_EN(d, v) (d) = (((d) & ~IPMI_BT_B2H_IRQ_EN_MASK) | \
+ (((v & 1) << IPMI_BT_B2H_IRQ_EN_BIT)))
+
+#define IPMI_BT_B2H_IRQ_MASK (1 << IPMI_BT_B2H_IRQ_BIT)
+#define IPMI_BT_GET_B2H_IRQ(d) (((d) >> IPMI_BT_B2H_IRQ_BIT) & 0x1)
+#define IPMI_BT_SET_B2H_IRQ(d, v) (d) = (((d) & ~IPMI_BT_B2H_IRQ_MASK) | \
+ (((v & 1) << IPMI_BT_B2H_IRQ_BIT)))
+
+typedef struct IPMIBtInterface {
+ IPMIInterface intf;
+
+ uint8_t control_reg;
+ uint8_t mask_reg;
+
+ /*
+ * This is a response number that we send with the command to make
+ * sure that the response matches the command.
+ */
+ uint8_t waiting_rsp;
+ uint8_t waiting_seq;
+} IPMIBtInterface;
+
+#define IPMI_CMD_GET_BT_INTF_CAP 0x36
+
+static void ipmi_bt_handle_event(IPMIInterface *s)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ ipmi_lock(s);
+ if (s->inlen < 4) {
+ goto out;
+ }
+ /* Note that overruns are handled by handle_command */
+ if (s->inmsg[0] != (s->inlen - 1)) {
+ /* Length mismatch, just ignore. */
+ IPMI_BT_SET_BBUSY(bt->control_reg, 1);
+ s->inlen = 0;
+ goto out;
+ }
+ if ((s->inmsg[1] == (IPMI_NETFN_APP << 2)) &&
+ (s->inmsg[3] == IPMI_CMD_GET_BT_INTF_CAP)) {
+ /* We handle this one ourselves. */
+ s->outmsg[0] = 9;
+ s->outmsg[1] = s->inmsg[1] | 0x04;
+ s->outmsg[2] = s->inmsg[2];
+ s->outmsg[3] = s->inmsg[3];
+ s->outmsg[4] = 0;
+ s->outmsg[5] = 1; /* Only support 1 outstanding request. */
+ if (sizeof(s->inmsg) > 0xff) { /* Input buffer size */
+ s->outmsg[6] = 0xff;
+ } else {
+ s->outmsg[6] = (unsigned char) sizeof(s->inmsg);
+ }
+ if (sizeof(s->outmsg) > 0xff) { /* Output buffer size */
+ s->outmsg[7] = 0xff;
+ } else {
+ s->outmsg[7] = (unsigned char) sizeof(s->outmsg);
+ }
+ s->outmsg[8] = 10; /* Max request to response time */
+ s->outmsg[9] = 0; /* Don't recommend retries */
+ s->outlen = 10;
+ IPMI_BT_SET_BBUSY(bt->control_reg, 0);
+ IPMI_BT_SET_B2H_ATN(bt->control_reg, 1);
+ if (s->use_irq && s->irqs_enabled &&
+ !IPMI_BT_GET_B2H_IRQ(bt->mask_reg) &&
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ goto out;
+ }
+ bt->waiting_seq = s->inmsg[2];
+ s->inmsg[2] = s->inmsg[1];
+ {
+ IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(s->bmc);
+ bk->handle_command(s->bmc, s->inmsg + 2, s->inlen - 2, sizeof(s->inmsg),
+ bt->waiting_rsp);
+ }
+ out:
+ ipmi_unlock(s);
+}
+
+static void ipmi_bt_handle_rsp(IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ /* ipmi_lock is already claimed. */
+ if (bt->waiting_rsp == msg_id) {
+ bt->waiting_rsp++;
+ if (rsp_len > (sizeof(s->outmsg) - 2)) {
+ s->outmsg[0] = 4;
+ s->outmsg[1] = rsp[0];
+ s->outmsg[2] = bt->waiting_seq;
+ s->outmsg[3] = rsp[1];
+ s->outmsg[4] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
+ s->outlen = 5;
+ } else {
+ s->outmsg[0] = rsp_len + 1;
+ s->outmsg[1] = rsp[0];
+ s->outmsg[2] = bt->waiting_seq;
+ memcpy(s->outmsg + 3, rsp + 1, rsp_len - 1);
+ s->outlen = rsp_len + 2;
+ }
+ IPMI_BT_SET_BBUSY(bt->control_reg, 0);
+ IPMI_BT_SET_B2H_ATN(bt->control_reg, 1);
+ if (s->use_irq && s->irqs_enabled &&
+ !IPMI_BT_GET_B2H_IRQ(bt->mask_reg) &&
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ }
+}
+
+
+static uint64_t ipmi_bt_ioport_read(void *opaque, hwaddr addr, unsigned size)
+{
+ IPMIBtInterface *bt = opaque;
+ IPMIInterface *s = &bt->intf;
+ uint32_t ret = 0xff;
+
+ ipmi_lock(s);
+ switch (addr & 3) {
+ case 0:
+ ret = bt->control_reg;
+ break;
+ case 1:
+ if (s->outpos < s->outlen) {
+ ret = s->outmsg[s->outpos];
+ s->outpos++;
+ if (s->outpos == s->outlen) {
+ s->outpos = 0;
+ s->outlen = 0;
+ }
+ } else {
+ ret = 0xff;
+ }
+ break;
+ case 2:
+ ret = bt->mask_reg;
+ break;
+ }
+ ipmi_unlock(s);
+ return ret;
+}
+
+static void ipmi_bt_ioport_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ IPMIBtInterface *bt = opaque;
+ IPMIInterface *s = &bt->intf;
+
+ ipmi_lock(s);
+ switch (addr & 3) {
+ case 0:
+ if (IPMI_BT_GET_CLR_WR(val)) {
+ s->inlen = 0;
+ }
+ if (IPMI_BT_GET_CLR_RD(val)) {
+ s->outpos = 0;
+ }
+ if (IPMI_BT_GET_B2H_ATN(val)) {
+ IPMI_BT_SET_B2H_ATN(bt->control_reg, 0);
+ }
+ if (IPMI_BT_GET_SMS_ATN(val)) {
+ IPMI_BT_SET_SMS_ATN(bt->control_reg, 0);
+ }
+ if (IPMI_BT_GET_HBUSY(val)) {
+ /* Toggle */
+ IPMI_BT_SET_HBUSY(bt->control_reg,
+ !IPMI_BT_GET_HBUSY(bt->control_reg));
+ }
+ if (IPMI_BT_GET_H2B_ATN(val)) {
+ IPMI_BT_SET_BBUSY(bt->control_reg, 1);
+ ipmi_signal(s);
+ }
+ break;
+
+ case 1:
+ if (s->inlen < sizeof(s->inmsg)) {
+ s->inmsg[s->inlen] = val;
+ }
+ s->inlen++;
+ break;
+
+ case 2:
+ if (IPMI_BT_GET_B2H_IRQ_EN(val) !=
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ if (IPMI_BT_GET_B2H_IRQ_EN(val)) {
+ if (IPMI_BT_GET_B2H_ATN(bt->control_reg) ||
+ IPMI_BT_GET_SMS_ATN(bt->control_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ IPMI_BT_SET_B2H_IRQ_EN(bt->mask_reg, 1);
+ } else {
+ if (IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ IPMI_BT_SET_B2H_IRQ_EN(bt->mask_reg, 0);
+ }
+ }
+ if (IPMI_BT_GET_B2H_IRQ(val) && IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ }
+ ipmi_unlock(s);
+}
+
+static const MemoryRegionOps ipmi_bt_io_ops = {
+ .read = ipmi_bt_ioport_read,
+ .write = ipmi_bt_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ipmi_bt_set_atn(IPMIInterface *s, int val, int irq)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (!!val == IPMI_BT_GET_SMS_ATN(bt->control_reg)) {
+ return;
+ }
+
+ IPMI_BT_SET_SMS_ATN(bt->control_reg, val);
+ if (val) {
+ if (irq && s->use_irq && s->irqs_enabled &&
+ !IPMI_BT_GET_B2H_ATN(bt->control_reg) &&
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ } else {
+ if (!IPMI_BT_GET_B2H_ATN(bt->control_reg) &&
+ IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ }
+}
+
+static int ipmi_bt_init(IPMIInterface *s)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (!s->io_base) {
+ s->io_base = 0xe4;
+ }
+ s->io_length = 3;
+
+ memory_region_init_io(&s->io, OBJECT(s), &ipmi_bt_io_ops, bt, "ipmi-bt", 3);
+
+ return 0;
+}
+
+static void ipmi_bt_class_init(ObjectClass *klass, void *data)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_CLASS(klass);
+
+ k->init = ipmi_bt_init;
+ k->smbios_type = IPMI_SMBIOS_BT;
+ k->set_atn = ipmi_bt_set_atn;
+ k->handle_rsp = ipmi_bt_handle_rsp;
+ k->handle_if_event = ipmi_bt_handle_event;
+}
+
+static const TypeInfo ipmi_bt_type = {
+ .name = TYPE_IPMI_INTERFACE_BT,
+ .parent = TYPE_IPMI_INTERFACE,
+ .instance_size = sizeof(IPMIBtInterface),
+ .class_init = ipmi_bt_class_init,
+};
+
+static void ipmi_bt_register_types(void)
+{
+ type_register_static(&ipmi_bt_type);
+}
+
+type_init(ipmi_bt_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 09/16] ipmi: Add a local BMC simulation
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (7 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 08/16] ipmi: Add a BT " Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 10/16] ipmi: Add an external connection simulation interface Corey Minyard
` (6 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This provides a minimal local BMC, basically enough to comply with the
spec and provide a complete watchdog timer (including a sensor, SDR,
and event).
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_sim.c | 1552 ++++++++++++++++++++++++++++++++++++
4 files changed, 1555 insertions(+)
create mode 100644 hw/ipmi/ipmi_sim.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index ea3a3b4..fd38dc1 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -14,6 +14,7 @@ CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
+CONFIG_IPMI_LOCAL=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 89efe84..941b08c 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -14,6 +14,7 @@ CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
+CONFIG_IPMI_LOCAL=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index a8cd463..2366160 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -2,3 +2,4 @@ common-obj-$(CONFIG_IPMI) += ipmi.o
common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
+common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
diff --git a/hw/ipmi/ipmi_sim.c b/hw/ipmi/ipmi_sim.c
new file mode 100644
index 0000000..327a01c
--- /dev/null
+++ b/hw/ipmi/ipmi_sim.c
@@ -0,0 +1,1552 @@
+/*
+ * IPMI BMC emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include "qemu/timer.h"
+#include "ipmi.h"
+
+#define IPMI_NETFN_CHASSIS 0x00
+#define IPMI_NETFN_CHASSIS_MAXCMD 0x03
+
+#define IPMI_CMD_GET_CHASSIS_CAPABILITIES 0x00
+#define IPMI_CMD_GET_CHASSIS_STATUS 0x01
+#define IPMI_CMD_CHASSIS_CONTROL 0x02
+
+#define IPMI_NETFN_SENSOR_EVENT 0x04
+#define IPMI_NETFN_SENSOR_EVENT_MAXCMD 0x2e
+
+#define IPMI_CMD_SET_SENSOR_EVT_ENABLE 0x28
+#define IPMI_CMD_GET_SENSOR_EVT_ENABLE 0x29
+#define IPMI_CMD_REARM_SENSOR_EVTS 0x2a
+#define IPMI_CMD_GET_SENSOR_EVT_STATUS 0x2b
+#define IPMI_CMD_GET_SENSOR_READING 0x2d
+
+/* #define IPMI_NETFN_APP 0x06 In ipmi.h */
+#define IPMI_NETFN_APP_MAXCMD 0x36
+
+#define IPMI_CMD_GET_DEVICE_ID 0x01
+#define IPMI_CMD_RESET_WATCHDOG_TIMER 0x22
+#define IPMI_CMD_SET_WATCHDOG_TIMER 0x24
+#define IPMI_CMD_GET_WATCHDOG_TIMER 0x25
+#define IPMI_CMD_SET_BMC_GLOBAL_ENABLES 0x2e
+#define IPMI_CMD_GET_BMC_GLOBAL_ENABLES 0x2f
+#define IPMI_CMD_CLR_MSG_FLAGS 0x30
+#define IPMI_CMD_GET_MSG_FLAGS 0x31
+#define IPMI_CMD_READ_EVT_MSG_BUF 0x35
+
+#define IPMI_NETFN_STORAGE 0x0a
+#define IPMI_NETFN_STORAGE_MAXCMD 0x4a
+
+#define IPMI_CMD_GET_SDR_REP_INFO 0x20
+#define IPMI_CMD_GET_SDR_REP_ALLOC_INFO 0x21
+#define IPMI_CMD_RESERVE_SDR_REP 0x22
+#define IPMI_CMD_GET_SDR 0x23
+#define IPMI_CMD_ADD_SDR 0x24
+#define IPMI_CMD_PARTIAL_ADD_SDR 0x25
+#define IPMI_CMD_DELETE_SDR 0x26
+#define IPMI_CMD_CLEAR_SDR_REP 0x27
+#define IPMI_CMD_GET_SDR_REP_TIME 0x28
+#define IPMI_CMD_SET_SDR_REP_TIME 0x29
+#define IPMI_CMD_ENTER_SDR_REP_UPD_MODE 0x2A
+#define IPMI_CMD_EXIT_SDR_REP_UPD_MODE 0x2B
+#define IPMI_CMD_RUN_INIT_AGENT 0x2C
+#define IPMI_CMD_GET_SEL_INFO 0x40
+#define IPMI_CMD_GET_SEL_ALLOC_INFO 0x41
+#define IPMI_CMD_RESERVE_SEL 0x42
+#define IPMI_CMD_GET_SEL_ENTRY 0x43
+#define IPMI_CMD_ADD_SEL_ENTRY 0x44
+#define IPMI_CMD_PARTIAL_ADD_SEL_ENTRY 0x45
+#define IPMI_CMD_DELETE_SEL_ENTRY 0x46
+#define IPMI_CMD_CLEAR_SEL 0x47
+#define IPMI_CMD_GET_SEL_TIME 0x48
+#define IPMI_CMD_SET_SEL_TIME 0x49
+
+
+/* Same as a timespec struct. */
+struct ipmi_time {
+ long tv_sec;
+ long tv_nsec;
+};
+
+#define MAX_SEL_SIZE 128
+
+typedef struct IPMISel {
+ uint8_t sel[MAX_SEL_SIZE][16];
+ unsigned int next_free;
+ long time_offset;
+ uint16_t reservation;
+ uint8_t last_addition[4];
+ uint8_t last_clear[4];
+ uint8_t overflow;
+} IPMISel;
+
+#define MAX_SDR_SIZE 16384
+
+typedef struct IPMISdr {
+ uint8_t sdr[MAX_SDR_SIZE];
+ unsigned int next_free;
+ uint16_t next_rec_id;
+ uint16_t reservation;
+ uint8_t last_addition[4];
+ uint8_t last_clear[4];
+ uint8_t overflow;
+} IPMISdr;
+
+typedef struct IPMISensor {
+ uint8_t status;
+ uint8_t reading;
+ uint16_t states_suppt;
+ uint16_t assert_suppt;
+ uint16_t deassert_suppt;
+ uint16_t states;
+ uint16_t assert_states;
+ uint16_t deassert_states;
+ uint16_t assert_enable;
+ uint16_t deassert_enable;
+ uint8_t sensor_type;
+ uint8_t evt_reading_type_code;
+} IPMISensor;
+#define IPMI_SENSOR_GET_PRESENT(s) ((s)->status & 0x01)
+#define IPMI_SENSOR_SET_PRESENT(s, v) ((s)->status = (s->status & ~0x01) | \
+ !!(v))
+#define IPMI_SENSOR_GET_SCAN_ON(s) ((s)->status & 0x40)
+#define IPMI_SENSOR_SET_SCAN_ON(s, v) ((s)->status = (s->status & ~0x40) | \
+ ((!!(v)) << 6))
+#define IPMI_SENSOR_GET_EVENTS_ON(s) ((s)->status & 0x80)
+#define IPMI_SENSOR_SET_EVENTS_ON(s, v) ((s)->status = (s->status & ~0x80) | \
+ ((!!(v)) << 7))
+#define IPMI_SENSOR_GET_RET_STATUS(s) ((s)->status & 0xc0)
+#define IPMI_SENSOR_SET_RET_STATUS(s, v) ((s)->status = (s->status & ~0xc0) | \
+ (v & 0xc0))
+#define IPMI_SENSOR_IS_DISCRETE(s) ((s)->evt_reading_type_code != 1)
+
+#define MAX_SENSORS 20
+#define IPMI_WATCHDOG_SENSOR 0
+
+typedef struct IPMISimBmc IPMISimBmc;
+
+#define MAX_NETFNS 64
+typedef void (*IPMICmdHandler)(IPMISimBmc *s,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len);
+typedef struct IPMINetfn {
+ unsigned int cmd_nums;
+ const IPMICmdHandler *cmd_handlers;
+} IPMINetfn;
+
+#define IPMI_BMC_SIMULATOR(obj) OBJECT_CHECK(IPMISimBmc, (obj), \
+ TYPE_IPMI_BMC_SIMULATOR)
+struct IPMISimBmc {
+ IPMIBmc parent;
+
+ QEMUTimer *timer;
+
+ uint8_t bmc_global_enables;
+ uint8_t msg_flags;
+
+ bool watchdog_initialized;
+ uint8_t watchdog_use;
+ uint8_t watchdog_action;
+ uint8_t watchdog_pretimeout; /* In seconds */
+ bool watchdog_expired;
+ uint16_t watchdog_timeout; /* in 100's of milliseconds */
+
+ bool watchdog_running;
+ bool watchdog_preaction_ran;
+ int64_t watchdog_expiry;
+
+ uint8_t device_id;
+ uint8_t ipmi_version;
+ uint8_t device_rev;
+ uint8_t fwrev1;
+ uint8_t fwrev2;
+ uint8_t mfg_id[3];
+ uint8_t product_id[2];
+
+ IPMISel sel;
+ IPMISdr sdr;
+ IPMISensor sensors[MAX_SENSORS];
+
+ /* Odd netfns are for responses, so we only need the even ones. */
+ const IPMINetfn * netfns[MAX_NETFNS / 2];
+
+ /* We allow one event in the buffer */
+ uint8_t evtbuf[16];
+};
+
+#define IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK (1 << 3)
+#define IPMI_BMC_MSG_FLAG_EVT_BUF_FULL (1 << 1)
+#define IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE (1 << 0)
+#define IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK_SET(s) \
+ (IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK & (s)->msg_flags)
+#define IPMI_BMC_MSG_FLAG_EVT_BUF_FULL_SET(s) \
+ (IPMI_BMC_MSG_FLAG_EVT_BUF_FULL & (s)->msg_flags)
+#define IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE_SET(s) \
+ (IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE & (s)->msg_flags)
+
+#define IPMI_BMC_RCV_MSG_QUEUE_INT_BIT 0
+#define IPMI_BMC_EVBUF_FULL_INT_BIT 1
+#define IPMI_BMC_EVENT_MSG_BUF_BIT 2
+#define IPMI_BMC_EVENT_LOG_BIT 3
+#define IPMI_BMC_MSG_INTS_ON(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_RCV_MSG_QUEUE_INT_BIT))
+#define IPMI_BMC_EVBUF_FULL_INT_ENABLED(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_EVBUF_FULL_INT_BIT))
+#define IPMI_BMC_EVENT_LOG_ENABLED(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_EVENT_LOG_BIT))
+#define IPMI_BMC_EVENT_MSG_BUF_ENABLED(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_EVENT_MSG_BUF_BIT))
+
+#define IPMI_BMC_WATCHDOG_USE_MASK 0xc7
+#define IPMI_BMC_WATCHDOG_ACTION_MASK 0x77
+#define IPMI_BMC_WATCHDOG_GET_USE(s) ((s)->watchdog_use & 0x7)
+#define IPMI_BMC_WATCHDOG_GET_DONT_LOG(s) (((s)->watchdog_use >> 7) & 0x1)
+#define IPMI_BMC_WATCHDOG_GET_DONT_STOP(s) (((s)->watchdog_use >> 6) & 0x1)
+#define IPMI_BMC_WATCHDOG_GET_PRE_ACTION(s) (((s)->watchdog_action >> 4) & 0x7)
+#define IPMI_BMC_WATCHDOG_PRE_NONE 0
+#define IPMI_BMC_WATCHDOG_PRE_SMI 1
+#define IPMI_BMC_WATCHDOG_PRE_NMI 2
+#define IPMI_BMC_WATCHDOG_PRE_MSG_INT 3
+#define IPMI_BMC_WATCHDOG_GET_ACTION(s) ((s)->watchdog_action & 0x7)
+#define IPMI_BMC_WATCHDOG_ACTION_NONE 0
+#define IPMI_BMC_WATCHDOG_ACTION_RESET 1
+#define IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN 2
+#define IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE 3
+
+
+/* Add a byte to the response. */
+#define IPMI_ADD_RSP_DATA(b) \
+ do { \
+ if (*rsp_len >= max_rsp_len) { \
+ rsp[2] = IPMI_CC_REQUEST_DATA_TRUNCATED; \
+ goto out; \
+ } \
+ rsp[(*rsp_len)++] = (b); \
+ } while (0)
+
+/* Verify that the received command is a certain length. */
+#define IPMI_CHECK_CMD_LEN(l) \
+ if (cmd_len < l) { \
+ rsp[2] = IPMI_CC_REQUEST_DATA_LENGTH_INVALID; \
+ goto out; \
+ }
+
+/* Check that the reservation in the command is valid. */
+#define IPMI_CHECK_RESERVATION(off, r) \
+ do { \
+ if ((cmd[off] | (cmd[off + 1] << 8)) != r) { \
+ rsp[2] = IPMI_CC_INVALID_RESERVATION; \
+ goto out; \
+ } \
+ } while (0)
+
+
+static void ipmi_sim_handle_timeout(IPMISimBmc *ss);
+
+static void ipmi_gettime(struct ipmi_time *time)
+{
+ int64_t stime;
+
+ stime = get_clock_realtime();
+ time->tv_sec = stime / get_ticks_per_sec();
+ time->tv_nsec = stime % get_ticks_per_sec();
+}
+
+static int64_t ipmi_getmonotime(void)
+{
+ return get_clock_realtime();
+}
+
+static void ipmi_timeout(void *opaque)
+{
+ IPMISimBmc *ss = opaque;
+
+ ipmi_sim_handle_timeout(ss);
+}
+
+static void set_timestamp(IPMISimBmc *ss, uint8_t *ts)
+{
+ unsigned int val;
+ struct ipmi_time now;
+
+ ipmi_gettime(&now);
+ val = now.tv_sec + ss->sel.time_offset;
+ ts[0] = val & 0xff;
+ ts[1] = (val >> 8) & 0xff;
+ ts[2] = (val >> 16) & 0xff;
+ ts[3] = (val >> 24) & 0xff;
+}
+
+static void sdr_inc_reservation(IPMISdr *sdr)
+{
+ sdr->reservation++;
+ if (sdr->reservation == 0) {
+ sdr->reservation = 1;
+ }
+}
+
+static int sdr_add_entry(IPMISimBmc *ss, const uint8_t *entry,
+ unsigned int len, uint16_t *recid)
+{
+ if ((len < 5) || (len > 255)) {
+ return 1;
+ }
+
+ if (entry[ss->sdr.next_free + 4] != len) {
+ return 1;
+ }
+
+ if (ss->sdr.next_free + len > MAX_SDR_SIZE) {
+ ss->sdr.overflow = 1;
+ return 1;
+ }
+
+ memcpy(ss->sdr.sdr + ss->sdr.next_free, entry, len);
+ ss->sdr.sdr[ss->sdr.next_free] = ss->sdr.next_rec_id & 0xff;
+ ss->sdr.sdr[ss->sdr.next_free+1] = (ss->sdr.next_rec_id >> 8) & 0xff;
+ ss->sdr.sdr[ss->sdr.next_free+2] = 0x51; /* Conform to IPMI 1.5 spec */
+
+ if (recid) {
+ *recid = ss->sdr.next_rec_id;
+ }
+ ss->sdr.next_rec_id++;
+ set_timestamp(ss, ss->sdr.last_addition);
+ ss->sdr.next_free += len;
+ sdr_inc_reservation(&ss->sdr);
+ return 0;
+}
+
+static int sdr_find_entry(IPMISdr *sdr, uint16_t recid,
+ unsigned int *retpos, uint16_t *nextrec)
+{
+ unsigned int pos = *retpos;
+
+ while (pos < sdr->next_free) {
+ uint16_t trec = sdr->sdr[pos] | (sdr->sdr[pos + 1] << 8);
+ unsigned int nextpos = pos + sdr->sdr[pos + 4];
+
+ if (trec == recid) {
+ if (nextrec) {
+ if (nextpos >= sdr->next_free) {
+ *nextrec = 0xffff;
+ } else {
+ *nextrec = (sdr->sdr[nextpos] |
+ (sdr->sdr[nextpos + 1] << 8));
+ }
+ }
+ *retpos = pos;
+ return 0;
+ }
+ pos = nextpos;
+ }
+ return 1;
+}
+
+static void sel_inc_reservation(IPMISel *sel)
+{
+ sel->reservation++;
+ if (sel->reservation == 0) {
+ sel->reservation = 1;
+ }
+}
+
+/* Returns 1 if the SEL is full and can't hold the event. */
+static int sel_add_event(IPMISimBmc *ss, uint8_t *event)
+{
+ event[0] = 0xff;
+ event[1] = 0xff;
+ set_timestamp(ss, event + 3);
+ if (ss->sel.next_free == MAX_SEL_SIZE) {
+ ss->sel.overflow = 1;
+ return 1;
+ }
+ event[0] = ss->sel.next_free & 0xff;
+ event[1] = (ss->sel.next_free >> 8) & 0xff;
+ memcpy(ss->sel.last_addition, event + 3, 4);
+ memcpy(ss->sel.sel[ss->sel.next_free], event, 16);
+ ss->sel.next_free++;
+ sel_inc_reservation(&ss->sel);
+ return 0;
+}
+
+static int attn_irq_enabled(IPMISimBmc *s)
+{
+ return (IPMI_BMC_MSG_INTS_ON(s) && IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE_SET(s))
+ || (IPMI_BMC_EVBUF_FULL_INT_ENABLED(s) &&
+ IPMI_BMC_MSG_FLAG_EVT_BUF_FULL_SET(s));
+}
+
+static void gen_event(IPMISimBmc *ss, unsigned int sens_num, uint8_t deassert,
+ uint8_t evd1, uint8_t evd2, uint8_t evd3)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ uint8_t evt[16];
+ IPMISensor *sens = ss->sensors + sens_num;
+
+ if (!IPMI_BMC_EVENT_MSG_BUF_ENABLED(ss)) {
+ return;
+ }
+ if (!IPMI_SENSOR_GET_EVENTS_ON(sens)) {
+ return;
+ }
+
+ evt[2] = 0x2; /* System event record */
+ evt[7] = s->slave_addr;
+ evt[8] = 0;
+ evt[9] = 0x04; /* Format version */
+ evt[10] = sens->sensor_type;
+ evt[11] = sens_num;
+ evt[12] = sens->evt_reading_type_code | (!!deassert << 7);
+ evt[13] = evd1;
+ evt[14] = evd2;
+ evt[15] = evd3;
+
+ if (IPMI_BMC_EVENT_LOG_ENABLED(ss)) {
+ sel_add_event(ss, evt);
+ }
+
+ if (ss->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL) {
+ goto out;
+ }
+
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_EVT_BUF_FULL;
+ memcpy(ss->evtbuf, evt, 16);
+ if (k->set_atn &&
+ ~(ss->msg_flags & IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK)) {
+ k->set_atn(s, 1, attn_irq_enabled(ss));
+ }
+ out:
+ return;
+}
+
+static void sensor_set_discrete_bit(IPMISimBmc *ss, unsigned int sensor,
+ unsigned int bit, unsigned int val,
+ uint8_t evd1, uint8_t evd2, uint8_t evd3)
+{
+ IPMISensor *sens;
+ uint16_t mask;
+
+ if (sensor >= MAX_SENSORS) {
+ return;
+ }
+ if (bit >= 16) {
+ return;
+ }
+
+ mask = (1 << bit);
+ sens = ss->sensors + sensor;
+ if (val) {
+ sens->states |= mask & sens->states_suppt;
+ if (sens->assert_states & mask) {
+ return; /* Already asserted */
+ }
+ sens->assert_states |= mask & sens->assert_suppt;
+ if (sens->assert_enable & mask & sens->assert_states) {
+ /* Send an event on assert */
+ gen_event(ss, sensor, 0, evd1, evd2, evd3);
+ }
+ } else {
+ sens->states &= ~(mask & sens->states_suppt);
+ if (sens->deassert_states & mask) {
+ return; /* Already deasserted */
+ }
+ sens->deassert_states |= mask & sens->deassert_suppt;
+ if (sens->deassert_enable & mask & sens->deassert_states) {
+ /* Send an event on deassert */
+ gen_event(ss, sensor, 1, evd1, evd2, evd3);
+ }
+ }
+}
+
+static void ipmi_init_sensors_from_sdrs(IPMISimBmc *s)
+{
+ unsigned int i, pos;
+ IPMISensor *sens;
+
+ for (i = 0; i < MAX_SENSORS; i++) {
+ memset(s->sensors + i, 0, sizeof(*sens));
+ }
+
+ pos = 0;
+ for (i = 0; !sdr_find_entry(&s->sdr, i, &pos, NULL); i++) {
+ uint8_t *sdr = s->sdr.sdr + pos;
+ unsigned int len = sdr[4];
+
+ if (len < 20) {
+ continue;
+ }
+ if ((sdr[3] < 1) || (sdr[3] > 2)) {
+ continue; /* Not a sensor SDR we set from */
+ }
+
+ if (sdr[7] > MAX_SENSORS) {
+ continue;
+ }
+ sens = s->sensors + sdr[7];
+
+ IPMI_SENSOR_SET_PRESENT(sens, 1);
+ IPMI_SENSOR_SET_SCAN_ON(sens, (sdr[10] >> 6) & 1);
+ IPMI_SENSOR_SET_EVENTS_ON(sens, (sdr[10] >> 5) & 1);
+ sens->assert_suppt = sdr[14] | (sdr[15] << 8);
+ sens->deassert_suppt = sdr[16] | (sdr[17] << 8);
+ sens->states_suppt = sdr[18] | (sdr[19] << 8);
+ sens->sensor_type = sdr[12];
+ sens->evt_reading_type_code = sdr[13] & 0x7f;
+
+ /* Enable all the events that are supported. */
+ sens->assert_enable = sens->assert_suppt;
+ sens->deassert_enable = sens->deassert_suppt;
+ }
+}
+
+static int ipmi_register_netfn(IPMISimBmc *s, unsigned int netfn,
+ const IPMINetfn *netfnd)
+{
+ if ((netfn & 1) || (netfn > MAX_NETFNS) || (s->netfns[netfn / 2])) {
+ return -1;
+ }
+ s->netfns[netfn / 2] = netfnd;
+ return 0;
+}
+
+static void next_timeout(IPMISimBmc *ss)
+{
+ int64_t next;
+ if (ss->watchdog_running) {
+ next = ss->watchdog_expiry;
+ } else {
+ /* Wait a minute */
+ next = ipmi_getmonotime() + 60 * get_ticks_per_sec();
+ }
+ timer_mod(ss->timer, next);
+}
+
+static void ipmi_sim_handle_command(IPMIBmc *b,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id)
+{
+ IPMISimBmc *ss = IPMI_BMC_SIMULATOR(b);
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned int netfn;
+ uint8_t rsp[MAX_IPMI_MSG_SIZE];
+ unsigned int rsp_len_holder = 0;
+ unsigned int *rsp_len = &rsp_len_holder;
+ unsigned int max_rsp_len = sizeof(rsp);
+
+ /* Set up the response, set the low bit of NETFN. */
+ /* Note that max_rsp_len must be at least 3 */
+ IPMI_ADD_RSP_DATA(cmd[0] | 0x04);
+ IPMI_ADD_RSP_DATA(cmd[1]);
+ IPMI_ADD_RSP_DATA(0); /* Assume success */
+
+ /* If it's too short or it was truncated, return an error. */
+ if (cmd_len < 2) {
+ rsp[2] = IPMI_CC_REQUEST_DATA_LENGTH_INVALID;
+ goto out;
+ }
+ if (cmd_len > max_cmd_len) {
+ rsp[2] = IPMI_CC_REQUEST_DATA_TRUNCATED;
+ goto out;
+ }
+
+ if ((cmd[0] & 0x03) != 0) {
+ /* Only have stuff on LUN 0 */
+ rsp[2] = IPMI_CC_COMMAND_INVALID_FOR_LUN;
+ goto out;
+ }
+
+ netfn = cmd[0] >> 2;
+
+ /* Odd netfns are not valid, make sure the command is registered */
+ if ((netfn & 1) || !ss->netfns[netfn / 2] ||
+ (cmd[1] >= ss->netfns[netfn / 2]->cmd_nums) ||
+ (!ss->netfns[netfn / 2]->cmd_handlers[cmd[1]])) {
+ rsp[2] = IPMI_CC_INVALID_CMD;
+ goto out;
+ }
+
+ ss->netfns[netfn / 2]->cmd_handlers[cmd[1]](ss, cmd, cmd_len, rsp, rsp_len,
+ max_rsp_len);
+
+ out:
+ k->handle_rsp(s, msg_id, rsp, *rsp_len);
+
+ next_timeout(ss);
+}
+
+static void ipmi_sim_handle_timeout(IPMISimBmc *ss)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ if (!ss->watchdog_running) {
+ goto out;
+ }
+
+ if (!ss->watchdog_preaction_ran) {
+ switch (IPMI_BMC_WATCHDOG_GET_PRE_ACTION(ss)) {
+ case IPMI_BMC_WATCHDOG_PRE_NMI:
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK;
+ k->do_hw_op(s, IPMI_SEND_NMI, 0);
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 8, 1,
+ 0xc8, (2 << 4) | 0xf, 0xff);
+ break;
+
+ case IPMI_BMC_WATCHDOG_PRE_MSG_INT:
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK;
+ if (k->set_atn &&
+ !(ss->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL)) {
+ k->set_atn(s, 1, attn_irq_enabled(ss));
+ }
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 8, 1,
+ 0xc8, (3 << 4) | 0xf, 0xff);
+ break;
+
+ default:
+ goto do_full_expiry;
+ }
+
+ ss->watchdog_preaction_ran = 1;
+ /* Issued the pretimeout, do the rest of the timeout now. */
+ ss->watchdog_expiry = ipmi_getmonotime();
+ ss->watchdog_expiry += ss->watchdog_pretimeout * 1000000000LL;
+ goto out;
+ }
+
+ do_full_expiry:
+ ss->watchdog_running = 0; /* Stop the watchdog on a timeout */
+ ss->watchdog_expired |= (1 << IPMI_BMC_WATCHDOG_GET_USE(ss));
+ switch (IPMI_BMC_WATCHDOG_GET_ACTION(ss)) {
+ case IPMI_BMC_WATCHDOG_ACTION_NONE:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 0, 1,
+ 0xc0, ss->watchdog_use & 0xf, 0xff);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_RESET:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 1, 1,
+ 0xc1, ss->watchdog_use & 0xf, 0xff);
+ k->do_hw_op(s, IPMI_RESET_CHASSIS, 0);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 2, 1,
+ 0xc2, ss->watchdog_use & 0xf, 0xff);
+ k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 2, 1,
+ 0xc3, ss->watchdog_use & 0xf, 0xff);
+ k->do_hw_op(s, IPMI_POWERCYCLE_CHASSIS, 0);
+ break;
+ }
+
+ out:
+ next_timeout(ss);
+}
+
+static void chassis_capabilities(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ out:
+ return;
+}
+
+static void chassis_status(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(0x61); /* Unknown power restore, power is on */
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(0);
+ out:
+ return;
+}
+
+static void chassis_control(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ IPMI_CHECK_CMD_LEN(3);
+ switch (cmd[2] & 0xf) {
+ case 0: /* power down */
+ rsp[2] = k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0);
+ break;
+ case 1: /* power up */
+ rsp[2] = k->do_hw_op(s, IPMI_POWERON_CHASSIS, 0);
+ break;
+ case 2: /* power cycle */
+ rsp[2] = k->do_hw_op(s, IPMI_POWERCYCLE_CHASSIS, 0);
+ break;
+ case 3: /* hard reset */
+ rsp[2] = k->do_hw_op(s, IPMI_RESET_CHASSIS, 0);
+ break;
+ case 4: /* pulse diagnostic interrupt */
+ rsp[2] = k->do_hw_op(s, IPMI_PULSE_DIAG_IRQ, 0);
+ break;
+ case 5: /* soft shutdown via ACPI by overtemp emulation */
+ rsp[2] = k->do_hw_op(s,
+ IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP, 0);
+ break;
+ default:
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_device_id(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->device_id);
+ IPMI_ADD_RSP_DATA(ss->device_rev & 0xf);
+ IPMI_ADD_RSP_DATA(ss->fwrev1 & 0x7f);
+ IPMI_ADD_RSP_DATA(ss->fwrev2);
+ IPMI_ADD_RSP_DATA(ss->ipmi_version);
+ IPMI_ADD_RSP_DATA(0x07); /* sensor, SDR, and SEL. */
+ IPMI_ADD_RSP_DATA(ss->mfg_id[0]);
+ IPMI_ADD_RSP_DATA(ss->mfg_id[1]);
+ IPMI_ADD_RSP_DATA(ss->mfg_id[2]);
+ IPMI_ADD_RSP_DATA(ss->product_id[0]);
+ IPMI_ADD_RSP_DATA(ss->product_id[1]);
+ out:
+ return;
+}
+
+static void set_bmc_global_enables(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ uint8_t old_val = ss->bmc_global_enables;
+
+ IPMI_CHECK_CMD_LEN(3);
+ ss->bmc_global_enables = cmd[2];
+ if ((old_val & (1 << IPMI_BMC_RCV_MSG_QUEUE_INT_BIT))
+ != (cmd[2] & (1 << IPMI_BMC_RCV_MSG_QUEUE_INT_BIT))) {
+ k->set_irq_enable(s,
+ !!(cmd[2] & (1 << IPMI_BMC_RCV_MSG_QUEUE_INT_BIT)));
+ }
+ out:
+ return;
+}
+
+static void get_bmc_global_enables(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->bmc_global_enables);
+ out:
+ return;
+}
+
+static void clr_msg_flags(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ IPMI_CHECK_CMD_LEN(3);
+ if (cmd[2] & IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK) {
+ if (k->set_atn &&
+ !(ss->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL)) {
+ k->set_atn(s, 0, attn_irq_enabled(ss));
+ }
+ }
+ ss->msg_flags &= ~cmd[2];
+ out:
+ return;
+}
+
+static void get_msg_flags(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->msg_flags);
+ out:
+ return;
+}
+
+static void read_evt_msg_buf(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned int i;
+
+ if (!(ss->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL)) {
+ rsp[2] = 0x80;
+ goto out;
+ }
+ for (i = 0; i < 16; i++) {
+ IPMI_ADD_RSP_DATA(ss->evtbuf[i]);
+ }
+ ss->msg_flags &= ~IPMI_BMC_MSG_FLAG_EVT_BUF_FULL;
+ if (k->set_atn &&
+ ~(ss->msg_flags & IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK)) {
+ k->set_atn(s, 0, attn_irq_enabled(ss));
+ }
+ out:
+ return;
+}
+
+static void do_watchdog_reset(IPMISimBmc *ss)
+{
+ if (IPMI_BMC_WATCHDOG_GET_ACTION(ss) ==
+ IPMI_BMC_WATCHDOG_ACTION_NONE) {
+ ss->watchdog_running = 0;
+ return;
+ }
+ ss->watchdog_preaction_ran = 0;
+
+
+ /* Timeout is in tenths of a second, offset is in seconds */
+ ss->watchdog_expiry = ipmi_getmonotime();
+ ss->watchdog_expiry += ss->watchdog_timeout * 100000000LL;
+ if (IPMI_BMC_WATCHDOG_GET_PRE_ACTION(ss) != IPMI_BMC_WATCHDOG_PRE_NONE) {
+ ss->watchdog_expiry -= ss->watchdog_pretimeout * 1000000000LL;
+ }
+ ss->watchdog_running = 1;
+}
+
+static void reset_watchdog_timer(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ if (!ss->watchdog_initialized) {
+ rsp[2] = 0x80;
+ goto out;
+ }
+ do_watchdog_reset(ss);
+ out:
+ return;
+}
+
+static void set_watchdog_timer(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned int val;
+
+ IPMI_CHECK_CMD_LEN(8);
+ val = cmd[2] & 0x7; /* Validate use */
+ if (val == 0 || val > 5) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ val = cmd[3] & 0x7; /* Validate action */
+ switch (val) {
+ case IPMI_BMC_WATCHDOG_ACTION_NONE:
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_RESET:
+ rsp[2] = k->do_hw_op(s, IPMI_RESET_CHASSIS, 1);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN:
+ rsp[2] = k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 1);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE:
+ rsp[2] = k->do_hw_op(s, IPMI_POWERCYCLE_CHASSIS, 1);
+ break;
+
+ default:
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ }
+ if (rsp[2]) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+
+ val = (cmd[3] >> 4) & 0x7; /* Validate preaction */
+ switch (val) {
+ case IPMI_BMC_WATCHDOG_PRE_MSG_INT:
+ case IPMI_BMC_WATCHDOG_PRE_NONE:
+ break;
+
+ case IPMI_BMC_WATCHDOG_PRE_NMI:
+ if (!k->do_hw_op(s, IPMI_SEND_NMI, 1)) {
+ /* NMI not supported. */
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ default:
+ /* We don't support PRE_SMI */
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+
+ ss->watchdog_initialized = 1;
+ ss->watchdog_use = cmd[2] & IPMI_BMC_WATCHDOG_USE_MASK;
+ ss->watchdog_action = cmd[3] & IPMI_BMC_WATCHDOG_ACTION_MASK;
+ ss->watchdog_pretimeout = cmd[4];
+ ss->watchdog_expired &= ~cmd[5];
+ ss->watchdog_timeout = cmd[6] | (((uint16_t) cmd[7]) << 8);
+ if (ss->watchdog_running & IPMI_BMC_WATCHDOG_GET_DONT_STOP(ss)) {
+ do_watchdog_reset(ss);
+ } else {
+ ss->watchdog_running = 0;
+ }
+ out:
+ return;
+}
+
+static void get_watchdog_timer(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->watchdog_use);
+ IPMI_ADD_RSP_DATA(ss->watchdog_action);
+ IPMI_ADD_RSP_DATA(ss->watchdog_pretimeout);
+ IPMI_ADD_RSP_DATA(ss->watchdog_expired);
+ if (ss->watchdog_running) {
+ long timeout;
+ timeout = ((ss->watchdog_expiry - ipmi_getmonotime() + 50000000)
+ / 100000000);
+ IPMI_ADD_RSP_DATA(timeout & 0xff);
+ IPMI_ADD_RSP_DATA((timeout >> 8) & 0xff);
+ } else {
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(0);
+ }
+ out:
+ return;
+}
+
+static void get_sdr_rep_info(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int i;
+
+ IPMI_ADD_RSP_DATA(0x51); /* Conform to IPMI 1.5 spec */
+ IPMI_ADD_RSP_DATA(ss->sdr.next_rec_id & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sdr.next_rec_id >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA((MAX_SDR_SIZE - ss->sdr.next_free) & 0xff);
+ IPMI_ADD_RSP_DATA(((MAX_SDR_SIZE - ss->sdr.next_free) >> 8) & 0xff);
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sdr.last_addition[i]);
+ }
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sdr.last_clear[i]);
+ }
+ /* Only modal support, reserve supported */
+ IPMI_ADD_RSP_DATA((ss->sdr.overflow << 7) | 0x22);
+ out:
+ return;
+}
+
+static void reserve_sdr_rep(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->sdr.reservation & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sdr.reservation >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void get_sdr(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int pos;
+ uint16_t nextrec;
+
+ IPMI_CHECK_CMD_LEN(8);
+ if (cmd[6]) {
+ IPMI_CHECK_RESERVATION(2, ss->sdr.reservation);
+ }
+ pos = 0;
+ if (sdr_find_entry(&ss->sdr, cmd[4] | (cmd[5] << 8),
+ &pos, &nextrec)) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ if (cmd[6] > (ss->sdr.sdr[pos + 4])) {
+ rsp[2] = IPMI_CC_PARM_OUT_OF_RANGE;
+ goto out;
+ }
+
+ IPMI_ADD_RSP_DATA(nextrec & 0xff);
+ IPMI_ADD_RSP_DATA((nextrec >> 8) & 0xff);
+
+ if (cmd[7] == 0xff) {
+ cmd[7] = ss->sdr.sdr[pos + 4] - cmd[6];
+ }
+
+ if ((cmd[7] + *rsp_len) > max_rsp_len) {
+ rsp[2] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
+ goto out;
+ }
+ memcpy(rsp + *rsp_len, ss->sdr.sdr + pos + cmd[6], cmd[7]);
+ *rsp_len += cmd[7];
+ out:
+ return;
+}
+
+static void add_sdr(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ uint16_t recid;
+
+ if (sdr_add_entry(ss, cmd + 2, cmd_len - 2, &recid)) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ IPMI_ADD_RSP_DATA(recid & 0xff);
+ IPMI_ADD_RSP_DATA((recid >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void clear_sdr_rep(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(8);
+ IPMI_CHECK_RESERVATION(2, ss->sdr.reservation);
+ if (cmd[4] != 'C' || cmd[5] != 'L' || cmd[6] != 'R') {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ if (cmd[7] == 0xaa) {
+ ss->sdr.next_free = 0;
+ ss->sdr.overflow = 0;
+ set_timestamp(ss, ss->sdr.last_clear);
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ sdr_inc_reservation(&ss->sdr);
+ } else if (cmd[7] == 0) {
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ } else {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_sel_info(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int i, val;
+
+ IPMI_ADD_RSP_DATA(0x51); /* Conform to IPMI 1.5 */
+ IPMI_ADD_RSP_DATA(ss->sel.next_free & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sel.next_free >> 8) & 0xff);
+ val = (MAX_SEL_SIZE - ss->sel.next_free) * 16;
+ IPMI_ADD_RSP_DATA(val & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 8) & 0xff);
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sel.last_addition[i]);
+ }
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sel.last_clear[i]);
+ }
+ /* Only support Reserve SEL */
+ IPMI_ADD_RSP_DATA((ss->sel.overflow << 7) | 0x02);
+ out:
+ return;
+}
+
+static void reserve_sel(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->sel.reservation & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sel.reservation >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void get_sel_entry(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int val;
+
+ IPMI_CHECK_CMD_LEN(8);
+ if (cmd[6]) {
+ IPMI_CHECK_RESERVATION(2, ss->sel.reservation);
+ }
+ if (ss->sel.next_free == 0) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ if (cmd[6] > 15) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ if (cmd[7] == 0xff) {
+ cmd[7] = 16;
+ } else if ((cmd[7] + cmd[6]) > 16) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ } else {
+ cmd[7] += cmd[6];
+ }
+
+ val = cmd[4] | (cmd[5] << 8);
+ if (val == 0xffff) {
+ val = ss->sel.next_free - 1;
+ } else if (val >= ss->sel.next_free) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ if ((val + 1) == ss->sel.next_free) {
+ IPMI_ADD_RSP_DATA(0xff);
+ IPMI_ADD_RSP_DATA(0xff);
+ } else {
+ IPMI_ADD_RSP_DATA((val + 1) & 0xff);
+ IPMI_ADD_RSP_DATA(((val + 1) >> 8) & 0xff);
+ }
+ for (; cmd[6] < cmd[7]; cmd[6]++) {
+ IPMI_ADD_RSP_DATA(ss->sel.sel[val][cmd[6]]);
+ }
+ out:
+ return;
+}
+
+static void add_sel_entry(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(18);
+ if (sel_add_event(ss, cmd + 2)) {
+ rsp[2] = IPMI_CC_OUT_OF_SPACE;
+ goto out;
+ }
+ /* sel_add_event fills in the record number. */
+ IPMI_ADD_RSP_DATA(cmd[2]);
+ IPMI_ADD_RSP_DATA(cmd[3]);
+ out:
+ return;
+}
+
+static void clear_sel(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(8);
+ IPMI_CHECK_RESERVATION(2, ss->sel.reservation);
+ if (cmd[4] != 'C' || cmd[5] != 'L' || cmd[6] != 'R') {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ if (cmd[7] == 0xaa) {
+ ss->sel.next_free = 0;
+ ss->sel.overflow = 0;
+ set_timestamp(ss, ss->sdr.last_clear);
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ sel_inc_reservation(&ss->sel);
+ } else if (cmd[7] == 0) {
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ } else {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_sel_time(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ uint32_t val;
+ struct ipmi_time now;
+
+ ipmi_gettime(&now);
+ val = now.tv_sec + ss->sel.time_offset;
+ IPMI_ADD_RSP_DATA(val & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 16) & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 24) & 0xff);
+ out:
+ return;
+}
+
+static void set_sel_time(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ uint32_t val;
+ struct ipmi_time now;
+
+ IPMI_CHECK_CMD_LEN(6);
+ val = cmd[2] | (cmd[3] << 8) | (cmd[4] << 16) | (cmd[5] << 24);
+ ipmi_gettime(&now);
+ ss->sel.time_offset = now.tv_sec - ((long) val);
+ out:
+ return;
+}
+
+static void set_sensor_evt_enable(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(4);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ switch ((cmd[3] >> 4) & 0x3) {
+ case 0: /* Do not change */
+ break;
+ case 1: /* Enable bits */
+ if (cmd_len > 4) {
+ sens->assert_enable |= cmd[4];
+ }
+ if (cmd_len > 5) {
+ sens->assert_enable |= cmd[5] << 8;
+ }
+ if (cmd_len > 6) {
+ sens->deassert_enable |= cmd[6];
+ }
+ if (cmd_len > 7) {
+ sens->deassert_enable |= cmd[7] << 8;
+ }
+ break;
+ case 2: /* Disable bits */
+ if (cmd_len > 4) {
+ sens->assert_enable &= ~cmd[4];
+ }
+ if (cmd_len > 5) {
+ sens->assert_enable &= ~(cmd[5] << 8);
+ }
+ if (cmd_len > 6) {
+ sens->deassert_enable &= ~cmd[6];
+ }
+ if (cmd_len > 7) {
+ sens->deassert_enable &= ~(cmd[7] << 8);
+ }
+ break;
+ case 3:
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ IPMI_SENSOR_SET_RET_STATUS(sens, cmd[3]);
+ out:
+ return;
+}
+
+static void get_sensor_evt_enable(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(3);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ IPMI_ADD_RSP_DATA(IPMI_SENSOR_GET_RET_STATUS(sens));
+ IPMI_ADD_RSP_DATA(sens->assert_enable & 0xff);
+ IPMI_ADD_RSP_DATA((sens->assert_enable >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA(sens->deassert_enable & 0xff);
+ IPMI_ADD_RSP_DATA((sens->deassert_enable >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void rearm_sensor_evts(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(4);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+
+ if ((cmd[3] & 0x80) == 0) {
+ /* Just clear everything */
+ sens->states = 0;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_sensor_evt_status(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(3);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ IPMI_ADD_RSP_DATA(sens->reading);
+ IPMI_ADD_RSP_DATA(IPMI_SENSOR_GET_RET_STATUS(sens));
+ IPMI_ADD_RSP_DATA(sens->assert_states & 0xff);
+ IPMI_ADD_RSP_DATA((sens->assert_states >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA(sens->deassert_states & 0xff);
+ IPMI_ADD_RSP_DATA((sens->deassert_states >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void get_sensor_reading(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(3);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ IPMI_ADD_RSP_DATA(sens->reading);
+ IPMI_ADD_RSP_DATA(IPMI_SENSOR_GET_RET_STATUS(sens));
+ IPMI_ADD_RSP_DATA(sens->states & 0xff);
+ if (IPMI_SENSOR_IS_DISCRETE(sens)) {
+ IPMI_ADD_RSP_DATA((sens->states >> 8) & 0xff);
+ }
+ out:
+ return;
+}
+
+static const IPMICmdHandler chassis_cmds[IPMI_NETFN_CHASSIS_MAXCMD] = {
+ [IPMI_CMD_GET_CHASSIS_CAPABILITIES] = chassis_capabilities,
+ [IPMI_CMD_GET_CHASSIS_STATUS] = chassis_status,
+ [IPMI_CMD_CHASSIS_CONTROL] = chassis_control
+};
+static const IPMINetfn chassis_netfn = {
+ .cmd_nums = IPMI_NETFN_CHASSIS_MAXCMD,
+ .cmd_handlers = chassis_cmds
+};
+
+static const IPMICmdHandler
+sensor_event_cmds[IPMI_NETFN_SENSOR_EVENT_MAXCMD] = {
+ [IPMI_CMD_SET_SENSOR_EVT_ENABLE] = set_sensor_evt_enable,
+ [IPMI_CMD_GET_SENSOR_EVT_ENABLE] = get_sensor_evt_enable,
+ [IPMI_CMD_REARM_SENSOR_EVTS] = rearm_sensor_evts,
+ [IPMI_CMD_GET_SENSOR_EVT_STATUS] = get_sensor_evt_status,
+ [IPMI_CMD_GET_SENSOR_READING] = get_sensor_reading
+};
+static const IPMINetfn sensor_event_netfn = {
+ .cmd_nums = IPMI_NETFN_SENSOR_EVENT_MAXCMD,
+ .cmd_handlers = sensor_event_cmds
+};
+
+static const IPMICmdHandler app_cmds[IPMI_NETFN_APP_MAXCMD] = {
+ [IPMI_CMD_GET_DEVICE_ID] = get_device_id,
+ [IPMI_CMD_SET_BMC_GLOBAL_ENABLES] = set_bmc_global_enables,
+ [IPMI_CMD_GET_BMC_GLOBAL_ENABLES] = get_bmc_global_enables,
+ [IPMI_CMD_CLR_MSG_FLAGS] = clr_msg_flags,
+ [IPMI_CMD_GET_MSG_FLAGS] = get_msg_flags,
+ [IPMI_CMD_READ_EVT_MSG_BUF] = read_evt_msg_buf,
+ [IPMI_CMD_RESET_WATCHDOG_TIMER] = reset_watchdog_timer,
+ [IPMI_CMD_SET_WATCHDOG_TIMER] = set_watchdog_timer,
+ [IPMI_CMD_GET_WATCHDOG_TIMER] = get_watchdog_timer,
+};
+static const IPMINetfn app_netfn = {
+ .cmd_nums = IPMI_NETFN_APP_MAXCMD,
+ .cmd_handlers = app_cmds
+};
+
+static const IPMICmdHandler storage_cmds[IPMI_NETFN_STORAGE_MAXCMD] = {
+ [IPMI_CMD_GET_SDR_REP_INFO] = get_sdr_rep_info,
+ [IPMI_CMD_RESERVE_SDR_REP] = reserve_sdr_rep,
+ [IPMI_CMD_GET_SDR] = get_sdr,
+ [IPMI_CMD_ADD_SDR] = add_sdr,
+ [IPMI_CMD_CLEAR_SDR_REP] = clear_sdr_rep,
+ [IPMI_CMD_GET_SEL_INFO] = get_sel_info,
+ [IPMI_CMD_RESERVE_SEL] = reserve_sel,
+ [IPMI_CMD_GET_SEL_ENTRY] = get_sel_entry,
+ [IPMI_CMD_ADD_SEL_ENTRY] = add_sel_entry,
+ [IPMI_CMD_CLEAR_SEL] = clear_sel,
+ [IPMI_CMD_GET_SEL_TIME] = get_sel_time,
+ [IPMI_CMD_SET_SEL_TIME] = set_sel_time,
+};
+
+static const IPMINetfn storage_netfn = {
+ .cmd_nums = IPMI_NETFN_STORAGE_MAXCMD,
+ .cmd_handlers = storage_cmds
+};
+
+static void register_cmds(IPMISimBmc *s)
+{
+ ipmi_register_netfn(s, IPMI_NETFN_CHASSIS, &chassis_netfn);
+ ipmi_register_netfn(s, IPMI_NETFN_SENSOR_EVENT, &sensor_event_netfn);
+ ipmi_register_netfn(s, IPMI_NETFN_APP, &app_netfn);
+ ipmi_register_netfn(s, IPMI_NETFN_STORAGE, &storage_netfn);
+}
+
+static const uint8_t init_sdrs[] = {
+ /* Watchdog device */
+ 0x00, 0x00, 0x51, 0x02, 40, 0x20, 0x00, 0x00,
+ 0x23, 0x01, 0x63, 0x00, 0x23, 0x6f, 0x0f, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
+ 'W', 'a', 't', 'c', 'h', 'd', 'o', 'g',
+ /* End */
+ 0xff, 0xff, 0x00, 0x00, 0x00
+};
+
+static int ipmi_sim_init(IPMIBmc *b)
+{
+ unsigned int i;
+ unsigned int next_recid, recid;
+ IPMISimBmc *ss = IPMI_BMC_SIMULATOR(b);
+
+ ss->bmc_global_enables = (1 << IPMI_BMC_EVENT_LOG_BIT);
+ ss->device_id = 0x20;
+ ss->ipmi_version = 0x02; /* IPMI 2.0 */
+ for (i = 0; i < 4; i++) {
+ ss->sel.last_addition[i] = 0xff;
+ ss->sel.last_clear[i] = 0xff;
+ ss->sdr.last_addition[i] = 0xff;
+ ss->sdr.last_clear[i] = 0xff;
+ }
+
+ next_recid = 0;
+ for (i = 0;;) {
+ int len;
+ if ((i + 5) > sizeof(init_sdrs)) {
+ ipmi_debug("Problem with recid 0x%4.4x\n", i);
+ return 1;
+ }
+ len = init_sdrs[i + 4];
+ recid = init_sdrs[i] | (init_sdrs[i + 1] << 8);
+ if (recid == 0xffff) {
+ break;
+ }
+ if ((i + len) > sizeof(init_sdrs)) {
+ ipmi_debug("Problem with recid 0x%4.4x\n", i);
+ return 1;
+ }
+ if (recid != next_recid) {
+ ipmi_debug("Problem with recid 0x%4.4x\n", i);
+ return 1;
+ }
+ sdr_add_entry(ss, init_sdrs + i, len, NULL);
+ i += len;
+ }
+
+ ipmi_init_sensors_from_sdrs(ss);
+ register_cmds(ss);
+
+ ss->timer = timer_new(QEMU_CLOCK_VIRTUAL, SCALE_NS, ipmi_timeout, ss);
+
+ return 0;
+}
+
+static void ipmi_sim_class_init(ObjectClass *klass, void *data)
+{
+ IPMIBmcClass *bk = IPMI_BMC_CLASS(klass);
+
+ bk->init = ipmi_sim_init;
+ bk->handle_command = ipmi_sim_handle_command;
+}
+
+static const TypeInfo ipmi_sim_type = {
+ .name = TYPE_IPMI_BMC_SIMULATOR,
+ .parent = TYPE_IPMI_BMC,
+ .instance_size = sizeof(IPMISimBmc),
+ .class_init = ipmi_sim_class_init,
+};
+
+static void ipmi_sim_register_types(void)
+{
+ type_register_static(&ipmi_sim_type);
+}
+
+type_init(ipmi_sim_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 10/16] ipmi: Add an external connection simulation interface
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (8 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 09/16] ipmi: Add a local BMC simulation Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 11/16] ipmi: Add tests Corey Minyard
` (5 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
This adds an interface for IPMI that connects to a remote
BMC over a chardev (generally a TCP socket). The OpenIPMI
lanserv simulator describes this interface, see that for
interface details.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_extern.c | 476 +++++++++++++++++++++++++++++++++++++
4 files changed, 479 insertions(+)
create mode 100644 hw/ipmi/ipmi_extern.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index fd38dc1..fffeeca 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -15,6 +15,7 @@ CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
CONFIG_IPMI_LOCAL=y
+CONFIG_IPMI_EXTERN=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 941b08c..bf9454b 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -15,6 +15,7 @@ CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
CONFIG_IPMI_LOCAL=y
+CONFIG_IPMI_EXTERN=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 2366160..9dd05a8 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -3,3 +3,4 @@ common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
+common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_extern.o
diff --git a/hw/ipmi/ipmi_extern.c b/hw/ipmi/ipmi_extern.c
new file mode 100644
index 0000000..1cd7c11
--- /dev/null
+++ b/hw/ipmi/ipmi_extern.c
@@ -0,0 +1,476 @@
+/*
+ * IPMI BMC external connection
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * This is designed to connect with OpenIPMI's lanserv serial interface
+ * using the "VM" connection type. See that for details.
+ */
+
+#include <stdint.h>
+#include "qemu/timer.h"
+#include "sysemu/char.h"
+#include "ipmi.h"
+
+#define VM_MSG_CHAR 0xA0 /* Marks end of message */
+#define VM_CMD_CHAR 0xA1 /* Marks end of a command */
+#define VM_ESCAPE_CHAR 0xAA /* Set bit 4 from the next byte to 0 */
+
+#define VM_PROTOCOL_VERSION 1
+#define VM_CMD_VERSION 0xff /* A version number byte follows */
+#define VM_CMD_NOATTN 0x00
+#define VM_CMD_ATTN 0x01
+#define VM_CMD_ATTN_IRQ 0x02
+#define VM_CMD_POWEROFF 0x03
+#define VM_CMD_RESET 0x04
+#define VM_CMD_ENABLE_IRQ 0x05 /* Enable/disable the messaging irq */
+#define VM_CMD_DISABLE_IRQ 0x06
+#define VM_CMD_SEND_NMI 0x07
+#define VM_CMD_CAPABILITIES 0x08
+#define VM_CAPABILITIES_POWER 0x01
+#define VM_CAPABILITIES_RESET 0x02
+#define VM_CAPABILITIES_IRQ 0x04
+#define VM_CAPABILITIES_NMI 0x08
+#define VM_CAPABILITIES_ATTN 0x10
+
+#define IPMI_BMC_EXTERN(obj) OBJECT_CHECK(IPMIExternBmc, (obj), \
+ TYPE_IPMI_BMC_EXTERN)
+typedef struct IPMIExternBmc {
+ IPMIBmc parent;
+
+ int connected;
+ int is_listen;
+
+ unsigned char inbuf[MAX_IPMI_MSG_SIZE + 2];
+ unsigned int inpos;
+ int in_escape;
+ int in_too_many;
+ int waiting_rsp;
+ int sending_cmd;
+
+ unsigned char outbuf[(MAX_IPMI_MSG_SIZE + 2) * 2 + 1];
+ unsigned int outpos;
+ unsigned int outlen;
+
+ struct QEMUTimer *extern_timer;
+
+ /* A reset event is pending to be sent upstream. */
+ bool send_reset;
+} IPMIExternBmc;
+
+static int can_receive(void *opaque);
+static void receive(void *opaque, const uint8_t *buf, int size);
+static void chr_event(void *opaque, int event);
+
+static unsigned char
+ipmb_checksum(const unsigned char *data, int size, unsigned char start)
+{
+ unsigned char csum = start;
+
+ for (; size > 0; size--, data++) {
+ csum += *data;
+ }
+ return csum;
+}
+
+static void continue_send(IPMIExternBmc *es)
+{
+ if (es->outlen == 0) {
+ goto check_reset;
+ }
+ send:
+ es->outpos += qemu_chr_fe_write(es->parent.chr, es->outbuf + es->outpos,
+ es->outlen - es->outpos);
+ if (es->outpos < es->outlen) {
+ /* Not fully transmitted, try again in a 10ms */
+ timer_mod(es->extern_timer,
+ get_clock() + get_ticks_per_sec() / 100);
+ } else {
+ /* Sent */
+ es->outlen = 0;
+ es->outpos = 0;
+ if (!es->sending_cmd) {
+ es->waiting_rsp = 1;
+ } else {
+ es->sending_cmd = 0;
+ }
+ check_reset:
+ if (es->connected && es->send_reset) {
+ /* Send the reset */
+ es->outbuf[0] = VM_CMD_RESET;
+ es->outbuf[1] = VM_CMD_CHAR;
+ es->outlen = 2;
+ es->outpos = 0;
+ es->send_reset = 0;
+ es->sending_cmd = 1;
+ goto send;
+ }
+
+ if (es->waiting_rsp) {
+ /* Make sure we get a response within 4 seconds. */
+ timer_mod(es->extern_timer,
+ get_clock() + (4 * get_ticks_per_sec()));
+ }
+ }
+ return;
+}
+
+static void extern_timeout(void *opaque)
+{
+ IPMIExternBmc *es = opaque;
+ IPMIInterface *s = es->parent.intf;
+
+ ipmi_lock(s);
+ if (es->connected) {
+ if (es->waiting_rsp && (es->outlen == 0)) {
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ /* The message response timed out, return an error. */
+ es->waiting_rsp = 0;
+ es->inbuf[1] = es->outbuf[1] | 0x04;
+ es->inbuf[2] = es->outbuf[2];
+ es->inbuf[3] = IPMI_CC_TIMEOUT;
+ k->handle_rsp(s, es->outbuf[0], es->inbuf + 1, 3);
+ } else {
+ continue_send(es);
+ }
+ }
+ ipmi_unlock(s);
+}
+
+static void addchar(IPMIExternBmc *es, unsigned char ch)
+{
+ switch (ch) {
+ case VM_MSG_CHAR:
+ case VM_CMD_CHAR:
+ case VM_ESCAPE_CHAR:
+ es->outbuf[es->outlen] = VM_ESCAPE_CHAR;
+ es->outlen++;
+ ch |= 0x10;
+ /* No break */
+
+ default:
+ es->outbuf[es->outlen] = ch;
+ es->outlen++;
+ }
+}
+
+static void ipmi_extern_handle_command(IPMIBmc *b,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id)
+{
+ IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
+ IPMIInterface *s = es->parent.intf;
+ uint8_t err = 0, csum;
+ unsigned int i;
+
+ ipmi_lock(s);
+ if (es->outlen) {
+ /* We already have a command queued. Shouldn't ever happen. */
+ fprintf(stderr, "IPMI KCS: Got command when not finished with the"
+ " previous commmand\n");
+ abort();
+ }
+
+ /* If it's too short or it was truncated, return an error. */
+ if (cmd_len < 2) {
+ err = IPMI_CC_REQUEST_DATA_LENGTH_INVALID;
+ } else if ((cmd_len > max_cmd_len) || (cmd_len > MAX_IPMI_MSG_SIZE)) {
+ err = IPMI_CC_REQUEST_DATA_TRUNCATED;
+ } else if (!es->connected) {
+ err = IPMI_CC_BMC_INIT_IN_PROGRESS;
+ }
+ if (err) {
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned char rsp[3];
+ rsp[0] = cmd[0] | 0x04;
+ rsp[1] = cmd[1];
+ rsp[2] = err;
+ es->waiting_rsp = 0;
+ k->handle_rsp(s, msg_id, rsp, 3);
+ goto out;
+ }
+
+ addchar(es, msg_id);
+ for (i = 0; i < cmd_len; i++) {
+ addchar(es, cmd[i]);
+ }
+ csum = ipmb_checksum(&msg_id, 1, 0);
+ addchar(es, -ipmb_checksum(cmd, cmd_len, csum));
+
+ es->outbuf[es->outlen] = VM_MSG_CHAR;
+ es->outlen++;
+
+ /* Start the transmit */
+ continue_send(es);
+
+ out:
+ ipmi_unlock(s);
+ return;
+}
+
+static void handle_hw_op(IPMIExternBmc *es, unsigned char hw_op)
+{
+ IPMIInterface *s = es->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ switch (hw_op) {
+ case VM_CMD_VERSION:
+ /* We only support one version at this time. */
+ break;
+
+ case VM_CMD_NOATTN:
+ k->set_atn(s, 0, 0);
+ break;
+
+ case VM_CMD_ATTN:
+ k->set_atn(s, 1, 0);
+ break;
+
+ case VM_CMD_ATTN_IRQ:
+ k->set_atn(s, 1, 1);
+ break;
+
+ case VM_CMD_POWEROFF:
+ k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0);
+ break;
+
+ case VM_CMD_RESET:
+ k->do_hw_op(s, IPMI_RESET_CHASSIS, 0);
+ break;
+
+ case VM_CMD_ENABLE_IRQ:
+ k->set_irq_enable(s, 1);
+ break;
+
+ case VM_CMD_DISABLE_IRQ:
+ k->set_irq_enable(s, 0);
+ break;
+
+ case VM_CMD_SEND_NMI:
+ k->do_hw_op(s, IPMI_SEND_NMI, 0);
+ break;
+ }
+}
+
+static void handle_msg(IPMIExternBmc *es)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(es->parent.intf);
+
+ if (es->in_escape) {
+ ipmi_debug("msg escape not ended\n");
+ return;
+ }
+ if (es->inpos < 5) {
+ ipmi_debug("msg too short\n");
+ return;
+ }
+ if (es->in_too_many) {
+ es->inbuf[3] = IPMI_CC_REQUEST_DATA_TRUNCATED;
+ es->inpos = 4;
+ } else if (ipmb_checksum(es->inbuf, es->inpos, 0) != 0) {
+ ipmi_debug("msg checksum failure\n");
+ return;
+ } else {
+ es->inpos--; /* Remove checkum */
+ }
+
+ timer_del(es->extern_timer);
+ es->waiting_rsp = 0;
+ k->handle_rsp(es->parent.intf, es->inbuf[0], es->inbuf + 1, es->inpos - 1);
+}
+
+static int can_receive(void *opaque)
+{
+ return 1;
+}
+
+static void receive(void *opaque, const uint8_t *buf, int size)
+{
+ IPMIExternBmc *es = opaque;
+ IPMIInterface *s = es->parent.intf;
+ int i;
+ unsigned char hw_op;
+
+ ipmi_lock(s);
+ for (i = 0; i < size; i++) {
+ unsigned char ch = buf[i];
+
+ switch (ch) {
+ case VM_MSG_CHAR:
+ handle_msg(es);
+ es->in_too_many = 0;
+ es->inpos = 0;
+ break;
+
+ case VM_CMD_CHAR:
+ if (es->in_too_many) {
+ ipmi_debug("cmd in too many\n");
+ es->in_too_many = 0;
+ es->inpos = 0;
+ break;
+ }
+ if (es->in_escape) {
+ ipmi_debug("cmd in escape\n");
+ es->in_too_many = 0;
+ es->inpos = 0;
+ es->in_escape = 0;
+ break;
+ }
+ es->in_too_many = 0;
+ if (es->inpos < 1) {
+ break;
+ }
+ hw_op = es->inbuf[0];
+ es->inpos = 0;
+ goto out_hw_op;
+ break;
+
+ case VM_ESCAPE_CHAR:
+ es->in_escape = 1;
+ break;
+
+ default:
+ if (es->in_escape) {
+ ch &= ~0x10;
+ es->in_escape = 0;
+ }
+ if (es->in_too_many) {
+ break;
+ }
+ if (es->inpos >= sizeof(es->inbuf)) {
+ es->in_too_many = 1;
+ break;
+ }
+ es->inbuf[es->inpos] = ch;
+ es->inpos++;
+ break;
+ }
+ }
+ ipmi_unlock(s);
+ return;
+
+ out_hw_op:
+ ipmi_unlock(s);
+ /*
+ * We don't want to handle hardware operations while holding the
+ * lock, that may call back into this code to report a reset.
+ */
+ handle_hw_op(es, hw_op);
+}
+
+static void chr_event(void *opaque, int event)
+{
+ IPMIExternBmc *es = opaque;
+ IPMIInterface *s = es->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned char v;
+
+ ipmi_lock(s);
+ switch (event) {
+ case CHR_EVENT_OPENED:
+ es->connected = 1;
+ es->outpos = 0;
+ es->outlen = 0;
+ addchar(es, VM_CMD_VERSION);
+ addchar(es, VM_PROTOCOL_VERSION);
+ es->outbuf[es->outlen] = VM_CMD_CHAR;
+ es->outlen++;
+ addchar(es, VM_CMD_CAPABILITIES);
+ v = VM_CAPABILITIES_IRQ | VM_CAPABILITIES_ATTN;
+ if (k->do_hw_op(es->parent.intf, IPMI_POWEROFF_CHASSIS, 1) == 0) {
+ v |= VM_CAPABILITIES_POWER;
+ }
+ if (k->do_hw_op(es->parent.intf, IPMI_RESET_CHASSIS, 1) == 0) {
+ v |= VM_CAPABILITIES_RESET;
+ }
+ if (k->do_hw_op(es->parent.intf, IPMI_SEND_NMI, 1) == 0) {
+ v |= VM_CAPABILITIES_NMI;
+ }
+ addchar(es, v);
+ es->outbuf[es->outlen] = VM_CMD_CHAR;
+ es->outlen++;
+ es->sending_cmd = 0;
+ continue_send(es);
+ break;
+
+ case CHR_EVENT_CLOSED:
+ if (!es->connected) {
+ return;
+ }
+ es->connected = 0;
+ if (es->waiting_rsp) {
+ es->waiting_rsp = 0;
+ es->inbuf[1] = es->outbuf[1] | 0x04;
+ es->inbuf[2] = es->outbuf[2];
+ es->inbuf[3] = IPMI_CC_BMC_INIT_IN_PROGRESS;
+ k->handle_rsp(s, es->outbuf[0], es->inbuf + 1, 3);
+ }
+ break;
+ }
+ ipmi_unlock(s);
+}
+
+static void ipmi_extern_handle_reset(IPMIBmc *b)
+{
+ IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
+ IPMIInterface *s = es->parent.intf;
+
+ ipmi_lock(s);
+ es->send_reset = 1;
+ continue_send(es);
+ ipmi_unlock(s);
+}
+
+static int ipmi_extern_init(IPMIBmc *b)
+{
+ IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
+
+ es->extern_timer = timer_new(QEMU_CLOCK_REALTIME, SCALE_NS,
+ extern_timeout, es);
+ qemu_chr_add_handlers(es->parent.chr, can_receive, receive, chr_event, es);
+ return 0;
+}
+
+static void ipmi_extern_class_init(ObjectClass *klass, void *data)
+{
+ IPMIBmcClass *bk = IPMI_BMC_CLASS(klass);
+
+ bk->init = ipmi_extern_init;
+ bk->handle_command = ipmi_extern_handle_command;
+ bk->handle_reset = ipmi_extern_handle_reset;
+}
+
+static const TypeInfo ipmi_extern_type = {
+ .name = TYPE_IPMI_BMC_EXTERN,
+ .parent = TYPE_IPMI_BMC,
+ .instance_size = sizeof(IPMIExternBmc),
+ .class_init = ipmi_extern_class_init,
+};
+
+static void ipmi_extern_register_types(void)
+{
+ type_register_static(&ipmi_extern_type);
+}
+
+type_init(ipmi_extern_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 11/16] ipmi: Add tests
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (9 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 10/16] ipmi: Add an external connection simulation interface Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-13 14:12 ` Bret Ketchum
2013-11-12 16:33 ` [Qemu-devel] [PATCH 12/16] ipmi: Add documentation Corey Minyard
` (4 subsequent siblings)
15 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
Test the KCS interface with a local BMC and a BT interface with an
external BMC.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
tests/Makefile | 4 +
tests/ipmi-bt-test.c | 440 ++++++++++++++++++++++++++++++++++++++++++++++++++
tests/ipmi-kcs-test.c | 294 +++++++++++++++++++++++++++++++++
3 files changed, 738 insertions(+)
create mode 100644 tests/ipmi-bt-test.c
create mode 100644 tests/ipmi-kcs-test.c
diff --git a/tests/Makefile b/tests/Makefile
index fa4c9f0..044e7a8 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -65,6 +65,8 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
gcov-files-i386-y += hw/hd-geometry.c
check-qtest-i386-y += tests/boot-order-test$(EXESUF)
check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
check-qtest-i386-y += tests/i440fx-test$(EXESUF)
check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
@@ -169,6 +171,8 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/endianness-test$(EXESUF): tests/endianness-test.o
tests/fdc-test$(EXESUF): tests/fdc-test.o
tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
+tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
+tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
diff --git a/tests/ipmi-bt-test.c b/tests/ipmi-bt-test.c
new file mode 100644
index 0000000..c1da325
--- /dev/null
+++ b/tests/ipmi-bt-test.c
@@ -0,0 +1,440 @@
+/*
+ * IPMI BT test cases, using the external interface for checking
+ *
+ * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/tcp.h>
+
+#include <glib.h>
+
+#include "libqtest.h"
+#include "qemu-common.h"
+
+#define IPMI_IRQ 5
+
+#define IPMI_BT_BASE 0xe4
+
+#define IPMI_BT_CTLREG_CLR_WR_PTR 0
+#define IPMI_BT_CTLREG_CLR_RD_PTR 1
+#define IPMI_BT_CTLREG_H2B_ATN 2
+#define IPMI_BT_CTLREG_B2H_ATN 3
+#define IPMI_BT_CTLREG_SMS_ATN 4
+#define IPMI_BT_CTLREG_H_BUSY 6
+#define IPMI_BT_CTLREG_B_BUSY 7
+
+#define IPMI_BT_CTLREG_GET(b) ((bt_get_ctrlreg() >> (b)) & 1)
+#define IPMI_BT_CTLREG_GET_H2B_ATN() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H2B_ATN)
+#define IPMI_BT_CTLREG_GET_B2H_ATN() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B2H_ATN)
+#define IPMI_BT_CTLREG_GET_SMS_ATN() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_SMS_ATN)
+#define IPMI_BT_CTLREG_GET_H_BUSY() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H_BUSY)
+#define IPMI_BT_CTLREG_GET_B_BUSY() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B_BUSY)
+
+#define IPMI_BT_CTLREG_SET(b) bt_write_ctrlreg(1 << (b))
+#define IPMI_BT_CTLREG_SET_CLR_WR_PTR() IPMI_BT_CTLREG_SET( \
+ IPMI_BT_CTLREG_CLR_WR_PTR)
+#define IPMI_BT_CTLREG_SET_CLR_RD_PTR() IPMI_BT_CTLREG_SET( \
+ IPMI_BT_CTLREG_CLR_RD_PTR)
+#define IPMI_BT_CTLREG_SET_H2B_ATN() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H2B_ATN)
+#define IPMI_BT_CTLREG_SET_B2H_ATN() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_B2H_ATN)
+#define IPMI_BT_CTLREG_SET_SMS_ATN() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_SMS_ATN)
+#define IPMI_BT_CTLREG_SET_H_BUSY() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H_BUSY)
+
+static int bt_ints_enabled;
+
+static uint8_t bt_get_ctrlreg(void)
+{
+ return inb(IPMI_BT_BASE);
+}
+
+static void bt_write_ctrlreg(uint8_t val)
+{
+ outb(IPMI_BT_BASE, val);
+}
+
+static uint8_t bt_get_buf(void)
+{
+ return inb(IPMI_BT_BASE + 1);
+}
+
+static void bt_write_buf(uint8_t val)
+{
+ outb(IPMI_BT_BASE + 1, val);
+}
+
+static uint8_t bt_get_irqreg(void)
+{
+ return inb(IPMI_BT_BASE + 2);
+}
+
+static void bt_write_irqreg(uint8_t val)
+{
+ outb(IPMI_BT_BASE + 2, val);
+}
+
+static void bt_wait_b_busy(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_BT_CTLREG_GET_B_BUSY() != 0) {
+ g_assert(--count != 0);
+ }
+}
+
+static void bt_wait_b2h_atn(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_BT_CTLREG_GET_B2H_ATN() == 0) {
+ g_assert(--count != 0);
+ }
+}
+
+
+static int emu_lfd;
+static int emu_fd;
+static in_port_t emu_port;
+static uint8_t inbuf[100];
+static unsigned int inbuf_len;
+static unsigned int inbuf_pos;
+static int last_was_aa;
+
+static void read_emu_data(void)
+{
+ fd_set readfds;
+ int rv;
+ struct timeval tv;
+
+ FD_ZERO(&readfds);
+ FD_SET(emu_fd, &readfds);
+ tv.tv_sec = 10;
+ tv.tv_usec = 0;
+ rv = select(emu_fd + 1, &readfds, NULL, NULL, &tv);
+ if (rv == -1) {
+ perror("select");
+ }
+ g_assert(rv == 1);
+ rv = read(emu_fd, inbuf, sizeof(inbuf));
+ if (rv == -1) {
+ perror("read");
+ }
+ g_assert(rv > 0);
+ inbuf_len = rv;
+ inbuf_pos = 0;
+}
+
+static void write_emu_msg(uint8_t *msg, unsigned int len)
+{
+ int rv;
+
+#ifdef DEBUG_TEST
+ {
+ unsigned int i;
+ printf("sending:");
+ for (i = 0; i < len; i++) {
+ printf(" %2.2x", msg[i]);
+ }
+ printf("\n");
+ }
+#endif
+ rv = write(emu_fd, msg, len);
+ g_assert(rv == len);
+}
+
+static void get_emu_msg(uint8_t *msg, unsigned int *len)
+{
+ unsigned int outpos = 0;
+
+ for (;;) {
+ while (inbuf_pos < inbuf_len) {
+ uint8_t ch = inbuf[inbuf_pos++];
+
+ g_assert(outpos < *len);
+ if (last_was_aa) {
+ assert(ch & 0x10);
+ msg[outpos++] = ch & ~0x10;
+ last_was_aa = 0;
+ } else if (ch == 0xaa) {
+ last_was_aa = 1;
+ } else {
+ msg[outpos++] = ch;
+ if ((ch == 0xa0) || (ch == 0xa1)) {
+ /* Message complete */
+ *len = outpos;
+ goto done;
+ }
+ }
+ }
+ read_emu_data();
+ }
+ done:
+#ifdef DEBUG_TEST
+ {
+ unsigned int i;
+ printf("Msg:");
+ for (i = 0; i < outpos; i++) {
+ printf(" %2.2x", msg[i]);
+ }
+ printf("\n");
+ }
+#endif
+ return;
+}
+
+static uint8_t
+ipmb_checksum(const unsigned char *data, int size, unsigned char start)
+{
+ unsigned char csum = start;
+
+ for (; size > 0; size--, data++) {
+ csum += *data;
+ }
+ return csum;
+}
+
+static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
+static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x02, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
+static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
+static uint8_t enable_irq_cmd[] = { 0x05, 0xa1 };
+
+static void emu_msg_handler(void)
+{
+ uint8_t msg[100];
+ unsigned int msg_len = sizeof(msg);
+
+ get_emu_msg(msg, &msg_len);
+ g_assert(msg_len >= 5);
+ g_assert(msg[msg_len - 1] == 0xa0);
+ msg_len--;
+ g_assert(ipmb_checksum(msg, msg_len, 0) == 0);
+ msg_len--;
+ if ((msg[1] == get_dev_id_cmd[0]) && (msg[2] == get_dev_id_cmd[1])) {
+ memcpy(msg + 1, get_dev_id_rsp, sizeof(get_dev_id_rsp));
+ msg_len = sizeof(get_dev_id_rsp) + 1;
+ msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
+ msg_len++;
+ msg[msg_len++] = 0xa0;
+ write_emu_msg(msg, msg_len);
+ } else if ((msg[1] == set_bmc_globals_cmd[0]) &&
+ (msg[2] == set_bmc_globals_cmd[1])) {
+ memcpy(msg + 1, set_bmc_globals_rsp, sizeof(set_bmc_globals_rsp));
+ msg_len = sizeof(set_bmc_globals_rsp) + 1;
+ msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
+ msg_len++;
+ msg[msg_len++] = 0xa0;
+ write_emu_msg(msg, msg_len);
+ write_emu_msg(enable_irq_cmd, sizeof(enable_irq_cmd));
+ } else {
+ g_assert(0);
+ }
+}
+
+static void bt_cmd(uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len)
+{
+ unsigned int i, len, j = 0;
+ uint8_t seq = 5;
+
+ /* Should be idle */
+ g_assert(bt_get_ctrlreg() == 0);
+
+ bt_wait_b_busy();
+ IPMI_BT_CTLREG_SET_CLR_WR_PTR();
+ bt_write_buf(cmd_len + 1);
+ bt_write_buf(cmd[0]);
+ bt_write_buf(seq);
+ for (i = 1; i < cmd_len; i++) {
+ bt_write_buf(cmd[i]);
+ }
+ IPMI_BT_CTLREG_SET_H2B_ATN();
+
+ emu_msg_handler(); /* We should get a message on the socket here. */
+
+ bt_wait_b2h_atn();
+ if (bt_ints_enabled) {
+ g_assert((bt_get_irqreg() & 0x02) == 0x02);
+ g_assert(get_irq(IPMI_IRQ));
+ bt_write_irqreg(0x03);
+ } else {
+ g_assert(!get_irq(IPMI_IRQ));
+ }
+ IPMI_BT_CTLREG_SET_H_BUSY();
+ IPMI_BT_CTLREG_SET_B2H_ATN();
+ IPMI_BT_CTLREG_SET_CLR_RD_PTR();
+ len = bt_get_buf();
+ g_assert(len >= 4);
+ rsp[0] = bt_get_buf();
+ assert(bt_get_buf() == seq);
+ len--;
+ for (j = 1; j < len; j++) {
+ rsp[j] = bt_get_buf();
+ }
+ IPMI_BT_CTLREG_SET_H_BUSY();
+ *rsp_len = j;
+}
+
+
+/*
+ * We should get a connect request and a short message with capabilities.
+ */
+static void test_connect(void)
+{
+ fd_set readfds;
+ int rv;
+ int val;
+ struct timeval tv;
+ uint8_t msg[100];
+ unsigned int msglen;
+ static uint8_t exp1[] = { 0xff, 0x01, 0xa1 }; /* A protocol version */
+ static uint8_t exp2[] = { 0x08, 0x1f, 0xa1 }; /* A capabilities cmd */
+ static uint8_t exp3[] = { 0x04, 0xa1 }; /* A reset is reported */
+
+ FD_ZERO(&readfds);
+ FD_SET(emu_lfd, &readfds);
+ tv.tv_sec = 10;
+ tv.tv_usec = 0;
+ rv = select(emu_lfd + 1, &readfds, NULL, NULL, &tv);
+ g_assert(rv == 1);
+ emu_fd = accept(emu_lfd, NULL, 0);
+ if (emu_fd < 0) {
+ perror("accept");
+ }
+ g_assert(emu_fd >= 0);
+
+ val = 1;
+ rv = setsockopt(emu_fd, IPPROTO_TCP, TCP_NODELAY, &val, sizeof(val));
+ g_assert(rv != -1);
+
+ /* Report our version */
+ write_emu_msg(exp1, sizeof(exp1));
+
+ /* Validate that we get the info we expect. */
+ msglen = sizeof(msg);
+ get_emu_msg(msg, &msglen);
+ g_assert(msglen == sizeof(exp1));
+ g_assert(memcmp(msg, exp1, msglen) == 0);
+ msglen = sizeof(msg);
+ get_emu_msg(msg, &msglen);
+ g_assert(msglen == sizeof(exp2));
+ g_assert(memcmp(msg, exp2, msglen) == 0);
+ msglen = sizeof(msg);
+ get_emu_msg(msg, &msglen);
+ g_assert(msglen == sizeof(exp3));
+ g_assert(memcmp(msg, exp3, msglen) == 0);
+}
+
+/*
+ * Send a get_device_id to do a basic test.
+ */
+static void test_bt_base(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ bt_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(get_dev_id_rsp));
+ g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
+}
+
+/*
+ * Enable IRQs for the interface.
+ */
+static void test_enable_irq(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ bt_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(set_bmc_globals_rsp));
+ g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
+ bt_write_irqreg(0x01);
+ bt_ints_enabled = 1;
+}
+
+/*
+ * Create a local TCP socket with any port, then save off the port we got.
+ */
+static void open_socket(void)
+{
+ struct sockaddr_in myaddr;
+ socklen_t addrlen;
+
+ myaddr.sin_family = AF_INET;
+ myaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+ myaddr.sin_port = 0;
+ emu_lfd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
+ if (emu_lfd == -1) {
+ perror("socket");
+ exit(1);
+ }
+ if (bind(emu_lfd, (struct sockaddr *) &myaddr, sizeof(myaddr)) == -1) {
+ perror("bind");
+ exit(1);
+ }
+ addrlen = sizeof(myaddr);
+ if (getsockname(emu_lfd, (struct sockaddr *) &myaddr , &addrlen) == -1) {
+ perror("getsockname");
+ exit(1);
+ }
+ emu_port = ntohs(myaddr.sin_port);
+ assert(listen(emu_lfd, 1) != -1);
+}
+
+int main(int argc, char **argv)
+{
+ const char *arch = qtest_get_arch();
+ char *cmdline;
+ int ret;
+
+ /* Check architecture */
+ if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
+ g_test_message("Skipping test for non-x86\n");
+ return 0;
+ }
+
+ open_socket();
+
+ /* Run the tests */
+ g_test_init(&argc, &argv, NULL);
+
+ cmdline = g_strdup_printf("-vnc none"
+ " -chardev socket,id=ipmi0,host=localhost,port=%d,reconnect=10"
+ " -device isa-ipmi,interface=bt,chardev=ipmi0", emu_port);
+ qtest_start(cmdline);
+ qtest_irq_intercept_in(global_qtest, "ioapic");
+ qtest_add_func("/ipmi/extern/connect", test_connect);
+ qtest_add_func("/ipmi/extern/bt_base", test_bt_base);
+ qtest_add_func("/ipmi/extern/bt_enable_irq", test_enable_irq);
+ qtest_add_func("/ipmi/extern/bt_base_irq", test_bt_base);
+ ret = g_test_run();
+ qtest_quit(global_qtest);
+
+ return ret;
+}
diff --git a/tests/ipmi-kcs-test.c b/tests/ipmi-kcs-test.c
new file mode 100644
index 0000000..e2e1bdb
--- /dev/null
+++ b/tests/ipmi-kcs-test.c
@@ -0,0 +1,294 @@
+/*
+ * IPMI KCS test cases, using the local interface.
+ *
+ * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <glib.h>
+
+#include "libqtest.h"
+
+#define IPMI_IRQ 5
+
+#define IPMI_KCS_BASE 0xca2
+
+#define IPMI_KCS_STATUS_ABORT 0x60
+#define IPMI_KCS_CMD_WRITE_START 0x61
+#define IPMI_KCS_CMD_WRITE_END 0x62
+#define IPMI_KCS_CMD_READ 0x68
+
+#define IPMI_KCS_ABORTED_BY_CMD 0x01
+
+#define IPMI_KCS_CMDREG_GET_STATE() ((kcs_get_cmdreg() >> 6) & 3)
+#define IPMI_KCS_STATE_IDLE 0
+#define IPMI_KCS_STATE_READ 1
+#define IPMI_KCS_STATE_WRITE 2
+#define IPMI_KCS_STATE_ERROR 3
+#define IPMI_KCS_CMDREG_GET_CD() ((kcs_get_cmdreg() >> 3) & 1)
+#define IPMI_KCS_CMDREG_GET_ATN() ((kcs_get_cmdreg() >> 2) & 1)
+#define IPMI_KCS_CMDREG_GET_IBF() ((kcs_get_cmdreg() >> 1) & 1)
+#define IPMI_KCS_CMDREG_GET_OBF() ((kcs_get_cmdreg() >> 0) & 1)
+
+static int kcs_ints_enabled;
+
+static uint8_t kcs_get_cmdreg(void)
+{
+ return inb(IPMI_KCS_BASE + 1);
+}
+
+static void kcs_write_cmdreg(uint8_t val)
+{
+ outb(IPMI_KCS_BASE + 1, val);
+}
+
+static uint8_t kcs_get_datareg(void)
+{
+ return inb(IPMI_KCS_BASE);
+}
+
+static void kcs_write_datareg(uint8_t val)
+{
+ outb(IPMI_KCS_BASE, val);
+}
+
+static void kcs_wait_ibf(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_KCS_CMDREG_GET_IBF() != 0) {
+ g_assert(--count != 0);
+ }
+}
+
+static void kcs_wait_obf(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_KCS_CMDREG_GET_OBF() == 0) {
+ g_assert(--count != 0);
+ }
+}
+
+static void kcs_clear_obf(void)
+{
+ if (kcs_ints_enabled) {
+ g_assert(get_irq(IPMI_IRQ));
+ } else {
+ g_assert(!get_irq(IPMI_IRQ));
+ }
+ g_assert(IPMI_KCS_CMDREG_GET_OBF() == 1);
+ kcs_get_datareg();
+ g_assert(IPMI_KCS_CMDREG_GET_OBF() == 0);
+ g_assert(!get_irq(IPMI_IRQ));
+}
+
+static void kcs_check_state(uint8_t state)
+{
+ g_assert(IPMI_KCS_CMDREG_GET_STATE() == state);
+}
+
+static void kcs_cmd(uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len)
+{
+ unsigned int i, j = 0;
+
+ /* Should be idle */
+ g_assert(kcs_get_cmdreg() == 0);
+
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ for (i = 0; i < cmd_len; i++) {
+ kcs_write_datareg(cmd[i]);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ }
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ kcs_write_datareg(0);
+ next_read_byte:
+ kcs_wait_ibf();
+ switch (IPMI_KCS_CMDREG_GET_STATE()) {
+ case IPMI_KCS_STATE_READ:
+ kcs_wait_obf();
+ g_assert(j < *rsp_len);
+ rsp[j++] = kcs_get_datareg();
+ kcs_write_datareg(IPMI_KCS_CMD_READ);
+ goto next_read_byte;
+ break;
+
+ case IPMI_KCS_STATE_IDLE:
+ kcs_wait_obf();
+ kcs_get_datareg();
+ break;
+
+ default:
+ g_assert(0);
+ }
+ *rsp_len = j;
+}
+
+static void kcs_abort(uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len)
+{
+ unsigned int i, j = 0;
+ unsigned int retries = 4;
+
+ /* Should be idle */
+ g_assert(kcs_get_cmdreg() == 0);
+
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ for (i = 0; i < cmd_len; i++) {
+ kcs_write_datareg(cmd[i]);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ }
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ kcs_write_datareg(0);
+ kcs_wait_ibf();
+ switch (IPMI_KCS_CMDREG_GET_STATE()) {
+ case IPMI_KCS_STATE_READ:
+ kcs_wait_obf();
+ g_assert(j < *rsp_len);
+ rsp[j++] = kcs_get_datareg();
+ kcs_write_datareg(IPMI_KCS_CMD_READ);
+ break;
+
+ default:
+ g_assert(0);
+ }
+
+ /* Start the abort here */
+ retry_abort:
+ g_assert(retries > 0);
+
+ kcs_wait_ibf();
+ kcs_write_cmdreg(IPMI_KCS_STATUS_ABORT);
+ kcs_wait_ibf();
+ kcs_clear_obf();
+ kcs_write_datareg(0);
+ kcs_wait_ibf();
+ if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_READ) {
+ retries--;
+ goto retry_abort;
+ }
+ kcs_wait_obf();
+ rsp[0] = kcs_get_datareg();
+ kcs_write_datareg(IPMI_KCS_CMD_READ);
+ kcs_wait_ibf();
+ if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_IDLE) {
+ retries--;
+ goto retry_abort;
+ }
+ kcs_wait_obf();
+ kcs_clear_obf();
+
+ *rsp_len = j;
+}
+
+
+static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
+static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x02, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+/*
+ * Send a get_device_id to do a basic test.
+ */
+static void test_kcs_base(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ kcs_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(get_dev_id_rsp));
+ g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
+}
+
+/*
+ * Abort a kcs operation while reading
+ */
+static void test_kcs_abort(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ kcs_abort(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
+ g_assert(rsp[0] == IPMI_KCS_ABORTED_BY_CMD);
+}
+
+static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
+static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
+
+/*
+ * Enable interrupts
+ */
+static void test_enable_irq(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ kcs_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(set_bmc_globals_rsp));
+ g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
+ kcs_ints_enabled = 1;
+}
+
+int main(int argc, char **argv)
+{
+ const char *arch = qtest_get_arch();
+ char *cmdline;
+ int ret;
+
+ /* Check architecture */
+ if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
+ g_test_message("Skipping test for non-x86\n");
+ return 0;
+ }
+
+ /* Run the tests */
+ g_test_init(&argc, &argv, NULL);
+
+ cmdline = g_strdup_printf("-vnc none -device isa-ipmi");
+ qtest_start(cmdline);
+ qtest_irq_intercept_in(global_qtest, "ioapic");
+ qtest_add_func("/ipmi/local/kcs_base", test_kcs_base);
+ qtest_add_func("/ipmi/local/kcs_abort", test_kcs_abort);
+ qtest_add_func("/ipmi/local/kcs_enable_irq", test_enable_irq);
+ qtest_add_func("/ipmi/local/kcs_base_irq", test_kcs_base);
+ qtest_add_func("/ipmi/local/kcs_abort_irq", test_kcs_abort);
+ ret = g_test_run();
+ qtest_quit(global_qtest);
+
+ return ret;
+}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 11/16] ipmi: Add tests
2013-11-12 16:33 ` [Qemu-devel] [PATCH 11/16] ipmi: Add tests Corey Minyard
@ 2013-11-13 14:12 ` Bret Ketchum
2013-11-13 20:51 ` Corey Minyard
0 siblings, 1 reply; 42+ messages in thread
From: Bret Ketchum @ 2013-11-13 14:12 UTC (permalink / raw)
To: Corey Minyard; +Cc: Corey Minyard, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 27488 bytes --]
Having trouble with this patch (after the prior patches were
successfully applied):
git status
# On branch master
# Changes not staged for commit:
# (use "git add <file>..." to update what will be committed)
# (use "git checkout -- <file>..." to discard changes in working
directory)
#
# modified: ../../../backends/baum.c
# modified: ../../../backends/msmouse.c
# modified: ../../../default-configs/i386-softmmu.mak
# modified: ../../../default-configs/x86_64-softmmu.mak
# modified: ../../../hw/Makefile.objs
# modified: ../../../hw/misc/ivshmem.c
# modified: ../../../include/hw/nvram/fw_cfg.h
# modified: ../../../include/sysemu/char.h
# modified: ../../../include/ui/console.h
# modified: ../../../include/ui/qemu-spice.h
# modified: ../../../qemu-char.c
# modified: ../../../qemu-doc.texi
# modified: ../../../qemu-options.hx
# modified: ../../../spice-qemu-char.c
# modified: ../../../ui/console.c
#
# Untracked files:
# (use "git add <file>..." to include in what will be committed)
#
# ../../
# ../../../hw/ipmi/
no changes added to commit (use "git add" and/or "git commit -a")
[
git apply --verbos --check ../ipmi-patches/290712.mbox
Checking patch tests/Makefile...
error: while searching for:
gcov-files-i386-y += hw/hd-geometry.c
check-qtest-i386-y += tests/boot-order-test$(EXESUF)
check-qtest-i386-y += tests/rtc-test$(EXESUF)
check-qtest-i386-y += tests/i440fx-test$(EXESUF)
check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
error: patch failed: tests/Makefile:65
error: tests/Makefile: patch does not apply
Checking patch tests/ipmi-bt-test.c...
Checking patch tests/ipmi-kcs-test.c...
I believe the patch for tests/Makefile should look like:
diff --git a/tests/Makefile b/tests/Makefile
index f414f2c..0395cd4 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -65,6 +65,8 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
gcov-files-i386-y += hw/hd-geometry.c
check-qtest-i386-y += tests/boot-order-test$(EXESUF)
check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
check-qtest-i386-y += tests/i440fx-test$(EXESUF)
check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
check-qtest-i386-y += tests/qom-test$(EXESUF)
@@ -194,6 +196,8 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/endianness-test$(EXESUF): tests/endianness-test.o
tests/fdc-test$(EXESUF): tests/fdc-test.o
tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
+tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
+tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
On Tue, Nov 12, 2013 at 10:33 AM, Corey Minyard <minyard@acm.org> wrote:
> Test the KCS interface with a local BMC and a BT interface with an
> external BMC.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> ---
> tests/Makefile | 4 +
> tests/ipmi-bt-test.c | 440
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> tests/ipmi-kcs-test.c | 294 +++++++++++++++++++++++++++++++++
> 3 files changed, 738 insertions(+)
> create mode 100644 tests/ipmi-bt-test.c
> create mode 100644 tests/ipmi-kcs-test.c
>
> diff --git a/tests/Makefile b/tests/Makefile
> index fa4c9f0..044e7a8 100644
> --- a/tests/Makefile
> +++ b/tests/Makefile
> @@ -65,6 +65,8 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
> gcov-files-i386-y += hw/hd-geometry.c
> check-qtest-i386-y += tests/boot-order-test$(EXESUF)
> check-qtest-i386-y += tests/rtc-test$(EXESUF)
> +check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
> +check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
> check-qtest-i386-y += tests/i440fx-test$(EXESUF)
> check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
> check-qtest-x86_64-y = $(check-qtest-i386-y)
> @@ -169,6 +171,8 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
> tests/endianness-test$(EXESUF): tests/endianness-test.o
> tests/fdc-test$(EXESUF): tests/fdc-test.o
> tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
> +tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
> +tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
> tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
> tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
> tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
> diff --git a/tests/ipmi-bt-test.c b/tests/ipmi-bt-test.c
> new file mode 100644
> index 0000000..c1da325
> --- /dev/null
> +++ b/tests/ipmi-bt-test.c
> @@ -0,0 +1,440 @@
> +/*
> + * IPMI BT test cases, using the external interface for checking
> + *
> + * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> + * of this software and associated documentation files (the "Software"),
> to deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> IN
> + * THE SOFTWARE.
> + */
> +
> +#include <sys/types.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <stdio.h>
> +
> +#include <sys/socket.h>
> +#include <netinet/in.h>
> +#include <netinet/ip.h>
> +#include <netinet/tcp.h>
> +
> +#include <glib.h>
> +
> +#include "libqtest.h"
> +#include "qemu-common.h"
> +
> +#define IPMI_IRQ 5
> +
> +#define IPMI_BT_BASE 0xe4
> +
> +#define IPMI_BT_CTLREG_CLR_WR_PTR 0
> +#define IPMI_BT_CTLREG_CLR_RD_PTR 1
> +#define IPMI_BT_CTLREG_H2B_ATN 2
> +#define IPMI_BT_CTLREG_B2H_ATN 3
> +#define IPMI_BT_CTLREG_SMS_ATN 4
> +#define IPMI_BT_CTLREG_H_BUSY 6
> +#define IPMI_BT_CTLREG_B_BUSY 7
> +
> +#define IPMI_BT_CTLREG_GET(b) ((bt_get_ctrlreg() >> (b)) & 1)
> +#define IPMI_BT_CTLREG_GET_H2B_ATN()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H2B_ATN)
> +#define IPMI_BT_CTLREG_GET_B2H_ATN()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B2H_ATN)
> +#define IPMI_BT_CTLREG_GET_SMS_ATN()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_SMS_ATN)
> +#define IPMI_BT_CTLREG_GET_H_BUSY()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H_BUSY)
> +#define IPMI_BT_CTLREG_GET_B_BUSY()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B_BUSY)
> +
> +#define IPMI_BT_CTLREG_SET(b) bt_write_ctrlreg(1 << (b))
> +#define IPMI_BT_CTLREG_SET_CLR_WR_PTR() IPMI_BT_CTLREG_SET( \
> + IPMI_BT_CTLREG_CLR_WR_PTR)
> +#define IPMI_BT_CTLREG_SET_CLR_RD_PTR() IPMI_BT_CTLREG_SET( \
> + IPMI_BT_CTLREG_CLR_RD_PTR)
> +#define IPMI_BT_CTLREG_SET_H2B_ATN()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H2B_ATN)
> +#define IPMI_BT_CTLREG_SET_B2H_ATN()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_B2H_ATN)
> +#define IPMI_BT_CTLREG_SET_SMS_ATN()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_SMS_ATN)
> +#define IPMI_BT_CTLREG_SET_H_BUSY()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H_BUSY)
> +
> +static int bt_ints_enabled;
> +
> +static uint8_t bt_get_ctrlreg(void)
> +{
> + return inb(IPMI_BT_BASE);
> +}
> +
> +static void bt_write_ctrlreg(uint8_t val)
> +{
> + outb(IPMI_BT_BASE, val);
> +}
> +
> +static uint8_t bt_get_buf(void)
> +{
> + return inb(IPMI_BT_BASE + 1);
> +}
> +
> +static void bt_write_buf(uint8_t val)
> +{
> + outb(IPMI_BT_BASE + 1, val);
> +}
> +
> +static uint8_t bt_get_irqreg(void)
> +{
> + return inb(IPMI_BT_BASE + 2);
> +}
> +
> +static void bt_write_irqreg(uint8_t val)
> +{
> + outb(IPMI_BT_BASE + 2, val);
> +}
> +
> +static void bt_wait_b_busy(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_BT_CTLREG_GET_B_BUSY() != 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +static void bt_wait_b2h_atn(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_BT_CTLREG_GET_B2H_ATN() == 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +
> +static int emu_lfd;
> +static int emu_fd;
> +static in_port_t emu_port;
> +static uint8_t inbuf[100];
> +static unsigned int inbuf_len;
> +static unsigned int inbuf_pos;
> +static int last_was_aa;
> +
> +static void read_emu_data(void)
> +{
> + fd_set readfds;
> + int rv;
> + struct timeval tv;
> +
> + FD_ZERO(&readfds);
> + FD_SET(emu_fd, &readfds);
> + tv.tv_sec = 10;
> + tv.tv_usec = 0;
> + rv = select(emu_fd + 1, &readfds, NULL, NULL, &tv);
> + if (rv == -1) {
> + perror("select");
> + }
> + g_assert(rv == 1);
> + rv = read(emu_fd, inbuf, sizeof(inbuf));
> + if (rv == -1) {
> + perror("read");
> + }
> + g_assert(rv > 0);
> + inbuf_len = rv;
> + inbuf_pos = 0;
> +}
> +
> +static void write_emu_msg(uint8_t *msg, unsigned int len)
> +{
> + int rv;
> +
> +#ifdef DEBUG_TEST
> + {
> + unsigned int i;
> + printf("sending:");
> + for (i = 0; i < len; i++) {
> + printf(" %2.2x", msg[i]);
> + }
> + printf("\n");
> + }
> +#endif
> + rv = write(emu_fd, msg, len);
> + g_assert(rv == len);
> +}
> +
> +static void get_emu_msg(uint8_t *msg, unsigned int *len)
> +{
> + unsigned int outpos = 0;
> +
> + for (;;) {
> + while (inbuf_pos < inbuf_len) {
> + uint8_t ch = inbuf[inbuf_pos++];
> +
> + g_assert(outpos < *len);
> + if (last_was_aa) {
> + assert(ch & 0x10);
> + msg[outpos++] = ch & ~0x10;
> + last_was_aa = 0;
> + } else if (ch == 0xaa) {
> + last_was_aa = 1;
> + } else {
> + msg[outpos++] = ch;
> + if ((ch == 0xa0) || (ch == 0xa1)) {
> + /* Message complete */
> + *len = outpos;
> + goto done;
> + }
> + }
> + }
> + read_emu_data();
> + }
> + done:
> +#ifdef DEBUG_TEST
> + {
> + unsigned int i;
> + printf("Msg:");
> + for (i = 0; i < outpos; i++) {
> + printf(" %2.2x", msg[i]);
> + }
> + printf("\n");
> + }
> +#endif
> + return;
> +}
> +
> +static uint8_t
> +ipmb_checksum(const unsigned char *data, int size, unsigned char start)
> +{
> + unsigned char csum = start;
> +
> + for (; size > 0; size--, data++) {
> + csum += *data;
> + }
> + return csum;
> +}
> +
> +static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
> +static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00, 0x00,
> 0x00,
> + 0x02, 0x09, 0x00, 0x00, 0x00, 0x00,
> 0x00 };
> +
> +static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
> +static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
> +static uint8_t enable_irq_cmd[] = { 0x05, 0xa1 };
> +
> +static void emu_msg_handler(void)
> +{
> + uint8_t msg[100];
> + unsigned int msg_len = sizeof(msg);
> +
> + get_emu_msg(msg, &msg_len);
> + g_assert(msg_len >= 5);
> + g_assert(msg[msg_len - 1] == 0xa0);
> + msg_len--;
> + g_assert(ipmb_checksum(msg, msg_len, 0) == 0);
> + msg_len--;
> + if ((msg[1] == get_dev_id_cmd[0]) && (msg[2] == get_dev_id_cmd[1])) {
> + memcpy(msg + 1, get_dev_id_rsp, sizeof(get_dev_id_rsp));
> + msg_len = sizeof(get_dev_id_rsp) + 1;
> + msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
> + msg_len++;
> + msg[msg_len++] = 0xa0;
> + write_emu_msg(msg, msg_len);
> + } else if ((msg[1] == set_bmc_globals_cmd[0]) &&
> + (msg[2] == set_bmc_globals_cmd[1])) {
> + memcpy(msg + 1, set_bmc_globals_rsp, sizeof(set_bmc_globals_rsp));
> + msg_len = sizeof(set_bmc_globals_rsp) + 1;
> + msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
> + msg_len++;
> + msg[msg_len++] = 0xa0;
> + write_emu_msg(msg, msg_len);
> + write_emu_msg(enable_irq_cmd, sizeof(enable_irq_cmd));
> + } else {
> + g_assert(0);
> + }
> +}
> +
> +static void bt_cmd(uint8_t *cmd, unsigned int cmd_len,
> + uint8_t *rsp, unsigned int *rsp_len)
> +{
> + unsigned int i, len, j = 0;
> + uint8_t seq = 5;
> +
> + /* Should be idle */
> + g_assert(bt_get_ctrlreg() == 0);
> +
> + bt_wait_b_busy();
> + IPMI_BT_CTLREG_SET_CLR_WR_PTR();
> + bt_write_buf(cmd_len + 1);
> + bt_write_buf(cmd[0]);
> + bt_write_buf(seq);
> + for (i = 1; i < cmd_len; i++) {
> + bt_write_buf(cmd[i]);
> + }
> + IPMI_BT_CTLREG_SET_H2B_ATN();
> +
> + emu_msg_handler(); /* We should get a message on the socket here. */
> +
> + bt_wait_b2h_atn();
> + if (bt_ints_enabled) {
> + g_assert((bt_get_irqreg() & 0x02) == 0x02);
> + g_assert(get_irq(IPMI_IRQ));
> + bt_write_irqreg(0x03);
> + } else {
> + g_assert(!get_irq(IPMI_IRQ));
> + }
> + IPMI_BT_CTLREG_SET_H_BUSY();
> + IPMI_BT_CTLREG_SET_B2H_ATN();
> + IPMI_BT_CTLREG_SET_CLR_RD_PTR();
> + len = bt_get_buf();
> + g_assert(len >= 4);
> + rsp[0] = bt_get_buf();
> + assert(bt_get_buf() == seq);
> + len--;
> + for (j = 1; j < len; j++) {
> + rsp[j] = bt_get_buf();
> + }
> + IPMI_BT_CTLREG_SET_H_BUSY();
> + *rsp_len = j;
> +}
> +
> +
> +/*
> + * We should get a connect request and a short message with capabilities.
> + */
> +static void test_connect(void)
> +{
> + fd_set readfds;
> + int rv;
> + int val;
> + struct timeval tv;
> + uint8_t msg[100];
> + unsigned int msglen;
> + static uint8_t exp1[] = { 0xff, 0x01, 0xa1 }; /* A protocol version */
> + static uint8_t exp2[] = { 0x08, 0x1f, 0xa1 }; /* A capabilities cmd */
> + static uint8_t exp3[] = { 0x04, 0xa1 }; /* A reset is reported */
> +
> + FD_ZERO(&readfds);
> + FD_SET(emu_lfd, &readfds);
> + tv.tv_sec = 10;
> + tv.tv_usec = 0;
> + rv = select(emu_lfd + 1, &readfds, NULL, NULL, &tv);
> + g_assert(rv == 1);
> + emu_fd = accept(emu_lfd, NULL, 0);
> + if (emu_fd < 0) {
> + perror("accept");
> + }
> + g_assert(emu_fd >= 0);
> +
> + val = 1;
> + rv = setsockopt(emu_fd, IPPROTO_TCP, TCP_NODELAY, &val, sizeof(val));
> + g_assert(rv != -1);
> +
> + /* Report our version */
> + write_emu_msg(exp1, sizeof(exp1));
> +
> + /* Validate that we get the info we expect. */
> + msglen = sizeof(msg);
> + get_emu_msg(msg, &msglen);
> + g_assert(msglen == sizeof(exp1));
> + g_assert(memcmp(msg, exp1, msglen) == 0);
> + msglen = sizeof(msg);
> + get_emu_msg(msg, &msglen);
> + g_assert(msglen == sizeof(exp2));
> + g_assert(memcmp(msg, exp2, msglen) == 0);
> + msglen = sizeof(msg);
> + get_emu_msg(msg, &msglen);
> + g_assert(msglen == sizeof(exp3));
> + g_assert(memcmp(msg, exp3, msglen) == 0);
> +}
> +
> +/*
> + * Send a get_device_id to do a basic test.
> + */
> +static void test_bt_base(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + bt_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
> + g_assert(rsplen == sizeof(get_dev_id_rsp));
> + g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
> +}
> +
> +/*
> + * Enable IRQs for the interface.
> + */
> +static void test_enable_irq(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + bt_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp,
> &rsplen);
> + g_assert(rsplen == sizeof(set_bmc_globals_rsp));
> + g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
> + bt_write_irqreg(0x01);
> + bt_ints_enabled = 1;
> +}
> +
> +/*
> + * Create a local TCP socket with any port, then save off the port we got.
> + */
> +static void open_socket(void)
> +{
> + struct sockaddr_in myaddr;
> + socklen_t addrlen;
> +
> + myaddr.sin_family = AF_INET;
> + myaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
> + myaddr.sin_port = 0;
> + emu_lfd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
> + if (emu_lfd == -1) {
> + perror("socket");
> + exit(1);
> + }
> + if (bind(emu_lfd, (struct sockaddr *) &myaddr, sizeof(myaddr)) == -1)
> {
> + perror("bind");
> + exit(1);
> + }
> + addrlen = sizeof(myaddr);
> + if (getsockname(emu_lfd, (struct sockaddr *) &myaddr , &addrlen) ==
> -1) {
> + perror("getsockname");
> + exit(1);
> + }
> + emu_port = ntohs(myaddr.sin_port);
> + assert(listen(emu_lfd, 1) != -1);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + const char *arch = qtest_get_arch();
> + char *cmdline;
> + int ret;
> +
> + /* Check architecture */
> + if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
> + g_test_message("Skipping test for non-x86\n");
> + return 0;
> + }
> +
> + open_socket();
> +
> + /* Run the tests */
> + g_test_init(&argc, &argv, NULL);
> +
> + cmdline = g_strdup_printf("-vnc none"
> + " -chardev socket,id=ipmi0,host=localhost,port=%d,reconnect=10"
> + " -device isa-ipmi,interface=bt,chardev=ipmi0", emu_port);
> + qtest_start(cmdline);
> + qtest_irq_intercept_in(global_qtest, "ioapic");
> + qtest_add_func("/ipmi/extern/connect", test_connect);
> + qtest_add_func("/ipmi/extern/bt_base", test_bt_base);
> + qtest_add_func("/ipmi/extern/bt_enable_irq", test_enable_irq);
> + qtest_add_func("/ipmi/extern/bt_base_irq", test_bt_base);
> + ret = g_test_run();
> + qtest_quit(global_qtest);
> +
> + return ret;
> +}
> diff --git a/tests/ipmi-kcs-test.c b/tests/ipmi-kcs-test.c
> new file mode 100644
> index 0000000..e2e1bdb
> --- /dev/null
> +++ b/tests/ipmi-kcs-test.c
> @@ -0,0 +1,294 @@
> +/*
> + * IPMI KCS test cases, using the local interface.
> + *
> + * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> + * of this software and associated documentation files (the "Software"),
> to deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> IN
> + * THE SOFTWARE.
> + */
> +
> +#include <stdint.h>
> +#include <string.h>
> +#include <stdio.h>
> +
> +#include <glib.h>
> +
> +#include "libqtest.h"
> +
> +#define IPMI_IRQ 5
> +
> +#define IPMI_KCS_BASE 0xca2
> +
> +#define IPMI_KCS_STATUS_ABORT 0x60
> +#define IPMI_KCS_CMD_WRITE_START 0x61
> +#define IPMI_KCS_CMD_WRITE_END 0x62
> +#define IPMI_KCS_CMD_READ 0x68
> +
> +#define IPMI_KCS_ABORTED_BY_CMD 0x01
> +
> +#define IPMI_KCS_CMDREG_GET_STATE() ((kcs_get_cmdreg() >> 6) & 3)
> +#define IPMI_KCS_STATE_IDLE 0
> +#define IPMI_KCS_STATE_READ 1
> +#define IPMI_KCS_STATE_WRITE 2
> +#define IPMI_KCS_STATE_ERROR 3
> +#define IPMI_KCS_CMDREG_GET_CD() ((kcs_get_cmdreg() >> 3) & 1)
> +#define IPMI_KCS_CMDREG_GET_ATN() ((kcs_get_cmdreg() >> 2) & 1)
> +#define IPMI_KCS_CMDREG_GET_IBF() ((kcs_get_cmdreg() >> 1) & 1)
> +#define IPMI_KCS_CMDREG_GET_OBF() ((kcs_get_cmdreg() >> 0) & 1)
> +
> +static int kcs_ints_enabled;
> +
> +static uint8_t kcs_get_cmdreg(void)
> +{
> + return inb(IPMI_KCS_BASE + 1);
> +}
> +
> +static void kcs_write_cmdreg(uint8_t val)
> +{
> + outb(IPMI_KCS_BASE + 1, val);
> +}
> +
> +static uint8_t kcs_get_datareg(void)
> +{
> + return inb(IPMI_KCS_BASE);
> +}
> +
> +static void kcs_write_datareg(uint8_t val)
> +{
> + outb(IPMI_KCS_BASE, val);
> +}
> +
> +static void kcs_wait_ibf(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_KCS_CMDREG_GET_IBF() != 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +static void kcs_wait_obf(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_KCS_CMDREG_GET_OBF() == 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +static void kcs_clear_obf(void)
> +{
> + if (kcs_ints_enabled) {
> + g_assert(get_irq(IPMI_IRQ));
> + } else {
> + g_assert(!get_irq(IPMI_IRQ));
> + }
> + g_assert(IPMI_KCS_CMDREG_GET_OBF() == 1);
> + kcs_get_datareg();
> + g_assert(IPMI_KCS_CMDREG_GET_OBF() == 0);
> + g_assert(!get_irq(IPMI_IRQ));
> +}
> +
> +static void kcs_check_state(uint8_t state)
> +{
> + g_assert(IPMI_KCS_CMDREG_GET_STATE() == state);
> +}
> +
> +static void kcs_cmd(uint8_t *cmd, unsigned int cmd_len,
> + uint8_t *rsp, unsigned int *rsp_len)
> +{
> + unsigned int i, j = 0;
> +
> + /* Should be idle */
> + g_assert(kcs_get_cmdreg() == 0);
> +
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + for (i = 0; i < cmd_len; i++) {
> + kcs_write_datareg(cmd[i]);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + }
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + kcs_write_datareg(0);
> + next_read_byte:
> + kcs_wait_ibf();
> + switch (IPMI_KCS_CMDREG_GET_STATE()) {
> + case IPMI_KCS_STATE_READ:
> + kcs_wait_obf();
> + g_assert(j < *rsp_len);
> + rsp[j++] = kcs_get_datareg();
> + kcs_write_datareg(IPMI_KCS_CMD_READ);
> + goto next_read_byte;
> + break;
> +
> + case IPMI_KCS_STATE_IDLE:
> + kcs_wait_obf();
> + kcs_get_datareg();
> + break;
> +
> + default:
> + g_assert(0);
> + }
> + *rsp_len = j;
> +}
> +
> +static void kcs_abort(uint8_t *cmd, unsigned int cmd_len,
> + uint8_t *rsp, unsigned int *rsp_len)
> +{
> + unsigned int i, j = 0;
> + unsigned int retries = 4;
> +
> + /* Should be idle */
> + g_assert(kcs_get_cmdreg() == 0);
> +
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + for (i = 0; i < cmd_len; i++) {
> + kcs_write_datareg(cmd[i]);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + }
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + kcs_write_datareg(0);
> + kcs_wait_ibf();
> + switch (IPMI_KCS_CMDREG_GET_STATE()) {
> + case IPMI_KCS_STATE_READ:
> + kcs_wait_obf();
> + g_assert(j < *rsp_len);
> + rsp[j++] = kcs_get_datareg();
> + kcs_write_datareg(IPMI_KCS_CMD_READ);
> + break;
> +
> + default:
> + g_assert(0);
> + }
> +
> + /* Start the abort here */
> + retry_abort:
> + g_assert(retries > 0);
> +
> + kcs_wait_ibf();
> + kcs_write_cmdreg(IPMI_KCS_STATUS_ABORT);
> + kcs_wait_ibf();
> + kcs_clear_obf();
> + kcs_write_datareg(0);
> + kcs_wait_ibf();
> + if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_READ) {
> + retries--;
> + goto retry_abort;
> + }
> + kcs_wait_obf();
> + rsp[0] = kcs_get_datareg();
> + kcs_write_datareg(IPMI_KCS_CMD_READ);
> + kcs_wait_ibf();
> + if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_IDLE) {
> + retries--;
> + goto retry_abort;
> + }
> + kcs_wait_obf();
> + kcs_clear_obf();
> +
> + *rsp_len = j;
> +}
> +
> +
> +static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
> +static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00, 0x00,
> 0x00,
> + 0x02, 0x07, 0x00, 0x00, 0x00, 0x00,
> 0x00 };
> +
> +/*
> + * Send a get_device_id to do a basic test.
> + */
> +static void test_kcs_base(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + kcs_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
> + g_assert(rsplen == sizeof(get_dev_id_rsp));
> + g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
> +}
> +
> +/*
> + * Abort a kcs operation while reading
> + */
> +static void test_kcs_abort(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + kcs_abort(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
> + g_assert(rsp[0] == IPMI_KCS_ABORTED_BY_CMD);
> +}
> +
> +static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
> +static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
> +
> +/*
> + * Enable interrupts
> + */
> +static void test_enable_irq(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + kcs_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp,
> &rsplen);
> + g_assert(rsplen == sizeof(set_bmc_globals_rsp));
> + g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
> + kcs_ints_enabled = 1;
> +}
> +
> +int main(int argc, char **argv)
> +{
> + const char *arch = qtest_get_arch();
> + char *cmdline;
> + int ret;
> +
> + /* Check architecture */
> + if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
> + g_test_message("Skipping test for non-x86\n");
> + return 0;
> + }
> +
> + /* Run the tests */
> + g_test_init(&argc, &argv, NULL);
> +
> + cmdline = g_strdup_printf("-vnc none -device isa-ipmi");
> + qtest_start(cmdline);
> + qtest_irq_intercept_in(global_qtest, "ioapic");
> + qtest_add_func("/ipmi/local/kcs_base", test_kcs_base);
> + qtest_add_func("/ipmi/local/kcs_abort", test_kcs_abort);
> + qtest_add_func("/ipmi/local/kcs_enable_irq", test_enable_irq);
> + qtest_add_func("/ipmi/local/kcs_base_irq", test_kcs_base);
> + qtest_add_func("/ipmi/local/kcs_abort_irq", test_kcs_abort);
> + ret = g_test_run();
> + qtest_quit(global_qtest);
> +
> + return ret;
> +}
> --
> 1.8.3.1
>
>
[-- Attachment #2: Type: text/html, Size: 31324 bytes --]
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 11/16] ipmi: Add tests
2013-11-13 14:12 ` Bret Ketchum
@ 2013-11-13 20:51 ` Corey Minyard
0 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-13 20:51 UTC (permalink / raw)
To: Bret Ketchum, Corey Minyard; +Cc: qemu-devel
On 11/13/2013 08:12 AM, Bret Ketchum wrote:
> Having trouble with this patch (after the prior patches were
> successfully applied):
I was a couple of days behind and some other changes that came in
conflicted with this.
-corey
>
> git status
> # On branch master
> # Changes not staged for commit:
> # (use "git add <file>..." to update what will be committed)
> # (use "git checkout -- <file>..." to discard changes in working
> directory)
> #
> # modified: ../../../backends/baum.c
> # modified: ../../../backends/msmouse.c
> # modified: ../../../default-configs/i386-softmmu.mak
> # modified: ../../../default-configs/x86_64-softmmu.mak
> # modified: ../../../hw/Makefile.objs
> # modified: ../../../hw/misc/ivshmem.c
> # modified: ../../../include/hw/nvram/fw_cfg.h
> # modified: ../../../include/sysemu/char.h
> # modified: ../../../include/ui/console.h
> # modified: ../../../include/ui/qemu-spice.h
> # modified: ../../../qemu-char.c
> # modified: ../../../qemu-doc.texi
> # modified: ../../../qemu-options.hx
> # modified: ../../../spice-qemu-char.c
> # modified: ../../../ui/console.c
> #
> # Untracked files:
> # (use "git add <file>..." to include in what will be committed)
> #
> # ../../
> # ../../../hw/ipmi/
> no changes added to commit (use "git add" and/or "git commit -a")
> [
>
> git apply --verbos --check ../ipmi-patches/290712.mbox
> Checking patch tests/Makefile...
> error: while searching for:
> gcov-files-i386-y += hw/hd-geometry.c
> check-qtest-i386-y += tests/boot-order-test$(EXESUF)
> check-qtest-i386-y += tests/rtc-test$(EXESUF)
> check-qtest-i386-y += tests/i440fx-test$(EXESUF)
> check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
> check-qtest-x86_64-y = $(check-qtest-i386-y)
>
> error: patch failed: tests/Makefile:65
> error: tests/Makefile: patch does not apply
> Checking patch tests/ipmi-bt-test.c...
> Checking patch tests/ipmi-kcs-test.c...
>
>
>
> I believe the patch for tests/Makefile should look like:
>
> diff --git a/tests/Makefile b/tests/Makefile
> index f414f2c..0395cd4 100644
> --- a/tests/Makefile
> +++ b/tests/Makefile
> @@ -65,6 +65,8 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
> gcov-files-i386-y += hw/hd-geometry.c
> check-qtest-i386-y += tests/boot-order-test$(EXESUF)
> check-qtest-i386-y += tests/rtc-test$(EXESUF)
> +check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
> +check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
> check-qtest-i386-y += tests/i440fx-test$(EXESUF)
> check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
> check-qtest-i386-y += tests/qom-test$(EXESUF)
> @@ -194,6 +196,8 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
> tests/endianness-test$(EXESUF): tests/endianness-test.o
> tests/fdc-test$(EXESUF): tests/fdc-test.o
> tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
> +tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
> +tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
> tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
> tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
> tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
>
>
>
> On Tue, Nov 12, 2013 at 10:33 AM, Corey Minyard <minyard@acm.org
> <mailto:minyard@acm.org>> wrote:
>
> Test the KCS interface with a local BMC and a BT interface with an
> external BMC.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com
> <mailto:cminyard@mvista.com>>
> ---
> tests/Makefile | 4 +
> tests/ipmi-bt-test.c | 440
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> tests/ipmi-kcs-test.c | 294 +++++++++++++++++++++++++++++++++
> 3 files changed, 738 insertions(+)
> create mode 100644 tests/ipmi-bt-test.c
> create mode 100644 tests/ipmi-kcs-test.c
>
> diff --git a/tests/Makefile b/tests/Makefile
> index fa4c9f0..044e7a8 100644
> --- a/tests/Makefile
> +++ b/tests/Makefile
> @@ -65,6 +65,8 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
> gcov-files-i386-y += hw/hd-geometry.c
> check-qtest-i386-y += tests/boot-order-test$(EXESUF)
> check-qtest-i386-y += tests/rtc-test$(EXESUF)
> +check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
> +check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
> check-qtest-i386-y += tests/i440fx-test$(EXESUF)
> check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
> check-qtest-x86_64-y = $(check-qtest-i386-y)
> @@ -169,6 +171,8 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
> tests/endianness-test$(EXESUF): tests/endianness-test.o
> tests/fdc-test$(EXESUF): tests/fdc-test.o
> tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
> +tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
> +tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
> tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
> tests/boot-order-test$(EXESUF): tests/boot-order-test.o
> $(libqos-obj-y)
> tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
> diff --git a/tests/ipmi-bt-test.c b/tests/ipmi-bt-test.c
> new file mode 100644
> index 0000000..c1da325
> --- /dev/null
> +++ b/tests/ipmi-bt-test.c
> @@ -0,0 +1,440 @@
> +/*
> + * IPMI BT test cases, using the external interface for checking
> + *
> + * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com
> <mailto:cminyard@mvista.com>>
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> + * of this software and associated documentation files (the
> "Software"), to deal
> + * in the Software without restriction, including without
> limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense,
> and/or sell
> + * copies of the Software, and to permit persons to whom the
> Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include <sys/types.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <stdio.h>
> +
> +#include <sys/socket.h>
> +#include <netinet/in.h>
> +#include <netinet/ip.h>
> +#include <netinet/tcp.h>
> +
> +#include <glib.h>
> +
> +#include "libqtest.h"
> +#include "qemu-common.h"
> +
> +#define IPMI_IRQ 5
> +
> +#define IPMI_BT_BASE 0xe4
> +
> +#define IPMI_BT_CTLREG_CLR_WR_PTR 0
> +#define IPMI_BT_CTLREG_CLR_RD_PTR 1
> +#define IPMI_BT_CTLREG_H2B_ATN 2
> +#define IPMI_BT_CTLREG_B2H_ATN 3
> +#define IPMI_BT_CTLREG_SMS_ATN 4
> +#define IPMI_BT_CTLREG_H_BUSY 6
> +#define IPMI_BT_CTLREG_B_BUSY 7
> +
> +#define IPMI_BT_CTLREG_GET(b) ((bt_get_ctrlreg() >> (b)) & 1)
> +#define IPMI_BT_CTLREG_GET_H2B_ATN()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H2B_ATN)
> +#define IPMI_BT_CTLREG_GET_B2H_ATN()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B2H_ATN)
> +#define IPMI_BT_CTLREG_GET_SMS_ATN()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_SMS_ATN)
> +#define IPMI_BT_CTLREG_GET_H_BUSY()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H_BUSY)
> +#define IPMI_BT_CTLREG_GET_B_BUSY()
> IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B_BUSY)
> +
> +#define IPMI_BT_CTLREG_SET(b) bt_write_ctrlreg(1 << (b))
> +#define IPMI_BT_CTLREG_SET_CLR_WR_PTR() IPMI_BT_CTLREG_SET( \
> +
> IPMI_BT_CTLREG_CLR_WR_PTR)
> +#define IPMI_BT_CTLREG_SET_CLR_RD_PTR() IPMI_BT_CTLREG_SET( \
> +
> IPMI_BT_CTLREG_CLR_RD_PTR)
> +#define IPMI_BT_CTLREG_SET_H2B_ATN()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H2B_ATN)
> +#define IPMI_BT_CTLREG_SET_B2H_ATN()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_B2H_ATN)
> +#define IPMI_BT_CTLREG_SET_SMS_ATN()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_SMS_ATN)
> +#define IPMI_BT_CTLREG_SET_H_BUSY()
> IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H_BUSY)
> +
> +static int bt_ints_enabled;
> +
> +static uint8_t bt_get_ctrlreg(void)
> +{
> + return inb(IPMI_BT_BASE);
> +}
> +
> +static void bt_write_ctrlreg(uint8_t val)
> +{
> + outb(IPMI_BT_BASE, val);
> +}
> +
> +static uint8_t bt_get_buf(void)
> +{
> + return inb(IPMI_BT_BASE + 1);
> +}
> +
> +static void bt_write_buf(uint8_t val)
> +{
> + outb(IPMI_BT_BASE + 1, val);
> +}
> +
> +static uint8_t bt_get_irqreg(void)
> +{
> + return inb(IPMI_BT_BASE + 2);
> +}
> +
> +static void bt_write_irqreg(uint8_t val)
> +{
> + outb(IPMI_BT_BASE + 2, val);
> +}
> +
> +static void bt_wait_b_busy(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_BT_CTLREG_GET_B_BUSY() != 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +static void bt_wait_b2h_atn(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_BT_CTLREG_GET_B2H_ATN() == 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +
> +static int emu_lfd;
> +static int emu_fd;
> +static in_port_t emu_port;
> +static uint8_t inbuf[100];
> +static unsigned int inbuf_len;
> +static unsigned int inbuf_pos;
> +static int last_was_aa;
> +
> +static void read_emu_data(void)
> +{
> + fd_set readfds;
> + int rv;
> + struct timeval tv;
> +
> + FD_ZERO(&readfds);
> + FD_SET(emu_fd, &readfds);
> + tv.tv_sec = 10;
> + tv.tv_usec = 0;
> + rv = select(emu_fd + 1, &readfds, NULL, NULL, &tv);
> + if (rv == -1) {
> + perror("select");
> + }
> + g_assert(rv == 1);
> + rv = read(emu_fd, inbuf, sizeof(inbuf));
> + if (rv == -1) {
> + perror("read");
> + }
> + g_assert(rv > 0);
> + inbuf_len = rv;
> + inbuf_pos = 0;
> +}
> +
> +static void write_emu_msg(uint8_t *msg, unsigned int len)
> +{
> + int rv;
> +
> +#ifdef DEBUG_TEST
> + {
> + unsigned int i;
> + printf("sending:");
> + for (i = 0; i < len; i++) {
> + printf(" %2.2x", msg[i]);
> + }
> + printf("\n");
> + }
> +#endif
> + rv = write(emu_fd, msg, len);
> + g_assert(rv == len);
> +}
> +
> +static void get_emu_msg(uint8_t *msg, unsigned int *len)
> +{
> + unsigned int outpos = 0;
> +
> + for (;;) {
> + while (inbuf_pos < inbuf_len) {
> + uint8_t ch = inbuf[inbuf_pos++];
> +
> + g_assert(outpos < *len);
> + if (last_was_aa) {
> + assert(ch & 0x10);
> + msg[outpos++] = ch & ~0x10;
> + last_was_aa = 0;
> + } else if (ch == 0xaa) {
> + last_was_aa = 1;
> + } else {
> + msg[outpos++] = ch;
> + if ((ch == 0xa0) || (ch == 0xa1)) {
> + /* Message complete */
> + *len = outpos;
> + goto done;
> + }
> + }
> + }
> + read_emu_data();
> + }
> + done:
> +#ifdef DEBUG_TEST
> + {
> + unsigned int i;
> + printf("Msg:");
> + for (i = 0; i < outpos; i++) {
> + printf(" %2.2x", msg[i]);
> + }
> + printf("\n");
> + }
> +#endif
> + return;
> +}
> +
> +static uint8_t
> +ipmb_checksum(const unsigned char *data, int size, unsigned char
> start)
> +{
> + unsigned char csum = start;
> +
> + for (; size > 0; size--, data++) {
> + csum += *data;
> + }
> + return csum;
> +}
> +
> +static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
> +static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00,
> 0x00, 0x00,
> + 0x02, 0x09, 0x00, 0x00, 0x00,
> 0x00, 0x00 };
> +
> +static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
> +static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
> +static uint8_t enable_irq_cmd[] = { 0x05, 0xa1 };
> +
> +static void emu_msg_handler(void)
> +{
> + uint8_t msg[100];
> + unsigned int msg_len = sizeof(msg);
> +
> + get_emu_msg(msg, &msg_len);
> + g_assert(msg_len >= 5);
> + g_assert(msg[msg_len - 1] == 0xa0);
> + msg_len--;
> + g_assert(ipmb_checksum(msg, msg_len, 0) == 0);
> + msg_len--;
> + if ((msg[1] == get_dev_id_cmd[0]) && (msg[2] ==
> get_dev_id_cmd[1])) {
> + memcpy(msg + 1, get_dev_id_rsp, sizeof(get_dev_id_rsp));
> + msg_len = sizeof(get_dev_id_rsp) + 1;
> + msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
> + msg_len++;
> + msg[msg_len++] = 0xa0;
> + write_emu_msg(msg, msg_len);
> + } else if ((msg[1] == set_bmc_globals_cmd[0]) &&
> + (msg[2] == set_bmc_globals_cmd[1])) {
> + memcpy(msg + 1, set_bmc_globals_rsp,
> sizeof(set_bmc_globals_rsp));
> + msg_len = sizeof(set_bmc_globals_rsp) + 1;
> + msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
> + msg_len++;
> + msg[msg_len++] = 0xa0;
> + write_emu_msg(msg, msg_len);
> + write_emu_msg(enable_irq_cmd, sizeof(enable_irq_cmd));
> + } else {
> + g_assert(0);
> + }
> +}
> +
> +static void bt_cmd(uint8_t *cmd, unsigned int cmd_len,
> + uint8_t *rsp, unsigned int *rsp_len)
> +{
> + unsigned int i, len, j = 0;
> + uint8_t seq = 5;
> +
> + /* Should be idle */
> + g_assert(bt_get_ctrlreg() == 0);
> +
> + bt_wait_b_busy();
> + IPMI_BT_CTLREG_SET_CLR_WR_PTR();
> + bt_write_buf(cmd_len + 1);
> + bt_write_buf(cmd[0]);
> + bt_write_buf(seq);
> + for (i = 1; i < cmd_len; i++) {
> + bt_write_buf(cmd[i]);
> + }
> + IPMI_BT_CTLREG_SET_H2B_ATN();
> +
> + emu_msg_handler(); /* We should get a message on the socket
> here. */
> +
> + bt_wait_b2h_atn();
> + if (bt_ints_enabled) {
> + g_assert((bt_get_irqreg() & 0x02) == 0x02);
> + g_assert(get_irq(IPMI_IRQ));
> + bt_write_irqreg(0x03);
> + } else {
> + g_assert(!get_irq(IPMI_IRQ));
> + }
> + IPMI_BT_CTLREG_SET_H_BUSY();
> + IPMI_BT_CTLREG_SET_B2H_ATN();
> + IPMI_BT_CTLREG_SET_CLR_RD_PTR();
> + len = bt_get_buf();
> + g_assert(len >= 4);
> + rsp[0] = bt_get_buf();
> + assert(bt_get_buf() == seq);
> + len--;
> + for (j = 1; j < len; j++) {
> + rsp[j] = bt_get_buf();
> + }
> + IPMI_BT_CTLREG_SET_H_BUSY();
> + *rsp_len = j;
> +}
> +
> +
> +/*
> + * We should get a connect request and a short message with
> capabilities.
> + */
> +static void test_connect(void)
> +{
> + fd_set readfds;
> + int rv;
> + int val;
> + struct timeval tv;
> + uint8_t msg[100];
> + unsigned int msglen;
> + static uint8_t exp1[] = { 0xff, 0x01, 0xa1 }; /* A protocol
> version */
> + static uint8_t exp2[] = { 0x08, 0x1f, 0xa1 }; /* A
> capabilities cmd */
> + static uint8_t exp3[] = { 0x04, 0xa1 }; /* A reset is reported */
> +
> + FD_ZERO(&readfds);
> + FD_SET(emu_lfd, &readfds);
> + tv.tv_sec = 10;
> + tv.tv_usec = 0;
> + rv = select(emu_lfd + 1, &readfds, NULL, NULL, &tv);
> + g_assert(rv == 1);
> + emu_fd = accept(emu_lfd, NULL, 0);
> + if (emu_fd < 0) {
> + perror("accept");
> + }
> + g_assert(emu_fd >= 0);
> +
> + val = 1;
> + rv = setsockopt(emu_fd, IPPROTO_TCP, TCP_NODELAY, &val,
> sizeof(val));
> + g_assert(rv != -1);
> +
> + /* Report our version */
> + write_emu_msg(exp1, sizeof(exp1));
> +
> + /* Validate that we get the info we expect. */
> + msglen = sizeof(msg);
> + get_emu_msg(msg, &msglen);
> + g_assert(msglen == sizeof(exp1));
> + g_assert(memcmp(msg, exp1, msglen) == 0);
> + msglen = sizeof(msg);
> + get_emu_msg(msg, &msglen);
> + g_assert(msglen == sizeof(exp2));
> + g_assert(memcmp(msg, exp2, msglen) == 0);
> + msglen = sizeof(msg);
> + get_emu_msg(msg, &msglen);
> + g_assert(msglen == sizeof(exp3));
> + g_assert(memcmp(msg, exp3, msglen) == 0);
> +}
> +
> +/*
> + * Send a get_device_id to do a basic test.
> + */
> +static void test_bt_base(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + bt_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
> + g_assert(rsplen == sizeof(get_dev_id_rsp));
> + g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
> +}
> +
> +/*
> + * Enable IRQs for the interface.
> + */
> +static void test_enable_irq(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + bt_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp,
> &rsplen);
> + g_assert(rsplen == sizeof(set_bmc_globals_rsp));
> + g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
> + bt_write_irqreg(0x01);
> + bt_ints_enabled = 1;
> +}
> +
> +/*
> + * Create a local TCP socket with any port, then save off the
> port we got.
> + */
> +static void open_socket(void)
> +{
> + struct sockaddr_in myaddr;
> + socklen_t addrlen;
> +
> + myaddr.sin_family = AF_INET;
> + myaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
> + myaddr.sin_port = 0;
> + emu_lfd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
> + if (emu_lfd == -1) {
> + perror("socket");
> + exit(1);
> + }
> + if (bind(emu_lfd, (struct sockaddr *) &myaddr,
> sizeof(myaddr)) == -1) {
> + perror("bind");
> + exit(1);
> + }
> + addrlen = sizeof(myaddr);
> + if (getsockname(emu_lfd, (struct sockaddr *) &myaddr ,
> &addrlen) == -1) {
> + perror("getsockname");
> + exit(1);
> + }
> + emu_port = ntohs(myaddr.sin_port);
> + assert(listen(emu_lfd, 1) != -1);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + const char *arch = qtest_get_arch();
> + char *cmdline;
> + int ret;
> +
> + /* Check architecture */
> + if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
> + g_test_message("Skipping test for non-x86\n");
> + return 0;
> + }
> +
> + open_socket();
> +
> + /* Run the tests */
> + g_test_init(&argc, &argv, NULL);
> +
> + cmdline = g_strdup_printf("-vnc none"
> + " -chardev
> socket,id=ipmi0,host=localhost,port=%d,reconnect=10"
> + " -device isa-ipmi,interface=bt,chardev=ipmi0", emu_port);
> + qtest_start(cmdline);
> + qtest_irq_intercept_in(global_qtest, "ioapic");
> + qtest_add_func("/ipmi/extern/connect", test_connect);
> + qtest_add_func("/ipmi/extern/bt_base", test_bt_base);
> + qtest_add_func("/ipmi/extern/bt_enable_irq", test_enable_irq);
> + qtest_add_func("/ipmi/extern/bt_base_irq", test_bt_base);
> + ret = g_test_run();
> + qtest_quit(global_qtest);
> +
> + return ret;
> +}
> diff --git a/tests/ipmi-kcs-test.c b/tests/ipmi-kcs-test.c
> new file mode 100644
> index 0000000..e2e1bdb
> --- /dev/null
> +++ b/tests/ipmi-kcs-test.c
> @@ -0,0 +1,294 @@
> +/*
> + * IPMI KCS test cases, using the local interface.
> + *
> + * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com
> <mailto:cminyard@mvista.com>>
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> + * of this software and associated documentation files (the
> "Software"), to deal
> + * in the Software without restriction, including without
> limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense,
> and/or sell
> + * copies of the Software, and to permit persons to whom the
> Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include <stdint.h>
> +#include <string.h>
> +#include <stdio.h>
> +
> +#include <glib.h>
> +
> +#include "libqtest.h"
> +
> +#define IPMI_IRQ 5
> +
> +#define IPMI_KCS_BASE 0xca2
> +
> +#define IPMI_KCS_STATUS_ABORT 0x60
> +#define IPMI_KCS_CMD_WRITE_START 0x61
> +#define IPMI_KCS_CMD_WRITE_END 0x62
> +#define IPMI_KCS_CMD_READ 0x68
> +
> +#define IPMI_KCS_ABORTED_BY_CMD 0x01
> +
> +#define IPMI_KCS_CMDREG_GET_STATE() ((kcs_get_cmdreg() >> 6) & 3)
> +#define IPMI_KCS_STATE_IDLE 0
> +#define IPMI_KCS_STATE_READ 1
> +#define IPMI_KCS_STATE_WRITE 2
> +#define IPMI_KCS_STATE_ERROR 3
> +#define IPMI_KCS_CMDREG_GET_CD() ((kcs_get_cmdreg() >> 3) & 1)
> +#define IPMI_KCS_CMDREG_GET_ATN() ((kcs_get_cmdreg() >> 2) & 1)
> +#define IPMI_KCS_CMDREG_GET_IBF() ((kcs_get_cmdreg() >> 1) & 1)
> +#define IPMI_KCS_CMDREG_GET_OBF() ((kcs_get_cmdreg() >> 0) & 1)
> +
> +static int kcs_ints_enabled;
> +
> +static uint8_t kcs_get_cmdreg(void)
> +{
> + return inb(IPMI_KCS_BASE + 1);
> +}
> +
> +static void kcs_write_cmdreg(uint8_t val)
> +{
> + outb(IPMI_KCS_BASE + 1, val);
> +}
> +
> +static uint8_t kcs_get_datareg(void)
> +{
> + return inb(IPMI_KCS_BASE);
> +}
> +
> +static void kcs_write_datareg(uint8_t val)
> +{
> + outb(IPMI_KCS_BASE, val);
> +}
> +
> +static void kcs_wait_ibf(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_KCS_CMDREG_GET_IBF() != 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +static void kcs_wait_obf(void)
> +{
> + unsigned int count = 1000;
> + while (IPMI_KCS_CMDREG_GET_OBF() == 0) {
> + g_assert(--count != 0);
> + }
> +}
> +
> +static void kcs_clear_obf(void)
> +{
> + if (kcs_ints_enabled) {
> + g_assert(get_irq(IPMI_IRQ));
> + } else {
> + g_assert(!get_irq(IPMI_IRQ));
> + }
> + g_assert(IPMI_KCS_CMDREG_GET_OBF() == 1);
> + kcs_get_datareg();
> + g_assert(IPMI_KCS_CMDREG_GET_OBF() == 0);
> + g_assert(!get_irq(IPMI_IRQ));
> +}
> +
> +static void kcs_check_state(uint8_t state)
> +{
> + g_assert(IPMI_KCS_CMDREG_GET_STATE() == state);
> +}
> +
> +static void kcs_cmd(uint8_t *cmd, unsigned int cmd_len,
> + uint8_t *rsp, unsigned int *rsp_len)
> +{
> + unsigned int i, j = 0;
> +
> + /* Should be idle */
> + g_assert(kcs_get_cmdreg() == 0);
> +
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + for (i = 0; i < cmd_len; i++) {
> + kcs_write_datareg(cmd[i]);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + }
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + kcs_write_datareg(0);
> + next_read_byte:
> + kcs_wait_ibf();
> + switch (IPMI_KCS_CMDREG_GET_STATE()) {
> + case IPMI_KCS_STATE_READ:
> + kcs_wait_obf();
> + g_assert(j < *rsp_len);
> + rsp[j++] = kcs_get_datareg();
> + kcs_write_datareg(IPMI_KCS_CMD_READ);
> + goto next_read_byte;
> + break;
> +
> + case IPMI_KCS_STATE_IDLE:
> + kcs_wait_obf();
> + kcs_get_datareg();
> + break;
> +
> + default:
> + g_assert(0);
> + }
> + *rsp_len = j;
> +}
> +
> +static void kcs_abort(uint8_t *cmd, unsigned int cmd_len,
> + uint8_t *rsp, unsigned int *rsp_len)
> +{
> + unsigned int i, j = 0;
> + unsigned int retries = 4;
> +
> + /* Should be idle */
> + g_assert(kcs_get_cmdreg() == 0);
> +
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + for (i = 0; i < cmd_len; i++) {
> + kcs_write_datareg(cmd[i]);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + }
> + kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
> + kcs_wait_ibf();
> + kcs_check_state(IPMI_KCS_STATE_WRITE);
> + kcs_clear_obf();
> + kcs_write_datareg(0);
> + kcs_wait_ibf();
> + switch (IPMI_KCS_CMDREG_GET_STATE()) {
> + case IPMI_KCS_STATE_READ:
> + kcs_wait_obf();
> + g_assert(j < *rsp_len);
> + rsp[j++] = kcs_get_datareg();
> + kcs_write_datareg(IPMI_KCS_CMD_READ);
> + break;
> +
> + default:
> + g_assert(0);
> + }
> +
> + /* Start the abort here */
> + retry_abort:
> + g_assert(retries > 0);
> +
> + kcs_wait_ibf();
> + kcs_write_cmdreg(IPMI_KCS_STATUS_ABORT);
> + kcs_wait_ibf();
> + kcs_clear_obf();
> + kcs_write_datareg(0);
> + kcs_wait_ibf();
> + if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_READ) {
> + retries--;
> + goto retry_abort;
> + }
> + kcs_wait_obf();
> + rsp[0] = kcs_get_datareg();
> + kcs_write_datareg(IPMI_KCS_CMD_READ);
> + kcs_wait_ibf();
> + if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_IDLE) {
> + retries--;
> + goto retry_abort;
> + }
> + kcs_wait_obf();
> + kcs_clear_obf();
> +
> + *rsp_len = j;
> +}
> +
> +
> +static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
> +static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00,
> 0x00, 0x00,
> + 0x02, 0x07, 0x00, 0x00, 0x00,
> 0x00, 0x00 };
> +
> +/*
> + * Send a get_device_id to do a basic test.
> + */
> +static void test_kcs_base(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + kcs_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
> + g_assert(rsplen == sizeof(get_dev_id_rsp));
> + g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
> +}
> +
> +/*
> + * Abort a kcs operation while reading
> + */
> +static void test_kcs_abort(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + kcs_abort(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
> + g_assert(rsp[0] == IPMI_KCS_ABORTED_BY_CMD);
> +}
> +
> +static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
> +static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
> +
> +/*
> + * Enable interrupts
> + */
> +static void test_enable_irq(void)
> +{
> + uint8_t rsp[20];
> + unsigned int rsplen = sizeof(rsp);
> +
> + kcs_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd),
> rsp, &rsplen);
> + g_assert(rsplen == sizeof(set_bmc_globals_rsp));
> + g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
> + kcs_ints_enabled = 1;
> +}
> +
> +int main(int argc, char **argv)
> +{
> + const char *arch = qtest_get_arch();
> + char *cmdline;
> + int ret;
> +
> + /* Check architecture */
> + if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
> + g_test_message("Skipping test for non-x86\n");
> + return 0;
> + }
> +
> + /* Run the tests */
> + g_test_init(&argc, &argv, NULL);
> +
> + cmdline = g_strdup_printf("-vnc none -device isa-ipmi");
> + qtest_start(cmdline);
> + qtest_irq_intercept_in(global_qtest, "ioapic");
> + qtest_add_func("/ipmi/local/kcs_base", test_kcs_base);
> + qtest_add_func("/ipmi/local/kcs_abort", test_kcs_abort);
> + qtest_add_func("/ipmi/local/kcs_enable_irq", test_enable_irq);
> + qtest_add_func("/ipmi/local/kcs_base_irq", test_kcs_base);
> + qtest_add_func("/ipmi/local/kcs_abort_irq", test_kcs_abort);
> + ret = g_test_run();
> + qtest_quit(global_qtest);
> +
> + return ret;
> +}
> --
> 1.8.3.1
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 12/16] ipmi: Add documentation
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (10 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 11/16] ipmi: Add tests Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-13 16:08 ` Bret Ketchum
2013-11-12 16:33 ` [Qemu-devel] [PATCH 13/16] ipmi: Add migration capability to the IPMI device Corey Minyard
` (3 subsequent siblings)
15 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
Add some basic documentation for the IPMI device.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
qemu-options.hx | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 5bcfaa0..500d7c8 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -327,6 +327,41 @@ Add device @var{driver}. @var{prop}=@var{value} sets driver
properties. Valid properties depend on the driver. To get help on
possible drivers and properties, use @code{-device help} and
@code{-device @var{driver},help}.
+
+Some drivers are:
+@item -device isa-ipmi[,interface=kcs|bt][,iobase=@var{val}][,irq=@var{val}][,slave_addr=@var{val}][,chardev=name]
+
+Add an IPMI device. This also adds a corresponding SMBIOS entry to the
+SMBIOS tables for x86. The following options are handled:
+@table @option
+@item interface=kcs|bt
+Define the interface type to use. Currently the IPMI-defined KCS and
+BT interfaces are handled. The default is KCS.
+@item iobase=@var{val}
+Define the I/O address of the interface. The default is 0xca0 for KCS
+and 0xe4 for BT.
+@item irq=@var{val}
+Define the interrupt to use. The default is 5. To disable interrupts,
+set this to 0.
+@item slave_addr=@var{val}
+The IPMI slave address to use for the BMC. The default is 0x20.
+@item chardev=name
+If a chardev is not specified, the IPMI driver uses a built-in baseboard
+management controller (BMC) simulator. It provides a basic BMC with a
+watchdog timer and associated sensor.
+
+If a chardev is specified, A connection is made to an external BMC
+simulator. If you do this, it is strongly recommended that you use
+the "reconnect=" chardev option to reconnect to the simulator if the
+connection is lost. Note that if this is not used carefully, it can
+be a security issue, as the interface has the ability to send resets,
+NMIs, and power off the VM. It's best if QEMU makes a connection to
+an external simulator running on a secure port on localhost, so
+neither the simulator nor QEMU is exposed to any outside network.
+
+See the "lanserv/README.vm" file in the OpenIPMI library for more
+details on the external interface.
+@end table
ETEXI
DEF("name", HAS_ARG, QEMU_OPTION_name,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 12/16] ipmi: Add documentation
2013-11-12 16:33 ` [Qemu-devel] [PATCH 12/16] ipmi: Add documentation Corey Minyard
@ 2013-11-13 16:08 ` Bret Ketchum
0 siblings, 0 replies; 42+ messages in thread
From: Bret Ketchum @ 2013-11-13 16:08 UTC (permalink / raw)
To: Corey Minyard; +Cc: Corey Minyard, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2496 bytes --]
The actual default I/O address for KCS is 0xca2.
On Tue, Nov 12, 2013 at 10:33 AM, Corey Minyard <minyard@acm.org> wrote:
> Add some basic documentation for the IPMI device.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> ---
> qemu-options.hx | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 5bcfaa0..500d7c8 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -327,6 +327,41 @@ Add device @var{driver}. @var{prop}=@var{value} sets
> driver
> properties. Valid properties depend on the driver. To get help on
> possible drivers and properties, use @code{-device help} and
> @code{-device @var{driver},help}.
> +
> +Some drivers are:
> +@item -device
> isa-ipmi[,interface=kcs|bt][,iobase=@var{val}][,irq=@var{val}][,slave_addr=@var{val}][,chardev=name]
> +
> +Add an IPMI device. This also adds a corresponding SMBIOS entry to the
> +SMBIOS tables for x86. The following options are handled:
> +@table @option
> +@item interface=kcs|bt
> +Define the interface type to use. Currently the IPMI-defined KCS and
> +BT interfaces are handled. The default is KCS.
> +@item iobase=@var{val}
> +Define the I/O address of the interface. The default is 0xca0 for KCS
> +and 0xe4 for BT.
> +@item irq=@var{val}
> +Define the interrupt to use. The default is 5. To disable interrupts,
> +set this to 0.
> +@item slave_addr=@var{val}
> +The IPMI slave address to use for the BMC. The default is 0x20.
> +@item chardev=name
> +If a chardev is not specified, the IPMI driver uses a built-in baseboard
> +management controller (BMC) simulator. It provides a basic BMC with a
> +watchdog timer and associated sensor.
> +
> +If a chardev is specified, A connection is made to an external BMC
> +simulator. If you do this, it is strongly recommended that you use
> +the "reconnect=" chardev option to reconnect to the simulator if the
> +connection is lost. Note that if this is not used carefully, it can
> +be a security issue, as the interface has the ability to send resets,
> +NMIs, and power off the VM. It's best if QEMU makes a connection to
> +an external simulator running on a secure port on localhost, so
> +neither the simulator nor QEMU is exposed to any outside network.
> +
> +See the "lanserv/README.vm" file in the OpenIPMI library for more
> +details on the external interface.
> +@end table
> ETEXI
>
> DEF("name", HAS_ARG, QEMU_OPTION_name,
> --
> 1.8.3.1
>
>
[-- Attachment #2: Type: text/html, Size: 3114 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 13/16] ipmi: Add migration capability to the IPMI device.
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (11 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 12/16] ipmi: Add documentation Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg Corey Minyard
` (2 subsequent siblings)
15 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
Signed-off-by: Corey Minyard <cminyard@mvista.com
---
hw/ipmi/ipmi.c | 17 +++++++++++++++++
hw/ipmi/ipmi.h | 2 ++
hw/ipmi/ipmi_bt.c | 14 ++++++++++++++
hw/ipmi/ipmi_extern.c | 42 ++++++++++++++++++++++++++++++++++++++----
hw/ipmi/ipmi_kcs.c | 15 +++++++++++++++
hw/ipmi/ipmi_sim.c | 30 ++++++++++++++++++++++++++++++
hw/ipmi/isa_ipmi.c | 12 ++++++++++++
7 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c
index 21560a9..5f04085 100644
--- a/hw/ipmi/ipmi.c
+++ b/hw/ipmi/ipmi.c
@@ -150,6 +150,23 @@ int ipmi_bmc_init(IPMIBmc *s)
return 0;
}
+const VMStateDescription vmstate_IPMIInterface = {
+ .name = TYPE_IPMI_INTERFACE,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL(obf_irq_set, IPMIInterface),
+ VMSTATE_BOOL(atn_irq_set, IPMIInterface),
+ VMSTATE_BOOL(use_irq, IPMIInterface),
+ VMSTATE_BOOL(irqs_enabled, IPMIInterface),
+ VMSTATE_UINT32(outpos, IPMIInterface),
+ VMSTATE_UINT32(outlen, IPMIInterface),
+ VMSTATE_VBUFFER_UINT32(inmsg, IPMIInterface, 1, NULL, 0, inlen),
+ VMSTATE_BOOL(write_end, IPMIInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static TypeInfo ipmi_bmc_type_info = {
.name = TYPE_IPMI_BMC,
.parent = TYPE_OBJECT,
diff --git a/hw/ipmi/ipmi.h b/hw/ipmi/ipmi.h
index 8838023..a7cd4a3 100644
--- a/hw/ipmi/ipmi.h
+++ b/hw/ipmi/ipmi.h
@@ -187,6 +187,8 @@ typedef struct IPMIInterfaceClass {
unsigned char *rsp, unsigned int rsp_len);
} IPMIInterfaceClass;
+extern const VMStateDescription vmstate_IPMIInterface;
+
int ipmi_interface_init(IPMIInterface *s);
void ipmi_interface_reset(IPMIInterface *s);
diff --git a/hw/ipmi/ipmi_bt.c b/hw/ipmi/ipmi_bt.c
index ec256f4..b7ffdcf 100644
--- a/hw/ipmi/ipmi_bt.c
+++ b/hw/ipmi/ipmi_bt.c
@@ -327,6 +327,19 @@ static void ipmi_bt_set_atn(IPMIInterface *s, int val, int irq)
}
}
+static const VMStateDescription vmstate_ipmi_bt = {
+ .name = TYPE_IPMI_INTERFACE_BT,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(control_reg, IPMIBtInterface),
+ VMSTATE_UINT8(mask_reg, IPMIBtInterface),
+ VMSTATE_UINT8(waiting_rsp, IPMIBtInterface),
+ VMSTATE_UINT8(waiting_seq, IPMIBtInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static int ipmi_bt_init(IPMIInterface *s)
{
IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
@@ -337,6 +350,7 @@ static int ipmi_bt_init(IPMIInterface *s)
s->io_length = 3;
memory_region_init_io(&s->io, OBJECT(s), &ipmi_bt_io_ops, bt, "ipmi-bt", 3);
+ vmstate_register(NULL, 0, &vmstate_ipmi_bt, bt);
return 0;
}
diff --git a/hw/ipmi/ipmi_extern.c b/hw/ipmi/ipmi_extern.c
index 1cd7c11..d66797d 100644
--- a/hw/ipmi/ipmi_extern.c
+++ b/hw/ipmi/ipmi_extern.c
@@ -63,10 +63,10 @@ typedef struct IPMIExternBmc {
unsigned char inbuf[MAX_IPMI_MSG_SIZE + 2];
unsigned int inpos;
- int in_escape;
- int in_too_many;
- int waiting_rsp;
- int sending_cmd;
+ bool in_escape;
+ bool in_too_many;
+ bool waiting_rsp;
+ bool sending_cmd;
unsigned char outbuf[(MAX_IPMI_MSG_SIZE + 2) * 2 + 1];
unsigned int outpos;
@@ -442,6 +442,39 @@ static void ipmi_extern_handle_reset(IPMIBmc *b)
ipmi_unlock(s);
}
+static int ipmi_extern_post_migrate(void *opaque, int version_id)
+{
+ IPMIExternBmc *es = opaque;
+
+ /*
+ * We don't directly restore waiting_rsp, Instead, we return an
+ * error on the interface if a response was being waited for.
+ */
+ if (es->waiting_rsp) {
+ IPMIInterface *s = es->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ es->waiting_rsp = 0;
+ es->inbuf[1] = es->outbuf[1] | 0x04;
+ es->inbuf[2] = es->outbuf[2];
+ es->inbuf[3] = IPMI_CC_BMC_INIT_IN_PROGRESS;
+ k->handle_rsp(s, es->outbuf[0], es->inbuf + 1, 3);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_ipmi_extern = {
+ .name = TYPE_IPMI_BMC_EXTERN,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = ipmi_extern_post_migrate,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL(send_reset, IPMIExternBmc),
+ VMSTATE_BOOL(waiting_rsp, IPMIExternBmc),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static int ipmi_extern_init(IPMIBmc *b)
{
IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
@@ -449,6 +482,7 @@ static int ipmi_extern_init(IPMIBmc *b)
es->extern_timer = timer_new(QEMU_CLOCK_REALTIME, SCALE_NS,
extern_timeout, es);
qemu_chr_add_handlers(es->parent.chr, can_receive, receive, chr_event, es);
+ vmstate_register(NULL, 0, &vmstate_ipmi_extern, es);
return 0;
}
diff --git a/hw/ipmi/ipmi_kcs.c b/hw/ipmi/ipmi_kcs.c
index 056a369..81f0709 100644
--- a/hw/ipmi/ipmi_kcs.c
+++ b/hw/ipmi/ipmi_kcs.c
@@ -304,6 +304,20 @@ static void ipmi_kcs_set_atn(IPMIInterface *s, int val, int irq)
}
}
+static const VMStateDescription vmstate_ipmi_kcs = {
+ .name = TYPE_IPMI_INTERFACE_KCS,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(status_reg, IPMIKcsInterface),
+ VMSTATE_UINT8(data_out_reg, IPMIKcsInterface),
+ VMSTATE_INT16(data_in_reg, IPMIKcsInterface),
+ VMSTATE_INT16(cmd_reg, IPMIKcsInterface),
+ VMSTATE_UINT8(waiting_rsp, IPMIKcsInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static int ipmi_kcs_init(IPMIInterface *s)
{
IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
@@ -315,6 +329,7 @@ static int ipmi_kcs_init(IPMIInterface *s)
memory_region_init_io(&s->io, OBJECT(s), &ipmi_kcs_io_ops, kcs,
"ipmi-kcs", 2);
+ vmstate_register(NULL, 0, &vmstate_ipmi_kcs, kcs);
return 0;
}
diff --git a/hw/ipmi/ipmi_sim.c b/hw/ipmi/ipmi_sim.c
index 327a01c..fc124a7 100644
--- a/hw/ipmi/ipmi_sim.c
+++ b/hw/ipmi/ipmi_sim.c
@@ -1481,6 +1481,34 @@ static const uint8_t init_sdrs[] = {
0xff, 0xff, 0x00, 0x00, 0x00
};
+static const VMStateDescription vmstate_ipmi_sim = {
+ .name = TYPE_IPMI_BMC_SIMULATOR,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(bmc_global_enables, IPMISimBmc),
+ VMSTATE_UINT8(msg_flags, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_initialized, IPMISimBmc),
+ VMSTATE_UINT8(watchdog_use, IPMISimBmc),
+ VMSTATE_UINT8(watchdog_action, IPMISimBmc),
+ VMSTATE_UINT8(watchdog_pretimeout, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_expired, IPMISimBmc),
+ VMSTATE_UINT16(watchdog_timeout, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_running, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_preaction_ran, IPMISimBmc),
+ VMSTATE_INT64(watchdog_expiry, IPMISimBmc),
+ VMSTATE_UINT8_ARRAY(evtbuf, IPMISimBmc, 16),
+ VMSTATE_UINT8(sensors[IPMI_WATCHDOG_SENSOR].status, IPMISimBmc),
+ VMSTATE_UINT8(sensors[IPMI_WATCHDOG_SENSOR].reading, IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].states, IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].assert_states, IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].deassert_states,
+ IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].assert_enable, IPMISimBmc),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static int ipmi_sim_init(IPMIBmc *b)
{
unsigned int i;
@@ -1526,6 +1554,8 @@ static int ipmi_sim_init(IPMIBmc *b)
ss->timer = timer_new(QEMU_CLOCK_VIRTUAL, SCALE_NS, ipmi_timeout, ss);
+ vmstate_register(NULL, 0, &vmstate_ipmi_sim, ss);
+
return 0;
}
diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
index 0242a41..b38c846 100644
--- a/hw/ipmi/isa_ipmi.c
+++ b/hw/ipmi/isa_ipmi.c
@@ -124,12 +124,24 @@ static Property ipmi_isa_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static const VMStateDescription vmstate_isa_ipmi = {
+ .name = TYPE_ISA_IPMI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_POINTER(intf, ISAIPMIDevice, vmstate_IPMIInterface,
+ IPMIInterface *),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ipmi_isa_realizefn;
dc->reset = ipmi_isa_reset;
+ dc->vmsd = &vmstate_isa_ipmi;
dc->props = ipmi_isa_properties;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (12 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 13/16] ipmi: Add migration capability to the IPMI device Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-13 14:31 ` Bret Ketchum
2013-11-14 7:30 ` Michael S. Tsirkin
2013-11-12 16:33 ` [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry Corey Minyard
2013-11-12 16:33 ` [Qemu-devel] [PATCH 16/16] ipmi: Add SMBIOS table entry Corey Minyard
15 siblings, 2 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, Andreas Färber,
Michael S. Tsirkin
Postpone the addition of the ACPI and SMBIOS tables until after
device initialization. This allows devices to add entries to these
tables.
Signed-off-by: Corey Minyard <cminyard@mvsita.com>
---
hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index dee409d..765c95e 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
static FWCfgState *bochs_bios_init(void)
{
FWCfgState *fw_cfg;
- uint8_t *smbios_table;
- size_t smbios_len;
uint64_t *numa_fw_cfg;
int i, j;
unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
@@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
- acpi_tables, acpi_tables_len);
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
- smbios_table = smbios_get_table(&smbios_len);
- if (smbios_table)
- fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
- smbios_table, smbios_len);
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
&e820_table, sizeof(e820_table));
@@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
}
}
+struct pc_bios_post_init {
+ Notifier post_init;
+ void *fw_cfg;
+};
+
+/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
+ * This gives devices a chance to add to those tables.
+ */
+static void pc_bios_post_initfn(Notifier *n, void *opaque)
+{
+ struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
+ post_init);
+ uint8_t *smbios_table;
+ size_t smbios_len;
+
+ fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
+ acpi_tables, acpi_tables_len);
+ smbios_table = smbios_get_table(&smbios_len);
+ if (smbios_table)
+ fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
+ smbios_table, smbios_len);
+}
+
+static struct pc_bios_post_init post_init;
+
FWCfgState *pc_memory_init(MemoryRegion *system_memory,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
}
guest_info->fw_cfg = fw_cfg;
+
+ post_init.fw_cfg = fw_cfg;
+ post_init.post_init.notify = pc_bios_post_initfn;
+ qemu_add_machine_init_done_notifier(&post_init.post_init);
+
return fw_cfg;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-12 16:33 ` [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg Corey Minyard
@ 2013-11-13 14:31 ` Bret Ketchum
2013-11-14 7:30 ` Michael S. Tsirkin
1 sibling, 0 replies; 42+ messages in thread
From: Bret Ketchum @ 2013-11-13 14:31 UTC (permalink / raw)
To: Corey Minyard; +Cc: Corey Minyard, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 6703 bytes --]
Had trouble with this one:
git apply --verbos --check ../ipmi-patches/290708.mbox
Checking patch hw/i386/pc.c...
Hunk #1 succeeded at 622 (offset 15 lines).
error: while searching for:
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
acpi_tables, acpi_tables_len);
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE,
kvm_allows_irq0_override());
smbios_table = smbios_get_table(&smbios_len);
if (smbios_table)
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
smbios_table, smbios_len);
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
&e820_table, sizeof(e820_table));
error: patch failed: hw/i386/pc.c:631
error: hw/i386/pc.c: patch does not apply
Should probably look like:
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 12c436e..3ff6a89 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -622,8 +622,6 @@ static unsigned int pc_apic_id_limit(unsigned int
max_cpus)
static FWCfgState *bochs_bios_init(void)
{
FWCfgState *fw_cfg;
- uint8_t *smbios_table;
- size_t smbios_len;
uint64_t *numa_fw_cfg;
int i, j;
unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
@@ -646,14 +644,8 @@ static FWCfgState *bochs_bios_init(void)
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
- acpi_tables, acpi_tables_len);
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE,
kvm_allows_irq0_override());
- smbios_table = smbios_get_table(&smbios_len);
- if (smbios_table)
- fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
- smbios_table, smbios_len);
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
&e820_reserve, sizeof(e820_reserve));
fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
@@ -1144,6 +1136,31 @@ void pc_acpi_init(const char *default_dsdt)
}
}
+struct pc_bios_post_init {
+ Notifier post_init;
+ void *fw_cfg;
+};
+
+/* Add the ACPI and SMBIOS tables after all the hardware has been
initialized.
+ * This gives devices a chance to add to those tables.
+ */
+static void pc_bios_post_initfn(Notifier *n, void *opaque)
+{
+ struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
+ post_init);
+ uint8_t *smbios_table;
+ size_t smbios_len;
+
+ fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
+ acpi_tables, acpi_tables_len);
+ smbios_table = smbios_get_table(&smbios_len);
+ if (smbios_table)
+ fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
+ smbios_table, smbios_len);
+}
+
+static struct pc_bios_post_init post_init;
+
FWCfgState *pc_memory_init(MemoryRegion *system_memory,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -1207,6 +1224,11 @@ FWCfgState *pc_memory_init(MemoryRegion
*system_memory,
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
}
guest_info->fw_cfg = fw_cfg;
+
+ post_init.fw_cfg = fw_cfg;
+ post_init.post_init.notify = pc_bios_post_initfn;
+ qemu_add_machine_init_done_notifier(&post_init.post_init);
+
return fw_cfg;
}
On Tue, Nov 12, 2013 at 10:33 AM, Corey Minyard <minyard@acm.org> wrote:
> Postpone the addition of the ACPI and SMBIOS tables until after
> device initialization. This allows devices to add entries to these
> tables.
>
> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
> ---
> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
> 1 file changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index dee409d..765c95e 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int
> max_cpus)
> static FWCfgState *bochs_bios_init(void)
> {
> FWCfgState *fw_cfg;
> - uint8_t *smbios_table;
> - size_t smbios_len;
> uint64_t *numa_fw_cfg;
> int i, j;
> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
> - acpi_tables, acpi_tables_len);
> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE,
> kvm_allows_irq0_override());
>
> - smbios_table = smbios_get_table(&smbios_len);
> - if (smbios_table)
> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> - smbios_table, smbios_len);
> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
> &e820_table, sizeof(e820_table));
>
> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
> }
> }
>
> +struct pc_bios_post_init {
> + Notifier post_init;
> + void *fw_cfg;
> +};
> +
> +/* Add the ACPI and SMBIOS tables after all the hardware has been
> initialized.
> + * This gives devices a chance to add to those tables.
> + */
> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
> +{
> + struct pc_bios_post_init *p = container_of(n, struct
> pc_bios_post_init,
> + post_init);
> + uint8_t *smbios_table;
> + size_t smbios_len;
> +
> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
> + acpi_tables, acpi_tables_len);
> + smbios_table = smbios_get_table(&smbios_len);
> + if (smbios_table)
> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> + smbios_table, smbios_len);
> +}
> +
> +static struct pc_bios_post_init post_init;
> +
> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> const char *kernel_filename,
> const char *kernel_cmdline,
> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion
> *system_memory,
> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
> }
> guest_info->fw_cfg = fw_cfg;
> +
> + post_init.fw_cfg = fw_cfg;
> + post_init.post_init.notify = pc_bios_post_initfn;
> + qemu_add_machine_init_done_notifier(&post_init.post_init);
> +
> return fw_cfg;
> }
>
> --
> 1.8.3.1
>
>
[-- Attachment #2: Type: text/html, Size: 7793 bytes --]
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-12 16:33 ` [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg Corey Minyard
2013-11-13 14:31 ` Bret Ketchum
@ 2013-11-14 7:30 ` Michael S. Tsirkin
2013-11-14 13:28 ` Corey Minyard
1 sibling, 1 reply; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-14 7:30 UTC (permalink / raw)
To: Corey Minyard
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, qemu-devel,
Andreas Färber
On Tue, Nov 12, 2013 at 10:33:13AM -0600, Corey Minyard wrote:
> Postpone the addition of the ACPI and SMBIOS tables until after
> device initialization. This allows devices to add entries to these
> tables.
>
> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
Why delay adding FW_CFG_ACPI_TABLES?
These are normally specified by user so they are constant.
> ---
> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
> 1 file changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index dee409d..765c95e 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
> static FWCfgState *bochs_bios_init(void)
> {
> FWCfgState *fw_cfg;
> - uint8_t *smbios_table;
> - size_t smbios_len;
> uint64_t *numa_fw_cfg;
> int i, j;
> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
> - acpi_tables, acpi_tables_len);
> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
>
> - smbios_table = smbios_get_table(&smbios_len);
> - if (smbios_table)
> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> - smbios_table, smbios_len);
> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
> &e820_table, sizeof(e820_table));
>
> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
> }
> }
>
> +struct pc_bios_post_init {
> + Notifier post_init;
> + void *fw_cfg;
> +};
> +
> +/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
> + * This gives devices a chance to add to those tables.
> + */
> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
> +{
> + struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
> + post_init);
> + uint8_t *smbios_table;
> + size_t smbios_len;
> +
> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
> + acpi_tables, acpi_tables_len);
> + smbios_table = smbios_get_table(&smbios_len);
> + if (smbios_table)
> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> + smbios_table, smbios_len);
> +}
> +
> +static struct pc_bios_post_init post_init;
> +
> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> const char *kernel_filename,
> const char *kernel_cmdline,
> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
> }
> guest_info->fw_cfg = fw_cfg;
> +
> + post_init.fw_cfg = fw_cfg;
> + post_init.post_init.notify = pc_bios_post_initfn;
> + qemu_add_machine_init_done_notifier(&post_init.post_init);
> +
> return fw_cfg;
> }
>
> --
> 1.8.3.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-14 7:30 ` Michael S. Tsirkin
@ 2013-11-14 13:28 ` Corey Minyard
2013-11-14 13:38 ` Michael S. Tsirkin
0 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-14 13:28 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, qemu-devel,
Andreas Färber
On 11/14/2013 01:30 AM, Michael S. Tsirkin wrote:
> On Tue, Nov 12, 2013 at 10:33:13AM -0600, Corey Minyard wrote:
>> Postpone the addition of the ACPI and SMBIOS tables until after
>> device initialization. This allows devices to add entries to these
>> tables.
>>
>> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
> Why delay adding FW_CFG_ACPI_TABLES?
> These are normally specified by user so they are constant.
Because the IPMI device has to dynamically add an entry based on its
configuration. As it is the tables get added to the BIOS access before
devices initialize.
-corey
>
>> ---
>> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
>> 1 file changed, 30 insertions(+), 8 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index dee409d..765c95e 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
>> static FWCfgState *bochs_bios_init(void)
>> {
>> FWCfgState *fw_cfg;
>> - uint8_t *smbios_table;
>> - size_t smbios_len;
>> uint64_t *numa_fw_cfg;
>> int i, j;
>> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
>> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
>> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
>> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
>> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
>> - acpi_tables, acpi_tables_len);
>> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
>>
>> - smbios_table = smbios_get_table(&smbios_len);
>> - if (smbios_table)
>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
>> - smbios_table, smbios_len);
>> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
>> &e820_table, sizeof(e820_table));
>>
>> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
>> }
>> }
>>
>> +struct pc_bios_post_init {
>> + Notifier post_init;
>> + void *fw_cfg;
>> +};
>> +
>> +/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
>> + * This gives devices a chance to add to those tables.
>> + */
>> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
>> +{
>> + struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
>> + post_init);
>> + uint8_t *smbios_table;
>> + size_t smbios_len;
>> +
>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
>> + acpi_tables, acpi_tables_len);
>> + smbios_table = smbios_get_table(&smbios_len);
>> + if (smbios_table)
>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
>> + smbios_table, smbios_len);
>> +}
>> +
>> +static struct pc_bios_post_init post_init;
>> +
>> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
>> const char *kernel_filename,
>> const char *kernel_cmdline,
>> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
>> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
>> }
>> guest_info->fw_cfg = fw_cfg;
>> +
>> + post_init.fw_cfg = fw_cfg;
>> + post_init.post_init.notify = pc_bios_post_initfn;
>> + qemu_add_machine_init_done_notifier(&post_init.post_init);
>> +
>> return fw_cfg;
>> }
>>
>> --
>> 1.8.3.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-14 13:28 ` Corey Minyard
@ 2013-11-14 13:38 ` Michael S. Tsirkin
2013-11-14 13:40 ` Corey Minyard
0 siblings, 1 reply; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-14 13:38 UTC (permalink / raw)
To: Corey Minyard
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, qemu-devel,
Andreas Färber
On Thu, Nov 14, 2013 at 07:28:00AM -0600, Corey Minyard wrote:
> On 11/14/2013 01:30 AM, Michael S. Tsirkin wrote:
> > On Tue, Nov 12, 2013 at 10:33:13AM -0600, Corey Minyard wrote:
> >> Postpone the addition of the ACPI and SMBIOS tables until after
> >> device initialization. This allows devices to add entries to these
> >> tables.
> >>
> >> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
> > Why delay adding FW_CFG_ACPI_TABLES?
> > These are normally specified by user so they are constant.
>
> Because the IPMI device has to dynamically add an entry based on its
> configuration.
Where? Which patch does this? It would be a strange thing to do
because FW_CFG_ACPI_TABLES is normally intended for user-supplied tables
(though q35 misused it for other purposes).
> As it is the tables get added to the BIOS access before
> devices initialize.
>
> -corey
>
> >
> >> ---
> >> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
> >> 1 file changed, 30 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >> index dee409d..765c95e 100644
> >> --- a/hw/i386/pc.c
> >> +++ b/hw/i386/pc.c
> >> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
> >> static FWCfgState *bochs_bios_init(void)
> >> {
> >> FWCfgState *fw_cfg;
> >> - uint8_t *smbios_table;
> >> - size_t smbios_len;
> >> uint64_t *numa_fw_cfg;
> >> int i, j;
> >> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
> >> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
> >> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
> >> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
> >> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> >> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
> >> - acpi_tables, acpi_tables_len);
> >> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
> >>
> >> - smbios_table = smbios_get_table(&smbios_len);
> >> - if (smbios_table)
> >> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> >> - smbios_table, smbios_len);
> >> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
> >> &e820_table, sizeof(e820_table));
> >>
> >> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
> >> }
> >> }
> >>
> >> +struct pc_bios_post_init {
> >> + Notifier post_init;
> >> + void *fw_cfg;
> >> +};
> >> +
> >> +/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
> >> + * This gives devices a chance to add to those tables.
> >> + */
> >> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
> >> +{
> >> + struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
> >> + post_init);
> >> + uint8_t *smbios_table;
> >> + size_t smbios_len;
> >> +
> >> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
> >> + acpi_tables, acpi_tables_len);
> >> + smbios_table = smbios_get_table(&smbios_len);
> >> + if (smbios_table)
> >> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> >> + smbios_table, smbios_len);
> >> +}
> >> +
> >> +static struct pc_bios_post_init post_init;
> >> +
> >> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> >> const char *kernel_filename,
> >> const char *kernel_cmdline,
> >> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> >> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
> >> }
> >> guest_info->fw_cfg = fw_cfg;
> >> +
> >> + post_init.fw_cfg = fw_cfg;
> >> + post_init.post_init.notify = pc_bios_post_initfn;
> >> + qemu_add_machine_init_done_notifier(&post_init.post_init);
> >> +
> >> return fw_cfg;
> >> }
> >>
> >> --
> >> 1.8.3.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-14 13:38 ` Michael S. Tsirkin
@ 2013-11-14 13:40 ` Corey Minyard
2013-11-14 13:50 ` Michael S. Tsirkin
2013-11-26 10:03 ` Michael S. Tsirkin
0 siblings, 2 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-14 13:40 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, qemu-devel,
Andreas Färber
On 11/14/2013 07:38 AM, Michael S. Tsirkin wrote:
> On Thu, Nov 14, 2013 at 07:28:00AM -0600, Corey Minyard wrote:
>> On 11/14/2013 01:30 AM, Michael S. Tsirkin wrote:
>>> On Tue, Nov 12, 2013 at 10:33:13AM -0600, Corey Minyard wrote:
>>>> Postpone the addition of the ACPI and SMBIOS tables until after
>>>> device initialization. This allows devices to add entries to these
>>>> tables.
>>>>
>>>> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
>>> Why delay adding FW_CFG_ACPI_TABLES?
>>> These are normally specified by user so they are constant.
>> Because the IPMI device has to dynamically add an entry based on its
>> configuration.
> Where? Which patch does this? It would be a strange thing to do
> because FW_CFG_ACPI_TABLES is normally intended for user-supplied tables
> (though q35 misused it for other purposes).
I don't have that patch out yet. I had written some code to dynamically
generate ACPI tables, but that was rejected and from what I understand
something was done recently so these tables can be dynamically generated
some other way. I haven't had time to look into this, but I wanted to
get the main patch set out first.
I know that these tables are generally fixed, but the entry for IPMI
should only be present if the device is specified, and its contents
depend on the configuration supplied,
-corey
>
>> As it is the tables get added to the BIOS access before
>> devices initialize.
>>
>> -corey
>>
>>>> ---
>>>> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
>>>> 1 file changed, 30 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>>>> index dee409d..765c95e 100644
>>>> --- a/hw/i386/pc.c
>>>> +++ b/hw/i386/pc.c
>>>> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
>>>> static FWCfgState *bochs_bios_init(void)
>>>> {
>>>> FWCfgState *fw_cfg;
>>>> - uint8_t *smbios_table;
>>>> - size_t smbios_len;
>>>> uint64_t *numa_fw_cfg;
>>>> int i, j;
>>>> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
>>>> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
>>>> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
>>>> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
>>>> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
>>>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
>>>> - acpi_tables, acpi_tables_len);
>>>> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
>>>>
>>>> - smbios_table = smbios_get_table(&smbios_len);
>>>> - if (smbios_table)
>>>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
>>>> - smbios_table, smbios_len);
>>>> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
>>>> &e820_table, sizeof(e820_table));
>>>>
>>>> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
>>>> }
>>>> }
>>>>
>>>> +struct pc_bios_post_init {
>>>> + Notifier post_init;
>>>> + void *fw_cfg;
>>>> +};
>>>> +
>>>> +/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
>>>> + * This gives devices a chance to add to those tables.
>>>> + */
>>>> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
>>>> +{
>>>> + struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
>>>> + post_init);
>>>> + uint8_t *smbios_table;
>>>> + size_t smbios_len;
>>>> +
>>>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
>>>> + acpi_tables, acpi_tables_len);
>>>> + smbios_table = smbios_get_table(&smbios_len);
>>>> + if (smbios_table)
>>>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
>>>> + smbios_table, smbios_len);
>>>> +}
>>>> +
>>>> +static struct pc_bios_post_init post_init;
>>>> +
>>>> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
>>>> const char *kernel_filename,
>>>> const char *kernel_cmdline,
>>>> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
>>>> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
>>>> }
>>>> guest_info->fw_cfg = fw_cfg;
>>>> +
>>>> + post_init.fw_cfg = fw_cfg;
>>>> + post_init.post_init.notify = pc_bios_post_initfn;
>>>> + qemu_add_machine_init_done_notifier(&post_init.post_init);
>>>> +
>>>> return fw_cfg;
>>>> }
>>>>
>>>> --
>>>> 1.8.3.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-14 13:40 ` Corey Minyard
@ 2013-11-14 13:50 ` Michael S. Tsirkin
2013-11-26 10:03 ` Michael S. Tsirkin
1 sibling, 0 replies; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-14 13:50 UTC (permalink / raw)
To: Corey Minyard
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, qemu-devel,
Andreas Färber
On Thu, Nov 14, 2013 at 07:40:31AM -0600, Corey Minyard wrote:
> On 11/14/2013 07:38 AM, Michael S. Tsirkin wrote:
> > On Thu, Nov 14, 2013 at 07:28:00AM -0600, Corey Minyard wrote:
> >> On 11/14/2013 01:30 AM, Michael S. Tsirkin wrote:
> >>> On Tue, Nov 12, 2013 at 10:33:13AM -0600, Corey Minyard wrote:
> >>>> Postpone the addition of the ACPI and SMBIOS tables until after
> >>>> device initialization. This allows devices to add entries to these
> >>>> tables.
> >>>>
> >>>> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
> >>> Why delay adding FW_CFG_ACPI_TABLES?
> >>> These are normally specified by user so they are constant.
> >> Because the IPMI device has to dynamically add an entry based on its
> >> configuration.
> > Where? Which patch does this? It would be a strange thing to do
> > because FW_CFG_ACPI_TABLES is normally intended for user-supplied tables
> > (though q35 misused it for other purposes).
>
> I don't have that patch out yet. I had written some code to dynamically
> generate ACPI tables, but that was rejected and from what I understand
> something was done recently so these tables can be dynamically generated
> some other way. I haven't had time to look into this, but I wanted to
> get the main patch set out first.
OK so for review, it might be a good idea to split out the changes
required for necessary functionality as opposed to groundwork
that will be used down the line.
>
> I know that these tables are generally fixed, but the entry for IPMI
> should only be present if the device is specified, and its contents
> depend on the configuration supplied,
>
> -corey
I see. These tables are generated in hw/i386/acpi-build.c
This is invoked in machine done callback so there shouldn't
in an issue to probe for IPMI and it's configuration using QOM.
> >
> >> As it is the tables get added to the BIOS access before
> >> devices initialize.
> >>
> >> -corey
> >>
> >>>> ---
> >>>> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
> >>>> 1 file changed, 30 insertions(+), 8 deletions(-)
> >>>>
> >>>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >>>> index dee409d..765c95e 100644
> >>>> --- a/hw/i386/pc.c
> >>>> +++ b/hw/i386/pc.c
> >>>> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
> >>>> static FWCfgState *bochs_bios_init(void)
> >>>> {
> >>>> FWCfgState *fw_cfg;
> >>>> - uint8_t *smbios_table;
> >>>> - size_t smbios_len;
> >>>> uint64_t *numa_fw_cfg;
> >>>> int i, j;
> >>>> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
> >>>> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
> >>>> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
> >>>> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
> >>>> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> >>>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
> >>>> - acpi_tables, acpi_tables_len);
> >>>> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
> >>>>
> >>>> - smbios_table = smbios_get_table(&smbios_len);
> >>>> - if (smbios_table)
> >>>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> >>>> - smbios_table, smbios_len);
> >>>> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
> >>>> &e820_table, sizeof(e820_table));
> >>>>
> >>>> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
> >>>> }
> >>>> }
> >>>>
> >>>> +struct pc_bios_post_init {
> >>>> + Notifier post_init;
> >>>> + void *fw_cfg;
> >>>> +};
> >>>> +
> >>>> +/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
> >>>> + * This gives devices a chance to add to those tables.
> >>>> + */
> >>>> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
> >>>> +{
> >>>> + struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
> >>>> + post_init);
> >>>> + uint8_t *smbios_table;
> >>>> + size_t smbios_len;
> >>>> +
> >>>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
> >>>> + acpi_tables, acpi_tables_len);
> >>>> + smbios_table = smbios_get_table(&smbios_len);
> >>>> + if (smbios_table)
> >>>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> >>>> + smbios_table, smbios_len);
> >>>> +}
> >>>> +
> >>>> +static struct pc_bios_post_init post_init;
> >>>> +
> >>>> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> >>>> const char *kernel_filename,
> >>>> const char *kernel_cmdline,
> >>>> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> >>>> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
> >>>> }
> >>>> guest_info->fw_cfg = fw_cfg;
> >>>> +
> >>>> + post_init.fw_cfg = fw_cfg;
> >>>> + post_init.post_init.notify = pc_bios_post_initfn;
> >>>> + qemu_add_machine_init_done_notifier(&post_init.post_init);
> >>>> +
> >>>> return fw_cfg;
> >>>> }
> >>>>
> >>>> --
> >>>> 1.8.3.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg
2013-11-14 13:40 ` Corey Minyard
2013-11-14 13:50 ` Michael S. Tsirkin
@ 2013-11-26 10:03 ` Michael S. Tsirkin
1 sibling, 0 replies; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-26 10:03 UTC (permalink / raw)
To: Corey Minyard
Cc: Bret Ketchum, Corey Minyard, Corey Minyard, qemu-devel,
Andreas Färber
On Thu, Nov 14, 2013 at 07:40:31AM -0600, Corey Minyard wrote:
> On 11/14/2013 07:38 AM, Michael S. Tsirkin wrote:
> > On Thu, Nov 14, 2013 at 07:28:00AM -0600, Corey Minyard wrote:
> >> On 11/14/2013 01:30 AM, Michael S. Tsirkin wrote:
> >>> On Tue, Nov 12, 2013 at 10:33:13AM -0600, Corey Minyard wrote:
> >>>> Postpone the addition of the ACPI and SMBIOS tables until after
> >>>> device initialization. This allows devices to add entries to these
> >>>> tables.
> >>>>
> >>>> Signed-off-by: Corey Minyard <cminyard@mvsita.com>
> >>> Why delay adding FW_CFG_ACPI_TABLES?
> >>> These are normally specified by user so they are constant.
> >> Because the IPMI device has to dynamically add an entry based on its
> >> configuration.
> > Where? Which patch does this? It would be a strange thing to do
> > because FW_CFG_ACPI_TABLES is normally intended for user-supplied tables
> > (though q35 misused it for other purposes).
>
> I don't have that patch out yet. I had written some code to dynamically
> generate ACPI tables, but that was rejected and from what I understand
> something was done recently so these tables can be dynamically generated
> some other way. I haven't had time to look into this, but I wanted to
> get the main patch set out first.
>
> I know that these tables are generally fixed, but the entry for IPMI
> should only be present if the device is specified, and its contents
> depend on the configuration supplied,
>
> -corey
OK need some help with that?
Main options are
- write code in ASL, supply entry in ACPI always, patch some fields
to enable/disable it dynamically
see how pvpanic entry is disabled for an example
- write code in ASL append it to ACPI if necessary
see how CPU entries are added depending on number of CPUs for an example
- generate code in AML directly
see acpi based pci hotplug on pci branch in my tree for an example
> >
> >> As it is the tables get added to the BIOS access before
> >> devices initialize.
> >>
> >> -corey
> >>
> >>>> ---
> >>>> hw/i386/pc.c | 38 ++++++++++++++++++++++++++++++--------
> >>>> 1 file changed, 30 insertions(+), 8 deletions(-)
> >>>>
> >>>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >>>> index dee409d..765c95e 100644
> >>>> --- a/hw/i386/pc.c
> >>>> +++ b/hw/i386/pc.c
> >>>> @@ -607,8 +607,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
> >>>> static FWCfgState *bochs_bios_init(void)
> >>>> {
> >>>> FWCfgState *fw_cfg;
> >>>> - uint8_t *smbios_table;
> >>>> - size_t smbios_len;
> >>>> uint64_t *numa_fw_cfg;
> >>>> int i, j;
> >>>> unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
> >>>> @@ -631,14 +629,8 @@ static FWCfgState *bochs_bios_init(void)
> >>>> fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
> >>>> fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
> >>>> fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> >>>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
> >>>> - acpi_tables, acpi_tables_len);
> >>>> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
> >>>>
> >>>> - smbios_table = smbios_get_table(&smbios_len);
> >>>> - if (smbios_table)
> >>>> - fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> >>>> - smbios_table, smbios_len);
> >>>> fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
> >>>> &e820_table, sizeof(e820_table));
> >>>>
> >>>> @@ -1127,6 +1119,31 @@ void pc_acpi_init(const char *default_dsdt)
> >>>> }
> >>>> }
> >>>>
> >>>> +struct pc_bios_post_init {
> >>>> + Notifier post_init;
> >>>> + void *fw_cfg;
> >>>> +};
> >>>> +
> >>>> +/* Add the ACPI and SMBIOS tables after all the hardware has been initialized.
> >>>> + * This gives devices a chance to add to those tables.
> >>>> + */
> >>>> +static void pc_bios_post_initfn(Notifier *n, void *opaque)
> >>>> +{
> >>>> + struct pc_bios_post_init *p = container_of(n, struct pc_bios_post_init,
> >>>> + post_init);
> >>>> + uint8_t *smbios_table;
> >>>> + size_t smbios_len;
> >>>> +
> >>>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_ACPI_TABLES,
> >>>> + acpi_tables, acpi_tables_len);
> >>>> + smbios_table = smbios_get_table(&smbios_len);
> >>>> + if (smbios_table)
> >>>> + fw_cfg_add_bytes(p->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
> >>>> + smbios_table, smbios_len);
> >>>> +}
> >>>> +
> >>>> +static struct pc_bios_post_init post_init;
> >>>> +
> >>>> FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> >>>> const char *kernel_filename,
> >>>> const char *kernel_cmdline,
> >>>> @@ -1196,6 +1213,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
> >>>> rom_add_option(option_rom[i].name, option_rom[i].bootindex);
> >>>> }
> >>>> guest_info->fw_cfg = fw_cfg;
> >>>> +
> >>>> + post_init.fw_cfg = fw_cfg;
> >>>> + post_init.post_init.notify = pc_bios_post_initfn;
> >>>> + qemu_add_machine_init_done_notifier(&post_init.post_init);
> >>>> +
> >>>> return fw_cfg;
> >>>> }
> >>>>
> >>>> --
> >>>> 1.8.3.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (13 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 14/16] pc: Postpone adding ACPI and SMBIOS to fw_cfg Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-13 14:37 ` Bret Ketchum
2013-11-12 16:33 ` [Qemu-devel] [PATCH 16/16] ipmi: Add SMBIOS table entry Corey Minyard
15 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
There was no way to directly add a table entry to the SMBIOS table,
even though the BIOS supports this. So add a function to do this.
This is in preparation for the IPMI handler adding it's SMBIOS table
entry.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
hw/i386/smbios.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c
index d3f1ee6..9c53131 100644
--- a/hw/i386/smbios.c
+++ b/hw/i386/smbios.c
@@ -277,6 +277,33 @@ static void save_opt(const char **dest, QemuOpts *opts, const char *name)
}
}
+int smbios_table_entry_add(struct smbios_structure_header *entry)
+{
+ struct smbios_table *table;
+ struct smbios_structure_header *header;
+ unsigned int size = entry->length;
+
+ if (!smbios_entries) {
+ smbios_entries_len = sizeof(uint16_t);
+ smbios_entries = g_malloc0(smbios_entries_len);
+ }
+ smbios_entries = g_realloc(smbios_entries, smbios_entries_len +
+ sizeof(*table) + size);
+ table = (struct smbios_table *)(smbios_entries + smbios_entries_len);
+ table->header.type = SMBIOS_TABLE_ENTRY;
+ table->header.length = cpu_to_le16(sizeof(*table) + size);
+
+ header = (struct smbios_structure_header *)(table->data);
+ memcpy(header, entry, size);
+
+ smbios_check_collision(header->type, SMBIOS_TABLE_ENTRY);
+
+ smbios_entries_len += sizeof(*table) + size;
+ (*(uint16_t *)smbios_entries) =
+ cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1);
+ return 0;
+}
+
void smbios_entry_add(QemuOpts *opts)
{
Error *local_err = NULL;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry
2013-11-12 16:33 ` [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry Corey Minyard
@ 2013-11-13 14:37 ` Bret Ketchum
2013-11-13 16:22 ` Andreas Färber
2013-11-13 20:52 ` Corey Minyard
0 siblings, 2 replies; 42+ messages in thread
From: Bret Ketchum @ 2013-11-13 14:37 UTC (permalink / raw)
To: Corey Minyard
Cc: Corey Minyard, qemu-devel, Andreas Färber, Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 1935 bytes --]
Don't know if it matters much but this patch cannot be applied without
the prototype definition in 16/16.
On Tue, Nov 12, 2013 at 10:33 AM, Corey Minyard <minyard@acm.org> wrote:
> There was no way to directly add a table entry to the SMBIOS table,
> even though the BIOS supports this. So add a function to do this.
> This is in preparation for the IPMI handler adding it's SMBIOS table
> entry.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> ---
> hw/i386/smbios.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c
> index d3f1ee6..9c53131 100644
> --- a/hw/i386/smbios.c
> +++ b/hw/i386/smbios.c
> @@ -277,6 +277,33 @@ static void save_opt(const char **dest, QemuOpts
> *opts, const char *name)
> }
> }
>
> +int smbios_table_entry_add(struct smbios_structure_header *entry)
> +{
> + struct smbios_table *table;
> + struct smbios_structure_header *header;
> + unsigned int size = entry->length;
> +
> + if (!smbios_entries) {
> + smbios_entries_len = sizeof(uint16_t);
> + smbios_entries = g_malloc0(smbios_entries_len);
> + }
> + smbios_entries = g_realloc(smbios_entries, smbios_entries_len +
> + sizeof(*table) + size);
> + table = (struct smbios_table *)(smbios_entries + smbios_entries_len);
> + table->header.type = SMBIOS_TABLE_ENTRY;
> + table->header.length = cpu_to_le16(sizeof(*table) + size);
> +
> + header = (struct smbios_structure_header *)(table->data);
> + memcpy(header, entry, size);
> +
> + smbios_check_collision(header->type, SMBIOS_TABLE_ENTRY);
> +
> + smbios_entries_len += sizeof(*table) + size;
> + (*(uint16_t *)smbios_entries) =
> + cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1);
> + return 0;
> +}
> +
> void smbios_entry_add(QemuOpts *opts)
> {
> Error *local_err = NULL;
> --
> 1.8.3.1
>
>
[-- Attachment #2: Type: text/html, Size: 2529 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry
2013-11-13 14:37 ` Bret Ketchum
@ 2013-11-13 16:22 ` Andreas Färber
2013-11-13 20:52 ` Corey Minyard
1 sibling, 0 replies; 42+ messages in thread
From: Andreas Färber @ 2013-11-13 16:22 UTC (permalink / raw)
To: Bret Ketchum, Corey Minyard; +Cc: Corey Minyard, qemu-devel, Michael S. Tsirkin
Am 13.11.2013 15:37, schrieb Bret Ketchum:
>
> Don't know if it matters much but this patch cannot be applied
> without the prototype definition in 16/16.
It does matter for bisecting, thanks for pointing it out!
Cheers,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry
2013-11-13 14:37 ` Bret Ketchum
2013-11-13 16:22 ` Andreas Färber
@ 2013-11-13 20:52 ` Corey Minyard
1 sibling, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-13 20:52 UTC (permalink / raw)
To: Bret Ketchum, Corey Minyard
Cc: qemu-devel, Andreas Färber, Michael S. Tsirkin
On 11/13/2013 08:37 AM, Bret Ketchum wrote:
>
> Don't know if it matters much but this patch cannot be applied
> without the prototype definition in 16/16.
Thanks, I'll fix this.
-corey
>
>
> On Tue, Nov 12, 2013 at 10:33 AM, Corey Minyard <minyard@acm.org
> <mailto:minyard@acm.org>> wrote:
>
> There was no way to directly add a table entry to the SMBIOS table,
> even though the BIOS supports this. So add a function to do this.
> This is in preparation for the IPMI handler adding it's SMBIOS table
> entry.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com
> <mailto:cminyard@mvista.com>>
> ---
> hw/i386/smbios.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c
> index d3f1ee6..9c53131 100644
> --- a/hw/i386/smbios.c
> +++ b/hw/i386/smbios.c
> @@ -277,6 +277,33 @@ static void save_opt(const char **dest,
> QemuOpts *opts, const char *name)
> }
> }
>
> +int smbios_table_entry_add(struct smbios_structure_header *entry)
> +{
> + struct smbios_table *table;
> + struct smbios_structure_header *header;
> + unsigned int size = entry->length;
> +
> + if (!smbios_entries) {
> + smbios_entries_len = sizeof(uint16_t);
> + smbios_entries = g_malloc0(smbios_entries_len);
> + }
> + smbios_entries = g_realloc(smbios_entries, smbios_entries_len +
> + sizeof(*table) + size);
> + table = (struct smbios_table *)(smbios_entries +
> smbios_entries_len);
> + table->header.type = SMBIOS_TABLE_ENTRY;
> + table->header.length = cpu_to_le16(sizeof(*table) + size);
> +
> + header = (struct smbios_structure_header *)(table->data);
> + memcpy(header, entry, size);
> +
> + smbios_check_collision(header->type, SMBIOS_TABLE_ENTRY);
> +
> + smbios_entries_len += sizeof(*table) + size;
> + (*(uint16_t *)smbios_entries) =
> + cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1);
> + return 0;
> +}
> +
> void smbios_entry_add(QemuOpts *opts)
> {
> Error *local_err = NULL;
> --
> 1.8.3.1
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 16/16] ipmi: Add SMBIOS table entry
2013-11-12 16:32 [Qemu-devel] [PATCH 00/16] Add an IPMI device to QEMU Corey Minyard
` (14 preceding siblings ...)
2013-11-12 16:33 ` [Qemu-devel] [PATCH 15/16] smbios: Add a function to directly add an entry Corey Minyard
@ 2013-11-12 16:33 ` Corey Minyard
2013-11-14 7:46 ` Michael S. Tsirkin
15 siblings, 1 reply; 42+ messages in thread
From: Corey Minyard @ 2013-11-12 16:33 UTC (permalink / raw)
To: qemu-devel
Cc: Bret Ketchum, Corey Minyard, Andreas Färber, Michael S. Tsirkin
Add an IPMI table entry to the SMBIOS.
---
hw/ipmi/isa_ipmi.c | 29 +++++++++++++++++++++++++++++
include/hw/i386/smbios.h | 14 ++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
index b38c846..e40ca90 100644
--- a/hw/ipmi/isa_ipmi.c
+++ b/hw/ipmi/isa_ipmi.c
@@ -27,6 +27,7 @@
#include "qemu/timer.h"
#include "sysemu/char.h"
#include "sysemu/sysemu.h"
+#include "hw/i386/smbios.h"
#include "ipmi.h"
/* This is the type the user specifies on the -device command line */
@@ -36,13 +37,36 @@
typedef struct ISAIPMIDevice {
ISADevice dev;
char *interface;
+ int intftype;
uint32_t iobase;
uint32_t isairq;
uint8_t slave_addr;
+ uint8_t version;
CharDriverState *chr;
IPMIInterface *intf;
} ISAIPMIDevice;
+static void ipmi_encode_smbios(ISAIPMIDevice *info)
+{
+ struct smbios_type_38 smb38;
+
+ smb38.header.type = 38;
+ smb38.header.length = sizeof(smb38);
+ smb38.header.handle = cpu_to_le16(0x3000);
+ smb38.interface_type = info->intftype;
+ smb38.ipmi_spec_revision = info->version;
+ smb38.i2c_slave_address = info->slave_addr;
+ smb38.nv_storage_device_address = 0;
+
+ /* or 1 to set it to I/O space */
+ smb38.base_address = cpu_to_le64(info->iobase | 1);
+
+ /* 1-byte boundaries, addr bit0=0, level triggered irq */
+ smb38.base_address_modifier = 1;
+ smb38.interrupt_number = info->isairq;
+ smbios_table_entry_add((struct smbios_structure_header *) &smb38);
+}
+
static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
@@ -50,6 +74,7 @@ static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
char typename[20];
Object *intfobj;
IPMIInterface *intf;
+ IPMIInterfaceClass *intfk;
Object *bmcobj;
IPMIBmc *bmc;
int rc;
@@ -69,10 +94,13 @@ static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
TYPE_IPMI_INTERFACE_PREFIX "%s", isa->interface);
intfobj = object_new(typename);
intf = IPMI_INTERFACE(intfobj);
+ intfk = IPMI_INTERFACE_GET_CLASS(intf);
bmc->intf = intf;
intf->bmc = bmc;
intf->io_base = isa->iobase;
intf->slave_addr = isa->slave_addr;
+ isa->intftype = intfk->smbios_type;
+ isa->version = 0x20; /* Version 2.0 */
rc = ipmi_interface_init(intf);
if (rc) {
error_setg(errp, "Error initializing IPMI interface: %d\n", rc);
@@ -106,6 +134,7 @@ static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
isa_register_ioport(isadev, &intf->io, intf->io_base);
+ ipmi_encode_smbios(isa);
}
static void ipmi_isa_reset(DeviceState *dev)
diff --git a/include/hw/i386/smbios.h b/include/hw/i386/smbios.h
index b08ec71..8133faa 100644
--- a/include/hw/i386/smbios.h
+++ b/include/hw/i386/smbios.h
@@ -29,6 +29,8 @@ struct smbios_structure_header {
uint16_t handle;
} QEMU_PACKED;
+int smbios_table_entry_add(struct smbios_structure_header *entry);
+
/* SMBIOS type 0 - BIOS Information */
struct smbios_type_0 {
struct smbios_structure_header header;
@@ -155,6 +157,18 @@ struct smbios_type_32 {
uint8_t boot_status;
} QEMU_PACKED;
+/* SMBIOS type 38 - IPMI */
+struct smbios_type_38 {
+ struct smbios_structure_header header;
+ uint8_t interface_type;
+ uint8_t ipmi_spec_revision;
+ uint8_t i2c_slave_address;
+ uint8_t nv_storage_device_address;
+ uint64_t base_address;
+ uint8_t base_address_modifier;
+ uint8_t interrupt_number;
+} QEMU_PACKED;
+
/* SMBIOS type 127 -- End-of-table */
struct smbios_type_127 {
struct smbios_structure_header header;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PATCH 16/16] ipmi: Add SMBIOS table entry
2013-11-12 16:33 ` [Qemu-devel] [PATCH 16/16] ipmi: Add SMBIOS table entry Corey Minyard
@ 2013-11-14 7:46 ` Michael S. Tsirkin
2013-11-14 13:43 ` Corey Minyard
0 siblings, 1 reply; 42+ messages in thread
From: Michael S. Tsirkin @ 2013-11-14 7:46 UTC (permalink / raw)
To: Corey Minyard; +Cc: qemu-devel
BTW you included this:
Cc: qemu-devel@nongnu.org, Andreas Färber <afaerber@suse.de>,
Bret Ketchum <bcketchum@gmail.com>,
Corey Minyard <cminyard@mvista.com>
the last address: cminyard@mvista.com is bouncing.
--
MST
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 16/16] ipmi: Add SMBIOS table entry
2013-11-14 7:46 ` Michael S. Tsirkin
@ 2013-11-14 13:43 ` Corey Minyard
0 siblings, 0 replies; 42+ messages in thread
From: Corey Minyard @ 2013-11-14 13:43 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
On 11/14/2013 01:46 AM, Michael S. Tsirkin wrote:
> BTW you included this:
>
> Cc: qemu-devel@nongnu.org, Andreas Färber <afaerber@suse.de>,
> Bret Ketchum <bcketchum@gmail.com>,
> Corey Minyard <cminyard@mvista.com>
>
> the last address: cminyard@mvista.com is bouncing.
>
That's actually not the one bouncing. The one bouncing is
cminyard@mvsita.com, which I obviously didn't get right.
-corey
^ permalink raw reply [flat|nested] 42+ messages in thread