* [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
@ 2014-02-03 9:44 Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 01/22] exec: Make tb_invalidate_phys_addr input an AS Edgar E. Iglesias
` (23 more replies)
0 siblings, 24 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Hi,
I'm looking at modeling systems where multiple CPUs co-exist with
different views of their attached buses/devs.
With this series I'm trying to take some steps towards having
an address-space per CPU. It's not complete but good enough for
making it possible to model (to some extent) CPU local memories
for MicroBlaze systems in emulation mode (TCG). I'm updating the
petalogix-ml605 here and will follow-up later with the petalogix-s3adsp.
The per-cpu address space is added into the CPUState. I tried to
measure performance diff with having it in the CPUState->env.
For "normal" and even for IO heavy workloads on linux kernels,
the diff is not measurable. I also tested with a tight guest loop
that continuously does I/O accesses and there I can see a 2.5% drop in perf.
I dont think the runtime type check involved when casting from env to CS
will be much of a problem.
I've reordered the series and moved the AS props to the end, hoping
we can get through the bulk of the series with less controversy and
get it commited soon.
I've kept the interface with properties to set AddressSpace pointers
which I think is the more flexible approach but we can explore other
ideas if there are.
There is lots of future work needed, for example to transform more of
the cpu_* bus accessing functions. To add more usage of AddressSpace
properties to pass on address spaces to DMA models. Qtest mechanisms
to target specific address spaces, etc...
Cheers,
Edgar
v3 -> v4:
Rebase, Use error_abort.
v2 -> v3:
Move CPU address-space prop into CPUState level.
v1 -> v2:
Add braces in cpu_memory_rw_debug.
Avoid mixing var/code declarations in tcg_commit.
Move per-cpu address space into CPUState.
Reorder patch series to add the AS properties last.
Edgar E. Iglesias (22):
exec: Make tb_invalidate_phys_addr input an AS
exec: Make iotlb_to_region input an AS
exec: Always initialize MemorySection address spaces
exec: Make memory_region_section_get_iotlb use section AS
memory: Add MemoryListener to typedefs.h
cpu: Add per-cpu address space
exec: On AS changes, only flush affected CPU TLBs
exec: Make ldl_*_phys input an AddressSpace
exec: Make ldq/ldub_*_phys input an AddressSpace
exec: Make lduw_*_phys input an AddressSpace
exec: Make stq_*_phys input an AddressSpace
exec: Make stl_*_phys input an AddressSpace
exec: Make stl_phys_notdirty input an AddressSpace
exec: Make stw_*_phys input an AddressSpace
exec: Make stb_phys input an AddressSpace
exec: Make cpu_physical_memory_write_rom input an AS
exec: Make cpu_memory_rw_debug use the CPUs AS
memory: Add address_space_find_by_name()
qdev: Add qdev property type for AddressSpaces
cpu: Add address-space property
petalogix-ml605: Create the CPU with object_new()
petalogix-ml605: Make the LMB visible only to the CPU
cpu-exec.c | 5 +-
cpus.c | 2 +
cputlb.c | 7 +-
exec.c | 183 ++++++++++++----------
hw/alpha/dp264.c | 5 +-
hw/alpha/typhoon.c | 2 +-
hw/arm/boot.c | 5 +-
hw/arm/highbank.c | 6 +-
hw/core/loader.c | 3 +-
hw/core/qdev-properties-system.c | 8 +
hw/core/qdev-properties.c | 54 +++++++
hw/display/sm501.c | 1 +
hw/display/sm501_template.h | 2 +-
hw/dma/pl080.c | 9 +-
hw/dma/sun4m_iommu.c | 3 +-
hw/intc/apic.c | 3 +-
hw/microblaze/petalogix_ml605_mmu.c | 24 ++-
hw/net/vmware_utils.h | 16 +-
hw/pci/msi.c | 2 +-
hw/pci/msix.c | 2 +-
hw/ppc/ppc405_uc.c | 45 +++---
hw/ppc/spapr_hcall.c | 50 +++---
hw/s390x/css.c | 11 +-
hw/s390x/s390-virtio-bus.c | 36 +++--
hw/s390x/s390-virtio.c | 2 +-
hw/s390x/virtio-ccw.c | 40 +++--
hw/scsi/megasas.c | 22 ++-
hw/scsi/vmw_pvscsi.c | 6 +-
hw/sh4/r2d.c | 4 +-
hw/sparc/sun4m.c | 3 +-
hw/timer/hpet.c | 3 +-
hw/virtio/virtio.c | 31 ++--
include/exec/cpu-common.h | 44 +++---
include/exec/exec-all.h | 5 +-
include/exec/memory.h | 11 +-
include/exec/softmmu_template.h | 7 +-
include/hw/ppc/spapr.h | 4 +-
include/hw/qdev-properties.h | 5 +
include/qemu/typedefs.h | 1 +
include/qom/cpu.h | 3 +
memory.c | 12 ++
monitor.c | 2 +-
qom/cpu.c | 7 +
stubs/Makefile.objs | 1 +
stubs/memory.c | 6 +
target-alpha/helper.c | 7 +-
target-alpha/helper.h | 8 +-
target-alpha/mem_helper.c | 36 +++--
target-alpha/translate.c | 8 +-
target-arm/helper.c | 21 ++-
target-i386/arch_memory_mapping.c | 46 +++---
target-i386/helper.c | 48 +++---
target-i386/seg_helper.c | 14 +-
target-i386/smm_helper.c | 300 ++++++++++++++++++------------------
target-i386/svm_helper.c | 299 +++++++++++++++++++++--------------
target-ppc/excp_helper.c | 4 +-
target-ppc/mmu-hash32.h | 12 +-
target-ppc/mmu-hash64.h | 14 +-
target-s390x/cpu.c | 2 +-
target-s390x/helper.c | 11 +-
target-s390x/mem_helper.c | 9 +-
target-sparc/ldst_helper.c | 72 +++++----
target-sparc/mmu_helper.c | 22 +--
target-unicore32/softmmu.c | 5 +-
target-xtensa/helper.c | 3 +-
target-xtensa/op_helper.c | 3 +-
translate-all.c | 14 +-
67 files changed, 990 insertions(+), 671 deletions(-)
create mode 100644 stubs/memory.c
--
1.8.1.2
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 01/22] exec: Make tb_invalidate_phys_addr input an AS
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 02/22] exec: Make iotlb_to_region " Edgar E. Iglesias
` (22 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 3 ++-
include/exec/exec-all.h | 2 +-
target-xtensa/op_helper.c | 3 ++-
translate-all.c | 4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 9ad0a4b..fc8ae65 100644
--- a/exec.c
+++ b/exec.c
@@ -488,7 +488,8 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
- tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK));
+ tb_invalidate_phys_addr(&address_space_memory,
+ phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 3b03cbf..9d6c36b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -102,7 +102,7 @@ void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..89a72b5 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -29,6 +29,7 @@
#include "helper.h"
#include "qemu/host-utils.h"
#include "exec/softmmu_exec.h"
+#include "exec/address-spaces.h"
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
@@ -90,7 +91,7 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
- tb_invalidate_phys_addr(paddr);
+ tb_invalidate_phys_addr(&address_space_memory, paddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index 543e1ff..1ac0246 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1357,13 +1357,13 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
hwaddr l = 1;
- mr = address_space_translate(&address_space_memory, addr, &addr, &l, false);
+ mr = address_space_translate(as, addr, &addr, &l, false);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
return;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 02/22] exec: Make iotlb_to_region input an AS
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 01/22] exec: Make tb_invalidate_phys_addr input an AS Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 03/22] exec: Always initialize MemorySection address spaces Edgar E. Iglesias
` (21 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cputlb.c | 2 +-
exec.c | 5 ++---
include/exec/exec-all.h | 2 +-
include/exec/softmmu_template.h | 5 +++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index b533f3f..71cf64f 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -313,7 +313,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
- mr = iotlb_to_region(pd);
+ mr = iotlb_to_region(&address_space_memory, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index fc8ae65..8a90867 100644
--- a/exec.c
+++ b/exec.c
@@ -1731,10 +1731,9 @@ static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
return phys_section_add(map, §ion);
}
-MemoryRegion *iotlb_to_region(hwaddr index)
+MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
{
- return address_space_memory.dispatch->map.sections[
- index & ~TARGET_PAGE_MASK].mr;
+ return as->dispatch->map.sections[index & ~TARGET_PAGE_MASK].mr;
}
static void io_mem_init(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9d6c36b..75fd1da 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -325,7 +325,7 @@ extern uintptr_t tci_tb_ptr;
void phys_mem_set_alloc(void *(*alloc)(size_t));
-struct MemoryRegion *iotlb_to_region(hwaddr index);
+struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c6a5440..69d856a 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -22,6 +22,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/timer.h"
+#include "exec/address-spaces.h"
#include "exec/memory.h"
#define DATA_SIZE (1 << SHIFT)
@@ -118,7 +119,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
uintptr_t retaddr)
{
uint64_t val;
- MemoryRegion *mr = iotlb_to_region(physaddr);
+ MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
env->mem_io_pc = retaddr;
@@ -324,7 +325,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
- MemoryRegion *mr = iotlb_to_region(physaddr);
+ MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 03/22] exec: Always initialize MemorySection address spaces
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 01/22] exec: Make tb_invalidate_phys_addr input an AS Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 02/22] exec: Make iotlb_to_region " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 04/22] exec: Make memory_region_section_get_iotlb use section AS Edgar E. Iglesias
` (20 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index 8a90867..3814a7e 100644
--- a/exec.c
+++ b/exec.c
@@ -877,6 +877,7 @@ static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *secti
if (!(existing->mr->subpage)) {
subpage = subpage_init(d->as, base);
+ subsection.address_space = d->as;
subsection.mr = &subpage->iomem;
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
phys_section_add(&d->map, &subsection));
@@ -1722,6 +1723,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
{
MemoryRegionSection section = {
+ .address_space = &address_space_memory,
.mr = mr,
.offset_within_address_space = 0,
.offset_within_region = 0,
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 04/22] exec: Make memory_region_section_get_iotlb use section AS
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (2 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 03/22] exec: Always initialize MemorySection address spaces Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 05/22] memory: Add MemoryListener to typedefs.h Edgar E. Iglesias
` (19 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index 3814a7e..d8cfe52 100644
--- a/exec.c
+++ b/exec.c
@@ -781,7 +781,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
iotlb |= PHYS_SECTION_ROM;
}
} else {
- iotlb = section - address_space_memory.dispatch->map.sections;
+ iotlb = section - section->address_space->dispatch->map.sections;
iotlb += xlat;
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 05/22] memory: Add MemoryListener to typedefs.h
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (3 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 04/22] exec: Make memory_region_section_get_iotlb use section AS Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space Edgar E. Iglesias
` (18 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/exec/memory.h | 2 --
include/qemu/typedefs.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 296d6ab..9101fc3 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -163,8 +163,6 @@ struct MemoryRegion {
NotifierList iommu_notify;
};
-typedef struct MemoryListener MemoryListener;
-
/**
* MemoryListener: callbacks structure for updates to the physical memory map
*
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 4524496..5b4e333 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -26,6 +26,7 @@ typedef struct BusClass BusClass;
typedef struct AddressSpace AddressSpace;
typedef struct MemoryRegion MemoryRegion;
typedef struct MemoryRegionSection MemoryRegionSection;
+typedef struct MemoryListener MemoryListener;
typedef struct MemoryMappingList MemoryMappingList;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (4 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 05/22] memory: Add MemoryListener to typedefs.h Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-11 19:52 ` Andreas Färber
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 07/22] exec: On AS changes, only flush affected CPU TLBs Edgar E. Iglesias
` (17 subsequent siblings)
23 siblings, 1 reply; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cpus.c | 2 ++
cputlb.c | 7 ++++---
exec.c | 27 +++++++++++++++++++--------
include/exec/exec-all.h | 1 +
include/exec/softmmu_template.h | 6 ++++--
include/qom/cpu.h | 3 +++
6 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/cpus.c b/cpus.c
index ca4c59f..945d85b 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1119,6 +1119,8 @@ void resume_all_vcpus(void)
static void qemu_tcg_init_vcpu(CPUState *cpu)
{
+ tcg_cpu_address_space_init(cpu, cpu->as);
+
/* share a single thread for all cpus with TCG */
if (!tcg_cpu_thread) {
cpu->thread = g_malloc0(sizeof(QemuThread));
diff --git a/cputlb.c b/cputlb.c
index 71cf64f..0fbaa39 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -232,6 +232,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
uintptr_t addend;
CPUTLBEntry *te;
hwaddr iotlb, xlat, sz;
+ CPUState *cpu = ENV_GET_CPU(env);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
@@ -239,7 +240,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
sz = size;
- section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+ section = address_space_translate_for_iotlb(cpu->as, paddr,
&xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
@@ -305,6 +306,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
int mmu_idx, page_index, pd;
void *p;
MemoryRegion *mr;
+ CPUState *cpu = ENV_GET_CPU(env1);
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = cpu_mmu_index(env1);
@@ -313,9 +315,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
- mr = iotlb_to_region(&address_space_memory, pd);
+ mr = iotlb_to_region(cpu->as, pd);
if (memory_region_is_unassigned(mr)) {
- CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->do_unassigned_access) {
diff --git a/exec.c b/exec.c
index d8cfe52..f299d06 100644
--- a/exec.c
+++ b/exec.c
@@ -138,6 +138,7 @@ typedef struct subpage_t {
static void io_mem_init(void);
static void memory_map_init(void);
+static void tcg_commit(MemoryListener *listener);
static MemoryRegion io_mem_watch;
#endif
@@ -438,6 +439,22 @@ CPUState *qemu_get_cpu(int index)
return NULL;
}
+#if !defined(CONFIG_USER_ONLY)
+void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as)
+{
+ /* We only support one address space per cpu at the moment. */
+ assert(cpu->as == as);
+
+ if (cpu->tcg_as_listener) {
+ memory_listener_unregister(cpu->tcg_as_listener);
+ } else {
+ cpu->tcg_as_listener = g_new0(MemoryListener, 1);
+ }
+ cpu->tcg_as_listener->commit = tcg_commit;
+ memory_listener_register(cpu->tcg_as_listener, as);
+}
+#endif
+
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
@@ -457,6 +474,7 @@ void cpu_exec_init(CPUArchState *env)
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
+ cpu->as = &address_space_memory;
cpu->thread_id = qemu_get_thread_id();
#endif
QTAILQ_INSERT_TAIL(&cpus, cpu, node);
@@ -488,7 +506,7 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
- tb_invalidate_phys_addr(&address_space_memory,
+ tb_invalidate_phys_addr(cpu->as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -1815,10 +1833,6 @@ static MemoryListener core_memory_listener = {
.priority = 1,
};
-static MemoryListener tcg_memory_listener = {
- .commit = tcg_commit,
-};
-
void address_space_init_dispatch(AddressSpace *as)
{
as->dispatch = NULL;
@@ -1854,9 +1868,6 @@ static void memory_map_init(void)
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);
- if (tcg_enabled()) {
- memory_listener_register(&tcg_memory_listener, &address_space_memory);
- }
}
MemoryRegion *get_system_memory(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 75fd1da..a387922 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -96,6 +96,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
+void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 69d856a..26215f9 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -119,7 +119,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
uintptr_t retaddr)
{
uint64_t val;
- MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
+ CPUState *cpu = ENV_GET_CPU(env);
+ MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
env->mem_io_pc = retaddr;
@@ -325,7 +326,8 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
- MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
+ CPUState *cpu = ENV_GET_CPU(env);
+ MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7739e00..367eda1 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -186,6 +186,9 @@ struct CPUState {
uint32_t interrupt_request;
int singlestep_enabled;
+ AddressSpace *as;
+ MemoryListener *tcg_as_listener;
+
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
struct GDBRegisterState *gdb_regs;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 07/22] exec: On AS changes, only flush affected CPU TLBs
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (5 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 08/22] exec: Make ldl_*_phys input an AddressSpace Edgar E. Iglesias
` (16 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index f299d06..a1d8bbe 100644
--- a/exec.c
+++ b/exec.c
@@ -1813,6 +1813,11 @@ static void tcg_commit(MemoryListener *listener)
CPU_FOREACH(cpu) {
CPUArchState *env = cpu->env_ptr;
+ /* FIXME: Disentangle the cpu.h circular files deps so we can
+ directly get the right CPU from listener. */
+ if (cpu->tcg_as_listener != listener) {
+ continue;
+ }
tlb_flush(env, 1);
}
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 08/22] exec: Make ldl_*_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (6 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 07/22] exec: On AS changes, only flush affected CPU TLBs Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 09/22] exec: Make ldq/ldub_*_phys " Edgar E. Iglesias
` (15 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cpu-exec.c | 5 +-
exec.c | 19 ++++---
hw/dma/pl080.c | 9 ++--
hw/dma/sun4m_iommu.c | 3 +-
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 13 +++--
hw/s390x/css.c | 3 +-
hw/s390x/s390-virtio-bus.c | 2 +-
hw/s390x/virtio-ccw.c | 5 +-
hw/scsi/megasas.c | 4 +-
hw/scsi/vmw_pvscsi.c | 3 +-
hw/virtio/virtio.c | 3 +-
include/exec/cpu-common.h | 6 +--
include/hw/ppc/spapr.h | 2 +-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 11 ++--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 15 +++---
target-i386/arch_memory_mapping.c | 36 ++++++-------
target-i386/helper.c | 9 ++--
target-i386/seg_helper.c | 6 ++-
target-i386/smm_helper.c | 103 ++++++++++++++++++++------------------
target-i386/svm_helper.c | 28 ++++++-----
target-ppc/excp_helper.c | 4 +-
target-ppc/mmu-hash32.h | 6 ++-
target-s390x/cpu.c | 2 +-
target-sparc/ldst_helper.c | 8 +--
target-sparc/mmu_helper.c | 20 ++++----
target-unicore32/softmmu.c | 5 +-
target-xtensa/helper.c | 3 +-
30 files changed, 190 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a6c01f4..8943493 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -395,7 +395,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
- intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
+ intno = ldl_phys(cpu->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+ control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index a1d8bbe..aa208be 100644
--- a/exec.c
+++ b/exec.c
@@ -1599,7 +1599,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
- case 4: return ldl_phys(addr);
+ case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2345,7 +2345,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2354,8 +2354,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+ mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2388,19 +2387,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index cb7bda9..741dd20 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E 0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
- ch->src = ldl_le_phys(ch->lli);
- ch->dest = ldl_le_phys(ch->lli + 4);
- ch->ctrl = ldl_le_phys(ch->lli + 12);
- ch->lli = ldl_le_phys(ch->lli + 8);
+ ch->src = ldl_le_phys(&address_space_memory, ch->lli);
+ ch->dest = ldl_le_phys(&address_space_memory, ch->lli + 4);
+ ch->ctrl = ldl_le_phys(&address_space_memory, ch->lli + 12);
+ ch->lli = ldl_le_phys(&address_space_memory, ch->lli + 8);
} else {
ch->conf &= ~PL080_CCONF_E;
}
diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4m_iommu.c
index a04409a..723f66d 100644
--- a/hw/dma/sun4m_iommu.c
+++ b/hw/dma/sun4m_iommu.c
@@ -24,6 +24,7 @@
#include "hw/sparc/sun4m.h"
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#include "trace.h"
/*
@@ -262,7 +263,7 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
- ret = ldl_be_phys(iopte);
+ ret = ldl_be_phys(&address_space_memory, iopte);
trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
return ret;
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 5307e2c..b465eb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -95,7 +95,7 @@ vmw_shmem_st16(hwaddr addr, uint16_t value)
static inline uint32_t
vmw_shmem_ld32(hwaddr addr)
{
- uint32_t res = ldl_le_phys(addr);
+ uint32_t res = ldl_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f755a53..7669b4a 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -390,6 +390,7 @@ static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint32_t size;
if (addr == 0) {
@@ -397,7 +398,7 @@ static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
- size = ldl_be_phys(addr + 0x4);
+ size = ldl_be_phys(cs->as, addr + 0x4);
if (size < 0x8) {
return H_PARAMETER;
}
@@ -425,6 +426,7 @@ static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint32_t size;
if (addr == 0) {
@@ -432,7 +434,7 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
- size = ldl_be_phys(addr + 0x4);
+ size = ldl_be_phys(cs->as, addr + 0x4);
if (size < 48) {
return H_PARAMETER;
@@ -532,6 +534,7 @@ static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
+ CPUState *cs = CPU(cpu);
target_ulong size = args[0];
target_ulong addr = args[1];
@@ -543,7 +546,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = lduw_phys(addr);
return H_SUCCESS;
case 4:
- args[0] = ldl_phys(addr);
+ args[0] = ldl_phys(cs->as, addr);
return H_SUCCESS;
case 8:
args[0] = ldq_phys(addr);
@@ -579,6 +582,8 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
+ CPUState *cs = CPU(cpu);
+
target_ulong dst = args[0]; /* Destination address */
target_ulong src = args[1]; /* Source address */
target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
@@ -611,7 +616,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = lduw_phys(src);
break;
case 2:
- tmp = ldl_phys(src);
+ tmp = ldl_phys(cs->as, src);
break;
case 3:
tmp = ldq_phys(src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 101da63..41b1903 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -11,6 +11,7 @@
#include <hw/qdev.h>
#include "qemu/bitops.h"
+#include "exec/address-spaces.h"
#include "cpu.h"
#include "ioinst.h"
#include "css.h"
@@ -667,7 +668,7 @@ static void css_update_chnmon(SubchDev *sch)
/* Format 1, per-subchannel area. */
uint32_t count;
- count = ldl_phys(sch->curr_status.mba);
+ count = ldl_phys(&address_space_memory, sch->curr_status.mba);
count++;
stl_phys(sch->curr_status.mba, count);
} else {
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 46c5ff1..3867708 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -409,7 +409,7 @@ void s390_virtio_device_update_status(VirtIOS390Device *dev)
/* Update guest supported feature bitmap */
- features = bswap32(ldl_be_phys(dev->feat_offs));
+ features = bswap32(ldl_be_phys(&address_space_memory, dev->feat_offs));
virtio_set_features(vdev, features);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index bc88712..8b0ab4a 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -263,7 +263,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
info.queue = ldq_phys(ccw.cda);
- info.align = ldl_phys(ccw.cda + sizeof(info.queue));
+ info.align = ldl_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue));
info.index = lduw_phys(ccw.cda + sizeof(info.queue)
+ sizeof(info.align));
info.num = lduw_phys(ccw.cda + sizeof(info.queue)
@@ -320,7 +321,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
features.index = ldub_phys(ccw.cda + sizeof(features.features));
- features.features = ldl_le_phys(ccw.cda);
+ features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
vdev->guest_features = features.features;
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 7c5a1a2..a655980 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -602,8 +602,8 @@ static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
pa_lo = le32_to_cpu(initq->pi_addr_lo);
pa_hi = le32_to_cpu(initq->pi_addr_hi);
s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
- s->reply_queue_head = ldl_le_phys(s->producer_pa);
- s->reply_queue_tail = ldl_le_phys(s->consumer_pa);
+ s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
+ s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
flags = le32_to_cpu(initq->flags);
if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
s->flags |= MEGASAS_MASK_USE_QUEUE64;
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 94b328f..6cc6c1b 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -43,7 +43,8 @@
(sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
#define RS_GET_FIELD(rs_pa, field) \
- (ldl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field)))
+ (ldl_le_phys(&address_space_memory, \
+ rs_pa + offsetof(struct PVSCSIRingsState, field)))
#define RS_SET_FIELD(rs_pa, field, val) \
(stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val))
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index a001e66..23d7544 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -14,6 +14,7 @@
#include <inttypes.h>
#include "trace.h"
+#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/virtio/virtio.h"
#include "qemu/atomic.h"
@@ -111,7 +112,7 @@ static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
- return ldl_phys(pa);
+ return ldl_phys(&address_space_memory, pa);
}
static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 8f33122..2b3d8f0 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -86,8 +86,8 @@ void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
-uint32_t ldl_le_phys(hwaddr addr);
-uint32_t ldl_be_phys(hwaddr addr);
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(hwaddr addr);
uint64_t ldq_be_phys(hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
@@ -100,7 +100,7 @@ void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(hwaddr addr);
-uint32_t ldl_phys(hwaddr addr);
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index b2f11e9..6c705f1 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -348,7 +348,7 @@ static inline uint64_t ppc64_phys_to_real(uint64_t addr)
static inline uint32_t rtas_ld(target_ulong phys, int n)
{
- return ldl_be_phys(ppc64_phys_to_real(phys + 4*n));
+ return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
}
static inline void rtas_st(target_ulong phys, int n, uint32_t val)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 5a0e78c..3977702 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -101,7 +101,7 @@ DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
-DEF_HELPER_1(ldl_phys, i64, i64)
+DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_1(ldq_phys, i64, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 7160a1c..61e8164 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -24,9 +24,10 @@
/* Softmmu support */
#ifndef CONFIG_USER_ONLY
-uint64_t helper_ldl_phys(uint64_t p)
+uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p)
{
- return (int32_t)ldl_phys(p);
+ CPUState *cs = ENV_GET_CPU(env);
+ return (int32_t)ldl_phys(cs->as, p);
}
uint64_t helper_ldq_phys(uint64_t p)
@@ -36,8 +37,9 @@ uint64_t helper_ldq_phys(uint64_t p)
uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
{
+ CPUState *cs = ENV_GET_CPU(env);
env->lock_addr = p;
- return env->lock_value = (int32_t)ldl_phys(p);
+ return env->lock_value = (int32_t)ldl_phys(cs->as, p);
}
uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
@@ -58,10 +60,11 @@ void helper_stq_phys(uint64_t p, uint64_t v)
uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
if (p == env->lock_addr) {
- int32_t old = ldl_phys(p);
+ int32_t old = ldl_phys(cs->as, p);
if (old == (int32_t)env->lock_value) {
stl_phys(p, v);
ret = 1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1155e86..802c49a 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2912,7 +2912,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
- gen_helper_ldl_phys(cpu_ir[ra], addr);
+ gen_helper_ldl_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ca5b000..4b4628a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2455,8 +2455,9 @@ static void v7m_push(CPUARMState *env, uint32_t val)
static uint32_t v7m_pop(CPUARMState *env)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint32_t val;
- val = ldl_phys(env->regs[13]);
+ val = ldl_phys(cs->as, env->regs[13]);
env->regs[13] += 4;
return val;
}
@@ -2611,7 +2612,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
- addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
+ addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
}
@@ -2816,6 +2817,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
int is_user, hwaddr *phys_ptr,
int *prot, target_ulong *page_size)
{
+ CPUState *cs = ENV_GET_CPU(env);
int code;
uint32_t table;
uint32_t desc;
@@ -2828,7 +2830,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
- desc = ldl_phys(table);
+ desc = ldl_phys(cs->as, table);
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
@@ -2859,7 +2861,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
- desc = ldl_phys(table);
+ desc = ldl_phys(cs->as, table);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
@@ -2911,6 +2913,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
int is_user, hwaddr *phys_ptr,
int *prot, target_ulong *page_size)
{
+ CPUState *cs = ENV_GET_CPU(env);
int code;
uint32_t table;
uint32_t desc;
@@ -2925,7 +2928,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
- desc = ldl_phys(table);
+ desc = ldl_phys(cs->as, table);
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
@@ -2967,7 +2970,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
}
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
- desc = ldl_phys(table);
+ desc = ldl_phys(cs->as, table);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c
index 462f984..a194709 100644
--- a/target-i386/arch_memory_mapping.c
+++ b/target-i386/arch_memory_mapping.c
@@ -16,7 +16,8 @@
#include "sysemu/memory_mapping.h"
/* PAE Paging or IA-32e Paging */
-static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
+static void walk_pte(MemoryMappingList *list, AddressSpace *as,
+ hwaddr pte_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pte_addr, start_paddr;
@@ -45,7 +46,7 @@ static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
}
/* 32-bit Paging */
-static void walk_pte2(MemoryMappingList *list,
+static void walk_pte2(MemoryMappingList *list, AddressSpace *as,
hwaddr pte_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -56,7 +57,7 @@ static void walk_pte2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pte_addr = (pte_start_addr + i * 4) & a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -77,7 +78,8 @@ static void walk_pte2(MemoryMappingList *list,
/* PAE Paging or IA-32e Paging */
#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */
-static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
+static void walk_pde(MemoryMappingList *list, AddressSpace *as,
+ hwaddr pde_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pde_addr, pte_start_addr, start_paddr;
@@ -108,12 +110,12 @@ static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
}
pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
- walk_pte(list, pte_start_addr, a20_mask, line_addr);
+ walk_pte(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* 32-bit Paging */
-static void walk_pde2(MemoryMappingList *list,
+static void walk_pde2(MemoryMappingList *list, AddressSpace *as,
hwaddr pde_start_addr, int32_t a20_mask,
bool pse)
{
@@ -124,7 +126,7 @@ static void walk_pde2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pde_addr = (pde_start_addr + i * 4) & a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -150,12 +152,12 @@ static void walk_pde2(MemoryMappingList *list,
}
pte_start_addr = (pde & ~0xfff) & a20_mask;
- walk_pte2(list, pte_start_addr, a20_mask, line_addr);
+ walk_pte2(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* PAE Paging */
-static void walk_pdpe2(MemoryMappingList *list,
+static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask)
{
hwaddr pdpe_addr, pde_start_addr;
@@ -173,13 +175,13 @@ static void walk_pdpe2(MemoryMappingList *list,
line_addr = (((unsigned int)i & 0x3) << 30);
pde_start_addr = (pdpe & ~0xfff) & a20_mask;
- walk_pde(list, pde_start_addr, a20_mask, line_addr);
+ walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
#ifdef TARGET_X86_64
/* IA-32e Paging */
-static void walk_pdpe(MemoryMappingList *list,
+static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -211,12 +213,12 @@ static void walk_pdpe(MemoryMappingList *list,
}
pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
- walk_pde(list, pde_start_addr, a20_mask, line_addr);
+ walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
/* IA-32e Paging */
-static void walk_pml4e(MemoryMappingList *list,
+static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
hwaddr pml4e_start_addr, int32_t a20_mask)
{
hwaddr pml4e_addr, pdpe_start_addr;
@@ -234,7 +236,7 @@ static void walk_pml4e(MemoryMappingList *list,
line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
- walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
+ walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr);
}
}
#endif
@@ -256,14 +258,14 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
hwaddr pml4e_addr;
pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
- walk_pml4e(list, pml4e_addr, env->a20_mask);
+ walk_pml4e(list, cs->as, pml4e_addr, env->a20_mask);
} else
#endif
{
hwaddr pdpe_addr;
pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
- walk_pdpe2(list, pdpe_addr, env->a20_mask);
+ walk_pdpe2(list, cs->as, pdpe_addr, env->a20_mask);
}
} else {
hwaddr pde_addr;
@@ -271,7 +273,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
pse = !!(env->cr[4] & CR4_PSE_MASK);
- walk_pde2(list, pde_addr, env->a20_mask, pse);
+ walk_pde2(list, cs->as, pde_addr, env->a20_mask, pse);
}
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index fe613b2..2899779 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -515,6 +515,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write1, int mmu_idx)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
int error_code, is_dirty, prot, page_size, is_write, is_user;
@@ -734,7 +735,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
env->a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -792,7 +793,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
env->a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -963,7 +964,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK))
return -1;
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@@ -972,7 +973,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
} else {
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK))
return -1;
page_size = 4096;
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index e789102..6b18b3e 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1131,7 +1131,8 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
static void handle_even_inj(CPUX86State *env, int intno, int is_int,
int error_code, int is_hw, int rm)
{
- uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ CPUState *cs = ENV_GET_CPU(env);
+ uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
if (!(event_inj & SVM_EVTINJ_VALID)) {
@@ -1225,7 +1226,8 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & HF_SVMI_MASK) {
- uint32_t event_inj = ldl_phys(env->vm_vmcb +
+ CPUState *cs = CPU(cpu);
+ uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.event_inj));
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 6cb4551..67a73c0 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -180,6 +180,7 @@ void do_smm_enter(X86CPU *cpu)
void helper_rsm(CPUX86State *env)
{
+ CPUState *cs = ENV_GET_CPU(env);
X86CPU *cpu = x86_env_get_cpu(env);
target_ulong sm_state;
int i, offset;
@@ -194,25 +195,25 @@ void helper_rsm(CPUX86State *env)
cpu_x86_load_seg_cache(env, i,
lduw_phys(sm_state + offset),
ldq_phys(sm_state + offset + 8),
- ldl_phys(sm_state + offset + 4),
+ ldl_phys(cs->as, sm_state + offset + 4),
(lduw_phys(sm_state + offset + 2) &
0xf0ff) << 8);
}
env->gdt.base = ldq_phys(sm_state + 0x7e68);
- env->gdt.limit = ldl_phys(sm_state + 0x7e64);
+ env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64);
env->ldt.selector = lduw_phys(sm_state + 0x7e70);
env->ldt.base = ldq_phys(sm_state + 0x7e78);
- env->ldt.limit = ldl_phys(sm_state + 0x7e74);
+ env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7e74);
env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
env->idt.base = ldq_phys(sm_state + 0x7e88);
- env->idt.limit = ldl_phys(sm_state + 0x7e84);
+ env->idt.limit = ldl_phys(cs->as, sm_state + 0x7e84);
env->tr.selector = lduw_phys(sm_state + 0x7e90);
env->tr.base = ldq_phys(sm_state + 0x7e98);
- env->tr.limit = ldl_phys(sm_state + 0x7e94);
+ env->tr.limit = ldl_phys(cs->as, sm_state + 0x7e94);
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
@@ -227,51 +228,51 @@ void helper_rsm(CPUX86State *env)
env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
}
env->eip = ldq_phys(sm_state + 0x7f78);
- cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
+ cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7f70),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
- env->dr[6] = ldl_phys(sm_state + 0x7f68);
- env->dr[7] = ldl_phys(sm_state + 0x7f60);
+ env->dr[6] = ldl_phys(cs->as, sm_state + 0x7f68);
+ env->dr[7] = ldl_phys(cs->as, sm_state + 0x7f60);
- cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
- cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
- cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
+ cpu_x86_update_cr4(env, ldl_phys(cs->as, sm_state + 0x7f48));
+ cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7f50));
+ cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7f58));
- val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+ val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
+ env->smbase = ldl_phys(cs->as, sm_state + 0x7f00) & ~0x7fff;
}
#else
- cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
- cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
- cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
+ cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7ffc));
+ cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7ff8));
+ cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7ff4),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
- env->eip = ldl_phys(sm_state + 0x7ff0);
- env->regs[R_EDI] = ldl_phys(sm_state + 0x7fec);
- env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8);
- env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
- env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
- env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
- env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
- env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
- env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
- env->dr[6] = ldl_phys(sm_state + 0x7fcc);
- env->dr[7] = ldl_phys(sm_state + 0x7fc8);
-
- env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
- env->tr.base = ldl_phys(sm_state + 0x7f64);
- env->tr.limit = ldl_phys(sm_state + 0x7f60);
- env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
-
- env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
- env->ldt.base = ldl_phys(sm_state + 0x7f80);
- env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
- env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
-
- env->gdt.base = ldl_phys(sm_state + 0x7f74);
- env->gdt.limit = ldl_phys(sm_state + 0x7f70);
-
- env->idt.base = ldl_phys(sm_state + 0x7f58);
- env->idt.limit = ldl_phys(sm_state + 0x7f54);
+ env->eip = ldl_phys(cs->as, sm_state + 0x7ff0);
+ env->regs[R_EDI] = ldl_phys(cs->as, sm_state + 0x7fec);
+ env->regs[R_ESI] = ldl_phys(cs->as, sm_state + 0x7fe8);
+ env->regs[R_EBP] = ldl_phys(cs->as, sm_state + 0x7fe4);
+ env->regs[R_ESP] = ldl_phys(cs->as, sm_state + 0x7fe0);
+ env->regs[R_EBX] = ldl_phys(cs->as, sm_state + 0x7fdc);
+ env->regs[R_EDX] = ldl_phys(cs->as, sm_state + 0x7fd8);
+ env->regs[R_ECX] = ldl_phys(cs->as, sm_state + 0x7fd4);
+ env->regs[R_EAX] = ldl_phys(cs->as, sm_state + 0x7fd0);
+ env->dr[6] = ldl_phys(cs->as, sm_state + 0x7fcc);
+ env->dr[7] = ldl_phys(cs->as, sm_state + 0x7fc8);
+
+ env->tr.selector = ldl_phys(cs->as, sm_state + 0x7fc4) & 0xffff;
+ env->tr.base = ldl_phys(cs->as, sm_state + 0x7f64);
+ env->tr.limit = ldl_phys(cs->as, sm_state + 0x7f60);
+ env->tr.flags = (ldl_phys(cs->as, sm_state + 0x7f5c) & 0xf0ff) << 8;
+
+ env->ldt.selector = ldl_phys(cs->as, sm_state + 0x7fc0) & 0xffff;
+ env->ldt.base = ldl_phys(cs->as, sm_state + 0x7f80);
+ env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7f7c);
+ env->ldt.flags = (ldl_phys(cs->as, sm_state + 0x7f78) & 0xf0ff) << 8;
+
+ env->gdt.base = ldl_phys(cs->as, sm_state + 0x7f74);
+ env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7f70);
+
+ env->idt.base = ldl_phys(cs->as, sm_state + 0x7f58);
+ env->idt.limit = ldl_phys(cs->as, sm_state + 0x7f54);
for (i = 0; i < 6; i++) {
if (i < 3) {
@@ -280,16 +281,18 @@ void helper_rsm(CPUX86State *env)
offset = 0x7f2c + (i - 3) * 12;
}
cpu_x86_load_seg_cache(env, i,
- ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
- ldl_phys(sm_state + offset + 8),
- ldl_phys(sm_state + offset + 4),
- (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
+ ldl_phys(cs->as,
+ sm_state + 0x7fa8 + i * 4) & 0xffff,
+ ldl_phys(cs->as, sm_state + offset + 8),
+ ldl_phys(cs->as, sm_state + offset + 4),
+ (ldl_phys(cs->as,
+ sm_state + offset) & 0xf0ff) << 8);
}
- cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
+ cpu_x86_update_cr4(env, ldl_phys(cs->as, sm_state + 0x7f14));
- val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+ val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
+ env->smbase = ldl_phys(cs->as, sm_state + 0x7ef8) & ~0x7fff;
}
#endif
CC_OP = CC_OP_EFLAGS;
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 4a7de42..6c3c8bf 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -101,11 +101,12 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
SegmentCache *sc)
{
+ CPUState *cs = ENV_GET_CPU(env);
unsigned int flags;
sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
- sc->limit = ldl_phys(addr + offsetof(struct vmcb_seg, limit));
+ sc->limit = ldl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit));
flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
@@ -122,6 +123,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
{
+ CPUState *cs = ENV_GET_CPU(env);
target_ulong addr;
uint32_t event_inj;
uint32_t int_ctl;
@@ -190,7 +192,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->intercept_dr_write = lduw_phys(env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_write));
- env->intercept_exceptions = ldl_phys(env->vm_vmcb +
+ env->intercept_exceptions = ldl_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_exceptions
));
@@ -203,12 +205,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.base));
- env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->gdt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.limit));
env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.idtr.base));
- env->idt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->idt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.limit));
/* clear exit_info_2 so we behave like the real hardware */
@@ -221,7 +223,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.cr3)));
env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
- int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ int_ctl = ldl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
if (int_ctl & V_INTR_MASKING_MASK) {
env->v_tpr = int_ctl & V_TPR_MASK;
@@ -277,12 +280,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
}
/* maybe we need to inject an event */
- event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
if (event_inj & SVM_EVTINJ_VALID) {
uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK;
uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR;
- uint32_t event_inj_err = ldl_phys(env->vm_vmcb +
+ uint32_t event_inj_err = ldl_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.event_inj_err));
@@ -594,7 +597,8 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
- int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ int_ctl = ldl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK);
int_ctl |= env->v_tpr & V_TPR_MASK;
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
@@ -623,12 +627,12 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.gdtr.base));
- env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->gdt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.limit));
env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.idtr.base));
- env->idt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->idt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.limit));
cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
@@ -674,10 +678,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
exit_info_1);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
- ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj)));
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
- ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err)));
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 26c57d9..d541929 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -180,12 +180,14 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
msr |= env->error_code;
goto store_next;
case POWERPC_EXCP_EXTERNAL: /* External input */
+ cs = CPU(cpu);
+
if (lpes0 == 1) {
new_msr |= (target_ulong)MSR_HVB;
}
if (env->mpic_proxy) {
/* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(env->mpic_iack);
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
}
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 884786b..b403d77 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -68,15 +68,17 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
hwaddr pte_offset)
{
+ CPUState *cs = ENV_GET_CPU(env);
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(env->htab_base + pte_offset);
+ return ldl_phys(cs->as, env->htab_base + pte_offset);
}
static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
hwaddr pte_offset)
{
+ CPUState *cs = ENV_GET_CPU(env);
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
+ return ldl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
}
static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 3c89f8a..ff57b80 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -70,7 +70,7 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
static void s390_cpu_load_normal(CPUState *s)
{
S390CPU *cpu = S390_CPU(s);
- cpu->env.psw.addr = ldl_phys(4) & PSW_MASK_ESA_ADDR;
+ cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR;
cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64;
s390_add_running_cpu(cpu);
}
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2936b58..6f95105 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -447,6 +447,7 @@ static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int sign)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_addr = addr;
@@ -615,7 +616,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 4:
- ret = ldl_phys(addr);
+ ret = ldl_phys(cs->as, addr);
break;
case 8:
ret = ldq_phys(addr);
@@ -634,7 +635,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 4:
- ret = ldl_phys((hwaddr)addr
+ ret = ldl_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
case 8:
@@ -1284,6 +1285,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int sign)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
#if defined(DEBUG_ASI)
target_ulong last_addr = addr;
@@ -1438,7 +1440,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = lduw_phys(addr);
break;
case 4:
- ret = ldl_phys(addr);
+ ret = ldl_phys(cs->as, addr);
break;
default:
case 8:
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index ef12a0a..46bb038 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -86,6 +86,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
uint32_t pde;
int error_code = 0, is_dirty, is_user;
unsigned long page_offset;
+ CPUState *cs = ENV_GET_CPU(env);
is_user = mmu_idx == MMU_USER_IDX;
@@ -108,7 +109,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
/* Ctx pde */
switch (pde & PTE_ENTRYTYPE_MASK) {
@@ -120,7 +121,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return 4 << 2;
case 1: /* L0 PDE */
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -130,7 +131,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return (1 << 8) | (4 << 2);
case 1: /* L1 PDE */
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -140,7 +141,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return (2 << 8) | (4 << 2);
case 1: /* L2 PDE */
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -244,13 +245,14 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
{
+ CPUState *cs = ENV_GET_CPU(env);
hwaddr pde_ptr;
uint32_t pde;
/* Context base + context number */
pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -263,7 +265,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -277,7 +279,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -291,7 +293,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -317,7 +319,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
uint32_t pde;
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(cs->as, pde_ptr);
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 1e13a85..22defc6 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -121,6 +121,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
int access_type, int is_user, uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
{
+ CPUState *cs = ENV_GET_CPU(env);
int code;
uint32_t table;
uint32_t desc;
@@ -130,7 +131,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
/* Lookup l1 descriptor. */
table = env->cp0.c2_base & 0xfffff000;
table |= (address >> 20) & 0xffc;
- desc = ldl_phys(table);
+ desc = ldl_phys(cs->as, table);
code = 0;
switch (PAGETABLE_TYPE(desc)) {
case 3:
@@ -152,7 +153,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
goto do_fault;
}
table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
- desc = ldl_phys(table);
+ desc = ldl_phys(cs->as, table);
/* 4k page. */
if (is_user) {
DPRINTF("PTE address %x, desc %x\n", table, desc);
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index a0f9993..60cb055 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -552,6 +552,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint32_t paddr;
uint32_t page_size;
unsigned access;
@@ -564,7 +565,7 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
vaddr, ret ? ~0 : paddr);
if (ret == 0) {
- *pte = ldl_phys(paddr);
+ *pte = ldl_phys(cs->as, paddr);
}
return ret;
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 09/22] exec: Make ldq/ldub_*_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (7 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 08/22] exec: Make ldl_*_phys input an AddressSpace Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 10/22] exec: Make lduw_*_phys " Edgar E. Iglesias
` (14 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 22 +++----
hw/alpha/typhoon.c | 2 +-
hw/display/sm501.c | 1 +
hw/display/sm501_template.h | 2 +-
hw/net/vmware_utils.h | 4 +-
hw/ppc/spapr_hcall.c | 11 ++--
hw/s390x/s390-virtio-bus.c | 5 +-
hw/s390x/virtio-ccw.c | 18 +++---
hw/scsi/megasas.c | 3 +-
hw/virtio/virtio.c | 2 +-
include/exec/cpu-common.h | 8 +--
monitor.c | 2 +-
target-alpha/helper.c | 7 ++-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 11 ++--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 3 +-
target-i386/arch_memory_mapping.c | 10 ++--
target-i386/helper.c | 20 +++----
target-i386/smm_helper.c | 32 +++++------
target-i386/svm_helper.c | 117 +++++++++++++++++++++++---------------
target-ppc/mmu-hash64.h | 7 ++-
target-s390x/helper.c | 3 +-
target-s390x/mem_helper.c | 3 +-
target-sparc/ldst_helper.c | 25 ++++----
25 files changed, 185 insertions(+), 137 deletions(-)
diff --git a/exec.c b/exec.c
index aa208be..3bc4497 100644
--- a/exec.c
+++ b/exec.c
@@ -1597,7 +1597,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
- case 1: return ldub_phys(addr);
+ case 1: return ldub_phys(&address_space_memory, addr);
case 2: return lduw_phys(addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
@@ -2403,7 +2403,7 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(hwaddr addr,
+static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2412,7 +2412,7 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
hwaddr l = 8;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 8 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2446,26 +2446,26 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
return val;
}
-uint64_t ldq_phys(hwaddr addr)
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
{
- return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(hwaddr addr)
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
{
- return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(hwaddr addr)
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
{
- return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(hwaddr addr)
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
{
uint8_t val;
- cpu_physical_memory_read(addr, &val, 1);
+ address_space_rw(as, addr, &val, 1, 0);
return val;
}
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 71a5a37..67a1070 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -613,7 +613,7 @@ static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask, IOMMUTLBEntry *ret)
translation, given the address of the PTE. */
static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)
{
- uint64_t pte = ldq_phys(pte_addr);
+ uint64_t pte = ldq_phys(&address_space_memory, pte_addr);
/* Check valid bit. */
if ((pte & 1) == 0) {
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index c75d6ac..0b5f993 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
+#include "exec/address-spaces.h"
/*
* Status: 2010/05/07
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 2d4a3d8..d4cea9e 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -120,7 +120,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt,
/* get pixel value */
if (i % 4 == 0) {
- bitset = ldub_phys(cursor_addr);
+ bitset = ldub_phys(&address_space_memory, cursor_addr);
cursor_addr++;
}
v = bitset & 3;
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index b465eb6..eb98d2a 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -65,7 +65,7 @@ vmw_shmem_set(hwaddr addr, uint8 val, int len)
static inline uint32_t
vmw_shmem_ld8(hwaddr addr)
{
- uint8_t res = ldub_phys(addr);
+ uint8_t res = ldub_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
@@ -110,7 +110,7 @@ vmw_shmem_st32(hwaddr addr, uint32_t value)
static inline uint64_t
vmw_shmem_ld64(hwaddr addr)
{
- uint64_t res = ldq_le_phys(addr);
+ uint64_t res = ldq_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 7669b4a..6e61a91 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -341,6 +341,7 @@ static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint16_t size;
uint8_t tmp;
@@ -367,7 +368,7 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
env->vpa_addr = vpa;
- tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET);
+ tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
@@ -540,7 +541,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
switch (size) {
case 1:
- args[0] = ldub_phys(addr);
+ args[0] = ldub_phys(cs->as, addr);
return H_SUCCESS;
case 2:
args[0] = lduw_phys(addr);
@@ -549,7 +550,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = ldl_phys(cs->as, addr);
return H_SUCCESS;
case 8:
- args[0] = ldq_phys(addr);
+ args[0] = ldq_phys(cs->as, addr);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -610,7 +611,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
while (count--) {
switch (esize) {
case 0:
- tmp = ldub_phys(src);
+ tmp = ldub_phys(cs->as, src);
break;
case 1:
tmp = lduw_phys(src);
@@ -619,7 +620,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = ldl_phys(cs->as, src);
break;
case 3:
- tmp = ldq_phys(src);
+ tmp = ldq_phys(cs->as, src);
break;
default:
return H_PARAMETER;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 3867708..83e7287 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -324,7 +324,7 @@ static uint64_t s390_virtio_device_vq_token(VirtIOS390Device *dev, int vq)
(vq * VIRTIO_VQCONFIG_LEN) +
VIRTIO_VQCONFIG_OFFS_TOKEN;
- return ldq_be_phys(token_off);
+ return ldq_be_phys(&address_space_memory, token_off);
}
static ram_addr_t s390_virtio_device_num_vq(VirtIOS390Device *dev)
@@ -405,7 +405,8 @@ void s390_virtio_device_update_status(VirtIOS390Device *dev)
VirtIODevice *vdev = dev->vdev;
uint32_t features;
- virtio_set_status(vdev, ldub_phys(dev->dev_offs + VIRTIO_DEV_OFFS_STATUS));
+ virtio_set_status(vdev, ldub_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_STATUS));
/* Update guest supported feature bitmap */
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 8b0ab4a..d301f00 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -262,7 +262,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- info.queue = ldq_phys(ccw.cda);
+ info.queue = ldq_phys(&address_space_memory, ccw.cda);
info.align = ldl_phys(&address_space_memory,
ccw.cda + sizeof(info.queue));
info.index = lduw_phys(ccw.cda + sizeof(info.queue)
@@ -294,7 +294,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- features.index = ldub_phys(ccw.cda + sizeof(features.features));
+ features.index = ldub_phys(&address_space_memory,
+ ccw.cda + sizeof(features.features));
if (features.index < ARRAY_SIZE(dev->host_features)) {
features.features = dev->host_features[features.index];
} else {
@@ -320,7 +321,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- features.index = ldub_phys(ccw.cda + sizeof(features.features));
+ features.index = ldub_phys(&address_space_memory,
+ ccw.cda + sizeof(features.features));
features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
@@ -398,7 +400,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- status = ldub_phys(ccw.cda);
+ status = ldub_phys(&address_space_memory, ccw.cda);
if (!(status & VIRTIO_CONFIG_S_DRIVER_OK)) {
virtio_ccw_stop_ioeventfd(dev);
}
@@ -427,7 +429,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- indicators = ldq_phys(ccw.cda);
+ indicators = ldq_phys(&address_space_memory, ccw.cda);
dev->indicators = indicators;
sch->curr_status.scsw.count = ccw.count - sizeof(indicators);
ret = 0;
@@ -447,7 +449,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- indicators = ldq_phys(ccw.cda);
+ indicators = ldq_phys(&address_space_memory, ccw.cda);
dev->indicators2 = indicators;
sch->curr_status.scsw.count = ccw.count - sizeof(indicators);
ret = 0;
@@ -867,7 +869,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
if (!dev->indicators) {
return;
}
- indicators = ldq_phys(dev->indicators);
+ indicators = ldq_phys(&address_space_memory, dev->indicators);
indicators |= 1ULL << vector;
stq_phys(dev->indicators, indicators);
} else {
@@ -875,7 +877,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
return;
}
vector = 0;
- indicators = ldq_phys(dev->indicators2);
+ indicators = ldq_phys(&address_space_memory, dev->indicators2);
indicators |= 1ULL << vector;
stq_phys(dev->indicators2, indicators);
}
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index a655980..33bcb97 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -158,7 +158,8 @@ static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
*/
static uint64_t megasas_frame_get_context(unsigned long frame)
{
- return ldq_le_phys(frame + offsetof(struct mfi_frame_header, context));
+ return ldq_le_phys(&address_space_memory,
+ frame + offsetof(struct mfi_frame_header, context));
}
static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 23d7544..4c04a69 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -105,7 +105,7 @@ static inline uint64_t vring_desc_addr(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, addr);
- return ldq_phys(pa);
+ return ldq_phys(&address_space_memory, pa);
}
static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 2b3d8f0..6f60f2c 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -83,13 +83,13 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr);
*/
void qemu_flush_coalesced_mmio_buffer(void);
-uint32_t ldub_phys(hwaddr addr);
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
-uint64_t ldq_le_phys(hwaddr addr);
-uint64_t ldq_be_phys(hwaddr addr);
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
@@ -101,7 +101,7 @@ void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
-uint64_t ldq_phys(hwaddr addr);
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(hwaddr addr, uint32_t val);
diff --git a/monitor.c b/monitor.c
index cba56bc..a55fb04 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1445,7 +1445,7 @@ static void do_sum(Monitor *mon, const QDict *qdict)
sum = 0;
for(addr = start; addr < (start + size); addr++) {
- uint8_t val = ldub_phys(addr);
+ uint8_t val = ldub_phys(&address_space_memory, addr);
/* BSD sum algorithm ('sum' Unix command) */
sum = (sum >> 1) | (sum << 15);
sum += val;
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index fc61bb0..025fdaf 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -213,6 +213,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
int prot_need, int mmu_idx,
target_ulong *pphys, int *pprot)
{
+ CPUState *cs = ENV_GET_CPU(env);
target_long saddr = addr;
target_ulong phys = 0;
target_ulong L1pte, L2pte, L3pte;
@@ -251,7 +252,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L1 page table read. */
index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
- L1pte = ldq_phys(pt + index*8);
+ L1pte = ldq_phys(cs->as, pt + index*8);
if (unlikely((L1pte & PTE_VALID) == 0)) {
ret = MM_K_TNV;
@@ -264,7 +265,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L2 page table read. */
index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff;
- L2pte = ldq_phys(pt + index*8);
+ L2pte = ldq_phys(cs->as, pt + index*8);
if (unlikely((L2pte & PTE_VALID) == 0)) {
ret = MM_K_TNV;
@@ -277,7 +278,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L3 page table read. */
index = (addr >> TARGET_PAGE_BITS) & 0x3ff;
- L3pte = ldq_phys(pt + index*8);
+ L3pte = ldq_phys(cs->as, pt + index*8);
phys = L3pte >> 32 << TARGET_PAGE_BITS;
if (unlikely((L3pte & PTE_VALID) == 0)) {
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 3977702..74dbd07 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -102,7 +102,7 @@ DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
DEF_HELPER_2(ldl_phys, i64, env, i64)
-DEF_HELPER_1(ldq_phys, i64, i64)
+DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
DEF_HELPER_2(stl_phys, void, i64, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 61e8164..5b47b04 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -30,9 +30,10 @@ uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p)
return (int32_t)ldl_phys(cs->as, p);
}
-uint64_t helper_ldq_phys(uint64_t p)
+uint64_t helper_ldq_phys(CPUAlphaState *env, uint64_t p)
{
- return ldq_phys(p);
+ CPUState *cs = ENV_GET_CPU(env);
+ return ldq_phys(cs->as, p);
}
uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
@@ -44,8 +45,9 @@ uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
{
+ CPUState *cs = ENV_GET_CPU(env);
env->lock_addr = p;
- return env->lock_value = ldq_phys(p);
+ return env->lock_value = ldq_phys(cs->as, p);
}
void helper_stl_phys(uint64_t p, uint64_t v)
@@ -77,10 +79,11 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
if (p == env->lock_addr) {
- uint64_t old = ldq_phys(p);
+ uint64_t old = ldq_phys(cs->as, p);
if (old == env->lock_value) {
stq_phys(p, v);
ret = 1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 802c49a..f60ee35 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2916,7 +2916,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
- gen_helper_ldq_phys(cpu_ir[ra], addr);
+ gen_helper_ldq_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4b4628a..6a3db66 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3036,6 +3036,7 @@ static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
hwaddr *phys_ptr, int *prot,
target_ulong *page_size_ptr)
{
+ CPUState *cs = ENV_GET_CPU(env);
/* Read an LPAE long-descriptor translation table. */
MMUFaultType fault_type = translation_fault;
uint32_t level = 1;
@@ -3124,7 +3125,7 @@ static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
uint64_t descriptor;
descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
- descriptor = ldq_phys(descaddr);
+ descriptor = ldq_phys(cs->as, descaddr);
if (!(descriptor & 1) ||
(!(descriptor & 2) && (level == 3))) {
/* Invalid, or the Reserved level 3 encoding */
diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c
index a194709..2d35f63 100644
--- a/target-i386/arch_memory_mapping.c
+++ b/target-i386/arch_memory_mapping.c
@@ -27,7 +27,7 @@ static void walk_pte(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pte_addr = (pte_start_addr + i * 8) & a20_mask;
- pte = ldq_phys(pte_addr);
+ pte = ldq_phys(as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -89,7 +89,7 @@ static void walk_pde(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pde_addr = (pde_start_addr + i * 8) & a20_mask;
- pde = ldq_phys(pde_addr);
+ pde = ldq_phys(as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -167,7 +167,7 @@ static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 4; i++) {
pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -192,7 +192,7 @@ static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -228,7 +228,7 @@ static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
- pml4e = ldq_phys(pml4e_addr);
+ pml4e = ldq_phys(as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK)) {
/* not present */
continue;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2899779..02a68bd 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -563,7 +563,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
env->a20_mask;
- pml4e = ldq_phys(pml4e_addr);
+ pml4e = ldq_phys(cs->as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -579,7 +579,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(cs->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -599,7 +599,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* XXX: load them when cr3 is loaded ? */
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(cs->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -609,7 +609,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
env->a20_mask;
- pde = ldq_phys(pde_addr);
+ pde = ldq_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -674,7 +674,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
}
pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
env->a20_mask;
- pte = ldq_phys(pte_addr);
+ pte = ldq_phys(cs->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -920,13 +920,13 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
env->a20_mask;
- pml4e = ldq_phys(pml4e_addr);
+ pml4e = ldq_phys(cs->as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK))
return -1;
pdpe_addr = ((pml4e & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
(((addr >> 30) & 0x1ff) << 3)) & env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(cs->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK))
return -1;
} else
@@ -934,14 +934,14 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(cs->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK))
return -1;
}
pde_addr = ((pdpe & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
(((addr >> 21) & 0x1ff) << 3)) & env->a20_mask;
- pde = ldq_phys(pde_addr);
+ pde = ldq_phys(cs->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
return -1;
}
@@ -954,7 +954,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
pte_addr = ((pde & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
(((addr >> 12) & 0x1ff) << 3)) & env->a20_mask;
page_size = 4096;
- pte = ldq_phys(pte_addr);
+ pte = ldq_phys(cs->as, pte_addr);
}
pte &= ~(PG_NX_MASK | PG_HI_USER_MASK);
if (!(pte & PG_PRESENT_MASK))
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 67a73c0..17a568c 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -188,46 +188,46 @@ void helper_rsm(CPUX86State *env)
sm_state = env->smbase + 0x8000;
#ifdef TARGET_X86_64
- cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));
+ cpu_load_efer(env, ldq_phys(cs->as, sm_state + 0x7ed0));
for (i = 0; i < 6; i++) {
offset = 0x7e00 + i * 16;
cpu_x86_load_seg_cache(env, i,
lduw_phys(sm_state + offset),
- ldq_phys(sm_state + offset + 8),
+ ldq_phys(cs->as, sm_state + offset + 8),
ldl_phys(cs->as, sm_state + offset + 4),
(lduw_phys(sm_state + offset + 2) &
0xf0ff) << 8);
}
- env->gdt.base = ldq_phys(sm_state + 0x7e68);
+ env->gdt.base = ldq_phys(cs->as, sm_state + 0x7e68);
env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64);
env->ldt.selector = lduw_phys(sm_state + 0x7e70);
- env->ldt.base = ldq_phys(sm_state + 0x7e78);
+ env->ldt.base = ldq_phys(cs->as, sm_state + 0x7e78);
env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7e74);
env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
- env->idt.base = ldq_phys(sm_state + 0x7e88);
+ env->idt.base = ldq_phys(cs->as, sm_state + 0x7e88);
env->idt.limit = ldl_phys(cs->as, sm_state + 0x7e84);
env->tr.selector = lduw_phys(sm_state + 0x7e90);
- env->tr.base = ldq_phys(sm_state + 0x7e98);
+ env->tr.base = ldq_phys(cs->as, sm_state + 0x7e98);
env->tr.limit = ldl_phys(cs->as, sm_state + 0x7e94);
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
- env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
- env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
- env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
- env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
- env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
- env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
- env->regs[R_ESI] = ldq_phys(sm_state + 0x7fc8);
- env->regs[R_EDI] = ldq_phys(sm_state + 0x7fc0);
+ env->regs[R_EAX] = ldq_phys(cs->as, sm_state + 0x7ff8);
+ env->regs[R_ECX] = ldq_phys(cs->as, sm_state + 0x7ff0);
+ env->regs[R_EDX] = ldq_phys(cs->as, sm_state + 0x7fe8);
+ env->regs[R_EBX] = ldq_phys(cs->as, sm_state + 0x7fe0);
+ env->regs[R_ESP] = ldq_phys(cs->as, sm_state + 0x7fd8);
+ env->regs[R_EBP] = ldq_phys(cs->as, sm_state + 0x7fd0);
+ env->regs[R_ESI] = ldq_phys(cs->as, sm_state + 0x7fc8);
+ env->regs[R_EDI] = ldq_phys(cs->as, sm_state + 0x7fc0);
for (i = 8; i < 16; i++) {
- env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
+ env->regs[i] = ldq_phys(cs->as, sm_state + 0x7ff8 - i * 8);
}
- env->eip = ldq_phys(sm_state + 0x7f78);
+ env->eip = ldq_phys(cs->as, sm_state + 0x7f78);
cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7f70),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
env->dr[6] = ldl_phys(cs->as, sm_state + 0x7f68);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 6c3c8bf..cc6de20 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -105,7 +105,7 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
unsigned int flags;
sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
- sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
+ sc->base = ldq_phys(cs->as, addr + offsetof(struct vmcb_seg, base));
sc->limit = ldl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit));
flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
@@ -178,7 +178,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* load the interception bitmaps so we do not need to access the
vmcb in svm mode */
- env->intercept = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->intercept = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.intercept));
env->intercept_cr_read = lduw_phys(env->vm_vmcb +
offsetof(struct vmcb,
@@ -200,15 +200,15 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* enable intercepts */
env->hflags |= HF_SVMI_MASK;
- env->tsc_offset = ldq_phys(env->vm_vmcb +
+ env->tsc_offset = ldq_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb, control.tsc_offset));
- env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->gdt.base = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.base));
env->gdt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.limit));
- env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->idt.base = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.base));
env->idt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.limit));
@@ -216,13 +216,17 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* clear exit_info_2 so we behave like the real hardware */
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
- cpu_x86_update_cr0(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_x86_update_cr0(env, ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cr0)));
- cpu_x86_update_cr4(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_x86_update_cr4(env, ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cr4)));
- cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_x86_update_cr3(env, ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cr3)));
- env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
+ env->cr[2] = ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr2));
int_ctl = ldl_phys(cs->as,
env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
@@ -235,9 +239,11 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
}
cpu_load_efer(env,
- ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer)));
+ ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.efer)));
env->eflags = 0;
- cpu_load_eflags(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_load_eflags(env, ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.rflags)),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
CC_OP = CC_OP_EFLAGS;
@@ -251,18 +257,25 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
R_DS);
- env->eip = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
-
- env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
- env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
- env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
- env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
- cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->eip = ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rip));
+
+ env->regs[R_ESP] = ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rsp));
+ env->regs[R_EAX] = ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rax));
+ env->dr[7] = ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr7));
+ env->dr[6] = ldq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr6));
+ cpu_x86_set_cpl(env, ldub_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cpl)));
/* FIXME: guest state consistency checks */
- switch (ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
+ switch (ldub_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
case TLB_CONTROL_DO_NOTHING:
break;
case TLB_CONTROL_FLUSH_ALL_ASID:
@@ -339,6 +352,7 @@ void helper_vmmcall(CPUX86State *env)
void helper_vmload(CPUX86State *env, int aflag)
{
+ CPUState *cs = ENV_GET_CPU(env);
target_ulong addr;
cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0);
@@ -351,7 +365,7 @@ void helper_vmload(CPUX86State *env, int aflag)
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
- addr, ldq_phys(addr + offsetof(struct vmcb,
+ addr, ldq_phys(cs->as, addr + offsetof(struct vmcb,
save.fs.base)),
env->segs[R_FS].base);
@@ -361,22 +375,24 @@ void helper_vmload(CPUX86State *env, int aflag)
svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
#ifdef TARGET_X86_64
- env->kernelgsbase = ldq_phys(addr + offsetof(struct vmcb,
+ env->kernelgsbase = ldq_phys(cs->as, addr + offsetof(struct vmcb,
save.kernel_gs_base));
- env->lstar = ldq_phys(addr + offsetof(struct vmcb, save.lstar));
- env->cstar = ldq_phys(addr + offsetof(struct vmcb, save.cstar));
- env->fmask = ldq_phys(addr + offsetof(struct vmcb, save.sfmask));
+ env->lstar = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.lstar));
+ env->cstar = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.cstar));
+ env->fmask = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.sfmask));
#endif
- env->star = ldq_phys(addr + offsetof(struct vmcb, save.star));
- env->sysenter_cs = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_cs));
- env->sysenter_esp = ldq_phys(addr + offsetof(struct vmcb,
+ env->star = ldq_phys(cs->as, addr + offsetof(struct vmcb, save.star));
+ env->sysenter_cs = ldq_phys(cs->as,
+ addr + offsetof(struct vmcb, save.sysenter_cs));
+ env->sysenter_esp = ldq_phys(cs->as, addr + offsetof(struct vmcb,
save.sysenter_esp));
- env->sysenter_eip = ldq_phys(addr + offsetof(struct vmcb,
+ env->sysenter_eip = ldq_phys(cs->as, addr + offsetof(struct vmcb,
save.sysenter_eip));
}
void helper_vmsave(CPUX86State *env, int aflag)
{
+ CPUState *cs = ENV_GET_CPU(env);
target_ulong addr;
cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0);
@@ -389,7 +405,8 @@ void helper_vmsave(CPUX86State *env, int aflag)
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
- addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
+ addr, ldq_phys(cs->as,
+ addr + offsetof(struct vmcb, save.fs.base)),
env->segs[R_FS].base);
svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),
@@ -455,6 +472,8 @@ void helper_invlpga(CPUX86State *env, int aflag)
void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
uint64_t param)
{
+ CPUState *cs = ENV_GET_CPU(env);
+
if (likely(!(env->hflags & HF_SVMI_MASK))) {
return;
}
@@ -487,7 +506,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
case SVM_EXIT_MSR:
if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */
- uint64_t addr = ldq_phys(env->vm_vmcb +
+ uint64_t addr = ldq_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.msrpm_base_pa));
uint32_t t0, t1;
@@ -513,7 +532,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
t1 = 0;
break;
}
- if (ldub_phys(addr + t1) & ((1 << param) << t0)) {
+ if (ldub_phys(cs->as, addr + t1) & ((1 << param) << t0)) {
helper_vmexit(env, type, param);
}
}
@@ -535,9 +554,10 @@ void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
uint32_t next_eip_addend)
{
+ CPUState *cs = ENV_GET_CPU(env);
if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */
- uint64_t addr = ldq_phys(env->vm_vmcb +
+ uint64_t addr = ldq_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb, control.iopm_base_pa));
uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
@@ -559,7 +579,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
PRIx64 ", " TARGET_FMT_lx ")!\n",
exit_code, exit_info_1,
- ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.exit_info_2)),
env->eip);
@@ -625,29 +645,33 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
env->tsc_offset = 0;
- env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->gdt.base = ldq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.base));
env->gdt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.limit));
- env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->idt.base = ldq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.base));
env->idt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.limit));
- cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_x86_update_cr0(env, ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.cr0)) |
CR0_PE_MASK);
- cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_x86_update_cr4(env, ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.cr4)));
- cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_x86_update_cr3(env, ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.cr3)));
/* we need to set the efer after the crs so the hidden flags get
set properly */
- cpu_load_efer(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_load_efer(env, ldq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,
save.efer)));
env->eflags = 0;
- cpu_load_eflags(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_load_eflags(env, ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.rflags)),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
CC_OP = CC_OP_EFLAGS;
@@ -661,14 +685,17 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
R_DS);
- env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
- env->regs[R_ESP] = ldq_phys(env->vm_hsave +
+ env->eip = ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rip));
+ env->regs[R_ESP] = ldq_phys(cs->as, env->vm_hsave +
offsetof(struct vmcb, save.rsp));
- env->regs[R_EAX] = ldq_phys(env->vm_hsave +
+ env->regs[R_EAX] = ldq_phys(cs->as, env->vm_hsave +
offsetof(struct vmcb, save.rax));
- env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
- env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
+ env->dr[6] = ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr6));
+ env->dr[7] = ldq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr7));
/* other setups */
cpu_x86_set_cpl(env, 0);
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 55f5a23..b1a7de3 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -78,20 +78,23 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
hwaddr pte_offset)
{
+ CPUState *cs = ENV_GET_CPU(env);
if (env->external_htab) {
return ldq_p(env->external_htab + pte_offset);
} else {
- return ldq_phys(env->htab_base + pte_offset);
+ return ldq_phys(cs->as, env->htab_base + pte_offset);
}
}
static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
hwaddr pte_offset)
{
+ CPUState *cs = ENV_GET_CPU(env);
if (env->external_htab) {
return ldq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2);
} else {
- return ldq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
+ return ldq_phys(cs->as,
+ env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
}
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index da33b38..d6afe14 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -168,6 +168,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
uint64_t asc, uint64_t asce, int level,
target_ulong *raddr, int *flags, int rw)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t offs = 0;
uint64_t origin;
uint64_t new_asce;
@@ -218,7 +219,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
/* XXX region protection flags */
/* *flags &= ~PAGE_WRITE */
- new_asce = ldq_phys(origin + offs);
+ new_asce = ldq_phys(cs->as, origin + offs);
PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
__func__, origin, offs, new_asce);
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 1422ae9..1fd0e96 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -955,6 +955,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
uint64_t mode1, uint64_t a2, uint64_t mode2)
{
+ CPUState *cs = ENV_GET_CPU(env);
target_ulong src, dest;
int flags, cc = 0, i;
@@ -984,7 +985,7 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
mvc_asc(env, l - i, a1 + i, mode1, a2 + i, mode2);
break;
}
- stb_phys(dest + i, ldub_phys(src + i));
+ stb_phys(dest + i, ldub_phys(cs->as, src + i));
}
return cc;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 6f95105..f343fb3 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -609,7 +609,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
case 0x1c: /* LEON MMU passthrough */
switch (size) {
case 1:
- ret = ldub_phys(addr);
+ ret = ldub_phys(cs->as, addr);
break;
case 2:
ret = lduw_phys(addr);
@@ -619,14 +619,14 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = ldl_phys(cs->as, addr);
break;
case 8:
- ret = ldq_phys(addr);
+ ret = ldq_phys(cs->as, addr);
break;
}
break;
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
switch (size) {
case 1:
- ret = ldub_phys((hwaddr)addr
+ ret = ldub_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
case 2:
@@ -639,7 +639,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
| ((hwaddr)(asi & 0xf) << 32));
break;
case 8:
- ret = ldq_phys((hwaddr)addr
+ ret = ldq_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
}
@@ -716,6 +716,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
int size)
{
+ CPUState *cs = ENV_GET_CPU(env);
helper_check_align(env, addr, size - 1);
switch (asi) {
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
@@ -772,13 +773,17 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
"%08x: unimplemented access size: %d\n", addr,
size);
}
- env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[0] = ldq_phys(cs->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
0);
- env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[1] = ldq_phys(cs->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
8);
- env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[2] = ldq_phys(cs->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
16);
- env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[3] = ldq_phys(cs->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
24);
break;
case 0x01c00200: /* MXCC stream destination */
@@ -1434,7 +1439,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
{
switch (size) {
case 1:
- ret = ldub_phys(addr);
+ ret = ldub_phys(cs->as, addr);
break;
case 2:
ret = lduw_phys(addr);
@@ -1444,7 +1449,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 8:
- ret = ldq_phys(addr);
+ ret = ldq_phys(cs->as, addr);
break;
}
break;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 10/22] exec: Make lduw_*_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (8 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 09/22] exec: Make ldq/ldub_*_phys " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 11/22] exec: Make stq_*_phys " Edgar E. Iglesias
` (13 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 18 +++++++++---------
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 6 +++---
hw/s390x/css.c | 3 ++-
hw/s390x/virtio-ccw.c | 8 +++++---
hw/virtio/virtio.c | 16 ++++++++--------
include/exec/cpu-common.h | 6 +++---
target-i386/smm_helper.c | 12 ++++++------
target-i386/svm_helper.c | 15 ++++++++-------
target-sparc/ldst_helper.c | 6 +++---
10 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index 3bc4497..11abe89 100644
--- a/exec.c
+++ b/exec.c
@@ -1598,7 +1598,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
case 1: return ldub_phys(&address_space_memory, addr);
- case 2: return lduw_phys(addr);
+ case 2: return lduw_phys(&address_space_memory, addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
@@ -2470,7 +2470,7 @@ uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(hwaddr addr,
+static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2479,7 +2479,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
hwaddr l = 2;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 2 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2513,19 +2513,19 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
return val;
}
-uint32_t lduw_phys(hwaddr addr)
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
{
- return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(hwaddr addr)
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
{
- return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(hwaddr addr)
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
{
- return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index eb98d2a..7877cb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -80,7 +80,7 @@ vmw_shmem_st8(hwaddr addr, uint8_t value)
static inline uint32_t
vmw_shmem_ld16(hwaddr addr)
{
- uint16_t res = lduw_le_phys(addr);
+ uint16_t res = lduw_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 6e61a91..a2893ad 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -355,7 +355,7 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
}
/* FIXME: bounds check the address */
- size = lduw_be_phys(vpa + 0x4);
+ size = lduw_be_phys(cs->as, vpa + 0x4);
if (size < VPA_MIN_SIZE) {
return H_PARAMETER;
@@ -544,7 +544,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = ldub_phys(cs->as, addr);
return H_SUCCESS;
case 2:
- args[0] = lduw_phys(addr);
+ args[0] = lduw_phys(cs->as, addr);
return H_SUCCESS;
case 4:
args[0] = ldl_phys(cs->as, addr);
@@ -614,7 +614,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = ldub_phys(cs->as, src);
break;
case 1:
- tmp = lduw_phys(src);
+ tmp = lduw_phys(cs->as, src);
break;
case 2:
tmp = ldl_phys(cs->as, src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 41b1903..d42d7ec 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -677,7 +677,8 @@ static void css_update_chnmon(SubchDev *sch)
uint16_t count;
offset = sch->curr_status.pmcw.mbi << 5;
- count = lduw_phys(channel_subsys->chnmon_area + offset);
+ count = lduw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset);
count++;
stw_phys(channel_subsys->chnmon_area + offset, count);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index d301f00..50d852a 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -265,9 +265,11 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
info.queue = ldq_phys(&address_space_memory, ccw.cda);
info.align = ldl_phys(&address_space_memory,
ccw.cda + sizeof(info.queue));
- info.index = lduw_phys(ccw.cda + sizeof(info.queue)
+ info.index = lduw_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue)
+ sizeof(info.align));
- info.num = lduw_phys(ccw.cda + sizeof(info.queue)
+ info.num = lduw_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue)
+ sizeof(info.align)
+ sizeof(info.index));
ret = virtio_ccw_set_vqs(sch, info.queue, info.align, info.index,
@@ -469,7 +471,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- vq_config.index = lduw_phys(ccw.cda);
+ vq_config.index = lduw_phys(&address_space_memory, ccw.cda);
vq_config.num_max = virtio_queue_get_num(vdev,
vq_config.index);
stw_phys(ccw.cda + sizeof(vq_config.index), vq_config.num_max);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 4c04a69..3c2b0a0 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -119,35 +119,35 @@ static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, flags);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_desc_next(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, next);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_avail_flags(VirtQueue *vq)
{
hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, flags);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_avail_idx(VirtQueue *vq)
{
hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, idx);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_avail_ring(VirtQueue *vq, int i)
{
hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, ring[i]);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_used_event(VirtQueue *vq)
@@ -173,7 +173,7 @@ static uint16_t vring_used_idx(VirtQueue *vq)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
@@ -187,14 +187,14 @@ static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(pa) | mask);
+ stw_phys(pa, lduw_phys(&address_space_memory, pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(pa) & ~mask);
+ stw_phys(pa, lduw_phys(&address_space_memory, pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6f60f2c..6e30bf6 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -84,8 +84,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr);
void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
-uint32_t lduw_le_phys(hwaddr addr);
-uint32_t lduw_be_phys(hwaddr addr);
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
@@ -99,7 +99,7 @@ void stq_le_phys(hwaddr addr, uint64_t val);
void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
-uint32_t lduw_phys(hwaddr addr);
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 17a568c..c5663e1 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -193,28 +193,28 @@ void helper_rsm(CPUX86State *env)
for (i = 0; i < 6; i++) {
offset = 0x7e00 + i * 16;
cpu_x86_load_seg_cache(env, i,
- lduw_phys(sm_state + offset),
+ lduw_phys(cs->as, sm_state + offset),
ldq_phys(cs->as, sm_state + offset + 8),
ldl_phys(cs->as, sm_state + offset + 4),
- (lduw_phys(sm_state + offset + 2) &
+ (lduw_phys(cs->as, sm_state + offset + 2) &
0xf0ff) << 8);
}
env->gdt.base = ldq_phys(cs->as, sm_state + 0x7e68);
env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64);
- env->ldt.selector = lduw_phys(sm_state + 0x7e70);
+ env->ldt.selector = lduw_phys(cs->as, sm_state + 0x7e70);
env->ldt.base = ldq_phys(cs->as, sm_state + 0x7e78);
env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7e74);
- env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
+ env->ldt.flags = (lduw_phys(cs->as, sm_state + 0x7e72) & 0xf0ff) << 8;
env->idt.base = ldq_phys(cs->as, sm_state + 0x7e88);
env->idt.limit = ldl_phys(cs->as, sm_state + 0x7e84);
- env->tr.selector = lduw_phys(sm_state + 0x7e90);
+ env->tr.selector = lduw_phys(cs->as, sm_state + 0x7e90);
env->tr.base = ldq_phys(cs->as, sm_state + 0x7e98);
env->tr.limit = ldl_phys(cs->as, sm_state + 0x7e94);
- env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
+ env->tr.flags = (lduw_phys(cs->as, sm_state + 0x7e92) & 0xf0ff) << 8;
env->regs[R_EAX] = ldq_phys(cs->as, sm_state + 0x7ff8);
env->regs[R_ECX] = ldq_phys(cs->as, sm_state + 0x7ff0);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index cc6de20..73bc496 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -104,10 +104,11 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
CPUState *cs = ENV_GET_CPU(env);
unsigned int flags;
- sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
+ sc->selector = lduw_phys(cs->as,
+ addr + offsetof(struct vmcb_seg, selector));
sc->base = ldq_phys(cs->as, addr + offsetof(struct vmcb_seg, base));
sc->limit = ldl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit));
- flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
+ flags = lduw_phys(cs->as, addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
@@ -180,16 +181,16 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
vmcb in svm mode */
env->intercept = ldq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.intercept));
- env->intercept_cr_read = lduw_phys(env->vm_vmcb +
+ env->intercept_cr_read = lduw_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_cr_read));
- env->intercept_cr_write = lduw_phys(env->vm_vmcb +
+ env->intercept_cr_write = lduw_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_cr_write));
- env->intercept_dr_read = lduw_phys(env->vm_vmcb +
+ env->intercept_dr_read = lduw_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_read));
- env->intercept_dr_write = lduw_phys(env->vm_vmcb +
+ env->intercept_dr_write = lduw_phys(cs->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_write));
env->intercept_exceptions = ldl_phys(cs->as, env->vm_vmcb +
@@ -561,7 +562,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
offsetof(struct vmcb, control.iopm_base_pa));
uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
- if (lduw_phys(addr + port / 8) & (mask << (port & 7))) {
+ if (lduw_phys(cs->as, addr + port / 8) & (mask << (port & 7))) {
/* next env->eip */
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
env->eip + next_eip_addend);
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index f343fb3..38d00f1 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -612,7 +612,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = ldub_phys(cs->as, addr);
break;
case 2:
- ret = lduw_phys(addr);
+ ret = lduw_phys(cs->as, addr);
break;
default:
case 4:
@@ -630,7 +630,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
| ((hwaddr)(asi & 0xf) << 32));
break;
case 2:
- ret = lduw_phys((hwaddr)addr
+ ret = lduw_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
default:
@@ -1442,7 +1442,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = ldub_phys(cs->as, addr);
break;
case 2:
- ret = lduw_phys(addr);
+ ret = lduw_phys(cs->as, addr);
break;
case 4:
ret = ldl_phys(cs->as, addr);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 11/22] exec: Make stq_*_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (9 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 10/22] exec: Make lduw_*_phys " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 12/22] exec: Make stl_*_phys " Edgar E. Iglesias
` (12 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 12 +++---
hw/alpha/dp264.c | 5 ++-
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 6 ++-
hw/s390x/s390-virtio-bus.c | 3 +-
hw/s390x/virtio-ccw.c | 4 +-
hw/scsi/megasas.c | 3 +-
include/exec/cpu-common.h | 6 +--
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 7 +--
target-alpha/translate.c | 2 +-
target-i386/helper.c | 3 +-
target-i386/smm_helper.c | 33 ++++++++-------
target-i386/svm_helper.c | 103 +++++++++++++++++++++++++++------------------
target-ppc/mmu-hash64.h | 7 ++-
target-s390x/helper.c | 8 +++-
target-s390x/mem_helper.c | 3 +-
target-sparc/ldst_helper.c | 15 ++++---
18 files changed, 132 insertions(+), 92 deletions(-)
diff --git a/exec.c b/exec.c
index 11abe89..f8be6da 100644
--- a/exec.c
+++ b/exec.c
@@ -2680,22 +2680,22 @@ void stw_be_phys(hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stq_phys(hwaddr addr, uint64_t val)
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
- cpu_physical_memory_write(addr, &val, 8);
+ address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_le_phys(hwaddr addr, uint64_t val)
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
- cpu_physical_memory_write(addr, &val, 8);
+ address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_be_phys(hwaddr addr, uint64_t val)
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
- cpu_physical_memory_write(addr, &val, 8);
+ address_space_rw(as, addr, (void *) &val, 8, 1);
}
/* virtual memory access for debug (includes writing to ROM) */
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 20795ac..1351ba5 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -161,8 +161,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
- stq_phys(param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);
- stq_phys(param_offset + 0x108, initrd_size);
+ stq_phys(&address_space_memory,
+ param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);
+ stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);
}
}
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 7877cb6..4cf0e79 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -119,7 +119,7 @@ static inline void
vmw_shmem_st64(hwaddr addr, uint64_t value)
{
VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
- stq_le_phys(addr, value);
+ stq_le_phys(&address_space_memory, addr, value);
}
/* Macros for simplification of operations on array-style registers */
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index a2893ad..5ce43ab 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -559,6 +559,8 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
+ CPUState *cs = CPU(cpu);
+
target_ulong size = args[0];
target_ulong addr = args[1];
target_ulong val = args[2];
@@ -574,7 +576,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stl_phys(addr, val);
return H_SUCCESS;
case 8:
- stq_phys(addr, val);
+ stq_phys(cs->as, addr, val);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -639,7 +641,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stl_phys(dst, tmp);
break;
case 3:
- stq_phys(dst, tmp);
+ stq_phys(cs->as, dst, tmp);
break;
}
dst = dst + step;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 83e7287..87a1591 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -378,7 +378,8 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
vring = s390_virtio_next_ring(bus);
virtio_queue_set_addr(dev->vdev, i, vring);
virtio_queue_set_vector(dev->vdev, i, i);
- stq_be_phys(vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
+ stq_be_phys(&address_space_memory,
+ vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM, virtio_queue_get_num(dev->vdev, i));
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 50d852a..20ad77e 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -873,7 +873,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
}
indicators = ldq_phys(&address_space_memory, dev->indicators);
indicators |= 1ULL << vector;
- stq_phys(dev->indicators, indicators);
+ stq_phys(&address_space_memory, dev->indicators, indicators);
} else {
if (!dev->indicators2) {
return;
@@ -881,7 +881,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
vector = 0;
indicators = ldq_phys(&address_space_memory, dev->indicators2);
indicators |= 1ULL << vector;
- stq_phys(dev->indicators2, indicators);
+ stq_phys(&address_space_memory, dev->indicators2, indicators);
}
css_conditional_io_interrupt(sch);
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 33bcb97..673cb61 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -517,7 +517,8 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
tail = s->reply_queue_head;
if (megasas_use_queue64(s)) {
queue_offset = tail * sizeof(uint64_t);
- stq_le_phys(s->reply_queue_pa + queue_offset, context);
+ stq_le_phys(&address_space_memory,
+ s->reply_queue_pa + queue_offset, context);
} else {
queue_offset = tail * sizeof(uint32_t);
stl_le_phys(s->reply_queue_pa + queue_offset, context);
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6e30bf6..856062e 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -95,8 +95,8 @@ void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
void stl_le_phys(hwaddr addr, uint32_t val);
void stl_be_phys(hwaddr addr, uint32_t val);
-void stq_le_phys(hwaddr addr, uint64_t val);
-void stq_be_phys(hwaddr addr, uint64_t val);
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
@@ -105,7 +105,7 @@ uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(hwaddr addr, uint32_t val);
-void stq_phys(hwaddr addr, uint64_t val);
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
void cpu_physical_memory_write_rom(hwaddr addr,
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 74dbd07..c67266b 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -106,7 +106,7 @@ DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
DEF_HELPER_2(stl_phys, void, i64, i64)
-DEF_HELPER_2(stq_phys, void, i64, i64)
+DEF_HELPER_3(stq_phys, void, env, i64, i64)
DEF_HELPER_3(stl_c_phys, i64, env, i64, i64)
DEF_HELPER_3(stq_c_phys, i64, env, i64, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 5b47b04..7e4ddc4 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -55,9 +55,10 @@ void helper_stl_phys(uint64_t p, uint64_t v)
stl_phys(p, v);
}
-void helper_stq_phys(uint64_t p, uint64_t v)
+void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
- stq_phys(p, v);
+ CPUState *cs = ENV_GET_CPU(env);
+ stq_phys(cs->as, p, v);
}
uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
@@ -85,7 +86,7 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
if (p == env->lock_addr) {
uint64_t old = ldq_phys(cs->as, p);
if (old == env->lock_value) {
- stq_phys(p, v);
+ stq_phys(cs->as, p, v);
ret = 1;
}
}
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index f60ee35..69e2334 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3229,7 +3229,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x1:
/* Quadword physical access */
- gen_helper_stq_phys(addr, val);
+ gen_helper_stq_phys(cpu_env, addr, val);
break;
case 0x2:
/* Longword physical access with lock */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 02a68bd..0606908 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -881,7 +881,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
error_code |= PG_ERROR_I_D_MASK;
if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
/* cr2 is not modified in case of exceptions */
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
addr);
} else {
env->cr[2] = addr;
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index c5663e1..d62261c 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -43,6 +43,7 @@ void helper_rsm(CPUX86State *env)
void do_smm_enter(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
target_ulong sm_state;
SegmentCache *dt;
int i, offset;
@@ -62,39 +63,39 @@ void do_smm_enter(X86CPU *cpu)
stw_phys(sm_state + offset, dt->selector);
stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
stl_phys(sm_state + offset + 4, dt->limit);
- stq_phys(sm_state + offset + 8, dt->base);
+ stq_phys(cs->as, sm_state + offset + 8, dt->base);
}
- stq_phys(sm_state + 0x7e68, env->gdt.base);
+ stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base);
stl_phys(sm_state + 0x7e64, env->gdt.limit);
stw_phys(sm_state + 0x7e70, env->ldt.selector);
- stq_phys(sm_state + 0x7e78, env->ldt.base);
+ stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base);
stl_phys(sm_state + 0x7e74, env->ldt.limit);
stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
- stq_phys(sm_state + 0x7e88, env->idt.base);
+ stq_phys(cs->as, sm_state + 0x7e88, env->idt.base);
stl_phys(sm_state + 0x7e84, env->idt.limit);
stw_phys(sm_state + 0x7e90, env->tr.selector);
- stq_phys(sm_state + 0x7e98, env->tr.base);
+ stq_phys(cs->as, sm_state + 0x7e98, env->tr.base);
stl_phys(sm_state + 0x7e94, env->tr.limit);
stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
- stq_phys(sm_state + 0x7ed0, env->efer);
+ stq_phys(cs->as, sm_state + 0x7ed0, env->efer);
- stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
- stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
- stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
- stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
- stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
- stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
- stq_phys(sm_state + 0x7fc8, env->regs[R_ESI]);
- stq_phys(sm_state + 0x7fc0, env->regs[R_EDI]);
+ stq_phys(cs->as, sm_state + 0x7ff8, env->regs[R_EAX]);
+ stq_phys(cs->as, sm_state + 0x7ff0, env->regs[R_ECX]);
+ stq_phys(cs->as, sm_state + 0x7fe8, env->regs[R_EDX]);
+ stq_phys(cs->as, sm_state + 0x7fe0, env->regs[R_EBX]);
+ stq_phys(cs->as, sm_state + 0x7fd8, env->regs[R_ESP]);
+ stq_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EBP]);
+ stq_phys(cs->as, sm_state + 0x7fc8, env->regs[R_ESI]);
+ stq_phys(cs->as, sm_state + 0x7fc0, env->regs[R_EDI]);
for (i = 8; i < 16; i++) {
- stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
+ stq_phys(cs->as, sm_state + 0x7ff8 - i * 8, env->regs[i]);
}
- stq_phys(sm_state + 0x7f78, env->eip);
+ stq_phys(cs->as, sm_state + 0x7f78, env->eip);
stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
stl_phys(sm_state + 0x7f68, env->dr[6]);
stl_phys(sm_state + 0x7f60, env->dr[7]);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 73bc496..6b371c8 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -88,9 +88,10 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
const SegmentCache *sc)
{
+ CPUState *cs = ENV_GET_CPU(env);
stw_phys(addr + offsetof(struct vmcb_seg, selector),
sc->selector);
- stq_phys(addr + offsetof(struct vmcb_seg, base),
+ stq_phys(cs->as, addr + offsetof(struct vmcb_seg, base),
sc->base);
stl_phys(addr + offsetof(struct vmcb_seg, limit),
sc->limit);
@@ -142,25 +143,33 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->vm_vmcb = addr;
/* save the current CPU state in the hsave page */
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
+ stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
stl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
+ stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
stl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]);
-
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags),
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]);
+
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rflags),
cpu_compute_eflags(env));
svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es),
@@ -172,10 +181,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
&env->segs[R_DS]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
+ stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.rip),
env->eip + next_eip_addend);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
+ stq_phys(cs->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
/* load the interception bitmaps so we do not need to access the
vmcb in svm mode */
@@ -215,7 +226,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
save.idtr.limit));
/* clear exit_info_2 so we behave like the real hardware */
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
cpu_x86_update_cr0(env, ldq_phys(cs->as,
env->vm_vmcb + offsetof(struct vmcb,
@@ -420,17 +432,18 @@ void helper_vmsave(CPUX86State *env, int aflag)
&env->ldt);
#ifdef TARGET_X86_64
- stq_phys(addr + offsetof(struct vmcb, save.kernel_gs_base),
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.kernel_gs_base),
env->kernelgsbase);
- stq_phys(addr + offsetof(struct vmcb, save.lstar), env->lstar);
- stq_phys(addr + offsetof(struct vmcb, save.cstar), env->cstar);
- stq_phys(addr + offsetof(struct vmcb, save.sfmask), env->fmask);
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.lstar), env->lstar);
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.cstar), env->cstar);
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.sfmask), env->fmask);
#endif
- stq_phys(addr + offsetof(struct vmcb, save.star), env->star);
- stq_phys(addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
- stq_phys(addr + offsetof(struct vmcb, save.sysenter_esp),
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.star), env->star);
+ stq_phys(cs->as,
+ addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.sysenter_esp),
env->sysenter_esp);
- stq_phys(addr + offsetof(struct vmcb, save.sysenter_eip),
+ stq_phys(cs->as, addr + offsetof(struct vmcb, save.sysenter_eip),
env->sysenter_eip);
}
@@ -564,7 +577,8 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
if (lduw_phys(cs->as, addr + port / 8) & (mask << (port & 7))) {
/* next env->eip */
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
env->eip + next_eip_addend);
helper_vmexit(env, SVM_EXIT_IOIO, param | (port << 16));
}
@@ -602,21 +616,26 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
&env->segs[R_DS]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
+ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
+ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
int_ctl = ldl_phys(cs->as,
env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
@@ -627,14 +646,18 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
}
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags),
+ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rflags),
cpu_compute_eflags(env));
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
+ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rip),
env->eip);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
+ stq_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl),
env->hflags & HF_CPL_MASK);
@@ -700,9 +723,9 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
/* other setups */
cpu_x86_set_cpl(env, 0);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_code),
+ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_code),
exit_code);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
+ stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
exit_info_1);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index b1a7de3..a8da558 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -101,20 +101,23 @@ static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
hwaddr pte_offset, target_ulong pte0)
{
+ CPUState *cs = ENV_GET_CPU(env);
if (env->external_htab) {
stq_p(env->external_htab + pte_offset, pte0);
} else {
- stq_phys(env->htab_base + pte_offset, pte0);
+ stq_phys(cs->as, env->htab_base + pte_offset, pte0);
}
}
static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
hwaddr pte_offset, target_ulong pte1)
{
+ CPUState *cs = ENV_GET_CPU(env);
if (env->external_htab) {
stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
} else {
- stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
+ stq_phys(cs->as,
+ env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
}
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index d6afe14..aa537e1 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -138,18 +138,21 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
uint64_t mode)
{
+ CPUState *cs = ENV_GET_CPU(env);
int ilen = ILEN_LATER_INC;
int bits = trans_bits(env, mode) | 4;
DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
- stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
+ stq_phys(cs->as,
+ env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
trigger_pgm_exception(env, PGM_PROTECTION, ilen);
}
static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
uint32_t type, uint64_t asc, int rw)
{
+ CPUState *cs = ENV_GET_CPU(env);
int ilen = ILEN_LATER;
int bits = trans_bits(env, asc);
@@ -160,7 +163,8 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
- stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
+ stq_phys(cs->as,
+ env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
trigger_pgm_exception(env, type, ilen);
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 1fd0e96..3e9a6d0 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1010,6 +1010,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
/* invalidate pte */
void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
{
+ CPUState *cs = ENV_GET_CPU(env);
uint64_t page = vaddr & TARGET_PAGE_MASK;
uint64_t pte = 0;
@@ -1019,7 +1020,7 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
According to spec we'd have to find it out ourselves */
/* XXX Linux is fine with overwriting the pte, the spec requires
us to only set the invalid bit */
- stq_phys(pte_addr, pte | _PAGE_INVALID);
+ stq_phys(cs->as, pte_addr, pte | _PAGE_INVALID);
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 38d00f1..ccd8b89 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -794,13 +794,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
"%08x: unimplemented access size: %d\n", addr,
size);
}
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
+ stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
env->mxccdata[0]);
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
+ stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
env->mxccdata[1]);
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
+ stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
env->mxccdata[2]);
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
+ stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
env->mxccdata[3]);
break;
case 0x01c00a00: /* MXCC control register */
@@ -1022,7 +1022,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
stl_phys(addr, val);
break;
case 8:
- stq_phys(addr, val);
+ stq_phys(cs->as, addr, val);
break;
}
}
@@ -1044,7 +1044,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 8:
- stq_phys((hwaddr)addr
+ stq_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
}
@@ -1660,6 +1660,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, int size)
{
+ CPUState *cs = ENV_GET_CPU(env);
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
#endif
@@ -1820,7 +1821,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
break;
case 8:
default:
- stq_phys(addr, val);
+ stq_phys(cs->as, addr, val);
break;
}
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 12/22] exec: Make stl_*_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (10 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 11/22] exec: Make stq_*_phys " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 13/22] exec: Make stl_phys_notdirty " Edgar E. Iglesias
` (11 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 19 +++++----
hw/net/vmware_utils.h | 2 +-
hw/pci/msi.c | 2 +-
hw/pci/msix.c | 2 +-
hw/ppc/ppc405_uc.c | 33 +++++++--------
hw/ppc/spapr_hcall.c | 4 +-
hw/s390x/css.c | 2 +-
hw/s390x/s390-virtio-bus.c | 2 +-
hw/s390x/virtio-ccw.c | 2 +-
hw/scsi/megasas.c | 6 ++-
hw/scsi/vmw_pvscsi.c | 3 +-
hw/sh4/r2d.c | 2 +-
hw/timer/hpet.c | 3 +-
hw/virtio/virtio.c | 4 +-
include/exec/cpu-common.h | 6 +--
include/hw/ppc/spapr.h | 2 +-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 7 ++--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 3 +-
target-i386/seg_helper.c | 8 ++--
target-i386/smm_helper.c | 100 ++++++++++++++++++++++-----------------------
target-i386/svm_helper.c | 28 ++++++++-----
target-ppc/mmu-hash32.h | 6 ++-
target-sparc/ldst_helper.c | 6 +--
25 files changed, 137 insertions(+), 119 deletions(-)
diff --git a/exec.c b/exec.c
index f8be6da..a1f720c 100644
--- a/exec.c
+++ b/exec.c
@@ -1616,7 +1616,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stw_phys(addr, val);
break;
case 4:
- stl_phys(addr, val);
+ stl_phys(&address_space_memory, addr, val);
break;
default: abort();
}
@@ -2561,7 +2561,8 @@ void stl_phys_notdirty(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(hwaddr addr, uint32_t val,
+static inline void stl_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2569,7 +2570,7 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
@@ -2601,19 +2602,19 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
}
}
-void stl_phys(hwaddr addr, uint32_t val)
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+ stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(hwaddr addr, uint32_t val)
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+ stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(hwaddr addr, uint32_t val)
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+ stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 4cf0e79..2ed73af 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -104,7 +104,7 @@ static inline void
vmw_shmem_st32(hwaddr addr, uint32_t value)
{
VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
- stl_le_phys(addr, value);
+ stl_le_phys(&address_space_memory, addr, value);
}
static inline uint64_t
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
index 2a04d18..a4a3040 100644
--- a/hw/pci/msi.c
+++ b/hw/pci/msi.c
@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)
"notify vector 0x%x"
" address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
vector, msg.address, msg.data);
- stl_le_phys(msg.address, msg.data);
+ stl_le_phys(&address_space_memory, msg.address, msg.data);
}
/* Normally called by pci_default_write_config(). */
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 3430770..5c49bfc 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector)
msg = msix_get_message(dev, vector);
- stl_le_phys(msg.address, msg.data);
+ stl_le_phys(&address_space_memory, msg.address, msg.data);
}
void msix_reset(PCIDevice *dev)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8109f92..47a4242 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -44,6 +44,7 @@
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
+ CPUState *cs = ENV_GET_CPU(env);
ram_addr_t bdloc;
int i, n;
@@ -52,30 +53,30 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
else
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
- stl_be_phys(bdloc + 0x00, bd->bi_memstart);
- stl_be_phys(bdloc + 0x04, bd->bi_memsize);
- stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
- stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
- stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
- stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
- stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
- stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
- stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
+ stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
+ stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
+ stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
+ stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
+ stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
+ stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
+ stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
+ stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
+ stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
- stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
- stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
- stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
+ stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
+ stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
}
- stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
- stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
@@ -84,10 +85,10 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++)
stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
- stl_be_phys(bdloc + n, bd->bi_opbfreq);
+ stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
n += 4;
for (i = 0; i < 2; i++) {
- stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
+ stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
n += 4;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 5ce43ab..f47c3ec 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -573,7 +573,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stw_phys(addr, val);
return H_SUCCESS;
case 4:
- stl_phys(addr, val);
+ stl_phys(cs->as, addr, val);
return H_SUCCESS;
case 8:
stq_phys(cs->as, addr, val);
@@ -638,7 +638,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stw_phys(dst, tmp);
break;
case 2:
- stl_phys(dst, tmp);
+ stl_phys(cs->as, dst, tmp);
break;
case 3:
stq_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index d42d7ec..cfa8a9b 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -670,7 +670,7 @@ static void css_update_chnmon(SubchDev *sch)
count = ldl_phys(&address_space_memory, sch->curr_status.mba);
count++;
- stl_phys(sch->curr_status.mba, count);
+ stl_phys(&address_space_memory, sch->curr_status.mba, count);
} else {
/* Format 0, global area. */
uint32_t offset;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 87a1591..2771306 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -388,7 +388,7 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
cur_offs += num_vq * VIRTIO_VQCONFIG_LEN;
/* Sync feature bitmap */
- stl_le_phys(cur_offs, dev->host_features);
+ stl_le_phys(&address_space_memory, cur_offs, dev->host_features);
dev->feat_offs = cur_offs + dev->feat_len;
cur_offs += dev->feat_len * 2;
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 20ad77e..4db1052 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -304,7 +304,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
/* Return zeroes if the guest supports more feature bits. */
features.features = 0;
}
- stl_le_phys(ccw.cda, features.features);
+ stl_le_phys(&address_space_memory, ccw.cda, features.features);
sch->curr_status.scsw.count = ccw.count - sizeof(features);
ret = 0;
}
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 673cb61..e12f80c 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -521,7 +521,8 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
s->reply_queue_pa + queue_offset, context);
} else {
queue_offset = tail * sizeof(uint32_t);
- stl_le_phys(s->reply_queue_pa + queue_offset, context);
+ stl_le_phys(&address_space_memory,
+ s->reply_queue_pa + queue_offset, context);
}
s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
trace_megasas_qf_complete(context, tail, queue_offset,
@@ -1951,7 +1952,8 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
if (s->producer_pa && megasas_intr_enabled(s)) {
/* Update reply queue pointer */
trace_megasas_qf_update(s->reply_queue_head, s->busy);
- stl_le_phys(s->producer_pa, s->reply_queue_head);
+ stl_le_phys(&address_space_memory,
+ s->producer_pa, s->reply_queue_head);
if (!msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
pci_irq_deassert(pci_dev);
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 6cc6c1b..7d344b9 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -46,7 +46,8 @@
(ldl_le_phys(&address_space_memory, \
rs_pa + offsetof(struct PVSCSIRingsState, field)))
#define RS_SET_FIELD(rs_pa, field, val) \
- (stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val))
+ (stl_le_phys(&address_space_memory, \
+ rs_pa + offsetof(struct PVSCSIRingsState, field), val))
#define TYPE_PVSCSI "pvscsi"
#define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 7b1de85..76ef869 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -318,7 +318,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
}
/* initialization which should be done by firmware */
- stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
+ stl_phys(&address_space_memory, SH7750_BCR1, 1<<3); /* cs3 SDRAM */
stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
}
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 2fbbeb1..1264dfd 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -206,7 +206,8 @@ static void update_irq(struct HPETTimer *timer, int set)
}
}
} else if (timer_fsb_route(timer)) {
- stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
+ stl_le_phys(&address_space_memory,
+ timer->fsb >> 32, timer->fsb & 0xffffffff);
} else if (timer->config & HPET_TN_TYPE_LEVEL) {
s->isr |= mask;
/* fold the ICH PIRQ# pin's internal inversion logic into hpet */
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 3c2b0a0..4606e68 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -159,14 +159,14 @@ static inline void vring_used_ring_id(VirtQueue *vq, int i, uint32_t val)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].id);
- stl_phys(pa, val);
+ stl_phys(&address_space_memory, pa, val);
}
static inline void vring_used_ring_len(VirtQueue *vq, int i, uint32_t val)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].len);
- stl_phys(pa, val);
+ stl_phys(&address_space_memory, pa, val);
}
static uint16_t vring_used_idx(VirtQueue *vq)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 856062e..d005c98 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -93,8 +93,8 @@ uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
-void stl_le_phys(hwaddr addr, uint32_t val);
-void stl_be_phys(hwaddr addr, uint32_t val);
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
@@ -104,7 +104,7 @@ uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
-void stl_phys(hwaddr addr, uint32_t val);
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 6c705f1..449fc7c 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -353,7 +353,7 @@ static inline uint32_t rtas_ld(target_ulong phys, int n)
static inline void rtas_st(target_ulong phys, int n, uint32_t val)
{
- stl_be_phys(ppc64_phys_to_real(phys + 4*n), val);
+ stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
}
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index c67266b..4f127c4 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -105,7 +105,7 @@ DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
-DEF_HELPER_2(stl_phys, void, i64, i64)
+DEF_HELPER_3(stl_phys, void, env, i64, i64)
DEF_HELPER_3(stq_phys, void, env, i64, i64)
DEF_HELPER_3(stl_c_phys, i64, env, i64, i64)
DEF_HELPER_3(stq_c_phys, i64, env, i64, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 7e4ddc4..ea58704 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -50,9 +50,10 @@ uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
return env->lock_value = ldq_phys(cs->as, p);
}
-void helper_stl_phys(uint64_t p, uint64_t v)
+void helper_stl_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
- stl_phys(p, v);
+ CPUState *cs = ENV_GET_CPU(env);
+ stl_phys(cs->as, p, v);
}
void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
@@ -69,7 +70,7 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
if (p == env->lock_addr) {
int32_t old = ldl_phys(cs->as, p);
if (old == (int32_t)env->lock_value) {
- stl_phys(p, v);
+ stl_phys(cs->as, p, v);
ret = 1;
}
}
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 69e2334..4c94bed 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3225,7 +3225,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access */
- gen_helper_stl_phys(addr, val);
+ gen_helper_stl_phys(cpu_env, addr, val);
break;
case 0x1:
/* Quadword physical access */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6a3db66..5ae08c9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2449,8 +2449,9 @@ void switch_mode(CPUARMState *env, int mode)
static void v7m_push(CPUARMState *env, uint32_t val)
{
+ CPUState *cs = ENV_GET_CPU(env);
env->regs[13] -= 4;
- stl_phys(env->regs[13], val);
+ stl_phys(cs->as, env->regs[13], val);
}
static uint32_t v7m_pop(CPUARMState *env)
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 6b18b3e..959212b 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1146,11 +1146,12 @@ static void handle_even_inj(CPUX86State *env, int intno, int is_int,
event_inj = intno | type | SVM_EVTINJ_VALID;
if (!rm && exception_has_error_code(intno)) {
event_inj |= SVM_EVTINJ_VALID_ERR;
- stl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ stl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err),
error_code);
}
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
event_inj);
}
}
@@ -1231,7 +1232,8 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
offsetof(struct vmcb,
control.event_inj));
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
event_inj & ~SVM_EVTINJ_VALID);
}
#endif
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index d62261c..88f6d7f 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -62,24 +62,24 @@ void do_smm_enter(X86CPU *cpu)
offset = 0x7e00 + i * 16;
stw_phys(sm_state + offset, dt->selector);
stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
- stl_phys(sm_state + offset + 4, dt->limit);
+ stl_phys(cs->as, sm_state + offset + 4, dt->limit);
stq_phys(cs->as, sm_state + offset + 8, dt->base);
}
stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base);
- stl_phys(sm_state + 0x7e64, env->gdt.limit);
+ stl_phys(cs->as, sm_state + 0x7e64, env->gdt.limit);
stw_phys(sm_state + 0x7e70, env->ldt.selector);
stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base);
- stl_phys(sm_state + 0x7e74, env->ldt.limit);
+ stl_phys(cs->as, sm_state + 0x7e74, env->ldt.limit);
stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
stq_phys(cs->as, sm_state + 0x7e88, env->idt.base);
- stl_phys(sm_state + 0x7e84, env->idt.limit);
+ stl_phys(cs->as, sm_state + 0x7e84, env->idt.limit);
stw_phys(sm_state + 0x7e90, env->tr.selector);
stq_phys(cs->as, sm_state + 0x7e98, env->tr.base);
- stl_phys(sm_state + 0x7e94, env->tr.limit);
+ stl_phys(cs->as, sm_state + 0x7e94, env->tr.limit);
stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
stq_phys(cs->as, sm_state + 0x7ed0, env->efer);
@@ -96,47 +96,47 @@ void do_smm_enter(X86CPU *cpu)
stq_phys(cs->as, sm_state + 0x7ff8 - i * 8, env->regs[i]);
}
stq_phys(cs->as, sm_state + 0x7f78, env->eip);
- stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
- stl_phys(sm_state + 0x7f68, env->dr[6]);
- stl_phys(sm_state + 0x7f60, env->dr[7]);
+ stl_phys(cs->as, sm_state + 0x7f70, cpu_compute_eflags(env));
+ stl_phys(cs->as, sm_state + 0x7f68, env->dr[6]);
+ stl_phys(cs->as, sm_state + 0x7f60, env->dr[7]);
- stl_phys(sm_state + 0x7f48, env->cr[4]);
- stl_phys(sm_state + 0x7f50, env->cr[3]);
- stl_phys(sm_state + 0x7f58, env->cr[0]);
+ stl_phys(cs->as, sm_state + 0x7f48, env->cr[4]);
+ stl_phys(cs->as, sm_state + 0x7f50, env->cr[3]);
+ stl_phys(cs->as, sm_state + 0x7f58, env->cr[0]);
- stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
- stl_phys(sm_state + 0x7f00, env->smbase);
+ stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID);
+ stl_phys(cs->as, sm_state + 0x7f00, env->smbase);
#else
- stl_phys(sm_state + 0x7ffc, env->cr[0]);
- stl_phys(sm_state + 0x7ff8, env->cr[3]);
- stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
- stl_phys(sm_state + 0x7ff0, env->eip);
- stl_phys(sm_state + 0x7fec, env->regs[R_EDI]);
- stl_phys(sm_state + 0x7fe8, env->regs[R_ESI]);
- stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
- stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
- stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
- stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
- stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
- stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
- stl_phys(sm_state + 0x7fcc, env->dr[6]);
- stl_phys(sm_state + 0x7fc8, env->dr[7]);
-
- stl_phys(sm_state + 0x7fc4, env->tr.selector);
- stl_phys(sm_state + 0x7f64, env->tr.base);
- stl_phys(sm_state + 0x7f60, env->tr.limit);
- stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
-
- stl_phys(sm_state + 0x7fc0, env->ldt.selector);
- stl_phys(sm_state + 0x7f80, env->ldt.base);
- stl_phys(sm_state + 0x7f7c, env->ldt.limit);
- stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
-
- stl_phys(sm_state + 0x7f74, env->gdt.base);
- stl_phys(sm_state + 0x7f70, env->gdt.limit);
-
- stl_phys(sm_state + 0x7f58, env->idt.base);
- stl_phys(sm_state + 0x7f54, env->idt.limit);
+ stl_phys(cs->as, sm_state + 0x7ffc, env->cr[0]);
+ stl_phys(cs->as, sm_state + 0x7ff8, env->cr[3]);
+ stl_phys(cs->as, sm_state + 0x7ff4, cpu_compute_eflags(env));
+ stl_phys(cs->as, sm_state + 0x7ff0, env->eip);
+ stl_phys(cs->as, sm_state + 0x7fec, env->regs[R_EDI]);
+ stl_phys(cs->as, sm_state + 0x7fe8, env->regs[R_ESI]);
+ stl_phys(cs->as, sm_state + 0x7fe4, env->regs[R_EBP]);
+ stl_phys(cs->as, sm_state + 0x7fe0, env->regs[R_ESP]);
+ stl_phys(cs->as, sm_state + 0x7fdc, env->regs[R_EBX]);
+ stl_phys(cs->as, sm_state + 0x7fd8, env->regs[R_EDX]);
+ stl_phys(cs->as, sm_state + 0x7fd4, env->regs[R_ECX]);
+ stl_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EAX]);
+ stl_phys(cs->as, sm_state + 0x7fcc, env->dr[6]);
+ stl_phys(cs->as, sm_state + 0x7fc8, env->dr[7]);
+
+ stl_phys(cs->as, sm_state + 0x7fc4, env->tr.selector);
+ stl_phys(cs->as, sm_state + 0x7f64, env->tr.base);
+ stl_phys(cs->as, sm_state + 0x7f60, env->tr.limit);
+ stl_phys(cs->as, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
+
+ stl_phys(cs->as, sm_state + 0x7fc0, env->ldt.selector);
+ stl_phys(cs->as, sm_state + 0x7f80, env->ldt.base);
+ stl_phys(cs->as, sm_state + 0x7f7c, env->ldt.limit);
+ stl_phys(cs->as, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
+
+ stl_phys(cs->as, sm_state + 0x7f74, env->gdt.base);
+ stl_phys(cs->as, sm_state + 0x7f70, env->gdt.limit);
+
+ stl_phys(cs->as, sm_state + 0x7f58, env->idt.base);
+ stl_phys(cs->as, sm_state + 0x7f54, env->idt.limit);
for (i = 0; i < 6; i++) {
dt = &env->segs[i];
@@ -145,15 +145,15 @@ void do_smm_enter(X86CPU *cpu)
} else {
offset = 0x7f2c + (i - 3) * 12;
}
- stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
- stl_phys(sm_state + offset + 8, dt->base);
- stl_phys(sm_state + offset + 4, dt->limit);
- stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
+ stl_phys(cs->as, sm_state + 0x7fa8 + i * 4, dt->selector);
+ stl_phys(cs->as, sm_state + offset + 8, dt->base);
+ stl_phys(cs->as, sm_state + offset + 4, dt->limit);
+ stl_phys(cs->as, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
}
- stl_phys(sm_state + 0x7f14, env->cr[4]);
+ stl_phys(cs->as, sm_state + 0x7f14, env->cr[4]);
- stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
- stl_phys(sm_state + 0x7ef8, env->smbase);
+ stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID);
+ stl_phys(cs->as, sm_state + 0x7ef8, env->smbase);
#endif
/* init SMM cpu state */
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 6b371c8..b9fd779 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -93,7 +93,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
sc->selector);
stq_phys(cs->as, addr + offsetof(struct vmcb_seg, base),
sc->base);
- stl_phys(addr + offsetof(struct vmcb_seg, limit),
+ stl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit),
sc->limit);
stw_phys(addr + offsetof(struct vmcb_seg, attrib),
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
@@ -145,12 +145,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* save the current CPU state in the hsave page */
stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
- stl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
+ stl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
stq_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
- stl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
+ stl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
stq_phys(cs->as,
@@ -599,11 +599,13 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->eip);
if (env->hflags & HF_INHIBIT_IRQ_MASK) {
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state),
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_state),
SVM_INTERRUPT_SHADOW_MASK);
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
} else {
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
}
/* Save the VM state in the vmcb */
@@ -618,12 +620,12 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
+ stl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
+ stl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
stq_phys(cs->as,
@@ -644,7 +646,8 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
int_ctl |= V_IRQ_MASK;
}
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.rflags),
cpu_compute_eflags(env));
@@ -728,13 +731,16 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
exit_info_1);
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj)));
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err)));
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
+ stl_phys(cs->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
env->hflags2 &= ~HF2_GIF_MASK;
/* FIXME: Resets the current ASID register to zero (host ASID). */
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index b403d77..4671141 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -84,15 +84,17 @@ static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
hwaddr pte_offset, target_ulong pte0)
{
+ CPUState *cs = ENV_GET_CPU(env);
assert(!env->external_htab); /* Not supported on 32-bit for now */
- stl_phys(env->htab_base + pte_offset, pte0);
+ stl_phys(cs->as, env->htab_base + pte_offset, pte0);
}
static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
hwaddr pte_offset, target_ulong pte1)
{
+ CPUState *cs = ENV_GET_CPU(env);
assert(!env->external_htab); /* Not supported on 32-bit for now */
- stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
+ stl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
}
typedef struct {
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index ccd8b89..0e87d79 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1019,7 +1019,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
break;
case 4:
default:
- stl_phys(addr, val);
+ stl_phys(cs->as, addr, val);
break;
case 8:
stq_phys(cs->as, addr, val);
@@ -1040,7 +1040,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
break;
case 4:
default:
- stl_phys((hwaddr)addr
+ stl_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 8:
@@ -1817,7 +1817,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
stw_phys(addr, val);
break;
case 4:
- stl_phys(addr, val);
+ stl_phys(cs->as, addr, val);
break;
case 8:
default:
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 13/22] exec: Make stl_phys_notdirty input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (11 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 12/22] exec: Make stl_*_phys " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 14/22] exec: Make stw_*_phys " Edgar E. Iglesias
` (10 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 4 ++--
hw/arm/boot.c | 5 +++--
hw/arm/highbank.c | 6 +++---
include/exec/cpu-common.h | 2 +-
target-i386/helper.c | 16 ++++++++--------
target-sparc/mmu_helper.c | 2 +-
6 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/exec.c b/exec.c
index a1f720c..9d4a4e0 100644
--- a/exec.c
+++ b/exec.c
@@ -2531,14 +2531,14 @@ uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(hwaddr addr, uint32_t val)
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
io_mem_write(mr, addr1, val, 4);
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 4036262..dc62918 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -16,6 +16,7 @@
#include "elf.h"
#include "sysemu/device_tree.h"
#include "qemu/config-file.h"
+#include "exec/address-spaces.h"
/* Kernel boot protocol is specified in the kernel docs
* Documentation/arm/Booting and Documentation/arm64/booting.txt
@@ -169,7 +170,7 @@ static void default_reset_secondary(ARMCPU *cpu,
{
CPUARMState *env = &cpu->env;
- stl_phys_notdirty(info->smp_bootreg_addr, 0);
+ stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
}
@@ -179,7 +180,7 @@ static inline bool have_dtb(const struct arm_boot_info *info)
}
#define WRITE_WORD(p, value) do { \
- stl_phys_notdirty(p, value); \
+ stl_phys_notdirty(&address_space_memory, p, value); \
p += 4; \
} while (0)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index d76a1d1..f66d57b 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -69,11 +69,11 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
switch (info->nb_cpus) {
case 4:
- stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
+ stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0);
case 3:
- stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
+ stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0);
case 2:
- stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
+ stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0);
env->regs[15] = SMP_BOOT_ADDR;
break;
default:
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d005c98..525fb62 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,7 +102,7 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
-void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 0606908..55c0457 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -574,7 +574,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
}
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pml4e_addr, pml4e);
+ stl_phys_notdirty(cs->as, pml4e_addr, pml4e);
}
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
@@ -591,7 +591,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
pdpe |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pdpe_addr, pdpe);
+ stl_phys_notdirty(cs->as, pdpe_addr, pdpe);
}
} else
#endif
@@ -661,7 +661,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(cs->as, pde_addr, pde);
}
/* align to page_size */
pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
@@ -670,7 +670,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* 4 KB page */
if (!(pde & PG_ACCESSED_MASK)) {
pde |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(cs->as, pde_addr, pde);
}
pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
env->a20_mask;
@@ -723,7 +723,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pte |= PG_ACCESSED_MASK;
if (is_dirty)
pte |= PG_DIRTY_MASK;
- stl_phys_notdirty(pte_addr, pte);
+ stl_phys_notdirty(cs->as, pte_addr, pte);
}
page_size = 4096;
virt_addr = addr & ~0xfff;
@@ -778,7 +778,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(cs->as, pde_addr, pde);
}
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
@@ -787,7 +787,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
} else {
if (!(pde & PG_ACCESSED_MASK)) {
pde |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(cs->as, pde_addr, pde);
}
/* page directory entry */
@@ -835,7 +835,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pte |= PG_ACCESSED_MASK;
if (is_dirty)
pte |= PG_DIRTY_MASK;
- stl_phys_notdirty(pte_addr, pte);
+ stl_phys_notdirty(cs->as, pte_addr, pte);
}
page_size = 4096;
virt_addr = addr & ~0xfff;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 46bb038..5fc2fd6 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -180,7 +180,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
if (is_dirty) {
pde |= PG_MODIFIED_MASK;
}
- stl_phys_notdirty(pde_ptr, pde);
+ stl_phys_notdirty(cs->as, pde_ptr, pde);
}
/* the page can be put in the TLB */
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 14/22] exec: Make stw_*_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (12 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 13/22] exec: Make stl_phys_notdirty " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 15/22] exec: Make stb_phys " Edgar E. Iglesias
` (9 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 20 ++++++++++----------
hw/net/vmware_utils.h | 2 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/spapr_hcall.c | 4 ++--
hw/s390x/css.c | 3 ++-
hw/s390x/s390-virtio-bus.c | 8 +++++---
hw/s390x/virtio-ccw.c | 3 ++-
hw/sh4/r2d.c | 2 +-
hw/virtio/virtio.c | 10 ++++++----
include/exec/cpu-common.h | 6 +++---
target-i386/smm_helper.c | 12 ++++++------
target-i386/svm_helper.c | 4 ++--
target-s390x/mem_helper.c | 3 ++-
target-sparc/ldst_helper.c | 6 +++---
14 files changed, 46 insertions(+), 39 deletions(-)
diff --git a/exec.c b/exec.c
index 9d4a4e0..3389b90 100644
--- a/exec.c
+++ b/exec.c
@@ -1613,7 +1613,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stb_phys(addr, val);
break;
case 2:
- stw_phys(addr, val);
+ stw_phys(&address_space_memory, addr, val);
break;
case 4:
stl_phys(&address_space_memory, addr, val);
@@ -2625,7 +2625,8 @@ void stb_phys(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(hwaddr addr, uint32_t val,
+static inline void stw_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2633,8 +2634,7 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
hwaddr l = 2;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- true);
+ mr = address_space_translate(as, addr, &addr1, &l, true);
if (l < 2 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
@@ -2665,19 +2665,19 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
}
}
-void stw_phys(hwaddr addr, uint32_t val)
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+ stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(hwaddr addr, uint32_t val)
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+ stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(hwaddr addr, uint32_t val)
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+ stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 2ed73af..d8f734f 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -89,7 +89,7 @@ static inline void
vmw_shmem_st16(hwaddr addr, uint16_t value)
{
VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
- stw_le_phys(addr, value);
+ stw_le_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 47a4242..b0a59c3 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -65,7 +65,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
- stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
+ stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f47c3ec..ebf09e9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -570,7 +570,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stb_phys(addr, val);
return H_SUCCESS;
case 2:
- stw_phys(addr, val);
+ stw_phys(cs->as, addr, val);
return H_SUCCESS;
case 4:
stl_phys(cs->as, addr, val);
@@ -635,7 +635,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stb_phys(dst, tmp);
break;
case 1:
- stw_phys(dst, tmp);
+ stw_phys(cs->as, dst, tmp);
break;
case 2:
stl_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index cfa8a9b..75b04b4 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -680,7 +680,8 @@ static void css_update_chnmon(SubchDev *sch)
count = lduw_phys(&address_space_memory,
channel_subsys->chnmon_area + offset);
count++;
- stw_phys(channel_subsys->chnmon_area + offset, count);
+ stw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset, count);
}
}
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 2771306..68f3e5a 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -77,10 +77,10 @@ void s390_virtio_reset_idx(VirtIOS390Device *dev)
for (i = 0; i < num_vq; i++) {
idx_addr = virtio_queue_get_avail_addr(dev->vdev, i) +
VIRTIO_VRING_AVAIL_IDX_OFFS;
- stw_phys(idx_addr, 0);
+ stw_phys(&address_space_memory, idx_addr, 0);
idx_addr = virtio_queue_get_used_addr(dev->vdev, i) +
VIRTIO_VRING_USED_IDX_OFFS;
- stw_phys(idx_addr, 0);
+ stw_phys(&address_space_memory, idx_addr, 0);
}
}
@@ -380,7 +380,9 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_queue_set_vector(dev->vdev, i, i);
stq_be_phys(&address_space_memory,
vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
- stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM, virtio_queue_get_num(dev->vdev, i));
+ stw_be_phys(&address_space_memory,
+ vq + VIRTIO_VQCONFIG_OFFS_NUM,
+ virtio_queue_get_num(dev->vdev, i));
}
cur_offs = dev->dev_offs;
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 4db1052..f6e0e3e 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -474,7 +474,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
vq_config.index = lduw_phys(&address_space_memory, ccw.cda);
vq_config.num_max = virtio_queue_get_num(vdev,
vq_config.index);
- stw_phys(ccw.cda + sizeof(vq_config.index), vq_config.num_max);
+ stw_phys(&address_space_memory,
+ ccw.cda + sizeof(vq_config.index), vq_config.num_max);
sch->curr_status.scsw.count = ccw.count - sizeof(vq_config);
ret = 0;
}
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 76ef869..eaeb7ed 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -319,7 +319,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
/* initialization which should be done by firmware */
stl_phys(&address_space_memory, SH7750_BCR1, 1<<3); /* cs3 SDRAM */
- stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
+ stw_phys(&address_space_memory, SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
}
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 4606e68..aeabf3a 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -180,21 +180,23 @@ static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
- stw_phys(pa, val);
+ stw_phys(&address_space_memory, pa, val);
}
static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(&address_space_memory, pa) | mask);
+ stw_phys(&address_space_memory,
+ pa, lduw_phys(&address_space_memory, pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(&address_space_memory, pa) & ~mask);
+ stw_phys(&address_space_memory,
+ pa, lduw_phys(&address_space_memory, pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
@@ -204,7 +206,7 @@ static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
return;
}
pa = vq->vring.used + offsetof(VRingUsed, ring[vq->vring.num]);
- stw_phys(pa, val);
+ stw_phys(&address_space_memory, pa, val);
}
void virtio_queue_set_notification(VirtQueue *vq, int enable)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 525fb62..aef373e 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -91,8 +91,8 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
-void stw_le_phys(hwaddr addr, uint32_t val);
-void stw_be_phys(hwaddr addr, uint32_t val);
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
@@ -103,7 +103,7 @@ uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
-void stw_phys(hwaddr addr, uint32_t val);
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 88f6d7f..71c64b2 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -60,8 +60,8 @@ void do_smm_enter(X86CPU *cpu)
for (i = 0; i < 6; i++) {
dt = &env->segs[i];
offset = 0x7e00 + i * 16;
- stw_phys(sm_state + offset, dt->selector);
- stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
+ stw_phys(cs->as, sm_state + offset, dt->selector);
+ stw_phys(cs->as, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
stl_phys(cs->as, sm_state + offset + 4, dt->limit);
stq_phys(cs->as, sm_state + offset + 8, dt->base);
}
@@ -69,18 +69,18 @@ void do_smm_enter(X86CPU *cpu)
stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base);
stl_phys(cs->as, sm_state + 0x7e64, env->gdt.limit);
- stw_phys(sm_state + 0x7e70, env->ldt.selector);
+ stw_phys(cs->as, sm_state + 0x7e70, env->ldt.selector);
stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base);
stl_phys(cs->as, sm_state + 0x7e74, env->ldt.limit);
- stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
+ stw_phys(cs->as, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
stq_phys(cs->as, sm_state + 0x7e88, env->idt.base);
stl_phys(cs->as, sm_state + 0x7e84, env->idt.limit);
- stw_phys(sm_state + 0x7e90, env->tr.selector);
+ stw_phys(cs->as, sm_state + 0x7e90, env->tr.selector);
stq_phys(cs->as, sm_state + 0x7e98, env->tr.base);
stl_phys(cs->as, sm_state + 0x7e94, env->tr.limit);
- stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
+ stw_phys(cs->as, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
stq_phys(cs->as, sm_state + 0x7ed0, env->efer);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index b9fd779..a86a99b 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -89,13 +89,13 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
const SegmentCache *sc)
{
CPUState *cs = ENV_GET_CPU(env);
- stw_phys(addr + offsetof(struct vmcb_seg, selector),
+ stw_phys(cs->as, addr + offsetof(struct vmcb_seg, selector),
sc->selector);
stq_phys(cs->as, addr + offsetof(struct vmcb_seg, base),
sc->base);
stl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit),
sc->limit);
- stw_phys(addr + offsetof(struct vmcb_seg, attrib),
+ stw_phys(cs->as, addr + offsetof(struct vmcb_seg, attrib),
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 3e9a6d0..ce3a08e 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1043,7 +1043,8 @@ void HELPER(ptlb)(CPUS390XState *env)
/* store using real address */
void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1)
{
- stw_phys(get_address(env, 0, 0, addr), (uint32_t)v1);
+ CPUState *cs = ENV_GET_CPU(env);
+ stw_phys(cs->as, get_address(env, 0, 0, addr), (uint32_t)v1);
}
/* load real address */
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 0e87d79..4bc2568 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1015,7 +1015,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
stb_phys(addr, val);
break;
case 2:
- stw_phys(addr, val);
+ stw_phys(cs->as, addr, val);
break;
case 4:
default:
@@ -1035,7 +1035,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 2:
- stw_phys((hwaddr)addr
+ stw_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 4:
@@ -1814,7 +1814,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
stb_phys(addr, val);
break;
case 2:
- stw_phys(addr, val);
+ stw_phys(cs->as, addr, val);
break;
case 4:
stl_phys(cs->as, addr, val);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 15/22] exec: Make stb_phys input an AddressSpace
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (13 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 14/22] exec: Make stw_*_phys " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 16/22] exec: Make cpu_physical_memory_write_rom input an AS Edgar E. Iglesias
` (8 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 6 +++---
hw/net/vmware_utils.h | 2 +-
hw/ppc/ppc405_uc.c | 10 +++++-----
hw/ppc/spapr_hcall.c | 6 +++---
hw/s390x/s390-virtio-bus.c | 16 +++++++++++-----
hw/s390x/s390-virtio.c | 2 +-
hw/scsi/megasas.c | 6 ++++--
include/exec/cpu-common.h | 2 +-
target-i386/svm_helper.c | 2 +-
target-s390x/mem_helper.c | 2 +-
target-sparc/ldst_helper.c | 6 +++---
11 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/exec.c b/exec.c
index 3389b90..248b824 100644
--- a/exec.c
+++ b/exec.c
@@ -1610,7 +1610,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(&address_space_memory, addr, val);
break;
case 2:
stw_phys(&address_space_memory, addr, val);
@@ -2618,10 +2618,10 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stb_phys(hwaddr addr, uint32_t val)
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t v = val;
- cpu_physical_memory_write(addr, &v, 1);
+ address_space_rw(as, addr, &v, 1, 1);
}
/* warning: addr must be aligned */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index d8f734f..1099df6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -74,7 +74,7 @@ static inline void
vmw_shmem_st8(hwaddr addr, uint8_t value)
{
VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
- stb_phys(addr, value);
+ stb_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b0a59c3..ca520e8 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -63,27 +63,27 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
- stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+ stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
- stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
+ stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
- stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
+ stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
- stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+ stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
n = 0x6A;
if (flags & 0x00000001) {
for (i = 0; i < 6; i++)
- stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
+ stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
n += 4;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index ebf09e9..3ffcc65 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -370,7 +370,7 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
- stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
+ stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
return H_SUCCESS;
}
@@ -567,7 +567,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(cs->as, addr, val);
return H_SUCCESS;
case 2:
stw_phys(cs->as, addr, val);
@@ -632,7 +632,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
}
switch (esize) {
case 0:
- stb_phys(dst, tmp);
+ stb_phys(cs->as, dst, tmp);
break;
case 1:
stw_phys(cs->as, dst, tmp);
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 68f3e5a..e4fc353 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -359,15 +359,21 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_reset(dev->vdev);
/* Sync dev space */
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ, s390_virtio_device_num_vq(dev));
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_FEATURE_LEN, dev->feat_len);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ,
+ s390_virtio_device_num_vq(dev));
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_FEATURE_LEN, dev->feat_len);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_CONFIG_LEN, dev->vdev->config_len);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_CONFIG_LEN, dev->vdev->config_len);
num_vq = s390_virtio_device_num_vq(dev);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ, num_vq);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ, num_vq);
/* Sync virtqueues */
for (i = 0; i < num_vq; i++) {
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 7adf92a..9eeda97 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -91,7 +91,7 @@ static int s390_virtio_hcall_reset(const uint64_t *args)
return -EINVAL;
}
virtio_reset(dev->vdev);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_STATUS, 0);
+ stb_phys(&address_space_memory, dev->dev_offs + VIRTIO_DEV_OFFS_STATUS, 0);
s390_virtio_device_sync(dev);
s390_virtio_reset_idx(dev);
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index e12f80c..59570e2 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -144,12 +144,14 @@ static bool megasas_is_jbod(MegasasState *s)
static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
{
- stb_phys(frame + offsetof(struct mfi_frame_header, cmd_status), v);
+ stb_phys(&address_space_memory,
+ frame + offsetof(struct mfi_frame_header, cmd_status), v);
}
static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
{
- stb_phys(frame + offsetof(struct mfi_frame_header, scsi_status), v);
+ stb_phys(&address_space_memory,
+ frame + offsetof(struct mfi_frame_header, scsi_status), v);
}
/*
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index aef373e..d0fe123 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -90,7 +90,7 @@ uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
-void stb_phys(hwaddr addr, uint32_t val);
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index a86a99b..b38d450 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -661,7 +661,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
stq_phys(cs->as,
env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
- stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl),
+ stb_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.cpl),
env->hflags & HF_CPL_MASK);
/* Reload the host state from vm_hsave */
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index ce3a08e..875ea95 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -985,7 +985,7 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
mvc_asc(env, l - i, a1 + i, mode1, a2 + i, mode2);
break;
}
- stb_phys(dest + i, ldub_phys(cs->as, src + i));
+ stb_phys(cs->as, dest + i, ldub_phys(cs->as, src + i));
}
return cc;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 4bc2568..92761ad 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1012,7 +1012,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
{
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(cs->as, addr, val);
break;
case 2:
stw_phys(cs->as, addr, val);
@@ -1031,7 +1031,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
{
switch (size) {
case 1:
- stb_phys((hwaddr)addr
+ stb_phys(cs->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 2:
@@ -1811,7 +1811,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
{
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(cs->as, addr, val);
break;
case 2:
stw_phys(cs->as, addr, val);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 16/22] exec: Make cpu_physical_memory_write_rom input an AS
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (14 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 15/22] exec: Make stb_phys " Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 17/22] exec: Make cpu_memory_rw_debug use the CPUs AS Edgar E. Iglesias
` (7 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 15 ++++++++-------
hw/core/loader.c | 3 ++-
hw/intc/apic.c | 3 ++-
hw/sparc/sun4m.c | 3 ++-
include/exec/cpu-common.h | 2 +-
5 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/exec.c b/exec.c
index 248b824..7045f76 100644
--- a/exec.c
+++ b/exec.c
@@ -2099,7 +2099,7 @@ enum write_rom_type {
FLUSH_CACHE,
};
-static inline void cpu_physical_memory_write_rom_internal(
+static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
{
hwaddr l;
@@ -2109,8 +2109,7 @@ static inline void cpu_physical_memory_write_rom_internal(
while (len > 0) {
l = len;
- mr = address_space_translate(&address_space_memory,
- addr, &addr1, &l, true);
+ mr = address_space_translate(as, addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -2136,10 +2135,10 @@ static inline void cpu_physical_memory_write_rom_internal(
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
- cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA);
+ cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
}
void cpu_flush_icache_range(hwaddr start, int len)
@@ -2154,7 +2153,8 @@ void cpu_flush_icache_range(hwaddr start, int len)
return;
}
- cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE);
+ cpu_physical_memory_write_rom_internal(&address_space_memory,
+ start, NULL, len, FLUSH_CACHE);
}
typedef struct {
@@ -2718,7 +2718,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
- cpu_physical_memory_write_rom(phys_addr, buf, l);
+ cpu_physical_memory_write_rom(&address_space_memory,
+ phys_addr, buf, l);
else
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 0634bee..e1c3f3a 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize);
} else {
- cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+ cpu_physical_memory_write_rom(&address_space_memory,
+ rom->addr, rom->data, rom->datasize);
}
if (rom->isrom) {
/* rom needs to be written only once */
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 3d3deb6..361ae90 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type)
}
vapic_state.irr = vector & 0xff;
- cpu_physical_memory_write_rom(s->vapic_paddr + start,
+ cpu_physical_memory_write_rom(&address_space_memory,
+ s->vapic_paddr + start,
((void *)&vapic_state) + start, length);
}
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f7950..2957d90 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
- cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+ cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d0fe123..a21b65a 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
void cpu_flush_icache_range(hwaddr start, int len);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 17/22] exec: Make cpu_memory_rw_debug use the CPUs AS
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (15 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 16/22] exec: Make cpu_physical_memory_write_rom input an AS Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 18/22] memory: Add address_space_find_by_name() Edgar E. Iglesias
` (6 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 7045f76..8c05087 100644
--- a/exec.c
+++ b/exec.c
@@ -2717,11 +2717,11 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
if (l > len)
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
- if (is_write)
- cpu_physical_memory_write_rom(&address_space_memory,
- phys_addr, buf, l);
- else
- cpu_physical_memory_rw(phys_addr, buf, l, is_write);
+ if (is_write) {
+ cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
+ } else {
+ address_space_rw(cpu->as, phys_addr, buf, l, 0);
+ }
len -= l;
buf += l;
addr += l;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 18/22] memory: Add address_space_find_by_name()
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (16 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 17/22] exec: Make cpu_memory_rw_debug use the CPUs AS Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 19/22] qdev: Add qdev property type for AddressSpaces Edgar E. Iglesias
` (5 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/exec/memory.h | 9 +++++++++
memory.c | 12 ++++++++++++
translate-all.c | 10 ++++++++--
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 9101fc3..8465d5b 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1054,4 +1054,13 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
#endif
+/**
+ * address_space_find_by_name: Find an AddressSpace * by name
+ *
+ * Returns an AddressSpace * if found.
+ *
+ * @name: name of an address space too look for.
+ */
+AddressSpace *address_space_find_by_name(const char *name);
+
#endif
diff --git a/memory.c b/memory.c
index 59ecc28..22fbe16 100644
--- a/memory.c
+++ b/memory.c
@@ -1720,6 +1720,18 @@ void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
memory_region_transaction_commit();
}
+AddressSpace *address_space_find_by_name(const char *name)
+{
+ AddressSpace *as;
+
+ QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
+ if (strcmp(as->name, name) == 0) {
+ return as;
+ }
+ }
+ return NULL;
+}
+
void address_space_destroy(AddressSpace *as)
{
/* Flush out anything from MemoryListeners listening in on this */
diff --git a/translate-all.c b/translate-all.c
index 1ac0246..9950c3b 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -52,9 +52,8 @@
#include <libutil.h>
#endif
#endif
-#else
-#include "exec/address-spaces.h"
#endif
+#include "exec/address-spaces.h"
#include "exec/cputlb.h"
#include "translate-all.h"
@@ -1565,6 +1564,13 @@ void cpu_interrupt(CPUState *cpu, int mask)
cpu->tcg_exit_req = 1;
}
+/* Find an address space by name in user emulation. */
+AddressSpace *address_space_find_by_name(const char *name)
+{
+ /* Unsupported. */
+ return NULL;
+}
+
/*
* Walks guest process memory "regions" one by one
* and calls callback function 'fn' for each region.
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 19/22] qdev: Add qdev property type for AddressSpaces
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (17 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 18/22] memory: Add address_space_find_by_name() Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 20/22] cpu: Add address-space property Edgar E. Iglesias
` (4 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/core/qdev-properties-system.c | 8 ++++++
hw/core/qdev-properties.c | 54 ++++++++++++++++++++++++++++++++++++++++
include/hw/qdev-properties.h | 5 ++++
stubs/Makefile.objs | 1 +
stubs/memory.c | 6 +++++
5 files changed, 74 insertions(+)
create mode 100644 stubs/memory.c
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 3f29b49..27c2899 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -365,6 +365,14 @@ void qdev_prop_set_netdev(DeviceState *dev, const char *name,
value ? value->name : "", name, &error_abort);
}
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value)
+{
+ assert(!value || value->name);
+ object_property_set_str(OBJECT(dev),
+ value ? value->name : "", name, &error_abort);
+}
+
void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
{
qdev_prop_set_macaddr(dev, "mac", nd->macaddr.a);
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index b949f0e..68e09e2 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -1176,3 +1176,57 @@ PropertyInfo qdev_prop_size = {
.get = get_size,
.set = set_size,
};
+
+/* --- AddressSpace --- */
+
+static int parse_address_space(DeviceState *dev, const char *name,
+ AddressSpace **ptr)
+{
+ AddressSpace *as = address_space_find_by_name(name);
+ if (as == NULL) {
+ return -ENOENT;
+ }
+ *ptr = as;
+ return 0;
+}
+
+static void get_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ AddressSpace *as = qdev_get_prop_ptr(DEVICE(obj), opaque);
+ char *p = (char *) (as ? as->name : "");
+
+ visit_type_str(v, &p, name, errp);
+}
+
+static void set_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ DeviceState *dev = DEVICE(obj);
+ Property *prop = opaque;
+ Error *local_err = NULL;
+ AddressSpace **as = qdev_get_prop_ptr(dev, prop);
+ char *str;
+ int ret;
+
+ if (dev->realized) {
+ qdev_prop_set_after_realize(dev, name, errp);
+ return;
+ }
+
+ visit_type_str(v, &str, name, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ ret = parse_address_space(dev, str, as);
+ error_set_from_qdev_prop_error(errp, ret, dev, prop, str);
+ g_free(str);
+}
+
+PropertyInfo qdev_prop_address_space = {
+ .name = "address_space",
+ .get = get_address_space,
+ .set = set_address_space,
+};
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 77c6f7c..020439f 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -19,6 +19,7 @@ extern PropertyInfo qdev_prop_size;
extern PropertyInfo qdev_prop_string;
extern PropertyInfo qdev_prop_chr;
extern PropertyInfo qdev_prop_ptr;
+extern PropertyInfo qdev_prop_address_space;
extern PropertyInfo qdev_prop_macaddr;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_bios_chs_trans;
@@ -141,6 +142,8 @@ extern PropertyInfo qdev_prop_arraylen;
#define DEFINE_PROP_PTR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*)
+#define DEFINE_PROP_ADDRESS_SPACE(_n, _s, _f) \
+ DEFINE_PROP(_n, _s, _f, qdev_prop_address_space, AddressSpace*)
#define DEFINE_PROP_CHR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharDriverState*)
#define DEFINE_PROP_STRING(_n, _s, _f) \
@@ -177,6 +180,8 @@ void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value);
void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value);
void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value);
void qdev_prop_set_string(DeviceState *dev, const char *name, const char *value);
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value);
void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState *value);
void qdev_prop_set_netdev(DeviceState *dev, const char *name, NetClientState *value);
int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState *value) QEMU_WARN_UNUSED_RESULT;
diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs
index df92fe5..9e1e5da 100644
--- a/stubs/Makefile.objs
+++ b/stubs/Makefile.objs
@@ -26,4 +26,5 @@ stub-obj-y += uuid.o
stub-obj-y += vm-stop.o
stub-obj-y += vmstate.o
stub-obj-$(CONFIG_WIN32) += fd-register.o
+stub-obj-y += memory.o
stub-obj-y += cpus.o
diff --git a/stubs/memory.c b/stubs/memory.c
new file mode 100644
index 0000000..b3b4736
--- /dev/null
+++ b/stubs/memory.c
@@ -0,0 +1,6 @@
+#include "exec/address-spaces.h"
+
+AddressSpace *address_space_find_by_name(const char *name)
+{
+ return NULL;
+}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 20/22] cpu: Add address-space property
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (18 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 19/22] qdev: Add qdev property type for AddressSpaces Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 21/22] petalogix-ml605: Create the CPU with object_new() Edgar E. Iglesias
` (3 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
qom/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/qom/cpu.c b/qom/cpu.c
index 9d62479..fc6dbff 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -24,6 +24,7 @@
#include "qemu/notify.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
bool cpu_exists(int64_t id)
{
@@ -237,6 +238,11 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
+static Property cpu_properties[] = {
+ DEFINE_PROP_ADDRESS_SPACE("address-space", CPUState, as),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -253,6 +259,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
+ dc->props = cpu_properties;
dc->realize = cpu_common_realizefn;
/*
* Reason: CPUs still need special care by board code: wiring up
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 21/22] petalogix-ml605: Create the CPU with object_new()
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (19 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 20/22] cpu: Add address-space property Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 22/22] petalogix-ml605: Make the LMB visible only to the CPU Edgar E. Iglesias
` (2 subsequent siblings)
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
This is to allow future patches to set properties before cpu::realize().
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/microblaze/petalogix_ml605_mmu.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 1a87756..37cbbfd 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -75,7 +75,6 @@ static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
- const char *cpu_model = args->cpu_model;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
@@ -89,10 +88,8 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
qemu_irq irq[32];
/* init CPUs */
- if (cpu_model == NULL) {
- cpu_model = "microblaze";
- }
- cpu = cpu_mb_init(cpu_model);
+ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (20 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 21/22] petalogix-ml605: Create the CPU with object_new() Edgar E. Iglesias
@ 2014-02-03 9:44 ` Edgar E. Iglesias
2014-02-05 18:44 ` [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Peter Maydell
2014-02-09 13:31 ` Andreas Färber
23 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-03 9:44 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/microblaze/petalogix_ml605_mmu.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 37cbbfd..d1acbff 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -86,16 +86,31 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
+ MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
+ AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
+
+ /* Setup the CPU specific address-space. */
+ memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
+ address_space_init(as_cpu, mr_cpu_root, "as/cpu");
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
+ /* Populate the CPU AS with the LMB only visible to the CPU. */
+ memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
+ address_space_mem, 0,
+ memory_region_size(address_space_mem));
+ memory_region_add_subregion(mr_cpu_root, 0x00000000, sysmem_alias);
+
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
- memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
+ memory_region_add_subregion_overlap(mr_cpu_root, 0x00000000,
+ phys_lmb_bram, 2);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (21 preceding siblings ...)
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 22/22] petalogix-ml605: Make the LMB visible only to the CPU Edgar E. Iglesias
@ 2014-02-05 18:44 ` Peter Maydell
2014-02-06 1:40 ` Edgar E. Iglesias
2014-02-09 13:31 ` Andreas Färber
23 siblings, 1 reply; 36+ messages in thread
From: Peter Maydell @ 2014-02-05 18:44 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On 3 February 2014 09:44, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> I'm looking at modeling systems where multiple CPUs co-exist with
> different views of their attached buses/devs.
>
> With this series I'm trying to take some steps towards having
> an address-space per CPU. It's not complete but good enough for
> making it possible to model (to some extent) CPU local memories
> for MicroBlaze systems in emulation mode (TCG). I'm updating the
> petalogix-ml605 here and will follow-up later with the petalogix-s3adsp.
Do you have a git tree with these patches in? With Anthony's
patches db stalled my usual process for reviewing large
patchsets isn't working at the moment :-(
thanks
-- PMM
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-05 18:44 ` [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Peter Maydell
@ 2014-02-06 1:40 ` Edgar E. Iglesias
0 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-06 1:40 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On Wed, Feb 05, 2014 at 06:44:56PM +0000, Peter Maydell wrote:
> On 3 February 2014 09:44, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > I'm looking at modeling systems where multiple CPUs co-exist with
> > different views of their attached buses/devs.
> >
> > With this series I'm trying to take some steps towards having
> > an address-space per CPU. It's not complete but good enough for
> > making it possible to model (to some extent) CPU local memories
> > for MicroBlaze systems in emulation mode (TCG). I'm updating the
> > petalogix-ml605 here and will follow-up later with the petalogix-s3adsp.
>
> Do you have a git tree with these patches in? With Anthony's
> patches db stalled my usual process for reviewing large
> patchsets isn't working at the moment :-(
Hi Peter,
You can find them here:
git://repo.or.cz/qemu/cris-port.git aspace.v4
Cheers,
Edgar
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
` (22 preceding siblings ...)
2014-02-05 18:44 ` [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Peter Maydell
@ 2014-02-09 13:31 ` Andreas Färber
2014-02-09 14:21 ` Peter Maydell
23 siblings, 1 reply; 36+ messages in thread
From: Andreas Färber @ 2014-02-09 13:31 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini
Cc: peter.maydell, blauwirbel, aliguori, pcrost, Edgar E. Iglesias,
aurelien, rth
Paolo,
Am 03.02.2014 10:44, schrieb Edgar E. Iglesias:
> Edgar E. Iglesias (22):
> exec: Make tb_invalidate_phys_addr input an AS
> exec: Make iotlb_to_region input an AS
> exec: Always initialize MemorySection address spaces
> exec: Make memory_region_section_get_iotlb use section AS
> memory: Add MemoryListener to typedefs.h
I've been waiting on your review of this series since CPU changes start
only with the next patch and I consider most of them a "memory" topic.
Do you intend to review them or should I go ahead and queue these on
qom-cpu if they compile and don't obviously break things?
Thanks in advance,
Andreas
> cpu: Add per-cpu address space
> exec: On AS changes, only flush affected CPU TLBs
> exec: Make ldl_*_phys input an AddressSpace
> exec: Make ldq/ldub_*_phys input an AddressSpace
> exec: Make lduw_*_phys input an AddressSpace
> exec: Make stq_*_phys input an AddressSpace
> exec: Make stl_*_phys input an AddressSpace
> exec: Make stl_phys_notdirty input an AddressSpace
> exec: Make stw_*_phys input an AddressSpace
> exec: Make stb_phys input an AddressSpace
> exec: Make cpu_physical_memory_write_rom input an AS
> exec: Make cpu_memory_rw_debug use the CPUs AS
> memory: Add address_space_find_by_name()
> qdev: Add qdev property type for AddressSpaces
> cpu: Add address-space property
> petalogix-ml605: Create the CPU with object_new()
> petalogix-ml605: Make the LMB visible only to the CPU
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-09 13:31 ` Andreas Färber
@ 2014-02-09 14:21 ` Peter Maydell
2014-02-09 22:15 ` Paolo Bonzini
2014-02-10 23:10 ` Edgar E. Iglesias
0 siblings, 2 replies; 36+ messages in thread
From: Peter Maydell @ 2014-02-09 14:21 UTC (permalink / raw)
To: Andreas Färber
Cc: Edgar E. Iglesias, QEMU Developers, Blue Swirl, Anthony Liguori,
pcrost, Paolo Bonzini, Aurelien Jarno, Richard Henderson
On 9 February 2014 13:31, Andreas Färber <afaerber@suse.de> wrote:
> Paolo,
>
> Am 03.02.2014 10:44, schrieb Edgar E. Iglesias:
>> Edgar E. Iglesias (22):
>> exec: Make tb_invalidate_phys_addr input an AS
>> exec: Make iotlb_to_region input an AS
>> exec: Always initialize MemorySection address spaces
>> exec: Make memory_region_section_get_iotlb use section AS
>> memory: Add MemoryListener to typedefs.h
>
> I've been waiting on your review of this series since CPU changes start
> only with the next patch and I consider most of them a "memory" topic.
>
> Do you intend to review them or should I go ahead and queue these on
> qom-cpu if they compile and don't obviously break things?
I've just had a look at these, and I think the first part of the series
(up to and including "exec: Make cpu_memory_rw_debug
use the CPUs AS") looks good. I didn't check the fine detail
of all the conversions of the ld/st*_phys changes but they look
mostly mechanical anyway. So for that set of patches:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
I think we could queue that initial set for committal now (via
your qom tree or paolo's tree) if nobody else has review comments
to make.
I'm not so sure about the "find address space by name" and
what looks like using address space name strings to wire
address spaces up to CPUs, though. Also I suspect that really
we ought to be using MemoryRegions for this interface:
Consider a board model which puts together some RAM and
devices. It ought to have the same interface for passing this
up to the CPU whether it's doing so directly or via some SoC
container device. For the SoC container case, this has to be
by passing a MemoryRegion, since the SoC will want to add
some devices of its own to that region. So the interface for
passing things to the CPU should also be a MemoryRegion
(which the CPU then turns into an AddressSpace for its own
internal use.)
Are there cases involving IOMMUs or some other edgecase
that mean we might need to pass AddressSpaces around directly?
thanks
-- PMM
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-09 14:21 ` Peter Maydell
@ 2014-02-09 22:15 ` Paolo Bonzini
2014-02-10 9:23 ` Peter Maydell
2014-02-10 23:10 ` Edgar E. Iglesias
1 sibling, 1 reply; 36+ messages in thread
From: Paolo Bonzini @ 2014-02-09 22:15 UTC (permalink / raw)
To: Peter Maydell, Andreas Färber
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Edgar E. Iglesias, Aurelien Jarno, Richard Henderson
Il 09/02/2014 15:21, Peter Maydell ha scritto:
> Consider a board model which puts together some RAM and
> devices. It ought to have the same interface for passing this
> up to the CPU whether it's doing so directly or via some SoC
> container device. For the SoC container case, this has to be
> by passing a MemoryRegion, since the SoC will want to add
> some devices of its own to that region. So the interface for
> passing things to the CPU should also be a MemoryRegion
> (which the CPU then turns into an AddressSpace for its own
> internal use.)
I haven't look closely at those final patches either, but I think I
agree with Peter.
It's certainly okay if Andreas picks up these patches, since there's no
formal MAINTAINER for the memory API.
However, I'd prefer to first apply the patch to fix exec.c in order to
keep bisection as clean as possible.
Thanks!
Paolo
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-09 22:15 ` Paolo Bonzini
@ 2014-02-10 9:23 ` Peter Maydell
2014-02-10 17:04 ` Paolo Bonzini
0 siblings, 1 reply; 36+ messages in thread
From: Peter Maydell @ 2014-02-10 9:23 UTC (permalink / raw)
To: Paolo Bonzini
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Edgar E. Iglesias, Andreas Färber, Aurelien Jarno,
Richard Henderson
On 9 February 2014 22:15, Paolo Bonzini <pbonzini@redhat.com> wrote:
> However, I'd prefer to first apply the patch to fix exec.c in order to keep
> bisection as clean as possible.
Agreed; can you point me at the pullreq (or failing that, patches you
want me to apply) that fixes that?
thanks
-- PMM
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-10 9:23 ` Peter Maydell
@ 2014-02-10 17:04 ` Paolo Bonzini
0 siblings, 0 replies; 36+ messages in thread
From: Paolo Bonzini @ 2014-02-10 17:04 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Edgar E. Iglesias, Andreas Färber, Aurelien Jarno,
Richard Henderson
Il 10/02/2014 10:23, Peter Maydell ha scritto:
> On 9 February 2014 22:15, Paolo Bonzini <pbonzini@redhat.com> wrote:
>> However, I'd prefer to first apply the patch to fix exec.c in order to keep
>> bisection as clean as possible.
>
> Agreed; can you point me at the pullreq (or failing that, patches you
> want me to apply) that fixes that?
Sure: http://article.gmane.org/gmane.comp.emulators.qemu/254614/raw
Paolo
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-09 14:21 ` Peter Maydell
2014-02-09 22:15 ` Paolo Bonzini
@ 2014-02-10 23:10 ` Edgar E. Iglesias
2014-02-10 23:42 ` Peter Maydell
1 sibling, 1 reply; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-10 23:10 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On Sun, Feb 09, 2014 at 02:21:31PM +0000, Peter Maydell wrote:
> On 9 February 2014 13:31, Andreas Färber <afaerber@suse.de> wrote:
> > Paolo,
> >
> > Am 03.02.2014 10:44, schrieb Edgar E. Iglesias:
> >> Edgar E. Iglesias (22):
> >> exec: Make tb_invalidate_phys_addr input an AS
> >> exec: Make iotlb_to_region input an AS
> >> exec: Always initialize MemorySection address spaces
> >> exec: Make memory_region_section_get_iotlb use section AS
> >> memory: Add MemoryListener to typedefs.h
> >
> > I've been waiting on your review of this series since CPU changes start
> > only with the next patch and I consider most of them a "memory" topic.
> >
> > Do you intend to review them or should I go ahead and queue these on
> > qom-cpu if they compile and don't obviously break things?
>
> I've just had a look at these, and I think the first part of the series
> (up to and including "exec: Make cpu_memory_rw_debug
> use the CPUs AS") looks good. I didn't check the fine detail
> of all the conversions of the ld/st*_phys changes but they look
> mostly mechanical anyway. So for that set of patches:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Thanks
>
> I think we could queue that initial set for committal now (via
> your qom tree or paolo's tree) if nobody else has review comments
> to make.
>
> I'm not so sure about the "find address space by name" and
> what looks like using address space name strings to wire
> address spaces up to CPUs, though. Also I suspect that really
> we ought to be using MemoryRegions for this interface:
>
> Consider a board model which puts together some RAM and
> devices. It ought to have the same interface for passing this
> up to the CPU whether it's doing so directly or via some SoC
> container device. For the SoC container case, this has to be
> by passing a MemoryRegion, since the SoC will want to add
> some devices of its own to that region. So the interface for
> passing things to the CPU should also be a MemoryRegion
> (which the CPU then turns into an AddressSpace for its own
> internal use.)
>
> Are there cases involving IOMMUs or some other edgecase
> that mean we might need to pass AddressSpaces around directly?
My thinking was in terms of trying to minimize the amount of
AS structures we create in cases were the nr of master outnumber
the nr of ASs. But there might be ways to achieve being light
even if we dont explicitely pass AS refs around. Will try to get
a chance to look at a MemoryRegion based interface instead
(if no one beats me to it).
Thanks,
Edgar
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-10 23:10 ` Edgar E. Iglesias
@ 2014-02-10 23:42 ` Peter Maydell
2014-02-10 23:53 ` Edgar E. Iglesias
0 siblings, 1 reply; 36+ messages in thread
From: Peter Maydell @ 2014-02-10 23:42 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On 10 February 2014 23:10, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> My thinking was in terms of trying to minimize the amount of
> AS structures we create in cases were the nr of master outnumber
> the nr of ASs. But there might be ways to achieve being light
> even if we dont explicitely pass AS refs around. Will try to get
> a chance to look at a MemoryRegion based interface instead
> (if no one beats me to it).
Is there that much overhead to creating an AS per master? I guess
you end up recalculating the same memory flatview for every AS
when a memory region gets mapped or unmapped.
In any case, if it's OK to share AddressSpaces between masters
then we can relatively easily do so, since there's already a list
of all AddressSpaces that you can run through to find the one
whose root MemoryRegion is the one you want. (Probably needs
a refcount in the AddressSpace struct as well.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-10 23:42 ` Peter Maydell
@ 2014-02-10 23:53 ` Edgar E. Iglesias
2014-02-11 21:40 ` Paolo Bonzini
0 siblings, 1 reply; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-10 23:53 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On Mon, Feb 10, 2014 at 11:42:35PM +0000, Peter Maydell wrote:
> On 10 February 2014 23:10, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > My thinking was in terms of trying to minimize the amount of
> > AS structures we create in cases were the nr of master outnumber
> > the nr of ASs. But there might be ways to achieve being light
> > even if we dont explicitely pass AS refs around. Will try to get
> > a chance to look at a MemoryRegion based interface instead
> > (if no one beats me to it).
>
> Is there that much overhead to creating an AS per master? I guess
> you end up recalculating the same memory flatview for every AS
> when a memory region gets mapped or unmapped.
> In any case, if it's OK to share AddressSpaces between masters
> then we can relatively easily do so, since there's already a list
> of all AddressSpaces that you can run through to find the one
> whose root MemoryRegion is the one you want. (Probably needs
> a refcount in the AddressSpace struct as well.)
Right, something like that might be worthwhile.
It might not make much difference until we start ramping
things up significantly (in terms of amount of masters).
Cheers,
Edgar
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space Edgar E. Iglesias
@ 2014-02-11 19:52 ` Andreas Färber
2014-02-14 5:36 ` Edgar E. Iglesias
0 siblings, 1 reply; 36+ messages in thread
From: Andreas Färber @ 2014-02-11 19:52 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, aurelien, rth
Edgar,
Am 03.02.2014 10:44, schrieb Edgar E. Iglesias:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> cpus.c | 2 ++
> cputlb.c | 7 ++++---
> exec.c | 27 +++++++++++++++++++--------
> include/exec/exec-all.h | 1 +
> include/exec/softmmu_template.h | 6 ++++--
> include/qom/cpu.h | 3 +++
> 6 files changed, 33 insertions(+), 13 deletions(-)
This CPU patch did not get a Reviewed-by or Acked-by from me and was
still committed, even without indicating so here! Had you asked me, you
would've got one and my go-ahead, but what annoys me is that I learned
about you committing this through it breaking my qom-cpu-13 branch with
a conflict in target-i386/helper.c in later patch I had not yet
reviewed... :/
Please a) indicate you committed patches as an email reply to that
series and b) read the replies - me, Peter and Paolo were converging on
giving me the okay to take a subset of this series into qom-cpu, you
neither asked nor did anyone propose committing them directly on the
mailing list.
Thanks,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces
2014-02-10 23:53 ` Edgar E. Iglesias
@ 2014-02-11 21:40 ` Paolo Bonzini
0 siblings, 0 replies; 36+ messages in thread
From: Paolo Bonzini @ 2014-02-11 21:40 UTC (permalink / raw)
To: Edgar E. Iglesias, Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Andreas Färber, Aurelien Jarno, Richard Henderson
Il 11/02/2014 00:53, Edgar E. Iglesias ha scritto:
>> > Is there that much overhead to creating an AS per master? I guess
>> > you end up recalculating the same memory flatview for every AS
>> > when a memory region gets mapped or unmapped.
>> > In any case, if it's OK to share AddressSpaces between masters
>> > then we can relatively easily do so, since there's already a list
>> > of all AddressSpaces that you can run through to find the one
>> > whose root MemoryRegion is the one you want. (Probably needs
>> > a refcount in the AddressSpace struct as well.)
> Right, something like that might be worthwhile.
>
> It might not make much difference until we start ramping
> things up significantly (in terms of amount of masters).
We already have a decent amount of masters for PCI, where each device
that can do bus-master DMA has basically its own copy of
address_space_memory. It has never been a problem in terms of time
spent updating the ASes.
Paolo
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space
2014-02-11 19:52 ` Andreas Färber
@ 2014-02-14 5:36 ` Edgar E. Iglesias
0 siblings, 0 replies; 36+ messages in thread
From: Edgar E. Iglesias @ 2014-02-14 5:36 UTC (permalink / raw)
To: Andreas Färber
Cc: peter.maydell, qemu-devel, blauwirbel, aliguori, pcrost,
pbonzini, aurelien, rth
On Tue, Feb 11, 2014 at 08:52:11PM +0100, Andreas Färber wrote:
> Edgar,
>
> Am 03.02.2014 10:44, schrieb Edgar E. Iglesias:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > cpus.c | 2 ++
> > cputlb.c | 7 ++++---
> > exec.c | 27 +++++++++++++++++++--------
> > include/exec/exec-all.h | 1 +
> > include/exec/softmmu_template.h | 6 ++++--
> > include/qom/cpu.h | 3 +++
> > 6 files changed, 33 insertions(+), 13 deletions(-)
>
> This CPU patch did not get a Reviewed-by or Acked-by from me and was
> still committed, even without indicating so here! Had you asked me, you
> would've got one and my go-ahead, but what annoys me is that I learned
> about you committing this through it breaking my qom-cpu-13 branch with
> a conflict in target-i386/helper.c in later patch I had not yet
> reviewed... :/
>
> Please a) indicate you committed patches as an email reply to that
> series and b) read the replies - me, Peter and Paolo were converging on
> giving me the okay to take a subset of this series into qom-cpu, you
Sorry, I must have missed that part of the discussion. If the merge
conflict was bad let me know and I'd be happy to help.
Cheers,
Edgar
> neither asked nor did anyone propose committing them directly on the
> mailing list.
>
> Thanks,
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2014-02-14 5:37 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-02-03 9:44 [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 01/22] exec: Make tb_invalidate_phys_addr input an AS Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 02/22] exec: Make iotlb_to_region " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 03/22] exec: Always initialize MemorySection address spaces Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 04/22] exec: Make memory_region_section_get_iotlb use section AS Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 05/22] memory: Add MemoryListener to typedefs.h Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 06/22] cpu: Add per-cpu address space Edgar E. Iglesias
2014-02-11 19:52 ` Andreas Färber
2014-02-14 5:36 ` Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 07/22] exec: On AS changes, only flush affected CPU TLBs Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 08/22] exec: Make ldl_*_phys input an AddressSpace Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 09/22] exec: Make ldq/ldub_*_phys " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 10/22] exec: Make lduw_*_phys " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 11/22] exec: Make stq_*_phys " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 12/22] exec: Make stl_*_phys " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 13/22] exec: Make stl_phys_notdirty " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 14/22] exec: Make stw_*_phys " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 15/22] exec: Make stb_phys " Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 16/22] exec: Make cpu_physical_memory_write_rom input an AS Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 17/22] exec: Make cpu_memory_rw_debug use the CPUs AS Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 18/22] memory: Add address_space_find_by_name() Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 19/22] qdev: Add qdev property type for AddressSpaces Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 20/22] cpu: Add address-space property Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 21/22] petalogix-ml605: Create the CPU with object_new() Edgar E. Iglesias
2014-02-03 9:44 ` [Qemu-devel] [PATCH v4 22/22] petalogix-ml605: Make the LMB visible only to the CPU Edgar E. Iglesias
2014-02-05 18:44 ` [Qemu-devel] [PATCH v4 00/22] Steps towards per CPU address-spaces Peter Maydell
2014-02-06 1:40 ` Edgar E. Iglesias
2014-02-09 13:31 ` Andreas Färber
2014-02-09 14:21 ` Peter Maydell
2014-02-09 22:15 ` Paolo Bonzini
2014-02-10 9:23 ` Peter Maydell
2014-02-10 17:04 ` Paolo Bonzini
2014-02-10 23:10 ` Edgar E. Iglesias
2014-02-10 23:42 ` Peter Maydell
2014-02-10 23:53 ` Edgar E. Iglesias
2014-02-11 21:40 ` Paolo Bonzini
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