From: Stephen Boyd <sboyd@codeaurora.org> To: Kumar Gala <galak@codeaurora.org> Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, Borislav Petkov <bp@alien8.de> Subject: [PATCH v6 5/5] ARM: dts: msm: Fix Krait CPU/L2 nodes Date: Fri, 4 Apr 2014 12:57:30 -0700 [thread overview] Message-ID: <1396641450-12854-6-git-send-email-sboyd@codeaurora.org> (raw) In-Reply-To: <1396641450-12854-1-git-send-email-sboyd@codeaurora.org> The error interrupt binding wasn't properly accepted when this was originally written. Fix the dts to match the binding. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- arch/arm/boot/dts/qcom-msm8960.dtsi | 29 +++++++++++++++------- arch/arm/boot/dts/qcom-msm8974.dtsi | 49 ++++++++++++++++++++++++++++--------- 2 files changed, 57 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 997b7b94e117..66a6e8c4fdcf 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -12,30 +12,41 @@ cpus { #address-cells = <1>; #size-cells = <0>; - interrupts = <1 14 0x304>; - compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; cpu@0 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&L1_0>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + + L1_0: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 14 0x104>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + interrupts = <0 2 0x4>; + }; }; cpu@1 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&L1_1>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - }; - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - interrupts = <0 2 0x4>; + L1_1: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 14 0x104>; + next-level-cache = <&L2>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index f68723918b3f..b4ac497b7d76 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -12,43 +12,68 @@ cpus { #address-cells = <1>; #size-cells = <0>; - interrupts = <1 9 0xf04>; - compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; cpu@0 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&L1_0>; qcom,acc = <&acc0>; + + L1_0: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x104>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + interrupts = <0 2 0x4>; + qcom,saw = <&saw_l2>; + }; }; cpu@1 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&L1_1>; qcom,acc = <&acc1>; + + L1_1: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x204>; + next-level-cache = <&L2>; + }; }; cpu@2 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&L1_2>; qcom,acc = <&acc2>; + + L1_2: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x404>; + next-level-cache = <&L2>; + }; }; cpu@3 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&L1_3>; qcom,acc = <&acc3>; - }; - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - interrupts = <0 2 0x4>; - qcom,saw = <&saw_l2>; + L1_3: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x804>; + next-level-cache = <&L2>; + }; }; }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 5/5] ARM: dts: msm: Fix Krait CPU/L2 nodes Date: Fri, 4 Apr 2014 12:57:30 -0700 [thread overview] Message-ID: <1396641450-12854-6-git-send-email-sboyd@codeaurora.org> (raw) In-Reply-To: <1396641450-12854-1-git-send-email-sboyd@codeaurora.org> The error interrupt binding wasn't properly accepted when this was originally written. Fix the dts to match the binding. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- arch/arm/boot/dts/qcom-msm8960.dtsi | 29 +++++++++++++++------- arch/arm/boot/dts/qcom-msm8974.dtsi | 49 ++++++++++++++++++++++++++++--------- 2 files changed, 57 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 997b7b94e117..66a6e8c4fdcf 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -12,30 +12,41 @@ cpus { #address-cells = <1>; #size-cells = <0>; - interrupts = <1 14 0x304>; - compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; cpu at 0 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&L1_0>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + + L1_0: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 14 0x104>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + interrupts = <0 2 0x4>; + }; }; cpu at 1 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&L1_1>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - }; - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - interrupts = <0 2 0x4>; + L1_1: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 14 0x104>; + next-level-cache = <&L2>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index f68723918b3f..b4ac497b7d76 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -12,43 +12,68 @@ cpus { #address-cells = <1>; #size-cells = <0>; - interrupts = <1 9 0xf04>; - compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; cpu at 0 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&L1_0>; qcom,acc = <&acc0>; + + L1_0: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x104>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + interrupts = <0 2 0x4>; + qcom,saw = <&saw_l2>; + }; }; cpu at 1 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&L1_1>; qcom,acc = <&acc1>; + + L1_1: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x204>; + next-level-cache = <&L2>; + }; }; cpu at 2 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&L1_2>; qcom,acc = <&acc2>; + + L1_2: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x404>; + next-level-cache = <&L2>; + }; }; cpu at 3 { + compatible = "qcom,krait"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&L1_3>; qcom,acc = <&acc3>; - }; - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - interrupts = <0 2 0x4>; - qcom,saw = <&saw_l2>; + L1_3: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 9 0x804>; + next-level-cache = <&L2>; + }; }; }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2014-04-04 19:57 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-04-04 19:57 [PATCH v6 0/5] Krait L1/L2 EDAC driver Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-04 19:57 ` [PATCH v6 1/5] genirq: export percpu irq functions for module usage Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-04 19:57 ` [PATCH v6 2/5] ARM: Add Krait L2 register accessor functions Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-07 20:18 ` Borislav Petkov 2014-04-07 20:18 ` Borislav Petkov 2014-04-07 21:56 ` Stephen Boyd 2014-04-07 21:56 ` Stephen Boyd 2014-04-08 6:43 ` Borislav Petkov 2014-04-08 6:43 ` Borislav Petkov 2014-04-08 14:25 ` Christopher Covington 2014-04-08 14:25 ` Christopher Covington 2014-04-08 15:10 ` Borislav Petkov 2014-04-08 15:10 ` Borislav Petkov 2014-04-08 16:19 ` One Thousand Gnomes 2014-04-08 16:19 ` One Thousand Gnomes 2014-04-08 16:42 ` Borislav Petkov 2014-04-08 16:42 ` Borislav Petkov 2014-04-04 19:57 ` [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-08 15:39 ` Borislav Petkov 2014-04-08 15:39 ` Borislav Petkov 2014-04-08 19:55 ` Stephen Boyd 2014-04-08 19:55 ` Stephen Boyd [not found] ` <20140408153925.GJ30077-fF5Pk5pvG8Y@public.gmane.org> 2014-04-29 10:34 ` Lorenzo Pieralisi 2014-04-29 10:34 ` Lorenzo Pieralisi 2014-04-29 10:34 ` Lorenzo Pieralisi 2014-04-29 19:02 ` Borislav Petkov 2014-04-29 19:02 ` Borislav Petkov 2014-04-29 19:02 ` Borislav Petkov 2014-04-04 19:57 ` [PATCH v6 4/5] edac: Add support for Krait CPU cache error detection Stephen Boyd 2014-04-04 19:57 ` Stephen Boyd 2014-04-08 17:35 ` Borislav Petkov 2014-04-08 17:35 ` Borislav Petkov 2014-04-08 19:54 ` Stephen Boyd 2014-04-08 19:54 ` Stephen Boyd 2014-04-09 15:24 ` Borislav Petkov 2014-04-09 15:24 ` Borislav Petkov 2014-04-04 19:57 ` Stephen Boyd [this message] 2014-04-04 19:57 ` [PATCH v6 5/5] ARM: dts: msm: Fix Krait CPU/L2 nodes Stephen Boyd
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