[PATCH V3] Add support for flag status register on Micron chips.

From: Graham Moore <grmoore@altera.com>
To: <ggrahammoore@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>,
	Brian Norris <computersforpeace@gmail.com>,
	ZY - marex <marex@denx.de>,
	Artem Bityutskiy <artem.bityutskiy@linux.intel.com>,
	Sourav Poddar <sourav.poddar@ti.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Geert Uytterhoeven <geert+renesas@linux-m68k.org>,
	Jingoo Han <jg1.han@samsung.com>,
	Insop Song <insop.song@gainspeed.com>,
	Graham Moore <grmoore@altera.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	Alan Tull <atull@altera.com>, Dinh Nguyen <dinguyen@altera.com>,
	Yves Vandervennet <rocket.yvanderv@gmail.com>
Subject: [PATCH V3] Add support for flag status register on Micron chips.
Date: Tue, 22 Apr 2014 09:03:15 -0500	[thread overview]
Message-ID: <1398175396-7560-1-git-send-email-grmoore@altera.com> (raw)

I rebased this patch onto the l2-mtd spinor branch.  Sorry it took so long, had to patch for our SoC, corporate network issues, etc.

The change to read the flag status register is, afaik, specific to Micron chips.  So, imo, the fsr ready check should be in the m25p80.c file.  But I put it into the spin-nor.c file, because I need to call the read_sr() function, which is declared static in spi-nor.c.

I *could* duplicate the read_sr code and put the wait_till_fsr_ready in m25p80, but I'm pretty sure that would attract some critique :)  Suggestions most welcome.

I also used n25q512ax3 for the id because there are two part numbers for the 512MB part with FSR, n25q512a13 and n25qa512a83.  The '83' version has a reset line.

Graham Moore (1):
  Add support for flag status register on Micron chips.

 drivers/mtd/spi-nor/spi-nor.c |   51 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h   |    4 ++++
 2 files changed, 55 insertions(+)

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1.7.9.5