All of lore.kernel.org
 help / color / mirror / Atom feed
From: George Cherian <george.cherian@ti.com>
To: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-omap@vger.kernel.org>
Cc: <davem@davemloft.net>, <richardcochran@gmail.com>,
	<jeffrey.t.kirsher@intel.com>, <dborkman@redhat.com>,
	<ast@plumgrid.com>, <tklauser@distanz.ch>, <mpa@pengutronix.de>,
	<bhutchings@solarflare.com>, <zonque@gmail.com>, <balbi@ti.com>,
	<mugunthanvnm@ti.com>, <george.cherian@ti.com>, <t-kristo@ti.com>,
	<mturquette@linaro.org>, <linux@arm.linux.org.uk>,
	<galak@codeaurora.org>, <ijc+devicetree@hellion.org.uk>,
	<mark.rutland@arm.com>, <pawel.moll@arm.com>,
	<robh+dt@kernel.org>, <tony@atomide.com>, <bcousson@baylibre.com>
Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 09:40:23 +0530	[thread overview]
Message-ID: <1398658225-25873-5-git-send-email-george.cherian@ti.com> (raw)
In-Reply-To: <1398658225-25873-1-git-send-email-george.cherian@ti.com>

Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.

while at that rename TS_BIT8 to TS_TTL_NONZERO

Signed-off-by: George Cherian <george.cherian@ti.com>
---
 drivers/net/ethernet/ti/cpsw.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 085ffb5..af1423b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -248,7 +248,8 @@ struct cpsw_ss_regs {
 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
-#define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
+#define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
+#define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
@@ -256,8 +257,9 @@ struct cpsw_ss_regs {
 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 
 #define CTRL_TS_BITS \
-	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
-	 TS_ANNEX_D_EN | TS_LTYPE1_EN)
+	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
+	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
+	 TS_LTYPE1_EN)
 
 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
-- 
1.8.3.1


WARNING: multiple messages have this Message-ID (diff)
From: George Cherian <george.cherian@ti.com>
To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-omap@vger.kernel.org
Cc: davem@davemloft.net, richardcochran@gmail.com,
	jeffrey.t.kirsher@intel.com, dborkman@redhat.com,
	ast@plumgrid.com, tklauser@distanz.ch, mpa@pengutronix.de,
	bhutchings@solarflare.com, zonque@gmail.com, balbi@ti.com,
	mugunthanvnm@ti.com, george.cherian@ti.com, t-kristo@ti.com,
	mturquette@linaro.org, linux@arm.linux.org.uk,
	galak@codeaurora.org, ijc+devicetree@hellion.org.uk,
	mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org,
	tony@atomide.com, bcousson@baylibre.com
Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 09:40:23 +0530	[thread overview]
Message-ID: <1398658225-25873-5-git-send-email-george.cherian@ti.com> (raw)
In-Reply-To: <1398658225-25873-1-git-send-email-george.cherian@ti.com>

Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.

while at that rename TS_BIT8 to TS_TTL_NONZERO

Signed-off-by: George Cherian <george.cherian@ti.com>
---
 drivers/net/ethernet/ti/cpsw.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 085ffb5..af1423b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -248,7 +248,8 @@ struct cpsw_ss_regs {
 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
-#define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
+#define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
+#define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
@@ -256,8 +257,9 @@ struct cpsw_ss_regs {
 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 
 #define CTRL_TS_BITS \
-	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
-	 TS_ANNEX_D_EN | TS_LTYPE1_EN)
+	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
+	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
+	 TS_LTYPE1_EN)
 
 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
-- 
1.8.3.1

WARNING: multiple messages have this Message-ID (diff)
From: george.cherian@ti.com (George Cherian)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 09:40:23 +0530	[thread overview]
Message-ID: <1398658225-25873-5-git-send-email-george.cherian@ti.com> (raw)
In-Reply-To: <1398658225-25873-1-git-send-email-george.cherian@ti.com>

Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.

while at that rename TS_BIT8 to TS_TTL_NONZERO

Signed-off-by: George Cherian <george.cherian@ti.com>
---
 drivers/net/ethernet/ti/cpsw.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 085ffb5..af1423b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -248,7 +248,8 @@ struct cpsw_ss_regs {
 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
-#define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
+#define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
+#define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
@@ -256,8 +257,9 @@ struct cpsw_ss_regs {
 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 
 #define CTRL_TS_BITS \
-	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
-	 TS_ANNEX_D_EN | TS_LTYPE1_EN)
+	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
+	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
+	 TS_LTYPE1_EN)
 
 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
-- 
1.8.3.1

  parent reply	other threads:[~2014-04-28  4:13 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-28  4:10 [PATCH 0/6] Add CPTS support for AM437x George Cherian
2014-04-28  4:10 ` George Cherian
2014-04-28  4:10 ` George Cherian
2014-04-28  4:10 ` George Cherian
2014-04-28  4:10 ` [PATCH 1/6] drivers: net: cpts: Remove hardcoded clock name for CPTS George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  6:55   ` Richard Cochran
2014-04-28  6:55     ` Richard Cochran
2014-04-28  6:55     ` Richard Cochran
2014-04-28 14:31   ` Felipe Balbi
2014-04-28 14:31     ` Felipe Balbi
2014-04-28 14:31     ` Felipe Balbi
2014-04-28 14:45     ` George Cherian
2014-04-28 14:45       ` George Cherian
2014-04-28 14:45       ` George Cherian
2014-04-28 14:45       ` George Cherian
2014-04-28  4:10 ` [PATCH 2/6] ARM: dts: am33xx: Add clock names for cpsw and cpts George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10 ` [PATCH 3/6] drivers: net: cpsw: Enable CPTS for DRA7xx and AM4372 George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10 ` George Cherian [this message]
2014-04-28  4:10   ` [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  7:55   ` Richard Cochran
2014-04-28  7:55     ` Richard Cochran
2014-04-28  7:55     ` Richard Cochran
2014-04-28 12:58     ` George Cherian
2014-04-28 12:58       ` George Cherian
2014-04-28 12:58       ` George Cherian
2014-04-28  4:10 ` [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  7:10   ` Richard Cochran
2014-04-28  7:10     ` Richard Cochran
2014-04-28 12:55     ` George Cherian
2014-04-28 12:55       ` George Cherian
2014-04-28 12:55       ` George Cherian
2014-04-28 16:18       ` Richard Cochran
2014-04-28 16:18         ` Richard Cochran
2014-04-29  4:28         ` George Cherian
2014-04-29  4:28           ` George Cherian
2014-04-29  4:28           ` George Cherian
2014-04-29  4:28           ` George Cherian
2014-04-28  4:10 ` [PATCH 6/6] ARM: dts: am4372: Add clock names for cpsw and cpts George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1398658225-25873-5-git-send-email-george.cherian@ti.com \
    --to=george.cherian@ti.com \
    --cc=ast@plumgrid.com \
    --cc=balbi@ti.com \
    --cc=bcousson@baylibre.com \
    --cc=bhutchings@solarflare.com \
    --cc=davem@davemloft.net \
    --cc=dborkman@redhat.com \
    --cc=devicetree@vger.kernel.org \
    --cc=galak@codeaurora.org \
    --cc=ijc+devicetree@hellion.org.uk \
    --cc=jeffrey.t.kirsher@intel.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-omap@vger.kernel.org \
    --cc=linux@arm.linux.org.uk \
    --cc=mark.rutland@arm.com \
    --cc=mpa@pengutronix.de \
    --cc=mturquette@linaro.org \
    --cc=mugunthanvnm@ti.com \
    --cc=netdev@vger.kernel.org \
    --cc=pawel.moll@arm.com \
    --cc=richardcochran@gmail.com \
    --cc=robh+dt@kernel.org \
    --cc=t-kristo@ti.com \
    --cc=tklauser@distanz.ch \
    --cc=tony@atomide.com \
    --cc=zonque@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.