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From: Richard Cochran <richardcochran@gmail.com>
To: George Cherian <george.cherian@ti.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-omap@vger.kernel.org, davem@davemloft.net,
	jeffrey.t.kirsher@intel.com, dborkman@redhat.com,
	ast@plumgrid.com, tklauser@distanz.ch, mpa@pengutronix.de,
	bhutchings@solarflare.com, zonque@gmail.com, balbi@ti.com,
	mugunthanvnm@ti.com, t-kristo@ti.com, mturquette@linaro.org,
	linux@arm.linux.org.uk, galak@codeaurora.org,
	ijc+devicetree@hellion.org.uk, mark.rutland@arm.com,
	pawel.moll@arm.com, robh+dt@kernel.org, tony@atomide.com,
	bcousson@baylibre.com
Subject: Re: [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk
Date: Mon, 28 Apr 2014 09:10:36 +0200	[thread overview]
Message-ID: <20140428071034.GB4380@netboy> (raw)
In-Reply-To: <1398658225-25873-6-git-send-email-george.cherian@ti.com>

On Mon, Apr 28, 2014 at 09:40:24AM +0530, George Cherian wrote:
> cpsw_cpts_rft_clk has got the choice of 3 clocksources
>  -dpll_core_m4_ck
>  -dpll_core_m5_ck
>  -dpll_disp_m2_ck
> 
> By default dpll_core_m4_ck is selected, witn this as clock
> source the CPTS doesnot work properly. It gives clockcheck errors
> while running PTP.
> 
>  clockcheck: clock jumped backward or running slower than expected!

It is strange that I have never seen this error, since I have often
tested linuxptp on a beagle bone white.

Can you please explain why this clock doesn't work correctly?

> By selecting dpll_core_m5_ck as the clocksource fixes this issue.
> In AM335x dpll_core_m5_ck is the default clocksource.

The choice of clock source in the CPTS driver originally came from
TI. It would be nice to know why that was the wrong choice.

Thanks,
Richard

WARNING: multiple messages have this Message-ID (diff)
From: richardcochran@gmail.com (Richard Cochran)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk
Date: Mon, 28 Apr 2014 09:10:36 +0200	[thread overview]
Message-ID: <20140428071034.GB4380@netboy> (raw)
In-Reply-To: <1398658225-25873-6-git-send-email-george.cherian@ti.com>

On Mon, Apr 28, 2014 at 09:40:24AM +0530, George Cherian wrote:
> cpsw_cpts_rft_clk has got the choice of 3 clocksources
>  -dpll_core_m4_ck
>  -dpll_core_m5_ck
>  -dpll_disp_m2_ck
> 
> By default dpll_core_m4_ck is selected, witn this as clock
> source the CPTS doesnot work properly. It gives clockcheck errors
> while running PTP.
> 
>  clockcheck: clock jumped backward or running slower than expected!

It is strange that I have never seen this error, since I have often
tested linuxptp on a beagle bone white.

Can you please explain why this clock doesn't work correctly?

> By selecting dpll_core_m5_ck as the clocksource fixes this issue.
> In AM335x dpll_core_m5_ck is the default clocksource.

The choice of clock source in the CPTS driver originally came from
TI. It would be nice to know why that was the wrong choice.

Thanks,
Richard

  reply	other threads:[~2014-04-28  7:10 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-28  4:10 [PATCH 0/6] Add CPTS support for AM437x George Cherian
2014-04-28  4:10 ` George Cherian
2014-04-28  4:10 ` George Cherian
2014-04-28  4:10 ` George Cherian
2014-04-28  4:10 ` [PATCH 1/6] drivers: net: cpts: Remove hardcoded clock name for CPTS George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  6:55   ` Richard Cochran
2014-04-28  6:55     ` Richard Cochran
2014-04-28  6:55     ` Richard Cochran
2014-04-28 14:31   ` Felipe Balbi
2014-04-28 14:31     ` Felipe Balbi
2014-04-28 14:31     ` Felipe Balbi
2014-04-28 14:45     ` George Cherian
2014-04-28 14:45       ` George Cherian
2014-04-28 14:45       ` George Cherian
2014-04-28 14:45       ` George Cherian
2014-04-28  4:10 ` [PATCH 2/6] ARM: dts: am33xx: Add clock names for cpsw and cpts George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10 ` [PATCH 3/6] drivers: net: cpsw: Enable CPTS for DRA7xx and AM4372 George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10 ` [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  7:55   ` Richard Cochran
2014-04-28  7:55     ` Richard Cochran
2014-04-28  7:55     ` Richard Cochran
2014-04-28 12:58     ` George Cherian
2014-04-28 12:58       ` George Cherian
2014-04-28 12:58       ` George Cherian
2014-04-28  4:10 ` [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  7:10   ` Richard Cochran [this message]
2014-04-28  7:10     ` Richard Cochran
2014-04-28 12:55     ` George Cherian
2014-04-28 12:55       ` George Cherian
2014-04-28 12:55       ` George Cherian
2014-04-28 16:18       ` Richard Cochran
2014-04-28 16:18         ` Richard Cochran
2014-04-29  4:28         ` George Cherian
2014-04-29  4:28           ` George Cherian
2014-04-29  4:28           ` George Cherian
2014-04-29  4:28           ` George Cherian
2014-04-28  4:10 ` [PATCH 6/6] ARM: dts: am4372: Add clock names for cpsw and cpts George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian
2014-04-28  4:10   ` George Cherian

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