[PATCH 0/2] ARM: at91: remove phy fixup for sama5d3xek boards

[PATCH 0/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Boris BREZILLON]

Hello,

This patch removes a board specific hook for sama5d3xek boards from the
sama5d3 generic DT board file.

This hook (which register a phy fixup configuring board specific delays
in the ksz9021 ethernet phy) is now replaced by the appropriate DT
properties definitions in the sama5d3xcm.dtsi file.

Best Regards,

Boris

Boris BREZILLON (2):
  ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek
    boards
  ARM: at91: remove phy fixup for sama5d3xek boards

 arch/arm/boot/dts/sama5d3xcm.dtsi   | 16 ++++++++++++++++
 arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
 2 files changed, 16 insertions(+), 22 deletions(-)

-- 
1.8.3.2

[PATCH 0/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Boris BREZILLON]

Hello,

This patch removes a board specific hook for sama5d3xek boards from the
sama5d3 generic DT board file.

This hook (which register a phy fixup configuring board specific delays
in the ksz9021 ethernet phy) is now replaced by the appropriate DT
properties definitions in the sama5d3xcm.dtsi file.

Best Regards,

Boris

Boris BREZILLON (2):
  ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek
    boards
  ARM: at91: remove phy fixup for sama5d3xek boards

 arch/arm/boot/dts/sama5d3xcm.dtsi   | 16 ++++++++++++++++
 arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
 2 files changed, 16 insertions(+), 22 deletions(-)

-- 
1.8.3.2

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
interrupt (connected to pin PB25).

Define board specific delays to apply to RGMII signals.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b0b1331..2185ad8 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -34,6 +34,22 @@
 
 			macb0: ethernet@f0028000 {
 				phy-mode = "rgmii";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ethernet-phy@1 {
+					interrupt-parent = <&pioB>;
+					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+					reg = <1>;
+					txen-skew-ps = <800>;
+					txc-skew-ps = <12000>;
+					rxdv-skew-ps = <400>;
+					rxc-skew-ps = <12000>;
+					rxd0-skew-ps = <400>;
+					rxd1-skew-ps = <400>;
+					rxd2-skew-ps = <400>;
+					rxd3-skew-ps = <400>;
+				};
 			};
 
 			pmc: pmc@fffffc00 {
-- 
1.8.3.2

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
interrupt (connected to pin PB25).

Define board specific delays to apply to RGMII signals.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b0b1331..2185ad8 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -34,6 +34,22 @@
 
 			macb0: ethernet at f0028000 {
 				phy-mode = "rgmii";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ethernet-phy at 1 {
+					interrupt-parent = <&pioB>;
+					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+					reg = <1>;
+					txen-skew-ps = <800>;
+					txc-skew-ps = <12000>;
+					rxdv-skew-ps = <400>;
+					rxc-skew-ps = <12000>;
+					rxd0-skew-ps = <400>;
+					rxd1-skew-ps = <400>;
+					rxd2-skew-ps = <400>;
+					rxd3-skew-ps = <400>;
+				};
 			};
 
 			pmc: pmc at fffffc00 {
-- 
1.8.3.2

[PATCH 2/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Boris BREZILLON]

These board specific delays are now configured through micrel's specific
DT bindings (see Documentation/devicetree/bindings/net/micrel-ksz9021.txt).

Remove this phy fixup registration from sama5 DT machine file to keep it
as generic as possible.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index d6fe04b..8c5814f 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -35,30 +35,8 @@ static void __init sama5_dt_timer_init(void)
 	at91sam926x_pit_init();
 }
 
-static int ksz9021rn_phy_fixup(struct phy_device *phy)
-{
-	int value;
-
-	/* Set delay values */
-	value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-	value = 0xF2F4;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-	value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-	value = 0x2222;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-
-	return 0;
-}
-
 static void __init sama5_dt_device_init(void)
 {
-	if (of_machine_is_compatible("atmel,sama5d3xcm") &&
-	    IS_ENABLED(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-			ksz9021rn_phy_fixup);
-
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.8.3.2

[PATCH 2/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Boris BREZILLON]

These board specific delays are now configured through micrel's specific
DT bindings (see Documentation/devicetree/bindings/net/micrel-ksz9021.txt).

Remove this phy fixup registration from sama5 DT machine file to keep it
as generic as possible.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index d6fe04b..8c5814f 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -35,30 +35,8 @@ static void __init sama5_dt_timer_init(void)
 	at91sam926x_pit_init();
 }
 
-static int ksz9021rn_phy_fixup(struct phy_device *phy)
-{
-	int value;
-
-	/* Set delay values */
-	value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-	value = 0xF2F4;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-	value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-	value = 0x2222;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-
-	return 0;
-}
-
 static void __init sama5_dt_device_init(void)
 {
-	if (of_machine_is_compatible("atmel,sama5d3xcm") &&
-	    IS_ENABLED(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-			ksz9021rn_phy_fixup);
-
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.8.3.2

Re: [PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
> interrupt (connected to pin PB25).
>
> Define board specific delays to apply to RGMII signals.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> ---
>   arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index b0b1331..2185ad8 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -34,6 +34,22 @@
>
>   			macb0: ethernet@f0028000 {
>   				phy-mode = "rgmii";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ethernet-phy@1 {

The GMAC PHY address is 0x7 while not 0x1.

> +					interrupt-parent = <&pioB>;
> +					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> +					reg = <1>;

Nitpick: as usual, we will add "0x" prefix in reg property.

> +					txen-skew-ps = <800>;
> +					txc-skew-ps = <12000>;
> +					rxdv-skew-ps = <400>;
> +					rxc-skew-ps = <12000>;
> +					rxd0-skew-ps = <400>;
> +					rxd1-skew-ps = <400>;
> +					rxd2-skew-ps = <400>;
> +					rxd3-skew-ps = <400>;
> +				};
>   			};
>
>   			pmc: pmc@fffffc00 {
>

Best Regards,
Bo Shen

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
> interrupt (connected to pin PB25).
>
> Define board specific delays to apply to RGMII signals.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> ---
>   arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index b0b1331..2185ad8 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -34,6 +34,22 @@
>
>   			macb0: ethernet at f0028000 {
>   				phy-mode = "rgmii";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ethernet-phy at 1 {

The GMAC PHY address is 0x7 while not 0x1.

> +					interrupt-parent = <&pioB>;
> +					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> +					reg = <1>;

Nitpick: as usual, we will add "0x" prefix in reg property.

> +					txen-skew-ps = <800>;
> +					txc-skew-ps = <12000>;
> +					rxdv-skew-ps = <400>;
> +					rxc-skew-ps = <12000>;
> +					rxd0-skew-ps = <400>;
> +					rxd1-skew-ps = <400>;
> +					rxd2-skew-ps = <400>;
> +					rxd3-skew-ps = <400>;
> +				};
>   			};
>
>   			pmc: pmc at fffffc00 {
>

Best Regards,
Bo Shen

Re: [PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

Hello Bo,

On 25/06/2014 08:59, Bo Shen wrote:
> Hi Boris,
>
> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>> interrupt (connected to pin PB25).
>>
>> Define board specific delays to apply to RGMII signals.
>>
>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>> ---
>>   arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>> index b0b1331..2185ad8 100644
>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>> @@ -34,6 +34,22 @@
>>
>>               macb0: ethernet@f0028000 {
>>                   phy-mode = "rgmii";
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +
>> +                ethernet-phy@1 {
>
> The GMAC PHY address is 0x7 while not 0x1.

Are you sure of that ? I checked sama5d3x-ek schematics.
On these schematics PHYAD0 is connected to a pull up resistor and
PHYAD1/2 are connected to a pull down one.
This gives PHYAD[4:0] = 0b00001 = 0x1.
Is there some bootloader mechanisms that changes PHYAD[0-2] pin status
and reset the PHY ?

>
>> +                    interrupt-parent = <&pioB>;
>> +                    interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>> +                    reg = <1>;
>
> Nitpick: as usual, we will add "0x" prefix in reg property.

Sure, I'll fix that.

>
>> +                    txen-skew-ps = <800>;
>> +                    txc-skew-ps = <12000>;

Should be 3000 (0xf * 200 ps) not 12000.

>> +                    rxdv-skew-ps = <400>;
>> +                    rxc-skew-ps = <12000>;

Ditto.

Best Regards,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

Hello Bo,

On 25/06/2014 08:59, Bo Shen wrote:
> Hi Boris,
>
> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>> interrupt (connected to pin PB25).
>>
>> Define board specific delays to apply to RGMII signals.
>>
>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>> ---
>>   arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>> index b0b1331..2185ad8 100644
>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>> @@ -34,6 +34,22 @@
>>
>>               macb0: ethernet at f0028000 {
>>                   phy-mode = "rgmii";
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +
>> +                ethernet-phy at 1 {
>
> The GMAC PHY address is 0x7 while not 0x1.

Are you sure of that ? I checked sama5d3x-ek schematics.
On these schematics PHYAD0 is connected to a pull up resistor and
PHYAD1/2 are connected to a pull down one.
This gives PHYAD[4:0] = 0b00001 = 0x1.
Is there some bootloader mechanisms that changes PHYAD[0-2] pin status
and reset the PHY ?

>
>> +                    interrupt-parent = <&pioB>;
>> +                    interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>> +                    reg = <1>;
>
> Nitpick: as usual, we will add "0x" prefix in reg property.

Sure, I'll fix that.

>
>> +                    txen-skew-ps = <800>;
>> +                    txc-skew-ps = <12000>;

Should be 3000 (0xf * 200 ps) not 12000.

>> +                    rxdv-skew-ps = <400>;
>> +                    rxc-skew-ps = <12000>;

Ditto.

Best Regards,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 06/25/2014 03:30 PM, Boris BREZILLON wrote:
> Hello Bo,
>
> On 25/06/2014 08:59, Bo Shen wrote:
>> Hi Boris,
>>
>> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>>> interrupt (connected to pin PB25).
>>>
>>> Define board specific delays to apply to RGMII signals.
>>>
>>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>>> ---
>>>    arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>>    1 file changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> index b0b1331..2185ad8 100644
>>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> @@ -34,6 +34,22 @@
>>>
>>>                macb0: ethernet@f0028000 {
>>>                    phy-mode = "rgmii";
>>> +                #address-cells = <1>;
>>> +                #size-cells = <0>;
>>> +
>>> +                ethernet-phy@1 {
>>
>> The GMAC PHY address is 0x7 while not 0x1.
>
> Are you sure of that ? I checked sama5d3x-ek schematics.

On sama5d3x-ek schematic, it is EMAC PHY (ksz8051RNL, it's address is 
0x1), while not GMAC PHY. You should check the sama5d3x-CM schematic.

> On these schematics PHYAD0 is connected to a pull up resistor and
> PHYAD1/2 are connected to a pull down one.
> This gives PHYAD[4:0] = 0b00001 = 0x1.
> Is there some bootloader mechanisms that changes PHYAD[0-2] pin status
> and reset the PHY ?
>
>>
>>> +                    interrupt-parent = <&pioB>;
>>> +                    interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>>> +                    reg = <1>;
>>
>> Nitpick: as usual, we will add "0x" prefix in reg property.
>
> Sure, I'll fix that.
>
>>
>>> +                    txen-skew-ps = <800>;
>>> +                    txc-skew-ps = <12000>;
>
> Should be 3000 (0xf * 200 ps) not 12000.
>
>>> +                    rxdv-skew-ps = <400>;
>>> +                    rxc-skew-ps = <12000>;
>
> Ditto.
>
> Best Regards,
>
> Boris

Best Regards,
Bo Shen

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 06/25/2014 03:30 PM, Boris BREZILLON wrote:
> Hello Bo,
>
> On 25/06/2014 08:59, Bo Shen wrote:
>> Hi Boris,
>>
>> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>>> interrupt (connected to pin PB25).
>>>
>>> Define board specific delays to apply to RGMII signals.
>>>
>>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>>> ---
>>>    arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>>    1 file changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> index b0b1331..2185ad8 100644
>>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>> @@ -34,6 +34,22 @@
>>>
>>>                macb0: ethernet at f0028000 {
>>>                    phy-mode = "rgmii";
>>> +                #address-cells = <1>;
>>> +                #size-cells = <0>;
>>> +
>>> +                ethernet-phy at 1 {
>>
>> The GMAC PHY address is 0x7 while not 0x1.
>
> Are you sure of that ? I checked sama5d3x-ek schematics.

On sama5d3x-ek schematic, it is EMAC PHY (ksz8051RNL, it's address is 
0x1), while not GMAC PHY. You should check the sama5d3x-CM schematic.

> On these schematics PHYAD0 is connected to a pull up resistor and
> PHYAD1/2 are connected to a pull down one.
> This gives PHYAD[4:0] = 0b00001 = 0x1.
> Is there some bootloader mechanisms that changes PHYAD[0-2] pin status
> and reset the PHY ?
>
>>
>>> +                    interrupt-parent = <&pioB>;
>>> +                    interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>>> +                    reg = <1>;
>>
>> Nitpick: as usual, we will add "0x" prefix in reg property.
>
> Sure, I'll fix that.
>
>>
>>> +                    txen-skew-ps = <800>;
>>> +                    txc-skew-ps = <12000>;
>
> Should be 3000 (0xf * 200 ps) not 12000.
>
>>> +                    rxdv-skew-ps = <400>;
>>> +                    rxc-skew-ps = <12000>;
>
> Ditto.
>
> Best Regards,
>
> Boris

Best Regards,
Bo Shen

Re: [PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

On 25/06/2014 09:35, Bo Shen wrote:
> Hi Boris,
>
> On 06/25/2014 03:30 PM, Boris BREZILLON wrote:
>> Hello Bo,
>>
>> On 25/06/2014 08:59, Bo Shen wrote:
>>> Hi Boris,
>>>
>>> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>>>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>>>> interrupt (connected to pin PB25).
>>>>
>>>> Define board specific delays to apply to RGMII signals.
>>>>
>>>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>>>> ---
>>>> arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>>> 1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> index b0b1331..2185ad8 100644
>>>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> @@ -34,6 +34,22 @@
>>>>
>>>> macb0: ethernet@f0028000 {
>>>> phy-mode = "rgmii";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + ethernet-phy@1 {
>>>
>>> The GMAC PHY address is 0x7 while not 0x1.
>>
>> Are you sure of that ? I checked sama5d3x-ek schematics.
>
> On sama5d3x-ek schematic, it is EMAC PHY (ksz8051RNL, it's address is
> 0x1), while not GMAC PHY. You should check the sama5d3x-CM schematic.

I checked "Figure 5-16. RONETIX GEthernet ETH0" and "Figure 5-15. EMBEST
GEthernet ETH0" of this document "11180A–ATARM–30-Jan-13", which,
AFAICT, are RGMII phy schematics of CPU Modules.
I might have an old datasheet though.
If this is the case could you point out the new one ?

Thanks,

Boris



>
>> On these schematics PHYAD0 is connected to a pull up resistor and
>> PHYAD1/2 are connected to a pull down one.
>> This gives PHYAD[4:0] = 0b00001 = 0x1.
>> Is there some bootloader mechanisms that changes PHYAD[0-2] pin status
>> and reset the PHY ?
>>
>>>
>>>> + interrupt-parent = <&pioB>;
>>>> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>>>> + reg = <1>;
>>>
>>> Nitpick: as usual, we will add "0x" prefix in reg property.
>>
>> Sure, I'll fix that.
>>
>>>
>>>> + txen-skew-ps = <800>;
>>>> + txc-skew-ps = <12000>;
>>
>> Should be 3000 (0xf * 200 ps) not 12000.
>>
>>>> + rxdv-skew-ps = <400>;
>>>> + rxc-skew-ps = <12000>;
>>
>> Ditto.
>>
>> Best Regards,
>>
>> Boris
>
> Best Regards,
> Bo Shen
>

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

On 25/06/2014 09:35, Bo Shen wrote:
> Hi Boris,
>
> On 06/25/2014 03:30 PM, Boris BREZILLON wrote:
>> Hello Bo,
>>
>> On 25/06/2014 08:59, Bo Shen wrote:
>>> Hi Boris,
>>>
>>> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>>>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>>>> interrupt (connected to pin PB25).
>>>>
>>>> Define board specific delays to apply to RGMII signals.
>>>>
>>>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>>>> ---
>>>> arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>>> 1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> index b0b1331..2185ad8 100644
>>>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>> @@ -34,6 +34,22 @@
>>>>
>>>> macb0: ethernet at f0028000 {
>>>> phy-mode = "rgmii";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + ethernet-phy at 1 {
>>>
>>> The GMAC PHY address is 0x7 while not 0x1.
>>
>> Are you sure of that ? I checked sama5d3x-ek schematics.
>
> On sama5d3x-ek schematic, it is EMAC PHY (ksz8051RNL, it's address is
> 0x1), while not GMAC PHY. You should check the sama5d3x-CM schematic.

I checked "Figure 5-16. RONETIX GEthernet ETH0" and "Figure 5-15. EMBEST
GEthernet ETH0" of this document "11180A?ATARM?30-Jan-13", which,
AFAICT, are RGMII phy schematics of CPU Modules.
I might have an old datasheet though.
If this is the case could you point out the new one ?

Thanks,

Boris



>
>> On these schematics PHYAD0 is connected to a pull up resistor and
>> PHYAD1/2 are connected to a pull down one.
>> This gives PHYAD[4:0] = 0b00001 = 0x1.
>> Is there some bootloader mechanisms that changes PHYAD[0-2] pin status
>> and reset the PHY ?
>>
>>>
>>>> + interrupt-parent = <&pioB>;
>>>> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>>>> + reg = <1>;
>>>
>>> Nitpick: as usual, we will add "0x" prefix in reg property.
>>
>> Sure, I'll fix that.
>>
>>>
>>>> + txen-skew-ps = <800>;
>>>> + txc-skew-ps = <12000>;
>>
>> Should be 3000 (0xf * 200 ps) not 12000.
>>
>>>> + rxdv-skew-ps = <400>;
>>>> + rxc-skew-ps = <12000>;
>>
>> Ditto.
>>
>> Best Regards,
>>
>> Boris
>
> Best Regards,
> Bo Shen
>

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 06/25/2014 03:45 PM, Boris BREZILLON wrote:
>
> On 25/06/2014 09:35, Bo Shen wrote:
>> Hi Boris,
>>
>> On 06/25/2014 03:30 PM, Boris BREZILLON wrote:
>>> Hello Bo,
>>>
>>> On 25/06/2014 08:59, Bo Shen wrote:
>>>> Hi Boris,
>>>>
>>>> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>>>>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>>>>> interrupt (connected to pin PB25).
>>>>>
>>>>> Define board specific delays to apply to RGMII signals.
>>>>>
>>>>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>>>>> ---
>>>>> arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>>>> 1 file changed, 16 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> index b0b1331..2185ad8 100644
>>>>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> @@ -34,6 +34,22 @@
>>>>>
>>>>> macb0: ethernet@f0028000 {
>>>>> phy-mode = "rgmii";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + ethernet-phy@1 {
>>>>
>>>> The GMAC PHY address is 0x7 while not 0x1.
>>>
>>> Are you sure of that ? I checked sama5d3x-ek schematics.
>>
>> On sama5d3x-ek schematic, it is EMAC PHY (ksz8051RNL, it's address is
>> 0x1), while not GMAC PHY. You should check the sama5d3x-CM schematic.
>
> I checked "Figure 5-16. RONETIX GEthernet ETH0" and "Figure 5-15. EMBEST
> GEthernet ETH0" of this document "11180A–ATARM–30-Jan-13", which,
> AFAICT, are RGMII phy schematics of CPU Modules.
> I might have an old datasheet though.
> If this is the case could you point out the new one ?

After checking the schematic carefully, I found it will make the user 
confuse.

When the PHY do strap the status of configuration pins. The phy address 
pin are all pull up.

The PHYADD2(LED2) pin pull up to v3.3, the PHYADD1 (LED1) pin pull up to 
v3.3, the RX_CLK (PHADD0) pin pull up by default through sama5d3 pin.

So, they are all "1", then the PHY address is 7.

> Thanks,
>
> Boris

Best Regards,
Bo Shen

[PATCH 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 06/25/2014 03:45 PM, Boris BREZILLON wrote:
>
> On 25/06/2014 09:35, Bo Shen wrote:
>> Hi Boris,
>>
>> On 06/25/2014 03:30 PM, Boris BREZILLON wrote:
>>> Hello Bo,
>>>
>>> On 25/06/2014 08:59, Bo Shen wrote:
>>>> Hi Boris,
>>>>
>>>> On 06/25/2014 06:44 AM, Boris BREZILLON wrote:
>>>>> Add ethernet-phy node to specify phy address (on the MDIO bus) and phy
>>>>> interrupt (connected to pin PB25).
>>>>>
>>>>> Define board specific delays to apply to RGMII signals.
>>>>>
>>>>> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
>>>>> ---
>>>>> arch/arm/boot/dts/sama5d3xcm.dtsi | 16 ++++++++++++++++
>>>>> 1 file changed, 16 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> index b0b1331..2185ad8 100644
>>>>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>>>>> @@ -34,6 +34,22 @@
>>>>>
>>>>> macb0: ethernet at f0028000 {
>>>>> phy-mode = "rgmii";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + ethernet-phy at 1 {
>>>>
>>>> The GMAC PHY address is 0x7 while not 0x1.
>>>
>>> Are you sure of that ? I checked sama5d3x-ek schematics.
>>
>> On sama5d3x-ek schematic, it is EMAC PHY (ksz8051RNL, it's address is
>> 0x1), while not GMAC PHY. You should check the sama5d3x-CM schematic.
>
> I checked "Figure 5-16. RONETIX GEthernet ETH0" and "Figure 5-15. EMBEST
> GEthernet ETH0" of this document "11180A?ATARM?30-Jan-13", which,
> AFAICT, are RGMII phy schematics of CPU Modules.
> I might have an old datasheet though.
> If this is the case could you point out the new one ?

After checking the schematic carefully, I found it will make the user 
confuse.

When the PHY do strap the status of configuration pins. The phy address 
pin are all pull up.

The PHYADD2(LED2) pin pull up to v3.3, the PHYADD1 (LED1) pin pull up to 
v3.3, the RX_CLK (PHADD0) pin pull up by default through sama5d3 pin.

So, they are all "1", then the PHY address is 7.

> Thanks,
>
> Boris

Best Regards,
Bo Shen