All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Yan, Zheng" <zheng.z.yan@intel.com>
To: linux-kernel@vger.kernel.org
Cc: a.p.zijlstra@chello.nl, mingo@kernel.org, acme@infradead.org,
	eranian@google.com, andi@firstfloor.org, "Yan,
	Zheng" <zheng.z.yan@intel.com>
Subject: [PATCH V4 06/16] perf, core: always switch pmu specific data during context switch
Date: Mon, 30 Jun 2014 16:50:43 +0800	[thread overview]
Message-ID: <1404118253-19532-7-git-send-email-zheng.z.yan@intel.com> (raw)
In-Reply-To: <1404118253-19532-1-git-send-email-zheng.z.yan@intel.com>

If two tasks were both forked from the same parent task, Events in
their perf task contexts can be the same. Perf core may leave out
switching the perf event contexts.

Previous patch inroduces pmu specific data. The data is for saving
the LBR stack, it is task specific. So we need to switch the data
even when context switch is optimized out.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
---
 kernel/events/core.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/kernel/events/core.c b/kernel/events/core.c
index 9f35d64..a856813 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -2339,6 +2339,7 @@ static void perf_event_context_sched_out(struct task_struct *task, int ctxn,
 		raw_spin_lock(&ctx->lock);
 		raw_spin_lock_nested(&next_ctx->lock, SINGLE_DEPTH_NESTING);
 		if (context_equiv(ctx, next_ctx)) {
+			void *ctx_data;
 			/*
 			 * XXX do we need a memory barrier of sorts
 			 * wrt to rcu_dereference() of perf_event_ctxp
@@ -2347,6 +2348,11 @@ static void perf_event_context_sched_out(struct task_struct *task, int ctxn,
 			next->perf_event_ctxp[ctxn] = ctx;
 			ctx->task = next;
 			next_ctx->task = task;
+
+			ctx_data = next_ctx->task_ctx_data;
+			next_ctx->task_ctx_data = ctx->task_ctx_data;
+			ctx->task_ctx_data = ctx_data;
+
 			do_switch = 0;
 
 			perf_event_sync_stat(ctx, next_ctx);
-- 
1.9.0


  parent reply	other threads:[~2014-06-30  8:51 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-30  8:50 [PATCH V4 00/16] perf, x86: Haswell LBR call stack support Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 01/16] perf, x86: Reduce lbr_sel_map size Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 02/16] perf, core: introduce pmu context switch callback Yan, Zheng
2014-07-02  8:48   ` Peter Zijlstra
2014-07-02 10:12   ` Peter Zijlstra
2014-07-03  5:47     ` Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 03/16] perf, x86: use context switch callback to flush LBR stack Yan, Zheng
2014-07-02  9:06   ` Peter Zijlstra
2014-07-03  5:44     ` Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 04/16] perf, x86: Basic Haswell LBR call stack support Yan, Zheng
2014-07-02 10:14   ` Peter Zijlstra
2014-06-30  8:50 ` [PATCH V4 05/16] perf, core: pmu specific data for perf task context Yan, Zheng
2014-07-02 10:18   ` Peter Zijlstra
2014-06-30  8:50 ` Yan, Zheng [this message]
2014-07-02 10:19   ` [PATCH V4 06/16] perf, core: always switch pmu specific data during context switch Peter Zijlstra
2014-06-30  8:50 ` [PATCH V4 07/16] perf, x86: track number of events that use LBR callstack Yan, Zheng
2014-07-02 10:21   ` Peter Zijlstra
2014-07-03  5:59     ` Yan, Zheng
2014-07-02 10:25   ` Peter Zijlstra
2014-06-30  8:50 ` [PATCH V4 08/16] perf, x86: allocate space for storing LBR stack Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 09/16] perf, x86: Save/resotre LBR stack during context switch Yan, Zheng
2014-07-02 10:49   ` Peter Zijlstra
2014-06-30  8:50 ` [PATCH V4 10/16] perf, core: simplify need branch stack check Yan, Zheng
2014-07-02 10:57   ` Peter Zijlstra
2014-07-02 11:08     ` Stephane Eranian
2014-07-02 12:27       ` Peter Zijlstra
2014-07-02 13:00         ` Stephane Eranian
2014-07-02 13:28           ` Peter Zijlstra
2014-06-30  8:50 ` [PATCH V4 11/16] perf, core: Pass perf_sample_data to perf_callchain() Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 12/16] perf, x86: use LBR call stack to get user callchain Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 13/16] perf, x86: re-organize code that implicitly enables LBR/PEBS Yan, Zheng
2014-06-30  8:50 ` [PATCH V4 14/16] perf, x86: enable LBR callstack when recording callchain Yan, Zheng
2014-06-30 14:45   ` Andi Kleen
2014-06-30  8:50 ` [PATCH V4 15/16] perf, x86: disable FREEZE_LBRS_ON_PMI when LBR operates in callstack mode Yan, Zheng
2014-07-02 11:13   ` Peter Zijlstra
2014-06-30  8:50 ` [PATCH V4 16/16] perf, x86: Discard zero length call entries in LBR call stack Yan, Zheng
  -- strict thread matches above, loose matches on Subject: below --
2014-03-17  5:57 [PATCH v4 00/16] perf, x86: Haswell LBR call stack support Yan, Zheng
2014-03-17  5:57 ` [PATCH v4 06/16] perf, core: always switch pmu specific data during context switch Yan, Zheng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1404118253-19532-7-git-send-email-zheng.z.yan@intel.com \
    --to=zheng.z.yan@intel.com \
    --cc=a.p.zijlstra@chello.nl \
    --cc=acme@infradead.org \
    --cc=andi@firstfloor.org \
    --cc=eranian@google.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.