[PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and pre-emph
levels as the values may differ in other scenarios like low vswing of eDP 1.4
where the values are different.
Updated in all the drivers as well

v2: Keeping the old defines in first patch and removing them in last patch. Used
cocci semantic patch to replace the defines.

Sonika Jindal (7):
  drm: Renaming DP training vswing pre emph defines
  drm/i915: Renaming DP training vswing pre emph defines
  drm/exynos: Renaming DP training vswing pre emph defines
  drm/gma500: Renaming DP training vswing pre emph defines
  drm/radeon: Renaming DP training vswing pre emph defines
  drm/tegra: Renaming DP training vswing pre emph defines
  drm: Remove old defines for vswing and pre-emph values

 drivers/gpu/drm/exynos/exynos_dp_core.c |    4 +-
 drivers/gpu/drm/gma500/cdv_intel_dp.c   |    4 +-
 drivers/gpu/drm/gma500/intel_bios.c     |   16 +--
 drivers/gpu/drm/i915/intel_bios.c       |   16 +--
 drivers/gpu/drm/i915/intel_dp.c         |  194 +++++++++++++++----------------
 drivers/gpu/drm/radeon/atombios_dp.c    |    4 +-
 drivers/gpu/drm/tegra/dpaux.c           |    4 +-
 include/drm/drm_dp_helper.h             |   16 +--
 8 files changed, 129 insertions(+), 129 deletions(-)

-- 
1.7.10.4

[PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Adding new defines, older one will be removed in the last patch in the series.
This is to rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...
Cc: dri-devel@lists.freedesktop.org

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 include/drm/drm_dp_helper.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index a21568b..3840a05 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -191,15 +191,23 @@
 # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
 # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
 # define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
 
 # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
 # define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
 # define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
 # define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
 # define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
 
 # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
-- 
1.7.10.4

Re: [Intel-gfx] [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Damien Lespiau]

On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Adding new defines, older one will be removed in the last patch in the series.
> This is to rename the defines to have levels instead of values for vswing and
> pre-emph levels as the values may differ in other scenarios like low vswing of
> eDP1.4 where the values are different.
> 
> Done using following cocci patch for each define:
> @@
> @@
> 
>  # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> 
> ...
> Cc: dri-devel@lists.freedesktop.org
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>


Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  include/drm/drm_dp_helper.h |    8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index a21568b..3840a05 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -191,15 +191,23 @@
>  # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
>  # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
>  # define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
> +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
>  # define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
> +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
>  # define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
> +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
>  # define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)
> +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
>  
>  # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
>  # define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
>  # define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
>  # define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
>  # define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
>  
>  # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
>  # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 1021 bytes --]

On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Adding new defines, older one will be removed in the last patch in the series.
> This is to rename the defines to have levels instead of values for vswing and
> pre-emph levels as the values may differ in other scenarios like low vswing of
> eDP1.4 where the values are different.
> 
> Done using following cocci patch for each define:
> @@
> @@
> 
>  # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

Could this perhaps be simply:

	#define DP_TRAIN_VOLTAGE_SWING(x) ((x) << 0)

As it is, there's no information about the value within the symbolic
name anyway, so _LEVEL_* really isn't that useful and keeping several
macros for each value seems isn't either.

An alternative would be to provide a second set of defines for eDP 1.4
where the name implies the meaning and then use them as appropriate.

Thierry

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Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Jindal, Sonika]

On 8/26/2014 4:58 PM, Thierry Reding wrote:
> On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jindal@intel.com wrote:
>> From: Sonika Jindal <sonika.jindal@intel.com>
>>
>> Adding new defines, older one will be removed in the last patch in the series.
>> This is to rename the defines to have levels instead of values for vswing and
>> pre-emph levels as the values may differ in other scenarios like low vswing of
>> eDP1.4 where the values are different.
>>
>> Done using following cocci patch for each define:
>> @@
>> @@
>>
>>   # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
>> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
>
> Could this perhaps be simply:
>
> 	#define DP_TRAIN_VOLTAGE_SWING(x) ((x) << 0)
>
> As it is, there's no information about the value within the symbolic
> name anyway, so _LEVEL_* really isn't that useful and keeping several
> macros for each value seems isn't either.
>
I feel _LEVEL_* makes it more readable and since there are only 4 values 
possible, it is ok to have 4 different macros for readability purpose. 
What do you think?
> An alternative would be to provide a second set of defines for eDP 1.4
> where the name implies the meaning and then use them as appropriate.
>
> Thierry
>

Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Jingoo Han]

On Wednesday, August 27, 2014 1:31 PM, Jindal, Sonika wrote:
> On 8/26/2014 4:58 PM, Thierry Reding wrote:
> > On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jindal@intel.com wrote:
> >> From: Sonika Jindal <sonika.jindal@intel.com>
> >>
> >> Adding new defines, older one will be removed in the last patch in the series.
> >> This is to rename the defines to have levels instead of values for vswing and
> >> pre-emph levels as the values may differ in other scenarios like low vswing of
> >> eDP1.4 where the values are different.
> >>
> >> Done using following cocci patch for each define:
> >> @@
> >> @@
> >>
> >>   # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> >> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> >
> > Could this perhaps be simply:
> >
> > 	#define DP_TRAIN_VOLTAGE_SWING(x) ((x) << 0)
> >
> > As it is, there's no information about the value within the symbolic
> > name anyway, so _LEVEL_* really isn't that useful and keeping several
> > macros for each value seems isn't either.
> >
> I feel _LEVEL_* makes it more readable and since there are only 4 values
> possible, it is ok to have 4 different macros for readability purpose.
> What do you think?

(+cc Damien Lespiau)

Personally, I also think that LEVEL_* looks more readable. 

Best regards,
Jingoo Han

> > An alternative would be to provide a second set of defines for eDP 1.4
> > where the name implies the meaning and then use them as appropriate.
> >
> > Thierry
> >
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Damien Lespiau]

On Tue, Aug 26, 2014 at 01:28:19PM +0200, Thierry Reding wrote:
> On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jindal@intel.com wrote:
> > From: Sonika Jindal <sonika.jindal@intel.com>
> > 
> > Adding new defines, older one will be removed in the last patch in the series.
> > This is to rename the defines to have levels instead of values for vswing and
> > pre-emph levels as the values may differ in other scenarios like low vswing of
> > eDP1.4 where the values are different.
> > 
> > Done using following cocci patch for each define:
> > @@
> > @@
> > 
> >  # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> > + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> 
> Could this perhaps be simply:
> 
> 	#define DP_TRAIN_VOLTAGE_SWING(x) ((x) << 0)
> 
> As it is, there's no information about the value within the symbolic
> name anyway, so _LEVEL_* really isn't that useful and keeping several
> macros for each value seems isn't either.

The _LEVEL_ part is quite important IMHO, that's what changes between those
different defines, controlling a level shifter, somewhere.

So we're left with

  #define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

Vs

  #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x)     ((x) << 0)

The second variant doesn't really bring much more clarity? Can we just
go with the first?

> An alternative would be to provide a second set of defines for eDP 1.4
> where the name implies the meaning and then use them as appropriate.

We went through the idea as well and:

I actually think the nominal voltage swing and pre-emph values are quite
misleading. The hw is free to implement a wildly different set of voltage
swing/pre-emph values.

eDP 1.4 changes those nominal values as described in the cover letter,
but there again, the actual hw implementation can choose fairly
different values than the nominal ones.

Also, the DP 1.2 spec documents this field as (see address 103h):

TRAINING_LANE0_SET : Link Training Control_Lane0
  Bits 1:0 = VOLTAGE SWING SET
    00 –Voltage swing level 0
    01 –Voltage swing level 1
    10 –Voltage swing level 2
    11 –Voltage swing level 3

So, in that sense, we're closer to the latest spec with those LEVEL_X
defines.

HTH,

-- 
Damien
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Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Damien Lespiau]

On Wed, Aug 27, 2014 at 08:47:54AM +0100, Damien Lespiau wrote:
> > An alternative would be to provide a second set of defines for eDP 1.4
> > where the name implies the meaning and then use them as appropriate.
> 
> We went through the idea as well and:
> 
> I actually think the nominal voltage swing and pre-emph values are quite
> misleading. The hw is free to implement a wildly different set of voltage
> swing/pre-emph values.
> 
> eDP 1.4 changes those nominal values as described in the cover letter,
> but there again, the actual hw implementation can choose fairly
> different values than the nominal ones.
> 
> Also, the DP 1.2 spec documents this field as (see address 103h):
> 
> TRAINING_LANE0_SET : Link Training Control_Lane0
>   Bits 1:0 = VOLTAGE SWING SET
>     00 –Voltage swing level 0
>     01 –Voltage swing level 1
>     10 –Voltage swing level 2
>     11 –Voltage swing level 3
> 
> So, in that sense, we're closer to the latest spec with those LEVEL_X
> defines.

I forgot to mention here that if we have separate defines for eDP 1.4,
then we lose the possibility to share training code with big DP and eDP
1.3, not something desirable.

-- 
Damien
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Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Thierry Reding]

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On Wed, Aug 27, 2014 at 08:51:35AM +0100, Damien Lespiau wrote:
> On Wed, Aug 27, 2014 at 08:47:54AM +0100, Damien Lespiau wrote:
> > > An alternative would be to provide a second set of defines for eDP 1.4
> > > where the name implies the meaning and then use them as appropriate.
> > 
> > We went through the idea as well and:
> > 
> > I actually think the nominal voltage swing and pre-emph values are quite
> > misleading. The hw is free to implement a wildly different set of voltage
> > swing/pre-emph values.
> > 
> > eDP 1.4 changes those nominal values as described in the cover letter,
> > but there again, the actual hw implementation can choose fairly
> > different values than the nominal ones.
> > 
> > Also, the DP 1.2 spec documents this field as (see address 103h):
> > 
> > TRAINING_LANE0_SET : Link Training Control_Lane0
> >   Bits 1:0 = VOLTAGE SWING SET
> >     00 –Voltage swing level 0
> >     01 –Voltage swing level 1
> >     10 –Voltage swing level 2
> >     11 –Voltage swing level 3
> > 
> > So, in that sense, we're closer to the latest spec with those LEVEL_X
> > defines.
> 
> I forgot to mention here that if we have separate defines for eDP 1.4,
> then we lose the possibility to share training code with big DP and eDP
> 1.3, not something desirable.

Yeah, I'd like to see the training sequences extracted into common
helpers.

Thierry

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Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 1725 bytes --]

On Wed, Aug 27, 2014 at 08:47:54AM +0100, Damien Lespiau wrote:
> On Tue, Aug 26, 2014 at 01:28:19PM +0200, Thierry Reding wrote:
> > On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jindal@intel.com wrote:
> > > From: Sonika Jindal <sonika.jindal@intel.com>
> > > 
> > > Adding new defines, older one will be removed in the last patch in the series.
> > > This is to rename the defines to have levels instead of values for vswing and
> > > pre-emph levels as the values may differ in other scenarios like low vswing of
> > > eDP1.4 where the values are different.
> > > 
> > > Done using following cocci patch for each define:
> > > @@
> > > @@
> > > 
> > >  # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> > > + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> > 
> > Could this perhaps be simply:
> > 
> > 	#define DP_TRAIN_VOLTAGE_SWING(x) ((x) << 0)
> > 
> > As it is, there's no information about the value within the symbolic
> > name anyway, so _LEVEL_* really isn't that useful and keeping several
> > macros for each value seems isn't either.
> 
> The _LEVEL_ part is quite important IMHO, that's what changes between those
> different defines, controlling a level shifter, somewhere.
> 
> So we're left with
> 
>   #define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> 
> Vs
> 
>   #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x)     ((x) << 0)
> 
> The second variant doesn't really bring much more clarity? Can we just
> go with the first?

I think the parameterized version is more convenient, especially if you
want to use that during training sequences and iterate over the levels.

But I don't feel too strongly about it, so either way is fine with me.

Thierry

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Re: [PATCH 1/7] drm: Renaming DP training vswing pre emph defines

[Damien Lespiau]

On Wed, Aug 27, 2014 at 03:11:08PM +0200, Thierry Reding wrote:
> > So we're left with
> > 
> >   #define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> > 
> > Vs
> > 
> >   #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x)     ((x) << 0)
> > 
> > The second variant doesn't really bring much more clarity? Can we just
> > go with the first?
> 
> I think the parameterized version is more convenient, especially if you
> want to use that during training sequences and iterate over the levels.

That's a fair point, but today's code manages to do without that nicety.

I think these kind of refinements could go in series with code actually
using them on top.

> But I don't feel too strongly about it, so either way is fine with me.

Thanks, taking some of your time to provide feedback is always
appreciated!

-- 
Damien

[PATCH 2/7] drm/i915: Renaming DP training vswing pre emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c |   16 +--
 drivers/gpu/drm/i915/intel_dp.c   |  194 ++++++++++++++++++-------------------
 2 files changed, 105 insertions(+), 105 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 031c565..e871f68 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -627,16 +627,16 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
 
 	switch (edp_link_params->preemphasis) {
 	case EDP_PREEMPHASIS_NONE:
-		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
+		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
 		break;
 	case EDP_PREEMPHASIS_3_5dB:
-		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
+		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
 		break;
 	case EDP_PREEMPHASIS_6dB:
-		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
+		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
 		break;
 	case EDP_PREEMPHASIS_9_5dB:
-		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
+		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
 		break;
 	default:
 		DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
@@ -646,16 +646,16 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
 
 	switch (edp_link_params->vswing) {
 	case EDP_VSWING_0_4V:
-		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
+		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 		break;
 	case EDP_VSWING_0_6V:
-		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
+		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
 		break;
 	case EDP_VSWING_0_8V:
-		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
+		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 		break;
 	case EDP_VSWING_1_2V:
-		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
+		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		break;
 	default:
 		DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 34e3c47..01f264c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2381,13 +2381,13 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 	enum port port = dp_to_dig_port(intel_dp)->port;
 
 	if (IS_VALLEYVIEW(dev))
-		return DP_TRAIN_VOLTAGE_SWING_1200;
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_GEN7(dev) && port == PORT_A)
-		return DP_TRAIN_VOLTAGE_SWING_800;
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 	else if (HAS_PCH_CPT(dev) && port != PORT_A)
-		return DP_TRAIN_VOLTAGE_SWING_1200;
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else
-		return DP_TRAIN_VOLTAGE_SWING_800;
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 }
 
 static uint8_t
@@ -2398,49 +2398,49 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
-			return DP_TRAIN_PRE_EMPHASIS_9_5;
-		case DP_TRAIN_VOLTAGE_SWING_600:
-			return DP_TRAIN_PRE_EMPHASIS_6;
-		case DP_TRAIN_VOLTAGE_SWING_800:
-			return DP_TRAIN_PRE_EMPHASIS_3_5;
-		case DP_TRAIN_VOLTAGE_SWING_1200:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+			return DP_TRAIN_PRE_EMPH_LEVEL_3;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+			return DP_TRAIN_PRE_EMPH_LEVEL_2;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+			return DP_TRAIN_PRE_EMPH_LEVEL_1;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 		default:
-			return DP_TRAIN_PRE_EMPHASIS_0;
+			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
 	} else if (IS_VALLEYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
-			return DP_TRAIN_PRE_EMPHASIS_9_5;
-		case DP_TRAIN_VOLTAGE_SWING_600:
-			return DP_TRAIN_PRE_EMPHASIS_6;
-		case DP_TRAIN_VOLTAGE_SWING_800:
-			return DP_TRAIN_PRE_EMPHASIS_3_5;
-		case DP_TRAIN_VOLTAGE_SWING_1200:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+			return DP_TRAIN_PRE_EMPH_LEVEL_3;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+			return DP_TRAIN_PRE_EMPH_LEVEL_2;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+			return DP_TRAIN_PRE_EMPH_LEVEL_1;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 		default:
-			return DP_TRAIN_PRE_EMPHASIS_0;
+			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
 	} else if (IS_GEN7(dev) && port == PORT_A) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
-			return DP_TRAIN_PRE_EMPHASIS_6;
-		case DP_TRAIN_VOLTAGE_SWING_600:
-		case DP_TRAIN_VOLTAGE_SWING_800:
-			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+			return DP_TRAIN_PRE_EMPH_LEVEL_2;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+			return DP_TRAIN_PRE_EMPH_LEVEL_1;
 		default:
-			return DP_TRAIN_PRE_EMPHASIS_0;
+			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
 	} else {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
-			return DP_TRAIN_PRE_EMPHASIS_6;
-		case DP_TRAIN_VOLTAGE_SWING_600:
-			return DP_TRAIN_PRE_EMPHASIS_6;
-		case DP_TRAIN_VOLTAGE_SWING_800:
-			return DP_TRAIN_PRE_EMPHASIS_3_5;
-		case DP_TRAIN_VOLTAGE_SWING_1200:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+			return DP_TRAIN_PRE_EMPH_LEVEL_2;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+			return DP_TRAIN_PRE_EMPH_LEVEL_2;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+			return DP_TRAIN_PRE_EMPH_LEVEL_1;
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 		default:
-			return DP_TRAIN_PRE_EMPHASIS_0;
+			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
 	}
 }
@@ -2459,22 +2459,22 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
 	int pipe = intel_crtc->pipe;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
-	case DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_PRE_EMPH_LEVEL_0:
 		preemph_reg_value = 0x0004000;
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			demph_reg_value = 0x2B405555;
 			uniqtranscale_reg_value = 0x552AB83A;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 			demph_reg_value = 0x2B404040;
 			uniqtranscale_reg_value = 0x5548B83A;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_800:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 			demph_reg_value = 0x2B245555;
 			uniqtranscale_reg_value = 0x5560B83A;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_1200:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 			demph_reg_value = 0x2B405555;
 			uniqtranscale_reg_value = 0x5598DA3A;
 			break;
@@ -2482,18 +2482,18 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
 			return 0;
 		}
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_PRE_EMPH_LEVEL_1:
 		preemph_reg_value = 0x0002000;
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			demph_reg_value = 0x2B404040;
 			uniqtranscale_reg_value = 0x5552B83A;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 			demph_reg_value = 0x2B404848;
 			uniqtranscale_reg_value = 0x5580B83A;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_800:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 			demph_reg_value = 0x2B404040;
 			uniqtranscale_reg_value = 0x55ADDA3A;
 			break;
@@ -2501,14 +2501,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
 			return 0;
 		}
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_PRE_EMPH_LEVEL_2:
 		preemph_reg_value = 0x0000000;
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			demph_reg_value = 0x2B305555;
 			uniqtranscale_reg_value = 0x5570B83A;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 			demph_reg_value = 0x2B2B4040;
 			uniqtranscale_reg_value = 0x55ADDA3A;
 			break;
@@ -2516,10 +2516,10 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
 			return 0;
 		}
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_9_5:
+	case DP_TRAIN_PRE_EMPH_LEVEL_3:
 		preemph_reg_value = 0x0006000;
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			demph_reg_value = 0x1B405555;
 			uniqtranscale_reg_value = 0x55ADDA3A;
 			break;
@@ -2558,21 +2558,21 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	int i;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
-	case DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_PRE_EMPH_LEVEL_0:
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			deemph_reg_value = 128;
 			margin_reg_value = 52;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 			deemph_reg_value = 128;
 			margin_reg_value = 77;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_800:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 			deemph_reg_value = 128;
 			margin_reg_value = 102;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_1200:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 			deemph_reg_value = 128;
 			margin_reg_value = 154;
 			/* FIXME extra to set for 1200 */
@@ -2581,17 +2581,17 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 			return 0;
 		}
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_PRE_EMPH_LEVEL_1:
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			deemph_reg_value = 85;
 			margin_reg_value = 78;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 			deemph_reg_value = 85;
 			margin_reg_value = 116;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_800:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 			deemph_reg_value = 85;
 			margin_reg_value = 154;
 			break;
@@ -2599,13 +2599,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 			return 0;
 		}
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_PRE_EMPH_LEVEL_2:
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			deemph_reg_value = 64;
 			margin_reg_value = 104;
 			break;
-		case DP_TRAIN_VOLTAGE_SWING_600:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 			deemph_reg_value = 64;
 			margin_reg_value = 154;
 			break;
@@ -2613,9 +2613,9 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 			return 0;
 		}
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_9_5:
+	case DP_TRAIN_PRE_EMPH_LEVEL_3:
 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			deemph_reg_value = 43;
 			margin_reg_value = 154;
 			break;
@@ -2662,9 +2662,9 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	}
 
 	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
-			== DP_TRAIN_PRE_EMPHASIS_0) &&
+			== DP_TRAIN_PRE_EMPH_LEVEL_0) &&
 		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
-			== DP_TRAIN_VOLTAGE_SWING_1200)) {
+			== DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
 
 		/*
 		 * The document said it needs to set bit 27 for ch0 and bit 26
@@ -2743,32 +2743,32 @@ intel_gen4_signal_levels(uint8_t train_set)
 	uint32_t	signal_levels = 0;
 
 	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
-	case DP_TRAIN_VOLTAGE_SWING_400:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 	default:
 		signal_levels |= DP_VOLTAGE_0_4;
 		break;
-	case DP_TRAIN_VOLTAGE_SWING_600:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
 		signal_levels |= DP_VOLTAGE_0_6;
 		break;
-	case DP_TRAIN_VOLTAGE_SWING_800:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
 		signal_levels |= DP_VOLTAGE_0_8;
 		break;
-	case DP_TRAIN_VOLTAGE_SWING_1200:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 		signal_levels |= DP_VOLTAGE_1_2;
 		break;
 	}
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
-	case DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_PRE_EMPH_LEVEL_0:
 	default:
 		signal_levels |= DP_PRE_EMPHASIS_0;
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_PRE_EMPH_LEVEL_1:
 		signal_levels |= DP_PRE_EMPHASIS_3_5;
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_PRE_EMPH_LEVEL_2:
 		signal_levels |= DP_PRE_EMPHASIS_6;
 		break;
-	case DP_TRAIN_PRE_EMPHASIS_9_5:
+	case DP_TRAIN_PRE_EMPH_LEVEL_3:
 		signal_levels |= DP_PRE_EMPHASIS_9_5;
 		break;
 	}
@@ -2782,19 +2782,19 @@ intel_gen6_edp_signal_levels(uint8_t train_set)
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
 	switch (signal_levels) {
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
 		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
-	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
-	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
-	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
 	default:
 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
@@ -2810,21 +2810,21 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
 	switch (signal_levels) {
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return EDP_LINK_TRAIN_400MV_0DB_IVB;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
 		return EDP_LINK_TRAIN_400MV_6DB_IVB;
 
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return EDP_LINK_TRAIN_600MV_0DB_IVB;
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
 
-	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return EDP_LINK_TRAIN_800MV_0DB_IVB;
-	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
 
 	default:
@@ -2841,25 +2841,25 @@ intel_hsw_signal_levels(uint8_t train_set)
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
 	switch (signal_levels) {
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return DDI_BUF_EMP_400MV_0DB_HSW;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return DDI_BUF_EMP_400MV_3_5DB_HSW;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
 		return DDI_BUF_EMP_400MV_6DB_HSW;
-	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
 		return DDI_BUF_EMP_400MV_9_5DB_HSW;
 
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return DDI_BUF_EMP_600MV_0DB_HSW;
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return DDI_BUF_EMP_600MV_3_5DB_HSW;
-	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
 		return DDI_BUF_EMP_600MV_6DB_HSW;
 
-	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
 		return DDI_BUF_EMP_800MV_0DB_HSW;
-	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
 		return DDI_BUF_EMP_800MV_3_5DB_HSW;
 	default:
 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
-- 
1.7.10.4

Re: [PATCH 2/7] drm/i915: Renaming DP training vswing pre emph defines

[Damien Lespiau]

On Fri, Aug 08, 2014 at 04:23:41PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Rename the defines to have levels instead of values for vswing and
> pre-emph levels as the values may differ in other scenarios like low vswing of
> eDP1.4 where the values are different.
> 
> Done using following cocci patch for each define:
> @@
> @@
> 
>  # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> 
> ...
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_bios.c |   16 +--
>  drivers/gpu/drm/i915/intel_dp.c   |  194 ++++++++++++++++++-------------------
>  2 files changed, 105 insertions(+), 105 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 031c565..e871f68 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -627,16 +627,16 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
>  
>  	switch (edp_link_params->preemphasis) {
>  	case EDP_PREEMPHASIS_NONE:
> -		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
> +		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		break;
>  	case EDP_PREEMPHASIS_3_5dB:
> -		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
> +		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
>  		break;
>  	case EDP_PREEMPHASIS_6dB:
> -		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
> +		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
>  		break;
>  	case EDP_PREEMPHASIS_9_5dB:
> -		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
> +		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
>  		break;
>  	default:
>  		DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
> @@ -646,16 +646,16 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
>  
>  	switch (edp_link_params->vswing) {
>  	case EDP_VSWING_0_4V:
> -		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
> +		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>  		break;
>  	case EDP_VSWING_0_6V:
> -		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
> +		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
>  		break;
>  	case EDP_VSWING_0_8V:
> -		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
> +		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  		break;
>  	case EDP_VSWING_1_2V:
> -		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
> +		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  		break;
>  	default:
>  		DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 34e3c47..01f264c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2381,13 +2381,13 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  	enum port port = dp_to_dig_port(intel_dp)->port;
>  
>  	if (IS_VALLEYVIEW(dev))
> -		return DP_TRAIN_VOLTAGE_SWING_1200;
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_GEN7(dev) && port == PORT_A)
> -		return DP_TRAIN_VOLTAGE_SWING_800;
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  	else if (HAS_PCH_CPT(dev) && port != PORT_A)
> -		return DP_TRAIN_VOLTAGE_SWING_1200;
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else
> -		return DP_TRAIN_VOLTAGE_SWING_800;
> +		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  }
>  
>  static uint8_t
> @@ -2398,49 +2398,49 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> -			return DP_TRAIN_PRE_EMPHASIS_9_5;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> -			return DP_TRAIN_PRE_EMPHASIS_6;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> -			return DP_TRAIN_PRE_EMPHASIS_3_5;
> -		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  		default:
> -			return DP_TRAIN_PRE_EMPHASIS_0;
> +			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> -			return DP_TRAIN_PRE_EMPHASIS_9_5;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> -			return DP_TRAIN_PRE_EMPHASIS_6;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> -			return DP_TRAIN_PRE_EMPHASIS_3_5;
> -		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  		default:
> -			return DP_TRAIN_PRE_EMPHASIS_0;
> +			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
>  	} else if (IS_GEN7(dev) && port == PORT_A) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> -			return DP_TRAIN_PRE_EMPHASIS_6;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> -			return DP_TRAIN_PRE_EMPHASIS_3_5;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_1;
>  		default:
> -			return DP_TRAIN_PRE_EMPHASIS_0;
> +			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
>  	} else {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> -			return DP_TRAIN_PRE_EMPHASIS_6;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> -			return DP_TRAIN_PRE_EMPHASIS_6;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> -			return DP_TRAIN_PRE_EMPHASIS_3_5;
> -		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> +			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  		default:
> -			return DP_TRAIN_PRE_EMPHASIS_0;
> +			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
>  	}
>  }
> @@ -2459,22 +2459,22 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
>  	int pipe = intel_crtc->pipe;
>  
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> -	case DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		preemph_reg_value = 0x0004000;
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			demph_reg_value = 0x2B405555;
>  			uniqtranscale_reg_value = 0x552AB83A;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  			demph_reg_value = 0x2B404040;
>  			uniqtranscale_reg_value = 0x5548B83A;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
>  			demph_reg_value = 0x2B245555;
>  			uniqtranscale_reg_value = 0x5560B83A;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  			demph_reg_value = 0x2B405555;
>  			uniqtranscale_reg_value = 0x5598DA3A;
>  			break;
> @@ -2482,18 +2482,18 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
>  			return 0;
>  		}
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		preemph_reg_value = 0x0002000;
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			demph_reg_value = 0x2B404040;
>  			uniqtranscale_reg_value = 0x5552B83A;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  			demph_reg_value = 0x2B404848;
>  			uniqtranscale_reg_value = 0x5580B83A;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
>  			demph_reg_value = 0x2B404040;
>  			uniqtranscale_reg_value = 0x55ADDA3A;
>  			break;
> @@ -2501,14 +2501,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
>  			return 0;
>  		}
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		preemph_reg_value = 0x0000000;
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			demph_reg_value = 0x2B305555;
>  			uniqtranscale_reg_value = 0x5570B83A;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  			demph_reg_value = 0x2B2B4040;
>  			uniqtranscale_reg_value = 0x55ADDA3A;
>  			break;
> @@ -2516,10 +2516,10 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
>  			return 0;
>  		}
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_9_5:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_3:
>  		preemph_reg_value = 0x0006000;
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			demph_reg_value = 0x1B405555;
>  			uniqtranscale_reg_value = 0x55ADDA3A;
>  			break;
> @@ -2558,21 +2558,21 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	int i;
>  
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> -	case DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			deemph_reg_value = 128;
>  			margin_reg_value = 52;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  			deemph_reg_value = 128;
>  			margin_reg_value = 77;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
>  			deemph_reg_value = 128;
>  			margin_reg_value = 102;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  			deemph_reg_value = 128;
>  			margin_reg_value = 154;
>  			/* FIXME extra to set for 1200 */
> @@ -2581,17 +2581,17 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  			return 0;
>  		}
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			deemph_reg_value = 85;
>  			margin_reg_value = 78;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  			deemph_reg_value = 85;
>  			margin_reg_value = 116;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_800:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
>  			deemph_reg_value = 85;
>  			margin_reg_value = 154;
>  			break;
> @@ -2599,13 +2599,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  			return 0;
>  		}
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			deemph_reg_value = 64;
>  			margin_reg_value = 104;
>  			break;
> -		case DP_TRAIN_VOLTAGE_SWING_600:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  			deemph_reg_value = 64;
>  			margin_reg_value = 154;
>  			break;
> @@ -2613,9 +2613,9 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  			return 0;
>  		}
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_9_5:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_3:
>  		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			deemph_reg_value = 43;
>  			margin_reg_value = 154;
>  			break;
> @@ -2662,9 +2662,9 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	}
>  
>  	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
> -			== DP_TRAIN_PRE_EMPHASIS_0) &&
> +			== DP_TRAIN_PRE_EMPH_LEVEL_0) &&
>  		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
> -			== DP_TRAIN_VOLTAGE_SWING_1200)) {
> +			== DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
>  
>  		/*
>  		 * The document said it needs to set bit 27 for ch0 and bit 26
> @@ -2743,32 +2743,32 @@ intel_gen4_signal_levels(uint8_t train_set)
>  	uint32_t	signal_levels = 0;
>  
>  	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -	case DP_TRAIN_VOLTAGE_SWING_400:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  	default:
>  		signal_levels |= DP_VOLTAGE_0_4;
>  		break;
> -	case DP_TRAIN_VOLTAGE_SWING_600:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>  		signal_levels |= DP_VOLTAGE_0_6;
>  		break;
> -	case DP_TRAIN_VOLTAGE_SWING_800:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
>  		signal_levels |= DP_VOLTAGE_0_8;
>  		break;
> -	case DP_TRAIN_VOLTAGE_SWING_1200:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  		signal_levels |= DP_VOLTAGE_1_2;
>  		break;
>  	}
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> -	case DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_0:
>  	default:
>  		signal_levels |= DP_PRE_EMPHASIS_0;
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		signal_levels |= DP_PRE_EMPHASIS_3_5;
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		signal_levels |= DP_PRE_EMPHASIS_6;
>  		break;
> -	case DP_TRAIN_PRE_EMPHASIS_9_5:
> +	case DP_TRAIN_PRE_EMPH_LEVEL_3:
>  		signal_levels |= DP_PRE_EMPHASIS_9_5;
>  		break;
>  	}
> @@ -2782,19 +2782,19 @@ intel_gen6_edp_signal_levels(uint8_t train_set)
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
>  	switch (signal_levels) {
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> -	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
> -	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> -	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
>  	default:
>  		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> @@ -2810,21 +2810,21 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
>  	switch (signal_levels) {
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return EDP_LINK_TRAIN_400MV_0DB_IVB;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		return EDP_LINK_TRAIN_400MV_6DB_IVB;
>  
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return EDP_LINK_TRAIN_600MV_0DB_IVB;
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
>  
> -	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return EDP_LINK_TRAIN_800MV_0DB_IVB;
> -	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
>  
>  	default:
> @@ -2841,25 +2841,25 @@ intel_hsw_signal_levels(uint8_t train_set)
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
>  	switch (signal_levels) {
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return DDI_BUF_EMP_400MV_0DB_HSW;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return DDI_BUF_EMP_400MV_3_5DB_HSW;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		return DDI_BUF_EMP_400MV_6DB_HSW;
> -	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
>  		return DDI_BUF_EMP_400MV_9_5DB_HSW;
>  
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return DDI_BUF_EMP_600MV_0DB_HSW;
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return DDI_BUF_EMP_600MV_3_5DB_HSW;
> -	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
>  		return DDI_BUF_EMP_600MV_6DB_HSW;
>  
> -	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
>  		return DDI_BUF_EMP_800MV_0DB_HSW;
> -	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
>  		return DDI_BUF_EMP_800MV_3_5DB_HSW;
>  	default:
>  		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/7] drm/exynos: Renaming DP training vswing pre emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/exynos/exynos_dp_core.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 4f3c7eb..02602a8 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		return retval;
 
 	for (lane = 0; lane < lane_count; lane++)
-		buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
-			    DP_TRAIN_VOLTAGE_SWING_400;
+		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
+			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, buf);
-- 
1.7.10.4

Re: [PATCH 3/7] drm/exynos: Renaming DP training vswing pre emph defines

[Jingoo Han]

On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
> 
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Rename the defines to have levels instead of values for vswing and
> pre-emph levels as the values may differ in other scenarios like low vswing of
> eDP1.4 where the values are different.
> 
> Done using following cocci patch for each define:
> @@
> @@
> 
>  # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> 
> ...
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>  drivers/gpu/drm/exynos/exynos_dp_core.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index 4f3c7eb..02602a8 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  		return retval;
> 
>  	for (lane = 0; lane < lane_count; lane++)
> -		buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
> -			    DP_TRAIN_VOLTAGE_SWING_400;
> +		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;

NAK!

It makes build error. Please build your patch, before sending the patch.
It is a rule when submitting patches.

Please, fix it as follows.

+		buf[lane] = DP_TRAIN_PRE_EMPHASIS_LEVEL_0|
+			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;

Best regards,
Jingoo Han

> 
>  	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>  			lane_count, buf);
> --
> 1.7.10.4

Re: [PATCH 3/7] drm/exynos: Renaming DP training vswing pre emph defines

[Jindal, Sonika]

On 8/28/2014 6:25 AM, Jingoo Han wrote:
> On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
>>
>> From: Sonika Jindal <sonika.jindal@intel.com>
>>
>> Rename the defines to have levels instead of values for vswing and
>> pre-emph levels as the values may differ in other scenarios like low vswing of
>> eDP1.4 where the values are different.
>>
>> Done using following cocci patch for each define:
>> @@
>> @@
>>
>>   # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
>> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
>>
>> ...
>>
>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>> ---
>>   drivers/gpu/drm/exynos/exynos_dp_core.c |    4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
>> index 4f3c7eb..02602a8 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>> @@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   		return retval;
>>
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
>> -			    DP_TRAIN_VOLTAGE_SWING_400;
>> +		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
>> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>
> NAK!
>
> It makes build error. Please build your patch, before sending the patch.
> It is a rule when submitting patches.
>
> Please, fix it as follows.
>
> +		buf[lane] = DP_TRAIN_PRE_EMPHASIS_LEVEL_0|
> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>
I think the first patch which you have taken (which adds new defines) is 
the one from the previous series for the same change. In the second 
version, I have named them as DP_TRAIN_PRE_EMPH_LEVEL_* which was done 
using cocci. Following is from that patch:
  # define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
  # define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
  # define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
  # define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
> Best regards,
> Jingoo Han
>
>>
>>   	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>>   			lane_count, buf);
>> --
>> 1.7.10.4
>

Re: [PATCH 3/7] drm/exynos: Renaming DP training vswing pre emph defines

[Jingoo Han]

On Thursday, August 28, 2014 1:33 PM, Sonika Sonika wrote:
> On 8/28/2014 6:25 AM, Jingoo Han wrote:
> > On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
> >>
> >> From: Sonika Jindal <sonika.jindal@intel.com>
> >>
> >> Rename the defines to have levels instead of values for vswing and
> >> pre-emph levels as the values may differ in other scenarios like low vswing of
> >> eDP1.4 where the values are different.
> >>
> >> Done using following cocci patch for each define:
> >> @@
> >> @@
> >>
> >>   # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
> >> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
> >>
> >> ...
> >>
> >> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> >> ---
> >>   drivers/gpu/drm/exynos/exynos_dp_core.c |    4 ++--
> >>   1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> index 4f3c7eb..02602a8 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> @@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
> >>   		return retval;
> >>
> >>   	for (lane = 0; lane < lane_count; lane++)
> >> -		buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
> >> -			    DP_TRAIN_VOLTAGE_SWING_400;
> >> +		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
> >> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> >
> > NAK!
> >
> > It makes build error. Please build your patch, before sending the patch.
> > It is a rule when submitting patches.
> >
> > Please, fix it as follows.
> >
> > +		buf[lane] = DP_TRAIN_PRE_EMPHASIS_LEVEL_0|
> > +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> >
> I think the first patch which you have taken (which adds new defines) is
> the one from the previous series for the same change. In the second
> version, I have named them as DP_TRAIN_PRE_EMPH_LEVEL_* which was done
> using cocci. Following is from that patch:

Oh, I see. Sorry for annoying you.
However, how about tagging V2, V3.. into patches? For instance,
'[PATCH V2 3/7] drm/exynos: Renaming DP training vswing pre emph defines'
It will be helpful, in order to prevent the same mistakes happening again.

Also, the patch looks good.
Acked-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

>   # define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
>   # define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
>   # define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
>   # define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
> +# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
> > Best regards,
> > Jingoo Han
> >
> >>
> >>   	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> >>   			lane_count, buf);
> >> --
> >> 1.7.10.4
> >

Re: [PATCH 3/7] drm/exynos: Renaming DP training vswing pre emph defines

[Jindal, Sonika]

On 8/28/2014 11:36 AM, Jingoo Han wrote:
> On Thursday, August 28, 2014 1:33 PM, Sonika Sonika wrote:
>> On 8/28/2014 6:25 AM, Jingoo Han wrote:
>>> On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
>>>>
>>>> From: Sonika Jindal <sonika.jindal@intel.com>
>>>>
>>>> Rename the defines to have levels instead of values for vswing and
>>>> pre-emph levels as the values may differ in other scenarios like low vswing of
>>>> eDP1.4 where the values are different.
>>>>
>>>> Done using following cocci patch for each define:
>>>> @@
>>>> @@
>>>>
>>>>    # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
>>>> + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)
>>>>
>>>> ...
>>>>
>>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/exynos/exynos_dp_core.c |    4 ++--
>>>>    1 file changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> index 4f3c7eb..02602a8 100644
>>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> @@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>>>    		return retval;
>>>>
>>>>    	for (lane = 0; lane < lane_count; lane++)
>>>> -		buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
>>>> -			    DP_TRAIN_VOLTAGE_SWING_400;
>>>> +		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
>>>> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>>>
>>> NAK!
>>>
>>> It makes build error. Please build your patch, before sending the patch.
>>> It is a rule when submitting patches.
>>>
>>> Please, fix it as follows.
>>>
>>> +		buf[lane] = DP_TRAIN_PRE_EMPHASIS_LEVEL_0|
>>> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>>>
>> I think the first patch which you have taken (which adds new defines) is
>> the one from the previous series for the same change. In the second
>> version, I have named them as DP_TRAIN_PRE_EMPH_LEVEL_* which was done
>> using cocci. Following is from that patch:
>
> Oh, I see. Sorry for annoying you.
> However, how about tagging V2, V3.. into patches? For instance,
> '[PATCH V2 3/7] drm/exynos: Renaming DP training vswing pre emph defines'
> It will be helpful, in order to prevent the same mistakes happening again.
>
Actually I had bumped the version in the cover letter. Because last time 
I had changed the version of all the patches (for some other feature), 
somebody asked me to just change the version at the top when it is a series.
Also, this was a different patch altogether done using cocci, so thought 
it should be fine. Will take care next time :)
Thanks,
Sonika
> Also, the patch looks good.
> Acked-by: Jingoo Han <jg1.han@samsung.com>
>
> Best regards,
> Jingoo Han
>
>>    # define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
>> +# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
>>    # define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
>> +# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
>>    # define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
>> +# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
>>    # define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
>> +# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
>>> Best regards,
>>> Jingoo Han
>>>
>>>>
>>>>    	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>>>>    			lane_count, buf);
>>>> --
>>>> 1.7.10.4
>>>
>

[PATCH 4/7] drm/gma500: Renaming DP training vswing pre emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/gma500/cdv_intel_dp.c |    4 ++--
 drivers/gpu/drm/gma500/intel_bios.c   |   16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index a4cc0e6..9f158ea 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -1089,7 +1089,7 @@ static char	*link_train_names[] = {
 };
 #endif
 
-#define CDV_DP_VOLTAGE_MAX	    DP_TRAIN_VOLTAGE_SWING_1200
+#define CDV_DP_VOLTAGE_MAX	    DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 /*
 static uint8_t
 cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
@@ -1276,7 +1276,7 @@ cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level
 		cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
 
 	/* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
-	if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
+	if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
 		cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
 	else
 		cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
diff --git a/drivers/gpu/drm/gma500/intel_bios.c b/drivers/gpu/drm/gma500/intel_bios.c
index d349734..63bde4e 100644
--- a/drivers/gpu/drm/gma500/intel_bios.c
+++ b/drivers/gpu/drm/gma500/intel_bios.c
@@ -116,30 +116,30 @@ parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb)
 
 	switch (edp_link_params->preemphasis) {
 	case 0:
-		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
+		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
 		break;
 	case 1:
-		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
+		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
 		break;
 	case 2:
-		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
+		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
 		break;
 	case 3:
-		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
+		dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
 		break;
 	}
 	switch (edp_link_params->vswing) {
 	case 0:
-		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_400;
+		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 		break;
 	case 1:
-		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_600;
+		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
 		break;
 	case 2:
-		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_800;
+		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 		break;
 	case 3:
-		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_1200;
+		dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 		break;
 	}
 	DRM_DEBUG_KMS("VBT reports EDP: VSwing  %d, Preemph %d\n",
-- 
1.7.10.4

[PATCH 5/7] drm/radeon: Renaming DP training vswing pre emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_1200     (3 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/radeon/atombios_dp.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index b1e11f8..95ea276 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -232,8 +232,8 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 
 /***** general DP utility functions *****/
 
-#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
-#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
+#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
+#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 
 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 				int lane_count,
-- 
1.7.10.4

[PATCH 6/7] drm/tegra: Renaming DP training vswing pre emph defines

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/tegra/dpaux.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 708f783..d6b55e3 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -533,9 +533,9 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
 
 	for (i = 0; i < link->num_lanes; i++)
 		values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
-			    DP_TRAIN_PRE_EMPHASIS_0 |
+			    DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_MAX_SWING_REACHED |
-			    DP_TRAIN_VOLTAGE_SWING_400;
+			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
 				link->num_lanes);
-- 
1.7.10.4

[PATCH 7/7] drm: Remove old defines for vswing and pre-emph values

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

This is the last patch in the series, so remove old defines

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 include/drm/drm_dp_helper.h |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3840a05..9305c71 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -190,23 +190,15 @@
 # define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
 # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
 # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
-# define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
-# define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
-# define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
-# define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)
 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
 
 # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
 # define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
 # define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
 # define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
 # define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
 
 # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
-- 
1.7.10.4

Re: [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[Jindal, Sonika]

Hi,

Did anybody get a chance to review other patches in this series?
I got r-b for 2 patches (patches with changes in drm and i915) from Damien.

Thanks,
Sonika

-----Original Message-----
From: Jindal, Sonika 
Sent: Friday, August 8, 2014 4:24 PM
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org; Jindal, Sonika
Subject: [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP 1.4 where the values are different.
Updated in all the drivers as well

v2: Keeping the old defines in first patch and removing them in last patch. Used cocci semantic patch to replace the defines.

Sonika Jindal (7):
  drm: Renaming DP training vswing pre emph defines
  drm/i915: Renaming DP training vswing pre emph defines
  drm/exynos: Renaming DP training vswing pre emph defines
  drm/gma500: Renaming DP training vswing pre emph defines
  drm/radeon: Renaming DP training vswing pre emph defines
  drm/tegra: Renaming DP training vswing pre emph defines
  drm: Remove old defines for vswing and pre-emph values

 drivers/gpu/drm/exynos/exynos_dp_core.c |    4 +-
 drivers/gpu/drm/gma500/cdv_intel_dp.c   |    4 +-
 drivers/gpu/drm/gma500/intel_bios.c     |   16 +--
 drivers/gpu/drm/i915/intel_bios.c       |   16 +--
 drivers/gpu/drm/i915/intel_dp.c         |  194 +++++++++++++++----------------
 drivers/gpu/drm/radeon/atombios_dp.c    |    4 +-
 drivers/gpu/drm/tegra/dpaux.c           |    4 +-
 include/drm/drm_dp_helper.h             |   16 +--
 8 files changed, 129 insertions(+), 129 deletions(-)

--
1.7.10.4

Re: [Intel-gfx] [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[Daniel Vetter]

On Tue, Aug 19, 2014 at 08:12:06AM +0000, Jindal, Sonika wrote:
> Hi,
> 
> Did anybody get a chance to review other patches in this series?
> I got r-b for 2 patches (patches with changes in drm and i915) from Damien.

It helps if you cc the relevant driver maintainers on patch submissions.
scripts/get_maintainer.pl run on individual patches will tell you the
relevant people, which you can add as Cc: tags so that git send-email will
automatically cc them.

Then after a week of silence ping relevant maintainers (most of them are
on irc) and if that doesn't get their attention I'll escalate to the
overall drm maintainer Dave Airlie.

I know there's a bit of beaurocratics involved for such changes, but if
you follow this protocol the patches usually can go in within 2 weeks.

I've already pinged tegra and radeon maintainers on irc for you.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[Jindal, Sonika]

Hi,

Did anybody get a chance to review the patches?
Adding respective owners for different drivers..

Thanks,
Sonika

-----Original Message-----
From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Jindal, Sonika
Sent: Tuesday, August 19, 2014 1:42 PM
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

Hi,

Did anybody get a chance to review other patches in this series?
I got r-b for 2 patches (patches with changes in drm and i915) from Damien.

Thanks,
Sonika

-----Original Message-----
From: Jindal, Sonika 
Sent: Friday, August 8, 2014 4:24 PM
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org; Jindal, Sonika
Subject: [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

From: Sonika Jindal <sonika.jindal@intel.com>

Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP 1.4 where the values are different.
Updated in all the drivers as well

v2: Keeping the old defines in first patch and removing them in last patch. Used cocci semantic patch to replace the defines.

Sonika Jindal (7):
  drm: Renaming DP training vswing pre emph defines
  drm/i915: Renaming DP training vswing pre emph defines
  drm/exynos: Renaming DP training vswing pre emph defines
  drm/gma500: Renaming DP training vswing pre emph defines
  drm/radeon: Renaming DP training vswing pre emph defines
  drm/tegra: Renaming DP training vswing pre emph defines
  drm: Remove old defines for vswing and pre-emph values

 drivers/gpu/drm/exynos/exynos_dp_core.c |    4 +-
 drivers/gpu/drm/gma500/cdv_intel_dp.c   |    4 +-
 drivers/gpu/drm/gma500/intel_bios.c     |   16 +--
 drivers/gpu/drm/i915/intel_bios.c       |   16 +--
 drivers/gpu/drm/i915/intel_dp.c         |  194 +++++++++++++++----------------
 drivers/gpu/drm/radeon/atombios_dp.c    |    4 +-
 drivers/gpu/drm/tegra/dpaux.c           |    4 +-
 include/drm/drm_dp_helper.h             |   16 +--
 8 files changed, 129 insertions(+), 129 deletions(-)

--
1.7.10.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

RE: [Intel-gfx] [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[Deucher, Alexander]

> -----Original Message-----
> From: Jindal, Sonika [mailto:sonika.jindal@intel.com]
> Sent: Wednesday, August 27, 2014 2:09 AM
> To: Jindal, Sonika; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; kgene.kim@samsung.com;
> jg1.han@samsung.com; airlied@linux.ie; Deucher, Alexander;
> thierry.reding@gmail.com; Lespiau, Damien
> Subject: RE: [Intel-gfx] [PATCH v2 0/7] Rename DP training vswing/pre-emph
> defines
> 
> Hi,
> 
> Did anybody get a chance to review the patches?
> Adding respective owners for different drivers..

I gave my RB to danvet on IRC, but if you need it:

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> 
> Thanks,
> Sonika
> 
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Jindal, Sonika
> Sent: Tuesday, August 19, 2014 1:42 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 0/7] Rename DP training vswing/pre-emph
> defines
> 
> Hi,
> 
> Did anybody get a chance to review other patches in this series?
> I got r-b for 2 patches (patches with changes in drm and i915) from Damien.
> 
> Thanks,
> Sonika
> 
> -----Original Message-----
> From: Jindal, Sonika
> Sent: Friday, August 8, 2014 4:24 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Jindal, Sonika
> Subject: [PATCH v2 0/7] Rename DP training vswing/pre-emph defines
> 
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Rename the defines to have levels instead of values for vswing and pre-
> emph levels as the values may differ in other scenarios like low vswing of
> eDP 1.4 where the values are different.
> Updated in all the drivers as well
> 
> v2: Keeping the old defines in first patch and removing them in last patch.
> Used cocci semantic patch to replace the defines.
> 
> Sonika Jindal (7):
>   drm: Renaming DP training vswing pre emph defines
>   drm/i915: Renaming DP training vswing pre emph defines
>   drm/exynos: Renaming DP training vswing pre emph defines
>   drm/gma500: Renaming DP training vswing pre emph defines
>   drm/radeon: Renaming DP training vswing pre emph defines
>   drm/tegra: Renaming DP training vswing pre emph defines
>   drm: Remove old defines for vswing and pre-emph values
> 
>  drivers/gpu/drm/exynos/exynos_dp_core.c |    4 +-
>  drivers/gpu/drm/gma500/cdv_intel_dp.c   |    4 +-
>  drivers/gpu/drm/gma500/intel_bios.c     |   16 +--
>  drivers/gpu/drm/i915/intel_bios.c       |   16 +--
>  drivers/gpu/drm/i915/intel_dp.c         |  194 +++++++++++++++----------------
>  drivers/gpu/drm/radeon/atombios_dp.c    |    4 +-
>  drivers/gpu/drm/tegra/dpaux.c           |    4 +-
>  include/drm/drm_dp_helper.h             |   16 +--
>  8 files changed, 129 insertions(+), 129 deletions(-)
> 
> --
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 0/7] Rename DP training vswing/pre-emph defines

[Daniel Vetter]

On Fri, Aug 08, 2014 at 04:23:39PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Rename the defines to have levels instead of values for vswing and pre-emph
> levels as the values may differ in other scenarios like low vswing of eDP 1.4
> where the values are different.
> Updated in all the drivers as well
> 
> v2: Keeping the old defines in first patch and removing them in last patch. Used
> cocci semantic patch to replace the defines.
> 
> Sonika Jindal (7):
>   drm: Renaming DP training vswing pre emph defines
>   drm/i915: Renaming DP training vswing pre emph defines
>   drm/exynos: Renaming DP training vswing pre emph defines
>   drm/gma500: Renaming DP training vswing pre emph defines
>   drm/radeon: Renaming DP training vswing pre emph defines
>   drm/tegra: Renaming DP training vswing pre emph defines
>   drm: Remove old defines for vswing and pre-emph values

I've pulled in the entire series with Dave's irc-ack for the non-i915
bits.

Thanks, Daniel

> 
>  drivers/gpu/drm/exynos/exynos_dp_core.c |    4 +-
>  drivers/gpu/drm/gma500/cdv_intel_dp.c   |    4 +-
>  drivers/gpu/drm/gma500/intel_bios.c     |   16 +--
>  drivers/gpu/drm/i915/intel_bios.c       |   16 +--
>  drivers/gpu/drm/i915/intel_dp.c         |  194 +++++++++++++++----------------
>  drivers/gpu/drm/radeon/atombios_dp.c    |    4 +-
>  drivers/gpu/drm/tegra/dpaux.c           |    4 +-
>  include/drm/drm_dp_helper.h             |   16 +--
>  8 files changed, 129 insertions(+), 129 deletions(-)
> 
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch