[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Anson Huang]

Currently, gpt timer's clock is from ipg_per, and ipg_per clock is from ipg
on most of i.MX6 series SOCs, but ipg's rate may be scaled when system enters
low bus mode for saving power, then gpt timer's clock rate will be scaled as
well, as system timer should be kept stable and NOT drift, better to keep gpt
timer's clk at fixed rate, on i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, there is
OSC clk available for gpt timer, we should enable this feature, the hardware
design is as below:

i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
    of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
    for gpt per clk, and we must enable GPT_CR_24MEM to
    enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
    is for pre-scaling of this OSC clk, here set it to 8
    to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
    implement this new clk source for gpt per.

Anson Huang (3):
  ARM: imx: add gpt_3m clk for i.mx6qdl
  ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
  ARM: imx: source gpt per clk from OSC for system timer

 arch/arm/boot/dts/imx6qdl.dtsi            |    2 +-
 arch/arm/boot/dts/imx6sx.dtsi             |    2 +-
 arch/arm/mach-imx/clk-imx6q.c             |    1 +
 arch/arm/mach-imx/time.c                  |   29 ++++++++++++++++++++++++-----
 include/dt-bindings/clock/imx6qdl-clock.h |    3 ++-
 5 files changed, 29 insertions(+), 8 deletions(-)

-- 
1.7.9.5

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[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Anson Huang]

Currently, gpt timer's clock is from ipg_per, and ipg_per clock is from ipg
on most of i.MX6 series SOCs, but ipg's rate may be scaled when system enters
low bus mode for saving power, then gpt timer's clock rate will be scaled as
well, as system timer should be kept stable and NOT drift, better to keep gpt
timer's clk at fixed rate, on i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, there is
OSC clk available for gpt timer, we should enable this feature, the hardware
design is as below:

i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
    of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
    for gpt per clk, and we must enable GPT_CR_24MEM to
    enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
    is for pre-scaling of this OSC clk, here set it to 8
    to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
    implement this new clk source for gpt per.

Anson Huang (3):
  ARM: imx: add gpt_3m clk for i.mx6qdl
  ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
  ARM: imx: source gpt per clk from OSC for system timer

 arch/arm/boot/dts/imx6qdl.dtsi            |    2 +-
 arch/arm/boot/dts/imx6sx.dtsi             |    2 +-
 arch/arm/mach-imx/clk-imx6q.c             |    1 +
 arch/arm/mach-imx/time.c                  |   29 ++++++++++++++++++++++++-----
 include/dt-bindings/clock/imx6qdl-clock.h |    3 ++-
 5 files changed, 29 insertions(+), 8 deletions(-)

-- 
1.7.9.5

[PATCH 1/3] ARM: imx: add gpt_3m clk for i.mx6qdl

[Anson Huang]

Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.

Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
 arch/arm/mach-imx/clk-imx6q.c             |    1 +
 include/dt-bindings/clock/imx6qdl-clock.h |    3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2edcebf..7e6b3dd 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -194,6 +194,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
 	clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
 	clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+	clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
 	if (cpu_is_imx6dl()) {
 		clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
 		clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 323e865..9bc2e07 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -220,6 +220,7 @@
 #define IMX6QDL_CLK_LVDS2_GATE			207
 #define IMX6QDL_CLK_ESAI_IPG			208
 #define IMX6QDL_CLK_ESAI_MEM			209
-#define IMX6QDL_CLK_END				210
+#define IMX6QDL_CLK_GPT_3M			210
+#define IMX6QDL_CLK_END				211
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
-- 
1.7.9.5

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[PATCH 1/3] ARM: imx: add gpt_3m clk for i.mx6qdl

[Anson Huang]

Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.

Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/mach-imx/clk-imx6q.c             |    1 +
 include/dt-bindings/clock/imx6qdl-clock.h |    3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2edcebf..7e6b3dd 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -194,6 +194,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
 	clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
 	clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+	clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
 	if (cpu_is_imx6dl()) {
 		clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
 		clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 323e865..9bc2e07 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -220,6 +220,7 @@
 #define IMX6QDL_CLK_LVDS2_GATE			207
 #define IMX6QDL_CLK_ESAI_IPG			208
 #define IMX6QDL_CLK_ESAI_MEM			209
-#define IMX6QDL_CLK_END				210
+#define IMX6QDL_CLK_GPT_3M			210
+#define IMX6QDL_CLK_END				211
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
-- 
1.7.9.5

[PATCH 2/3] ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx

[Anson Huang]

Original gpt per clk parent is from ipg_per clk which
may be scaled when system enter low bus mode, as ipg
clk will be lower in low bus mode, to keep system clk
NOT drift, select gpt per clk parent from OSC which
is at fixed freq always.

Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    2 +-
 arch/arm/boot/dts/imx6sx.dtsi  |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 70d7207..ccd6c1b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -401,7 +401,7 @@
 				reg = <0x02098000 0x4000>;
 				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
-					 <&clks IMX6QDL_CLK_GPT_IPG_PER>;
+					 <&clks IMX6QDL_CLK_GPT_3M>;
 				clock-names = "ipg", "per";
 			};
 
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 63d9d82..b5d8252 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -421,7 +421,7 @@
 				reg = <0x02098000 0x4000>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_GPT_BUS>,
-					 <&clks IMX6SX_CLK_GPT_SERIAL>;
+					 <&clks IMX6SX_CLK_GPT_3M>;
 				clock-names = "ipg", "per";
 			};
 
-- 
1.7.9.5

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[PATCH 2/3] ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx

[Anson Huang]

Original gpt per clk parent is from ipg_per clk which
may be scaled when system enter low bus mode, as ipg
clk will be lower in low bus mode, to keep system clk
NOT drift, select gpt per clk parent from OSC which
is at fixed freq always.

Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi |    2 +-
 arch/arm/boot/dts/imx6sx.dtsi  |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 70d7207..ccd6c1b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -401,7 +401,7 @@
 				reg = <0x02098000 0x4000>;
 				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
-					 <&clks IMX6QDL_CLK_GPT_IPG_PER>;
+					 <&clks IMX6QDL_CLK_GPT_3M>;
 				clock-names = "ipg", "per";
 			};
 
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 63d9d82..b5d8252 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -421,7 +421,7 @@
 				reg = <0x02098000 0x4000>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_GPT_BUS>,
-					 <&clks IMX6SX_CLK_GPT_SERIAL>;
+					 <&clks IMX6SX_CLK_GPT_3M>;
 				clock-names = "ipg", "per";
 			};
 
-- 
1.7.9.5

[PATCH 3/3] ARM: imx: source gpt per clk from OSC for system timer

[Anson Huang]

On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.

There are some difference on this implementation of
gpt per clock source, see below for details:

i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
    of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
    for gpt per clk, and we must enable GPT_CR_24MEM to
    enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
    is for pre-scaling of this OSC clk, here set it to 8
    to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
    implement this new clk source for gpt per.

Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/mach-imx/time.c |   29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bf92e5a..54d23c7 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -60,11 +60,15 @@
 #define MX2_TSTAT_CAPT		(1 << 1)
 #define MX2_TSTAT_COMP		(1 << 0)
 
-/* MX31, MX35, MX25, MX5 */
+/* MX31, MX35, MX25, MX5, MX6 */
 #define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
 #define V2_TCTL_CLK_IPG		(1 << 6)
 #define V2_TCTL_CLK_PER		(2 << 6)
+#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
+#define V2_TCTL_CLK_OSC		(7 << 6)
 #define V2_TCTL_FRR		(1 << 9)
+#define V2_TCTL_24MEN		(1 << 10)
+#define V2_TPRER_PRE24M		12
 #define V2_IR			0x0c
 #define V2_TSTAT		0x08
 #define V2_TSTAT_OF1		(1 << 0)
@@ -293,7 +297,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 static void __init _mxc_timer_init(int irq,
 				   struct clk *clk_per, struct clk *clk_ipg)
 {
-	uint32_t tctl_val;
+	uint32_t tctl_val, tprer_val;
 
 	if (IS_ERR(clk_per)) {
 		pr_err("i.MX timer: unable to get clk\n");
@@ -312,10 +316,25 @@ static void __init _mxc_timer_init(int irq,
 	__raw_writel(0, timer_base + MXC_TCTL);
 	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
-	if (timer_is_v2())
-		tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
-	else
+	if (timer_is_v2()) {
+		if ((cpu_is_imx6q() && imx_get_soc_revision() >
+			IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() ||
+			cpu_is_imx6sx()) {
+			tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR |
+				V2_TCTL_WAITEN | MXC_TCTL_TEN;
+			if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
+				/* 24 / 8 = 3 MHz */
+				tprer_val = 7 << V2_TPRER_PRE24M;
+				__raw_writel(tprer_val, timer_base + MXC_TPRER);
+				tctl_val |= V2_TCTL_24MEN;
+			}
+		} else {
+			tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR |
+				V2_TCTL_WAITEN | MXC_TCTL_TEN;
+		}
+	} else {
 		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
+	}
 
 	__raw_writel(tctl_val, timer_base + MXC_TCTL);
 
-- 
1.7.9.5

[PATCH 3/3] ARM: imx: source gpt per clk from OSC for system timer

[Anson Huang]

On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.

There are some difference on this implementation of
gpt per clock source, see below for details:

i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
    of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
    for gpt per clk, and we must enable GPT_CR_24MEM to
    enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
    is for pre-scaling of this OSC clk, here set it to 8
    to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
    implement this new clk source for gpt per.

Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/mach-imx/time.c |   29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bf92e5a..54d23c7 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -60,11 +60,15 @@
 #define MX2_TSTAT_CAPT		(1 << 1)
 #define MX2_TSTAT_COMP		(1 << 0)
 
-/* MX31, MX35, MX25, MX5 */
+/* MX31, MX35, MX25, MX5, MX6 */
 #define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
 #define V2_TCTL_CLK_IPG		(1 << 6)
 #define V2_TCTL_CLK_PER		(2 << 6)
+#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
+#define V2_TCTL_CLK_OSC		(7 << 6)
 #define V2_TCTL_FRR		(1 << 9)
+#define V2_TCTL_24MEN		(1 << 10)
+#define V2_TPRER_PRE24M		12
 #define V2_IR			0x0c
 #define V2_TSTAT		0x08
 #define V2_TSTAT_OF1		(1 << 0)
@@ -293,7 +297,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 static void __init _mxc_timer_init(int irq,
 				   struct clk *clk_per, struct clk *clk_ipg)
 {
-	uint32_t tctl_val;
+	uint32_t tctl_val, tprer_val;
 
 	if (IS_ERR(clk_per)) {
 		pr_err("i.MX timer: unable to get clk\n");
@@ -312,10 +316,25 @@ static void __init _mxc_timer_init(int irq,
 	__raw_writel(0, timer_base + MXC_TCTL);
 	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
-	if (timer_is_v2())
-		tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
-	else
+	if (timer_is_v2()) {
+		if ((cpu_is_imx6q() && imx_get_soc_revision() >
+			IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() ||
+			cpu_is_imx6sx()) {
+			tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR |
+				V2_TCTL_WAITEN | MXC_TCTL_TEN;
+			if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
+				/* 24 / 8 = 3 MHz */
+				tprer_val = 7 << V2_TPRER_PRE24M;
+				__raw_writel(tprer_val, timer_base + MXC_TPRER);
+				tctl_val |= V2_TCTL_24MEN;
+			}
+		} else {
+			tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR |
+				V2_TCTL_WAITEN | MXC_TCTL_TEN;
+		}
+	} else {
 		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
+	}
 
 	__raw_writel(tctl_val, timer_base + MXC_TCTL);
 
-- 
1.7.9.5

Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Shawn Guo]

On Wed, Sep 03, 2014 at 03:36:42PM +0800, Anson Huang wrote:
> Anson Huang (3):
>   ARM: imx: add gpt_3m clk for i.mx6qdl
>   ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
>   ARM: imx: source gpt per clk from OSC for system timer

Applied all, thanks.
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[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Shawn Guo]

On Wed, Sep 03, 2014 at 03:36:42PM +0800, Anson Huang wrote:
> Anson Huang (3):
>   ARM: imx: add gpt_3m clk for i.mx6qdl
>   ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
>   ARM: imx: source gpt per clk from OSC for system timer

Applied all, thanks.

Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Fabio Estevam]

On Wed, Sep 3, 2014 at 4:36 AM, Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
> Currently, gpt timer's clock is from ipg_per, and ipg_per clock is from ipg
> on most of i.MX6 series SOCs, but ipg's rate may be scaled when system enters
> low bus mode for saving power, then gpt timer's clock rate will be scaled as
> well, as system timer should be kept stable and NOT drift, better to keep gpt
> timer's clk at fixed rate, on i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, there is
> OSC clk available for gpt timer, we should enable this feature, the hardware
> design is as below:
>
> i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
>     of OSC / 8 for gpt per clk;
> i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
>     for gpt per clk, and we must enable GPT_CR_24MEM to
>     enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
>     is for pre-scaling of this OSC clk, here set it to 8
>     to make gpt per clk is 3MHz;
> i.MX6SL: ipg_per can be from OSC directly, so no need to
>     implement this new clk source for gpt per.
>
> Anson Huang (3):
>   ARM: imx: add gpt_3m clk for i.mx6qdl
>   ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
>   ARM: imx: source gpt per clk from OSC for system timer

This patch series works fine if we use the new dtb and new kernel.

However, booting a kernel with these series applied and using an old
dtb we get a system with broken timer.

'sleep 1' takes something like 20 seconds in this case.
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[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Fabio Estevam]

On Wed, Sep 3, 2014 at 4:36 AM, Anson Huang <b20788@freescale.com> wrote:
> Currently, gpt timer's clock is from ipg_per, and ipg_per clock is from ipg
> on most of i.MX6 series SOCs, but ipg's rate may be scaled when system enters
> low bus mode for saving power, then gpt timer's clock rate will be scaled as
> well, as system timer should be kept stable and NOT drift, better to keep gpt
> timer's clk at fixed rate, on i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, there is
> OSC clk available for gpt timer, we should enable this feature, the hardware
> design is as below:
>
> i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
>     of OSC / 8 for gpt per clk;
> i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
>     for gpt per clk, and we must enable GPT_CR_24MEM to
>     enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
>     is for pre-scaling of this OSC clk, here set it to 8
>     to make gpt per clk is 3MHz;
> i.MX6SL: ipg_per can be from OSC directly, so no need to
>     implement this new clk source for gpt per.
>
> Anson Huang (3):
>   ARM: imx: add gpt_3m clk for i.mx6qdl
>   ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
>   ARM: imx: source gpt per clk from OSC for system timer

This patch series works fine if we use the new dtb and new kernel.

However, booting a kernel with these series applied and using an old
dtb we get a system with broken timer.

'sleep 1' takes something like 20 seconds in this case.

Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Anson.Huang-KZfg59tc24xl57MIdRCFDg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 1853 bytes --]

Hi, Fabio
        can I know why you want to run the new kernel with old dtb?

Sent from Anson's iPhone

> ÔÚ 2014Äê9ÔÂ5ÈÕ£¬6:50£¬"Fabio Estevam" <festevam@gmail.com> дµÀ£º
> 
>> On Wed, Sep 3, 2014 at 4:36 AM, Anson Huang <b20788@freescale.com> wrote:
>> Currently, gpt timer's clock is from ipg_per, and ipg_per clock is from ipg
>> on most of i.MX6 series SOCs, but ipg's rate may be scaled when system enters
>> low bus mode for saving power, then gpt timer's clock rate will be scaled as
>> well, as system timer should be kept stable and NOT drift, better to keep gpt
>> timer's clk at fixed rate, on i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, there is
>> OSC clk available for gpt timer, we should enable this feature, the hardware
>> design is as below:
>> 
>> i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
>>    of OSC / 8 for gpt per clk;
>> i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
>>    for gpt per clk, and we must enable GPT_CR_24MEM to
>>    enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
>>    is for pre-scaling of this OSC clk, here set it to 8
>>    to make gpt per clk is 3MHz;
>> i.MX6SL: ipg_per can be from OSC directly, so no need to
>>    implement this new clk source for gpt per.
>> 
>> Anson Huang (3):
>>  ARM: imx: add gpt_3m clk for i.mx6qdl
>>  ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
>>  ARM: imx: source gpt per clk from OSC for system timer
> 
> This patch series works fine if we use the new dtb and new kernel.
> 
> However, booting a kernel with these series applied and using an old
> dtb we get a system with broken timer.
> 
> 'sleep 1' takes something like 20 seconds in this case.
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[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Anson.Huang at freescale.com]

Hi, Fabio
        can I know why you want to run the new kernel with old dtb?

Sent from Anson's iPhone

> ? 2014?9?5??6:50?"Fabio Estevam" <festevam@gmail.com> ???
> 
>> On Wed, Sep 3, 2014 at 4:36 AM, Anson Huang <b20788@freescale.com> wrote:
>> Currently, gpt timer's clock is from ipg_per, and ipg_per clock is from ipg
>> on most of i.MX6 series SOCs, but ipg's rate may be scaled when system enters
>> low bus mode for saving power, then gpt timer's clock rate will be scaled as
>> well, as system timer should be kept stable and NOT drift, better to keep gpt
>> timer's clk at fixed rate, on i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, there is
>> OSC clk available for gpt timer, we should enable this feature, the hardware
>> design is as below:
>> 
>> i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock
>>    of OSC / 8 for gpt per clk;
>> i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC
>>    for gpt per clk, and we must enable GPT_CR_24MEM to
>>    enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
>>    is for pre-scaling of this OSC clk, here set it to 8
>>    to make gpt per clk is 3MHz;
>> i.MX6SL: ipg_per can be from OSC directly, so no need to
>>    implement this new clk source for gpt per.
>> 
>> Anson Huang (3):
>>  ARM: imx: add gpt_3m clk for i.mx6qdl
>>  ARM: dts: imx6: change gpt per clk to gpt_3m on i.mx6qdl and i.mx6sx
>>  ARM: imx: source gpt per clk from OSC for system timer
> 
> This patch series works fine if we use the new dtb and new kernel.
> 
> However, booting a kernel with these series applied and using an old
> dtb we get a system with broken timer.
> 
> 'sleep 1' takes something like 20 seconds in this case.

Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Fabio Estevam]

Hi Anson,

On Thu, Sep 4, 2014 at 8:37 PM, Anson.Huang-KZfg59tc24xl57MIdRCFDg@public.gmane.org
<Anson.Huang-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
> Hi, Fabio
>         can I know why you want to run the new kernel with old dtb?

We can not break old dtb functionality.
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[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Fabio Estevam]

Hi Anson,

On Thu, Sep 4, 2014 at 8:37 PM, Anson.Huang at freescale.com
<Anson.Huang@freescale.com> wrote:
> Hi, Fabio
>         can I know why you want to run the new kernel with old dtb?

We can not break old dtb functionality.

Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Shawn Guo]

On Thu, Sep 04, 2014 at 07:50:35PM -0300, Fabio Estevam wrote:
> This patch series works fine if we use the new dtb and new kernel.
> 
> However, booting a kernel with these series applied and using an old
> dtb we get a system with broken timer.
> 
> 'sleep 1' takes something like 20 seconds in this case.

Oh, yes.  It breaks the compatibility with existing DTB.  Dropped the
patches for now.

Anson,

We may need to query the clock rate and then decide how to set up those
register bits?

Shawn

[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Shawn Guo]

On Thu, Sep 04, 2014 at 07:50:35PM -0300, Fabio Estevam wrote:
> This patch series works fine if we use the new dtb and new kernel.
> 
> However, booting a kernel with these series applied and using an old
> dtb we get a system with broken timer.
> 
> 'sleep 1' takes something like 20 seconds in this case.

Oh, yes.  It breaks the compatibility with existing DTB.  Dropped the
patches for now.

Anson,

We may need to query the clock rate and then decide how to set up those
register bits?

Shawn

RE: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Anson.Huang]

Hi, Shawn and Fabio
	Thanks for advice, I have sent out V2 patch, please help review.

Best regards!
Anson Huang


-----Original Message-----
From: Shawn Guo [mailto:shawn.guo@freescale.com] 
Sent: 2014-09-05 8:35 AM
To: Fabio Estevam
Cc: Huang Yongcai-B20788; Sascha Hauer; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

On Thu, Sep 04, 2014 at 07:50:35PM -0300, Fabio Estevam wrote:
> This patch series works fine if we use the new dtb and new kernel.
> 
> However, booting a kernel with these series applied and using an old 
> dtb we get a system with broken timer.
> 
> 'sleep 1' takes something like 20 seconds in this case.

Oh, yes.  It breaks the compatibility with existing DTB.  Dropped the patches for now.

Anson,

We may need to query the clock rate and then decide how to set up those register bits?

Shawn

[PATCH 0/3] move gpt per clk parent for ipg_per to OSC

[Anson.Huang at freescale.com]

Hi, Shawn and Fabio
	Thanks for advice, I have sent out V2 patch, please help review.

Best regards!
Anson Huang


-----Original Message-----
From: Shawn Guo [mailto:shawn.guo at freescale.com] 
Sent: 2014-09-05 8:35 AM
To: Fabio Estevam
Cc: Huang Yongcai-B20788; Sascha Hauer; devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC

On Thu, Sep 04, 2014 at 07:50:35PM -0300, Fabio Estevam wrote:
> This patch series works fine if we use the new dtb and new kernel.
> 
> However, booting a kernel with these series applied and using an old 
> dtb we get a system with broken timer.
> 
> 'sleep 1' takes something like 20 seconds in this case.

Oh, yes.  It breaks the compatibility with existing DTB.  Dropped the patches for now.

Anson,

We may need to query the clock rate and then decide how to set up those register bits?

Shawn