From: Linus Walleij <linus.walleij@linaro.org> To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, linux-pm@vger.kernel.org Cc: Arnd Bergmann <arnd@arndb.de>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Marc Zyngier <marc.zyngier@arm.com>, Will Deacon <will.deacon@arm.com>, Rob Herring <robh@kernel.org>, Florian Fainelli <f.fainelli@gmail.com>, Linus Walleij <linus.walleij@linaro.org> Subject: [PATCH 5/7 v6] ARM: l2c: parse 'cache-size' and 'cache-sets' properties Date: Mon, 8 Sep 2014 13:38:04 +0200 [thread overview] Message-ID: <1410176286-32533-6-git-send-email-linus.walleij@linaro.org> (raw) In-Reply-To: <1410176286-32533-1-git-send-email-linus.walleij@linaro.org> From: Florian Fainelli <f.fainelli@gmail.com> When both 'cache-size' and 'cache-sets' are specified for a L2 cache controller node, parse those properties and set up the way_size based on which type of L2 cache controller we are using. Update the L2 cache controller Device Tree binding with the optional 'cache-size' and 'cache-sets' properties. These both come from the ePAPR specification. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Documentation/devicetree/bindings/arm/l2cc.txt | 2 + arch/arm/mm/cache-l2x0.c | 61 ++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index af527ee111c2..d33ed2344c7e 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -44,6 +44,8 @@ Optional properties: I/O coherent mode. Valid only when the arm,pl310-cache compatible string is used. - interrupts : 1 combined interrupt. +- cache-size : specifies the size in bytes of the cache +- cache-sets : specifies the number of associativity sets of the cache - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 5f2c988a06ac..61a684c743c6 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -945,6 +945,61 @@ static int l2_wt_override; * pass it though the device tree */ static u32 cache_id_part_number_from_dt; +static void __init l2x0_cache_size_of_parse(const struct device_node *np, + u32 *aux_val, u32 *aux_mask, + u32 max_way_size) +{ + u32 mask = 0, val = 0; + u32 size = 0, sets = 0; + u32 way_size = 0, way_size_bits = 1; + + of_property_read_u32(np, "cache-size", &size); + of_property_read_u32(np, "cache-sets", &sets); + + if (!size || !sets) + return; + + way_size = size / sets; + + if (way_size > max_way_size) { + pr_warn("L2C: way size %dKB is too large\n", way_size >> 10); + return; + } + + way_size >>= 10; + switch (way_size) { + case 512: + way_size_bits = 6; + break; + case 256: + way_size_bits = 5; + break; + case 128: + way_size_bits = 4; + break; + case 64: + way_size_bits = 3; + break; + case 32: + way_size_bits = 2; + break; + case 16: + way_size_bits = 1; + break; + default: + pr_err("cache way size: %d KB is not mapped\n", + way_size); + break; + } + + mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; + val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); + + *aux_val &= ~mask; + *aux_val |= val; + *aux_mask &= ~mask; +} + static void __init l2x0_of_parse(const struct device_node *np, u32 *aux_val, u32 *aux_mask) { @@ -974,6 +1029,8 @@ static void __init l2x0_of_parse(const struct device_node *np, val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; } + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); + *aux_val &= ~mask; *aux_val |= val; *aux_mask &= ~mask; @@ -1047,6 +1104,8 @@ static void __init l2c310_of_parse(const struct device_node *np, writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, l2x0_base + L310_ADDR_FILTER_START); } + + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_512K); } static const struct l2c_init_data of_l2c310_data __initconst = { @@ -1253,6 +1312,8 @@ static void __init aurora_of_parse(const struct device_node *np, *aux_val &= ~mask; *aux_val |= val; *aux_mask &= ~mask; + + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); } static const struct l2c_init_data of_aurora_with_outer_data __initconst = { -- 1.9.3
WARNING: multiple messages have this Message-ID (diff)
From: linus.walleij@linaro.org (Linus Walleij) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/7 v6] ARM: l2c: parse 'cache-size' and 'cache-sets' properties Date: Mon, 8 Sep 2014 13:38:04 +0200 [thread overview] Message-ID: <1410176286-32533-6-git-send-email-linus.walleij@linaro.org> (raw) In-Reply-To: <1410176286-32533-1-git-send-email-linus.walleij@linaro.org> From: Florian Fainelli <f.fainelli@gmail.com> When both 'cache-size' and 'cache-sets' are specified for a L2 cache controller node, parse those properties and set up the way_size based on which type of L2 cache controller we are using. Update the L2 cache controller Device Tree binding with the optional 'cache-size' and 'cache-sets' properties. These both come from the ePAPR specification. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Documentation/devicetree/bindings/arm/l2cc.txt | 2 + arch/arm/mm/cache-l2x0.c | 61 ++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index af527ee111c2..d33ed2344c7e 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -44,6 +44,8 @@ Optional properties: I/O coherent mode. Valid only when the arm,pl310-cache compatible string is used. - interrupts : 1 combined interrupt. +- cache-size : specifies the size in bytes of the cache +- cache-sets : specifies the number of associativity sets of the cache - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 5f2c988a06ac..61a684c743c6 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -945,6 +945,61 @@ static int l2_wt_override; * pass it though the device tree */ static u32 cache_id_part_number_from_dt; +static void __init l2x0_cache_size_of_parse(const struct device_node *np, + u32 *aux_val, u32 *aux_mask, + u32 max_way_size) +{ + u32 mask = 0, val = 0; + u32 size = 0, sets = 0; + u32 way_size = 0, way_size_bits = 1; + + of_property_read_u32(np, "cache-size", &size); + of_property_read_u32(np, "cache-sets", &sets); + + if (!size || !sets) + return; + + way_size = size / sets; + + if (way_size > max_way_size) { + pr_warn("L2C: way size %dKB is too large\n", way_size >> 10); + return; + } + + way_size >>= 10; + switch (way_size) { + case 512: + way_size_bits = 6; + break; + case 256: + way_size_bits = 5; + break; + case 128: + way_size_bits = 4; + break; + case 64: + way_size_bits = 3; + break; + case 32: + way_size_bits = 2; + break; + case 16: + way_size_bits = 1; + break; + default: + pr_err("cache way size: %d KB is not mapped\n", + way_size); + break; + } + + mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; + val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); + + *aux_val &= ~mask; + *aux_val |= val; + *aux_mask &= ~mask; +} + static void __init l2x0_of_parse(const struct device_node *np, u32 *aux_val, u32 *aux_mask) { @@ -974,6 +1029,8 @@ static void __init l2x0_of_parse(const struct device_node *np, val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; } + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); + *aux_val &= ~mask; *aux_val |= val; *aux_mask &= ~mask; @@ -1047,6 +1104,8 @@ static void __init l2c310_of_parse(const struct device_node *np, writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, l2x0_base + L310_ADDR_FILTER_START); } + + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_512K); } static const struct l2c_init_data of_l2c310_data __initconst = { @@ -1253,6 +1312,8 @@ static void __init aurora_of_parse(const struct device_node *np, *aux_val &= ~mask; *aux_val |= val; *aux_mask &= ~mask; + + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); } static const struct l2c_init_data of_aurora_with_outer_data __initconst = { -- 1.9.3
next prev parent reply other threads:[~2014-09-08 11:38 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-08 11:37 [PATCH 0/7] ARM RealView DeviceTree support v6 Linus Walleij 2014-09-08 11:37 ` Linus Walleij 2014-09-08 11:38 ` [PATCH 1/7 v6] leds: add a driver for syscon-based LEDs Linus Walleij 2014-09-08 11:38 ` Linus Walleij 2014-09-12 8:56 ` Linus Walleij 2014-09-12 8:56 ` Linus Walleij 2014-09-18 22:39 ` Linus Walleij 2014-09-18 22:39 ` Linus Walleij 2015-01-13 20:19 ` Bryan Wu 2015-01-13 20:19 ` Bryan Wu 2014-09-08 11:38 ` [PATCH 2/7 v6] leds: add device tree bindings for register bit LEDs Linus Walleij 2014-09-08 11:38 ` Linus Walleij 2014-09-08 11:38 ` [PATCH 3/7 v6] power: reset: driver for the Versatile syscon reboot Linus Walleij 2014-09-08 11:38 ` Linus Walleij 2014-09-12 8:55 ` Linus Walleij 2014-09-12 8:55 ` Linus Walleij 2014-09-15 16:06 ` Sebastian Reichel 2014-09-15 16:06 ` Sebastian Reichel [not found] ` <1410176286-32533-1-git-send-email-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2014-09-08 11:38 ` [PATCH 4/7 v6] soc: add driver for the ARM RealView Linus Walleij 2014-09-08 11:38 ` Linus Walleij 2014-09-08 11:38 ` Linus Walleij [this message] 2014-09-08 11:38 ` [PATCH 5/7 v6] ARM: l2c: parse 'cache-size' and 'cache-sets' properties Linus Walleij 2014-09-08 12:20 ` Arnd Bergmann 2014-09-08 12:20 ` Arnd Bergmann 2014-09-08 12:36 ` Linus Walleij 2014-09-08 12:36 ` Linus Walleij 2014-09-08 13:16 ` Arnd Bergmann 2014-09-08 13:16 ` Arnd Bergmann 2014-09-08 20:33 ` Florian Fainelli 2014-09-08 20:33 ` Florian Fainelli 2014-09-08 20:41 ` Arnd Bergmann 2014-09-08 20:41 ` Arnd Bergmann 2014-09-09 7:14 ` Linus Walleij 2014-09-09 7:14 ` Linus Walleij [not found] ` <CACRpkdb_bS0P-fGxogiyCzG9CRPhJK1Gro=H3X1Ks_-UoXh52w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2014-09-08 19:57 ` Florian Fainelli 2014-09-08 19:57 ` Florian Fainelli 2014-09-08 11:38 ` [PATCH 6/7 v6] ARM: l2x0: calculate associativity from ePAPR cache props Linus Walleij 2014-09-08 11:38 ` Linus Walleij 2014-09-08 12:15 ` Arnd Bergmann 2014-09-08 12:15 ` Arnd Bergmann 2014-09-08 12:43 ` Linus Walleij 2014-09-08 12:43 ` Linus Walleij 2014-09-08 13:18 ` Arnd Bergmann 2014-09-08 13:18 ` Arnd Bergmann 2014-09-08 11:38 ` [PATCH 7/7 v6] ARM: realview: basic device tree implementation Linus Walleij 2014-09-08 11:38 ` Linus Walleij
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