From: Michael Neuling <mikey@neuling.org> To: greg@kroah.com, arnd@arndb.de, mpe@ellerman.id.au, benh@kernel.crashing.org Cc: mikey@neuling.org, anton@samba.org, linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, jk@ozlabs.org, imunsie@au.ibm.com, cbe-oss-dev@lists.ozlabs.org Subject: [PATCH 02/15] powerpc/cell: Move data segment faulting code out of cell platform Date: Thu, 18 Sep 2014 18:26:47 +1000 [thread overview] Message-ID: <1411028820-29933-3-git-send-email-mikey@neuling.org> (raw) In-Reply-To: <1411028820-29933-1-git-send-email-mikey@neuling.org> From: Ian Munsie <imunsie@au1.ibm.com> __spu_trap_data_seg() currently contains code to determine the VSID and ESID required for a particular EA and mm struct. This code is generically useful for other co-processors. This moves the code of the cell platform so it can be used by other powerpc code. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> --- arch/powerpc/include/asm/mmu-hash64.h | 2 ++ arch/powerpc/mm/copro_fault.c | 48 ++++++++++++++++++++++++++++++++++ arch/powerpc/mm/slb.c | 3 --- arch/powerpc/platforms/cell/spu_base.c | 41 +++-------------------------- 4 files changed, 54 insertions(+), 40 deletions(-) diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index d765144..fd19a53 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -180,6 +180,8 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) * we work in all cases including 4k page size. */ #define VPN_SHIFT 12 +#define slb_vsid_shift(ssize) \ + ((ssize) == MMU_SEGSIZE_256M ? SLB_VSID_SHIFT : SLB_VSID_SHIFT_1T) /* * HPTE Large Page (LP) details diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c index ba7df14..4105a63 100644 --- a/arch/powerpc/mm/copro_fault.c +++ b/arch/powerpc/mm/copro_fault.c @@ -90,3 +90,51 @@ out_unlock: return ret; } EXPORT_SYMBOL_GPL(copro_handle_mm_fault); + +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid) +{ + int psize, ssize; + + *esid = (ea & ESID_MASK) | SLB_ESID_V; + + switch (REGION_ID(ea)) { + case USER_REGION_ID: + pr_devel("copro_data_segment: 0x%llx -- USER_REGION_ID\n", ea); +#ifdef CONFIG_PPC_MM_SLICES + psize = get_slice_psize(mm, ea); +#else + psize = mm->context.user_psize; +#endif + ssize = user_segment_size(ea); + *vsid = (get_vsid(mm->context.id, ea, ssize) + << slb_vsid_shift(ssize)) | SLB_VSID_USER + | (ssize == MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0); + break; + case VMALLOC_REGION_ID: + pr_devel("copro_data_segment: 0x%llx -- VMALLOC_REGION_ID\n", ea); + if (ea < VMALLOC_END) + psize = mmu_vmalloc_psize; + else + psize = mmu_io_psize; + *vsid = (get_kernel_vsid(ea, mmu_kernel_ssize) + << SLB_VSID_SHIFT) | SLB_VSID_KERNEL + | (mmu_kernel_ssize == MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0); + break; + case KERNEL_REGION_ID: + pr_devel("copro_data_segment: 0x%llx -- KERNEL_REGION_ID\n", ea); + psize = mmu_linear_psize; + *vsid = (get_kernel_vsid(ea, mmu_kernel_ssize) + << SLB_VSID_SHIFT) | SLB_VSID_KERNEL + | (mmu_kernel_ssize == MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0); + break; + default: + /* Future: support kernel segments so that drivers can use the + * CoProcessors */ + pr_debug("invalid region access at %016llx\n", ea); + return 1; + } + *vsid |= mmu_psize_defs[psize].sllp; + + return 0; +} +EXPORT_SYMBOL_GPL(copro_data_segment); diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c index 0399a67..6e450ca 100644 --- a/arch/powerpc/mm/slb.c +++ b/arch/powerpc/mm/slb.c @@ -46,9 +46,6 @@ static inline unsigned long mk_esid_data(unsigned long ea, int ssize, return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | slot; } -#define slb_vsid_shift(ssize) \ - ((ssize) == MMU_SEGSIZE_256M? SLB_VSID_SHIFT: SLB_VSID_SHIFT_1T) - static inline unsigned long mk_vsid_data(unsigned long ea, int ssize, unsigned long flags) { diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index 2930d1e..fe004b1 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -167,45 +167,12 @@ static inline void spu_load_slb(struct spu *spu, int slbe, struct spu_slb *slb) static int __spu_trap_data_seg(struct spu *spu, unsigned long ea) { - struct mm_struct *mm = spu->mm; struct spu_slb slb; - int psize; - - pr_debug("%s\n", __func__); - - slb.esid = (ea & ESID_MASK) | SLB_ESID_V; + int ret; - switch(REGION_ID(ea)) { - case USER_REGION_ID: -#ifdef CONFIG_PPC_MM_SLICES - psize = get_slice_psize(mm, ea); -#else - psize = mm->context.user_psize; -#endif - slb.vsid = (get_vsid(mm->context.id, ea, MMU_SEGSIZE_256M) - << SLB_VSID_SHIFT) | SLB_VSID_USER; - break; - case VMALLOC_REGION_ID: - if (ea < VMALLOC_END) - psize = mmu_vmalloc_psize; - else - psize = mmu_io_psize; - slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) - << SLB_VSID_SHIFT) | SLB_VSID_KERNEL; - break; - case KERNEL_REGION_ID: - psize = mmu_linear_psize; - slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) - << SLB_VSID_SHIFT) | SLB_VSID_KERNEL; - break; - default: - /* Future: support kernel segments so that drivers - * can use SPUs. - */ - pr_debug("invalid region access at %016lx\n", ea); - return 1; - } - slb.vsid |= mmu_psize_defs[psize].sllp; + ret = copro_data_segment(spu->mm, ea, &slb.esid, &slb.vsid); + if (ret) + return ret; spu_load_slb(spu, spu->slb_replace, &slb); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Neuling <mikey@neuling.org> To: greg@kroah.com, arnd@arndb.de, mpe@ellerman.id.au, benh@kernel.crashing.org Cc: cbe-oss-dev@lists.ozlabs.org, mikey@neuling.org, imunsie@au.ibm.com, linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, jk@ozlabs.org, anton@samba.org Subject: [PATCH 02/15] powerpc/cell: Move data segment faulting code out of cell platform Date: Thu, 18 Sep 2014 18:26:47 +1000 [thread overview] Message-ID: <1411028820-29933-3-git-send-email-mikey@neuling.org> (raw) In-Reply-To: <1411028820-29933-1-git-send-email-mikey@neuling.org> From: Ian Munsie <imunsie@au1.ibm.com> __spu_trap_data_seg() currently contains code to determine the VSID and ESID required for a particular EA and mm struct. This code is generically useful for other co-processors. This moves the code of the cell platform so it can be used by other powerpc code. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> --- arch/powerpc/include/asm/mmu-hash64.h | 2 ++ arch/powerpc/mm/copro_fault.c | 48 ++++++++++++++++++++++++++++++++++ arch/powerpc/mm/slb.c | 3 --- arch/powerpc/platforms/cell/spu_base.c | 41 +++-------------------------- 4 files changed, 54 insertions(+), 40 deletions(-) diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index d765144..fd19a53 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -180,6 +180,8 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) * we work in all cases including 4k page size. */ #define VPN_SHIFT 12 +#define slb_vsid_shift(ssize) \ + ((ssize) == MMU_SEGSIZE_256M ? SLB_VSID_SHIFT : SLB_VSID_SHIFT_1T) /* * HPTE Large Page (LP) details diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c index ba7df14..4105a63 100644 --- a/arch/powerpc/mm/copro_fault.c +++ b/arch/powerpc/mm/copro_fault.c @@ -90,3 +90,51 @@ out_unlock: return ret; } EXPORT_SYMBOL_GPL(copro_handle_mm_fault); + +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid) +{ + int psize, ssize; + + *esid = (ea & ESID_MASK) | SLB_ESID_V; + + switch (REGION_ID(ea)) { + case USER_REGION_ID: + pr_devel("copro_data_segment: 0x%llx -- USER_REGION_ID\n", ea); +#ifdef CONFIG_PPC_MM_SLICES + psize = get_slice_psize(mm, ea); +#else + psize = mm->context.user_psize; +#endif + ssize = user_segment_size(ea); + *vsid = (get_vsid(mm->context.id, ea, ssize) + << slb_vsid_shift(ssize)) | SLB_VSID_USER + | (ssize == MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0); + break; + case VMALLOC_REGION_ID: + pr_devel("copro_data_segment: 0x%llx -- VMALLOC_REGION_ID\n", ea); + if (ea < VMALLOC_END) + psize = mmu_vmalloc_psize; + else + psize = mmu_io_psize; + *vsid = (get_kernel_vsid(ea, mmu_kernel_ssize) + << SLB_VSID_SHIFT) | SLB_VSID_KERNEL + | (mmu_kernel_ssize == MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0); + break; + case KERNEL_REGION_ID: + pr_devel("copro_data_segment: 0x%llx -- KERNEL_REGION_ID\n", ea); + psize = mmu_linear_psize; + *vsid = (get_kernel_vsid(ea, mmu_kernel_ssize) + << SLB_VSID_SHIFT) | SLB_VSID_KERNEL + | (mmu_kernel_ssize == MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0); + break; + default: + /* Future: support kernel segments so that drivers can use the + * CoProcessors */ + pr_debug("invalid region access at %016llx\n", ea); + return 1; + } + *vsid |= mmu_psize_defs[psize].sllp; + + return 0; +} +EXPORT_SYMBOL_GPL(copro_data_segment); diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c index 0399a67..6e450ca 100644 --- a/arch/powerpc/mm/slb.c +++ b/arch/powerpc/mm/slb.c @@ -46,9 +46,6 @@ static inline unsigned long mk_esid_data(unsigned long ea, int ssize, return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | slot; } -#define slb_vsid_shift(ssize) \ - ((ssize) == MMU_SEGSIZE_256M? SLB_VSID_SHIFT: SLB_VSID_SHIFT_1T) - static inline unsigned long mk_vsid_data(unsigned long ea, int ssize, unsigned long flags) { diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index 2930d1e..fe004b1 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -167,45 +167,12 @@ static inline void spu_load_slb(struct spu *spu, int slbe, struct spu_slb *slb) static int __spu_trap_data_seg(struct spu *spu, unsigned long ea) { - struct mm_struct *mm = spu->mm; struct spu_slb slb; - int psize; - - pr_debug("%s\n", __func__); - - slb.esid = (ea & ESID_MASK) | SLB_ESID_V; + int ret; - switch(REGION_ID(ea)) { - case USER_REGION_ID: -#ifdef CONFIG_PPC_MM_SLICES - psize = get_slice_psize(mm, ea); -#else - psize = mm->context.user_psize; -#endif - slb.vsid = (get_vsid(mm->context.id, ea, MMU_SEGSIZE_256M) - << SLB_VSID_SHIFT) | SLB_VSID_USER; - break; - case VMALLOC_REGION_ID: - if (ea < VMALLOC_END) - psize = mmu_vmalloc_psize; - else - psize = mmu_io_psize; - slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) - << SLB_VSID_SHIFT) | SLB_VSID_KERNEL; - break; - case KERNEL_REGION_ID: - psize = mmu_linear_psize; - slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) - << SLB_VSID_SHIFT) | SLB_VSID_KERNEL; - break; - default: - /* Future: support kernel segments so that drivers - * can use SPUs. - */ - pr_debug("invalid region access at %016lx\n", ea); - return 1; - } - slb.vsid |= mmu_psize_defs[psize].sllp; + ret = copro_data_segment(spu->mm, ea, &slb.esid, &slb.vsid); + if (ret) + return ret; spu_load_slb(spu, spu->slb_replace, &slb); -- 1.9.1
next prev parent reply other threads:[~2014-09-18 8:33 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-18 8:26 [PATCH 0/15] POWER8 Coherent Accelerator device driver Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 01/15] powerpc/cell: Move spu_handle_mm_fault() out of cell platform Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 10:00 ` Jeremy Kerr 2014-09-18 10:00 ` Jeremy Kerr 2014-09-18 23:26 ` Michael Neuling 2014-09-18 23:26 ` Michael Neuling 2014-09-26 3:57 ` Anton Blanchard 2014-09-26 3:57 ` Anton Blanchard 2014-09-18 8:26 ` Michael Neuling [this message] 2014-09-18 8:26 ` [PATCH 02/15] powerpc/cell: Move data segment faulting code " Michael Neuling 2014-09-18 10:27 ` Jeremy Kerr 2014-09-18 10:27 ` Jeremy Kerr 2014-09-18 23:45 ` Michael Neuling 2014-09-18 23:45 ` Michael Neuling 2014-09-26 4:05 ` Anton Blanchard 2014-09-26 4:05 ` Anton Blanchard 2014-09-26 11:19 ` Michael Neuling 2014-09-26 11:19 ` Michael Neuling 2014-09-29 8:30 ` Aneesh Kumar K.V 2014-09-29 8:30 ` Aneesh Kumar K.V 2014-09-30 4:40 ` Michael Neuling 2014-09-30 4:40 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 03/15] powerpc/msi: Improve IRQ bitmap allocator Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-19 20:16 ` Scott Wood 2014-09-19 20:16 ` Scott Wood 2014-09-19 20:19 ` Scott Wood 2014-09-19 20:19 ` Scott Wood 2014-09-22 8:26 ` Laurentiu Tudor 2014-09-22 8:26 ` Laurentiu Tudor 2014-09-22 23:50 ` Scott Wood 2014-09-22 23:50 ` Scott Wood 2014-09-22 8:25 ` Laurentiu Tudor 2014-09-22 8:25 ` Laurentiu Tudor 2014-09-22 8:29 ` Laurentiu Tudor 2014-09-22 8:29 ` Laurentiu Tudor 2014-09-22 22:59 ` Michael Neuling 2014-09-22 22:59 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 04/15] powerpc/mm: Export mmu_kernel_ssize and mmu_linear_psize Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 05/15] powerpc/powernv: Split out set MSI IRQ chip code Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-19 6:54 ` Gavin Shan 2014-09-19 6:54 ` Gavin Shan 2014-09-22 4:31 ` Michael Neuling 2014-09-22 4:31 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 06/15] cxl: Add new header for call backs and structs Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 07/15] powerpc/powerpc: Add new PCIe functions for allocating cxl interrupts Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-19 7:09 ` Gavin Shan 2014-09-19 7:09 ` Gavin Shan 2014-09-22 5:01 ` Michael Neuling 2014-09-22 5:01 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 08/15] powerpc/mm: Add new hash_page_mm() Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-29 8:50 ` Aneesh Kumar K.V 2014-09-29 8:50 ` Aneesh Kumar K.V [not found] ` <1412054407.1733.77.camel@ale.ozlabs.ibm.com> 2014-09-30 6:13 ` Michael Neuling 2014-09-30 6:13 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 09/15] powerpc/opal: Add PHB to cxl mode call Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-26 4:35 ` Anton Blanchard 2014-09-26 4:35 ` Anton Blanchard 2014-09-18 8:26 ` [PATCH 10/15] powerpc/mm: Add hooks for cxl Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-26 4:33 ` Anton Blanchard 2014-09-26 4:33 ` Anton Blanchard 2014-09-26 11:33 ` Michael Neuling 2014-09-26 11:33 ` Michael Neuling 2014-09-26 13:24 ` Anton Blanchard 2014-09-26 13:24 ` Anton Blanchard 2014-09-29 9:10 ` Aneesh Kumar K.V 2014-09-29 9:10 ` Aneesh Kumar K.V 2014-09-18 8:26 ` [PATCH 11/15] cxl: Add base builtin support Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 12/15] cxl: Driver code for powernv PCIe based cards for userspace access Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 13/15] cxl: Userspace header file Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:26 ` [PATCH 14/15] cxl: Add driver to Kbuild and Makefiles Michael Neuling 2014-09-18 8:26 ` Michael Neuling 2014-09-18 8:27 ` [PATCH 15/15] cxl: Add documentation for userspace APIs Michael Neuling 2014-09-18 8:27 ` Michael Neuling
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