[U-Boot] [PATCH v2 00/10] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[U-Boot] [PATCH v2 00/10] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Chen-Yu Tsai]

Hi everyone,

This is v2 of the A31 support series. This series add basic (UART and MMC)
support for Allwinner's A31 SoC. The patches, excluding the first one,
were cherry-picked from u-boot-sunxi. Due to the difference between u-boot
mainline and u-boot-sunxi, some patches were rearranged or squashed to
better fit the current state of u-boot, and not introduce any build breaks.
It follows Ian's initial merge method of sun7i support: introducing various
components first, then enabling them in the last commit. I tried to keep
the commits separate, thus retaining the original author and Signed-off-bys.

Patch 1 updates the current UART pinmuxing code to use macros for pull-up
values. This is for existing platforms, but is included as it would conflict
with patch 7.

Patch 2 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
to deal with breakage when USB support is not enabled.

Patch 3 adds memory addresses for some hardware blocks new in sun6i.

Patch 4 adds support for the new PRCM (power reset and clock management)
block, which also contains PLL bias voltage control.

Patch 5 adds support for the clock module. This patch is a bunch of
different sun6i related patches on the clock code, from when sun6i
support was introduced to u-boot-sunxi, up to its current form.
This is done to avoid various conflicts and needlessly introducing
then removing macros.

Patch 6 adds mmc support on sun6i.

Patch 7 adds uart0 pin macros.

Patch 8 adds uart0 muxing on sun6i.

Patch 9 enables sun6i support.

Patch 10 adds a defconfig for the Colombus board, which is an A31
evaluation board.


Changes since v1:

  - Added macros for sun6i uart pinmuxes (patch 7)

  - Use gpio macros when muxing uarts (patch 1, 8)

  - Clarify what is enabled in PRCM (patch 4)

  - Dropped old comments in commit message from Hans (patch 4)

  - Use setbits helpers in PRCM code (patch 4)

  - Drop SPL code block from clock code (patch 5)

  - Make mmc code use fifo in register structure definition, and
    add reserved area to adjust for sun6i's different fifo address
    (patch 6)

  - Rewrite patch 9 commit message to reflect what is supported

  - Split out Colombus board defconfig into separate patch (patch 10)


Cheers
ChenYu


Chen-Yu Tsai (5):
  ARM: sunxi: Use macro values for setting UART GPIO pull-ups
  ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
  ARM: sun6i: Add clock support
  ARM: sun6i: Define UART0 pins for A31
  ARM: sun6i: Add Colombus board defconfig

Hans de Goede (1):
  ARM: sunxi-mmc: Add mmc support for sun6i / A31

Maxime Ripard (2):
  ARM: sun6i: Setup the A31 UART0 muxing
  ARM: sunxi: Add basic A31 support

Oliver Schinagl (2):
  ARM: sun6i: Add base address for the new controllers in A31
  ARM: sun6i: Add support for the power reset control module found on
    the A31

 arch/arm/Kconfig                              |   3 +
 arch/arm/cpu/armv7/sunxi/Makefile             |   2 +
 arch/arm/cpu/armv7/sunxi/board.c              |  10 +-
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        |  70 ++++++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c           |   2 +
 arch/arm/cpu/armv7/sunxi/prcm.c               |  33 ++++
 arch/arm/include/asm/arch-sunxi/clock.h       |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/cpu.h         |   9 +
 arch/arm/include/asm/arch-sunxi/gpio.h        |   3 +
 arch/arm/include/asm/arch-sunxi/mmc.h         |   5 +-
 arch/arm/include/asm/arch-sunxi/prcm.h        | 238 ++++++++++++++++++++++++++
 board/sunxi/Kconfig                           |  10 +-
 configs/Colombus_defconfig                    |   4 +
 drivers/mmc/sunxi_mmc.c                       |  11 +-
 include/configs/sun6i.h                       |  26 +++
 include/configs/sunxi-common.h                |   8 +-
 17 files changed, 633 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h
 create mode 100644 configs/Colombus_defconfig
 create mode 100644 include/configs/sun6i.h

-- 
2.1.0

[U-Boot] [PATCH v2 01/10] ARM: sunxi: Use macro values for setting UART GPIO pull-ups

[Chen-Yu Tsai]

We have already defined macros for pull-up/down values in the
GPIO header. Use them instead of magic numbers when configuring
the UART pins.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/board.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f2cedbb..95a74c5 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -53,15 +53,15 @@ int gpio_init(void)
 #if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
-- 
2.1.0

[U-Boot] [PATCH v2 02/10] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Chen-Yu Tsai]

BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
 include/configs/sunxi-common.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d947d7..a31656e 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -233,10 +233,16 @@
 #define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 
+#ifdef CONFIG_USB_EHCI
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
-	func(USB, usb, 0) \
+	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 
-- 
2.1.0

[U-Boot] [PATCH v2 03/10] ARM: sun6i: Add base address for the new controllers in A31

[Chen-Yu Tsai]

From: Oliver Schinagl <oliver@schinagl.nl>

A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/include/asm/arch-sunxi/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index a987e51d..313e6c8 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -95,6 +95,11 @@
 #define SUNXI_MALI400_BASE		0x01c40000
 #define SUNXI_GMAC_BASE			0x01c50000
 
+#define SUNXI_DRAM_COM_BASE		0x01c62000
+#define SUNXI_DRAM_CTL_BASE		0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
 
@@ -105,6 +110,10 @@
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#define SUNXI_PRCM_BASE			0x01f01400
+#define SUNXI_R_PIO_BASE		0x01f02c00
+#define SUNXI_P2WI_BASE			0x01f03400
+
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE			0x3f500000
 
-- 
2.1.0

[U-Boot] [PATCH v2 04/10] ARM: sun6i: Add support for the power reset control module found on the A31

[Chen-Yu Tsai]

From: Oliver Schinagl <oliver@schinagl.nl>

The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: spacing fixes reported by checkpatch.pl]
[wens at csie.org: Use setbits helper in PRCM init function]
[wens at csie.org: rephrase commit message to explain what the hardware
		supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/prcm.c        |  33 +++++
 arch/arm/include/asm/arch-sunxi/prcm.h | 238 +++++++++++++++++++++++++++++++++
 3 files changed, 272 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index e9721b2..f0473d2 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
+obj-$(CONFIG_SUN6I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644
index 0000000..7b3ee89
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -0,0 +1,33 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void prcm_init_apb0(void)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
+				       PRCM_APB0_GATE_PIO);
+	setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
+					PRCM_APB0_RESET_PIO);
+}
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 0000000..1b40f09
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,238 @@
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+	__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+	__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+	__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
+#define PRCM_PLL_CTRL_USB_CLK_0 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
+#define PRCM_PLL_CTRL_USB_CLK_1 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
+#define PRCM_PLL_CTRL_USB_CLK_2 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
+#define PRCM_PLL_CTRL_USB_CLK_3 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
+#define PRCM_PLL_CTRL_HOSC_CLK_0 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
+#define PRCM_PLL_CTRL_HOSC_CLK_1 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
+#define PRCM_PLL_CTRL_HOSC_CLK_2 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
+#define PRCM_PLL_CTRL_HOSC_CLK_3 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
+#define PRCM_PLL_CTRL_LDO_OUT_MASK \
+	__PRCM_PLL_CTRL_LDO_OUT(0x7)
+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+
+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
+
+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
+#define __PRCM_CLK_OUTD_SRC_ERR 0x3
+#define PRCM_CLK_OUTD_SRC_LOSC2 \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
+#define PRCM_CLK_OUTD_SRC_LOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
+#define PRCM_CLK_OUTD_SRC_HOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
+#define PRCM_CLK_OUTD_SRC_ERR \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
+#define PRCM_CLK_OUTD_EN (0x1 << 31)
+
+#define PRCM_CPU0_PWROFF (0x1 << 0)
+#define PRCM_CPU1_PWROFF (0x1 << 1)
+#define PRCM_CPU2_PWROFF (0x1 << 2)
+#define PRCM_CPU3_PWROFF (0x1 << 3)
+#define PRCM_CPU_ALL_PWROFF (0xf << 0)
+
+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
+
+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
+
+#define PRCM_VDD_SYS_RESET (0x1 << 0)
+
+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
+
+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
+
+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+
+#ifndef __ASSEMBLY__
+struct sunxi_prcm_reg {
+	u32 cpus_cfg;		/* 0x000 */
+	u8 res0[0x8];		/* 0x004 */
+	u32 apb0_ratio;		/* 0x00c */
+	u32 cpu0_cfg;		/* 0x010 */
+	u32 cpu1_cfg;		/* 0x014 */
+	u32 cpu2_cfg;		/* 0x018 */
+	u32 cpu3_cfg;		/* 0x01c */
+	u8 res1[0x8];		/* 0x020 */
+	u32 apb0_gate;		/* 0x028 */
+	u8 res2[0x14];		/* 0x02c */
+	u32 pll_ctrl0;		/* 0x040 */
+	u32 pll_ctrl1;		/* 0x044 */
+	u8 res3[0x8];		/* 0x048 */
+	u32 clk_1wire;		/* 0x050 */
+	u32 clk_ir;		/* 0x054 */
+	u8 res4[0x58];		/* 0x058 */
+	u32 apb0_reset;		/* 0x0b0 */
+	u8 res5[0x3c];		/* 0x0b4 */
+	u32 clk_outd;		/* 0x0f0 */
+	u8 res6[0xc];		/* 0x0f4 */
+	u32 cpu_pwroff;		/* 0x100 */
+	u8 res7[0xc];		/* 0x104 */
+	u32 vdd_sys_pwroff;	/* 0x110 */
+	u8 res8[0x4];		/* 0x114 */
+	u32 gpu_pwroff;		/* 0x118 */
+	u8 res9[0x4];		/* 0x11c */
+	u32 vdd_pwr_reset;	/* 0x120 */
+	u8 res10[0x20];		/* 0x124 */
+	u32 cpu1_pwr_clamp;	/* 0x144 */
+	u32 cpu2_pwr_clamp;	/* 0x148 */
+	u32 cpu3_pwr_clamp;	/* 0x14c */
+	u8 res11[0x30];		/* 0x150 */
+	u32 dram_pwr;		/* 0x180 */
+	u8 res12[0xc];		/* 0x184 */
+	u32 dram_tst;		/* 0x190 */
+};
+
+void prcm_init_apb0(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _PRCM_H */
-- 
2.1.0

[U-Boot] [PATCH v2 05/10] ARM: sun6i: Add clock support

[Chen-Yu Tsai]

This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: styling fixes reported by checkpatch.pl]
[wens at csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
---
 arch/arm/cpu/armv7/sunxi/Makefile             |   1 +
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        |  70 +++++++++
 arch/arm/include/asm/arch-sunxi/clock.h       |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++++++
 4 files changed, 280 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index f0473d2..2a42dca 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,6 +14,7 @@ obj-y	+= pinmux.o
 obj-$(CONFIG_SUN6I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
new file mode 100644
index 0000000..8387b93
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -0,0 +1,70 @@
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* uart clock source is apb2 */
+	writel(APB2_CLK_SRC_OSC24M|
+	       APB2_CLK_RATE_N_1|
+	       APB2_CLK_RATE_M(1),
+	       &ccm->apb2_div);
+
+	/* open the clock for uart */
+	setbits_le32(&ccm->apb2_gate,
+		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+				       CONFIG_CONS_INDEX - 1));
+
+	/* deassert uart reset */
+	setbits_le32(&ccm->apb2_reset_cfg,
+		     1 << (APB2_RESET_UART_SHIFT +
+			   CONFIG_CONS_INDEX - 1));
+
+	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port > 3)
+		return -1;
+
+	/* set the apb clock gate for twi */
+	if (state)
+		setbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+	else
+		clrbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+
+	return 0;
+}
+
+unsigned int clock_get_pll6(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	uint32_t rval = readl(&ccm->pll6_cfg);
+	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+	return 24000000 * n * k / 2;
+}
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 5669f39..8f5d860 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,7 +15,11 @@
 #define CLK_GATE_CLOSE			0x0
 
 /* clock control module regs definition */
+#ifdef CONFIG_SUN6I
+#include <asm/arch/clock_sun6i.h>
+#else
 #include <asm/arch/clock_sun4i.h>
+#endif
 
 #ifndef __ASSEMBLY__
 int clock_init(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
new file mode 100644
index 0000000..1397b35
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -0,0 +1,205 @@
+/*
+ * sun6i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN6I_H
+#define _SUNXI_CLOCK_SUN6I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x00 pll1 control */
+	u32 reserved0;
+	u32 pll2_cfg;		/* 0x08 pll2 control */
+	u32 reserved1;
+	u32 pll3_cfg;		/* 0x10 pll3 control */
+	u32 reserved2;
+	u32 pll4_cfg;		/* 0x18 pll4 control */
+	u32 reserved3;
+	u32 pll5_cfg;		/* 0x20 pll5 control */
+	u32 reserved4;
+	u32 pll6_cfg;		/* 0x28 pll6 control */
+	u32 reserved5;
+	u32 pll7_cfg;		/* 0x30 pll7 control */
+	u32 reserved6;
+	u32 pll8_cfg;		/* 0x38 pll8 control */
+	u32 reserved7;
+	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
+	u32 pll9_cfg;		/* 0x44 pll9 control */
+	u32 pll10_cfg;		/* 0x48 pll10 control */
+	u32 reserved8;
+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
+	u32 axi_gate;		/* 0x5c axi module clock gating */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
+	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
+	u32 reserved9[4];
+	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
+	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
+	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
+	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
+	u32 reserved10[2];
+	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
+	u32 reserved11[2];
+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
+	u32 reserved12[7];
+	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
+	u32 reserved13[2];
+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
+	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
+	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
+	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
+	u32 mp_clk_cfg;		/* 0x114 MP module clock */
+	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
+	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
+	u32 reserved14[3];
+	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
+	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
+	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
+	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
+	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
+	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
+	u32 reserved15;
+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+	u32 ps_clk_cfg;		/* 0x154 PS module clock */
+	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
+	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
+	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+	u32 reserved16;
+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
+	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
+	u32 reserved17[4];
+	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
+	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
+	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
+	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
+	u32 reserved18[4];
+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
+	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
+	u32 reserved19[21];
+	u32 pll_lock;		/* 0x200 PLL Lock Time */
+	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
+	u32 reserved20[6];
+	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
+	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
+	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
+	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
+	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
+	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
+	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
+	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
+	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
+	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
+	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
+	u32 reserved21[13];
+	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
+	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
+	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
+	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
+	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
+	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
+	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
+	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
+	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
+	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
+	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
+	u32 reserved22[5];
+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
+	u32 reserved23;
+	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
+	u32 reserved24;
+	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC		(0x0 << 24)
+#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
+#define APB2_CLK_SRC_PLL6		(0x2 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 16)
+#define APB2_CLK_RATE_N_2		(0x1 << 16)
+#define APB2_CLK_RATE_N_4		(0x2 << 16)
+#define APB2_CLK_RATE_N_8		(0x3 << 16)
+#define APB2_CLK_RATE_N_MASK		(3 << 16)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT	(16)
+#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT	(0)
+#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT			0
+#define ATB_DIV_SHIFT			8
+#define CPU_CLK_SRC_SHIFT		16
+
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define ATB_DIV_1			0
+#define ATB_DIV_2			1
+#define ATB_DIV_4			2
+#define CPU_CLK_SRC_OSC24M		1
+#define CPU_CLK_SRC_PLL1		2
+
+#define PLL1_CFG_DEFAULT		0x90011b21
+
+#define PLL6_CFG_DEFAULT		0x90041811
+
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT		4
+#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define AHB_GATE_OFFSET_MMC3		11
+#define AHB_GATE_OFFSET_MMC2		10
+#define AHB_GATE_OFFSET_MMC1		9
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6   (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define AHB_RESET_OFFSET_MMC3		11
+#define AHB_RESET_OFFSET_MMC2		10
+#define AHB_RESET_OFFSET_MMC1		9
+#define AHB_RESET_OFFSET_MMC0		8
+#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT		(16)
+#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT		(0)
+#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
+
+#endif /* _SUNXI_CLOCK_SUN6I_H */
-- 
2.1.0

[U-Boot] [PATCH v2 06/10] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Chen-Yu Tsai]

From: Hans de Goede <hdegoede@redhat.com>

The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
		rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
 drivers/mmc/sunxi_mmc.c               | 11 +++++++----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 53196e3..6a31184 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,10 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-	u32 fifo;		/* 0x100 FIFO access address */
+#if defined(CONFIG_SUN6I)
+	u32 res2[64];
+#endif
+	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
 };
 
 #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index d4e574f..1982988 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -19,7 +19,6 @@
 struct sunxi_mmc_host {
 	unsigned mmc_no;
 	uint32_t *mclkreg;
-	unsigned database;
 	unsigned fatal_err;
 	unsigned mod_clk;
 	struct sunxi_mmc *reg;
@@ -57,7 +56,6 @@ static int mmc_resource_init(int sdc_no)
 		printf("Wrong mmc number %d\n", sdc_no);
 		return -1;
 	}
-	mmchost->database = (unsigned int)mmchost->reg + 0x100;
 	mmchost->mmc_no = sdc_no;
 
 	return 0;
@@ -75,6 +73,11 @@ static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
+#if defined(CONFIG_SUN6I)
+	/* unassert reset */
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+
 	/* config mod clock */
 	pll_clk = clock_get_pll6();
 	/* should be close to 100 MHz but no more, so round up */
@@ -194,9 +197,9 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 		}
 
 		if (reading)
-			buff[i] = readl(mmchost->database);
+			buff[i] = readl(&mmchost->reg->fifo);
 		else
-			writel(buff[i], mmchost->database);
+			writel(buff[i], &mmchost->reg->fifo);
 	}
 
 	return 0;
-- 
2.1.0

[U-Boot] [PATCH v2 07/10] ARM: sun6i: Define UART0 pins for A31

[Chen-Yu Tsai]

UART0 is the default debug/console UART on the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f7f3d8c..ba7e69b 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -132,6 +132,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPH22_SDC1	5
 
+#define SUN6I_GPH20_UART0_TX	2
+#define SUN6I_GPH21_UART0_RX	2
+
 #define SUN4I_GPI4_SDC3		2
 
 /* GPIO pin pull-up/down config */
-- 
2.1.0

[U-Boot] [PATCH v2 08/10] ARM: sun6i: Setup the A31 UART0 muxing

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
[wens at csie.org: reorder #ifs by SUN?I]
[wens at csie.org: replace magic numbers with GPIO definitions]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 95a74c5..b6d63db 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -58,6 +58,10 @@ int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-- 
2.1.0

[U-Boot] [PATCH v2 09/10] ARM: sunxi: Add basic A31 support

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

Add a new sun6i machine that supports UART and MMC.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
		around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/Kconfig                    |  3 +++
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  2 ++
 board/sunxi/Kconfig                 | 10 +++++++++-
 include/configs/sun6i.h             | 26 ++++++++++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/sun6i.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22f0f09..bfbe6f1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -439,6 +439,9 @@ config TARGET_SUN4I
 config TARGET_SUN5I
 	bool "Support sun5i"
 
+config TARGET_SUN6I
+	bool "Support sun6i"
+
 config TARGET_SUN7I
 	bool "Support sun7i"
 
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 5cf35ac..40c4e13 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -23,6 +23,8 @@ int print_cpuinfo(void)
 	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
 	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
 	}
+#elif defined CONFIG_SUN6I
+	puts("CPU:   Allwinner A31 (SUN6I)\n");
 #elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
 #else
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 7bdf958..c78750e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -14,6 +14,14 @@ config SYS_CONFIG_NAME
 
 endif
 
+if TARGET_SUN6I
+
+config SYS_CONFIG_NAME
+	string
+	default "sun6i"
+
+endif
+
 if TARGET_SUN7I
 
 config SYS_CONFIG_NAME
@@ -22,7 +30,7 @@ config SYS_CONFIG_NAME
 
 endif
 
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
 
 config SYS_CPU
 	string
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
new file mode 100644
index 0000000..93a1d96
--- /dev/null
+++ b/include/configs/sun6i.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+#define CONFIG_SUN6I		/* sun6i SoC generation */
+
+#define CONFIG_SYS_PROMPT		"sun6i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
-- 
2.1.0

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Chen-Yu Tsai]

The Colombus board is an A31 evaluation board from WITS Technology.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 configs/Colombus_defconfig | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 configs/Colombus_defconfig

diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
new file mode 100644
index 0000000..16800de
--- /dev/null
+++ b/configs/Colombus_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
+CONFIG_ARM=y
+CONFIG_TARGET_SUN6I=y
+CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
-- 
2.1.0

[U-Boot] [PATCH v2 01/10] ARM: sunxi: Use macro values for setting UART GPIO pull-ups

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> We have already defined macros for pull-up/down values in the
> GPIO header. Use them instead of magic numbers when configuring
> the UART pins.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH v2 04/10] ARM: sun6i: Add support for the power reset control module found on the A31

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> From: Oliver Schinagl <oliver@schinagl.nl>
> 
> The A31 has a new module called PRCM, or Power, Reset Control Module.
> This module controls clocks and resets for RTC block modules, and also
> PLL biasing in the main clock module.
> 
> This patch adds the register definitions, and also enables the clocks
> and resets for the RTC block PIO (pin controller) and P2WI (push-pull
> 2 wire interface) which is used to talk to the PMIC.
> 
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: spacing fixes reported by checkpatch.pl]
> [wens at csie.org: Use setbits helper in PRCM init function]
> [wens at csie.org: rephrase commit message to explain what the hardware
> 		supports and what we actually enable]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH v2 05/10] ARM: sun6i: Add clock support

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> This patch adds the basic clocks support for the Allwinner A31 (sun6i)
> processor. This code will not been compiled until the build is hooked
> up in a later patch. It has been split out to keep the patches manageable.
> 
> This includes changes from the following commits from u-boot-sunxi:
> 
> a92051b ARM: sunxi: Add sun6i clock controller structure
> 1f72c6f ARM: sun6i: Setup the UART0 clocks
> 5f2e712 ARM: sunxi: Enable pll6 by default on all models
> 2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
> 12e1633 ARM: sun6i: Add initial clock setup for SPL
> 1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
> 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
> b54c626 sunxi: avoid sr32 for APB1 clock setup.
> 68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
> c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
> 501ab1e ARM: sunxi: Fix sun6i PLL6 settings
> 37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
> 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: styling fixes reported by checkpatch.pl]
> [wens at csie.org: drop unsupported SPL code block and unused gpio.h header]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Cc: Tom Cubie <Mr.hipboi@gmail.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

(my contributions to what became this patch were minor enough that I
think this doesn't constitute a double dealing self-ack, if that might
have been a problem)

[U-Boot] [PATCH v2 06/10] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> From: Hans de Goede <hdegoede@redhat.com>
> 
> The mmc hardware on sun6i has an extra reset control that needs to
> be de-asserted prior to usage. Also the FIFO address is different.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
> 		rewrite different FIFO address handling, add commit message]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

Pantelis, unless you object I'd like to eventually take this into
u-boot-sunxi.git#next and merge for v2015.04.

> ---
>  arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
>  drivers/mmc/sunxi_mmc.c               | 11 +++++++----
>  2 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
> index 53196e3..6a31184 100644
> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -43,7 +43,10 @@ struct sunxi_mmc {
>  	u32 chda;		/* 0x90 */
>  	u32 cbda;		/* 0x94 */
>  	u32 res1[26];
> -	u32 fifo;		/* 0x100 FIFO access address */
> +#if defined(CONFIG_SUN6I)
> +	u32 res2[64];
> +#endif
> +	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
>  };
>  
>  #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index d4e574f..1982988 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -19,7 +19,6 @@
>  struct sunxi_mmc_host {
>  	unsigned mmc_no;
>  	uint32_t *mclkreg;
> -	unsigned database;
>  	unsigned fatal_err;
>  	unsigned mod_clk;
>  	struct sunxi_mmc *reg;
> @@ -57,7 +56,6 @@ static int mmc_resource_init(int sdc_no)
>  		printf("Wrong mmc number %d\n", sdc_no);
>  		return -1;
>  	}
> -	mmchost->database = (unsigned int)mmchost->reg + 0x100;
>  	mmchost->mmc_no = sdc_no;
>  
>  	return 0;
> @@ -75,6 +73,11 @@ static int mmc_clk_io_on(int sdc_no)
>  	/* config ahb clock */
>  	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
>  
> +#if defined(CONFIG_SUN6I)
> +	/* unassert reset */
> +	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
> +#endif
> +
>  	/* config mod clock */
>  	pll_clk = clock_get_pll6();
>  	/* should be close to 100 MHz but no more, so round up */
> @@ -194,9 +197,9 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
>  		}
>  
>  		if (reading)
> -			buff[i] = readl(mmchost->database);
> +			buff[i] = readl(&mmchost->reg->fifo);
>  		else
> -			writel(buff[i], mmchost->database);
> +			writel(buff[i], &mmchost->reg->fifo);
>  	}
>  
>  	return 0;

[U-Boot] [PATCH v2 07/10] ARM: sun6i: Define UART0 pins for A31

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> UART0 is the default debug/console UART on the A31.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH v2 08/10] ARM: sun6i: Setup the A31 UART0 muxing

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> From: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
> [wens at csie.org: reorder #ifs by SUN?I]
> [wens at csie.org: replace magic numbers with GPIO definitions]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH v2 09/10] ARM: sunxi: Add basic A31 support

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> From: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Add a new sun6i machine that supports UART and MMC.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
> 		around mmc and smp code, drop MACH_TYPE]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Ian Campbell]

On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> The Colombus board is an A31 evaluation board from WITS Technology.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

> ---
>  configs/Colombus_defconfig | 4 ++++
>  1 file changed, 4 insertions(+)
>  create mode 100644 configs/Colombus_defconfig
> 
> diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
> new file mode 100644
> index 0000000..16800de
> --- /dev/null
> +++ b/configs/Colombus_defconfig
> @@ -0,0 +1,4 @@
> +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"

Does this do anything other than define an unused #define?

Ah, I suppose eventually it will cause the inclusion of a suitable dram
file. Really ought to start moving things out of SYS_EXTRA though, but I
don't think you need to shave that yakk just to get this patch in, so:

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Ian Campbell]

On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> > The Colombus board is an A31 evaluation board from WITS Technology.
> > 
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> 
> > ---
> >  configs/Colombus_defconfig | 4 ++++
> >  1 file changed, 4 insertions(+)
> >  create mode 100644 configs/Colombus_defconfig
> > 
> > diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
> > new file mode 100644
> > index 0000000..16800de
> > --- /dev/null
> > +++ b/configs/Colombus_defconfig
> > @@ -0,0 +1,4 @@
> > +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
> 
> Does this do anything other than define an unused #define?
> 
> Ah, I suppose eventually it will cause the inclusion of a suitable dram
> file. Really ought to start moving things out of SYS_EXTRA though, but I
> don't think you need to shave that yakk just to get this patch in, so:
> 
> Acked-by: Ian Campbell <ijc@hellion.org.uk>

Although I've just noticed that lacks a board/sunxi/MAINTAINERS entry.

I think there is no need to resend the whole series, just this one
patch. With this minor tweak I think it's time add this to
u-boot-sunxi#next.

Ian.

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Chen-Yu Tsai]

On Sun, Sep 28, 2014 at 11:33 PM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
>> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
>> > The Colombus board is an A31 evaluation board from WITS Technology.
>> >
>> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>
>> > ---
>> >  configs/Colombus_defconfig | 4 ++++
>> >  1 file changed, 4 insertions(+)
>> >  create mode 100644 configs/Colombus_defconfig
>> >
>> > diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
>> > new file mode 100644
>> > index 0000000..16800de
>> > --- /dev/null
>> > +++ b/configs/Colombus_defconfig
>> > @@ -0,0 +1,4 @@
>> > +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
>>
>> Does this do anything other than define an unused #define?
>>
>> Ah, I suppose eventually it will cause the inclusion of a suitable dram
>> file. Really ought to start moving things out of SYS_EXTRA though, but I
>> don't think you need to shave that yakk just to get this patch in, so:
>>
>> Acked-by: Ian Campbell <ijc@hellion.org.uk>
>
> Although I've just noticed that lacks a board/sunxi/MAINTAINERS entry.
>
> I think there is no need to resend the whole series, just this one
> patch. With this minor tweak I think it's time add this to
> u-boot-sunxi#next.

Actually I don't have this board. I think Maxime has one. Not sure
if anyone else does. It was kind of a placeholder for all A31 boards.

I suppose you could just drop this patch. I can send another one
for the A31 Hummingbird, which I do have and can maintain.

ChenYu

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Hans de Goede]

Hi Ian,

On 09/28/2014 05:33 PM, Ian Campbell wrote:
> On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
>> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
>>> The Colombus board is an A31 evaluation board from WITS Technology.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>
>>> ---
>>>  configs/Colombus_defconfig | 4 ++++
>>>  1 file changed, 4 insertions(+)
>>>  create mode 100644 configs/Colombus_defconfig
>>>
>>> diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
>>> new file mode 100644
>>> index 0000000..16800de
>>> --- /dev/null
>>> +++ b/configs/Colombus_defconfig
>>> @@ -0,0 +1,4 @@
>>> +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
>>
>> Does this do anything other than define an unused #define?
>>
>> Ah, I suppose eventually it will cause the inclusion of a suitable dram
>> file. Really ought to start moving things out of SYS_EXTRA though, but I
>> don't think you need to shave that yakk just to get this patch in, so:
>>
>> Acked-by: Ian Campbell <ijc@hellion.org.uk>
> 
> Although I've just noticed that lacks a board/sunxi/MAINTAINERS entry.
> 
> I think there is no need to resend the whole series, just this one
> patch. With this minor tweak I think it's time add this to
> u-boot-sunxi#next.

Before you do that, note that I've just added 2 patches there, which I would
like to get into v2014.10. Specifically I'm hoping that I can get some
positive testing feedback on the bananapi gmac patch I've send (off-list),
and I believe we really should try to get the bananapi fix into v2014.10,
and if we're going todo a pull-req for v2014.10, we might as well include
the 2 patches I've just added to next. Do you agree ?

Still feel free to merge the sun6i series into next, I can just cherry pick
the 3 patches in question directly into master when I'm ready to send the
pull-req.

Regards,

Hans

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Ian Campbell]

On Sun, 2014-09-28 at 23:37 +0800, Chen-Yu Tsai wrote:
> On Sun, Sep 28, 2014 at 11:33 PM, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
> >> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> >> > The Colombus board is an A31 evaluation board from WITS Technology.
> >> >
> >> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >>
> >> > ---
> >> >  configs/Colombus_defconfig | 4 ++++
> >> >  1 file changed, 4 insertions(+)
> >> >  create mode 100644 configs/Colombus_defconfig
> >> >
> >> > diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
> >> > new file mode 100644
> >> > index 0000000..16800de
> >> > --- /dev/null
> >> > +++ b/configs/Colombus_defconfig
> >> > @@ -0,0 +1,4 @@
> >> > +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
> >>
> >> Does this do anything other than define an unused #define?
> >>
> >> Ah, I suppose eventually it will cause the inclusion of a suitable dram
> >> file. Really ought to start moving things out of SYS_EXTRA though, but I
> >> don't think you need to shave that yakk just to get this patch in, so:
> >>
> >> Acked-by: Ian Campbell <ijc@hellion.org.uk>
> >
> > Although I've just noticed that lacks a board/sunxi/MAINTAINERS entry.
> >
> > I think there is no need to resend the whole series, just this one
> > patch. With this minor tweak I think it's time add this to
> > u-boot-sunxi#next.
> 
> Actually I don't have this board. I think Maxime has one. Not sure
> if anyone else does. It was kind of a placeholder for all A31 boards.
> 
> I suppose you could just drop this patch. I can send another one
> for the A31 Hummingbird, which I do have and can maintain.

Unless Maxime agrees to having his name in the MAINTAINERS file I think
that would be best, actually if he does agree I see no reason not to
have both ;-)

Ian.

[U-Boot] [linux-sunxi] Re: [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Ian Campbell]

On Sun, 2014-09-28 at 17:40 +0200, Hans de Goede wrote:
> Hi Ian,
> 
> On 09/28/2014 05:33 PM, Ian Campbell wrote:
> > On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
> >> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
> >>> The Colombus board is an A31 evaluation board from WITS Technology.
> >>>
> >>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >>
> >>> ---
> >>>  configs/Colombus_defconfig | 4 ++++
> >>>  1 file changed, 4 insertions(+)
> >>>  create mode 100644 configs/Colombus_defconfig
> >>>
> >>> diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
> >>> new file mode 100644
> >>> index 0000000..16800de
> >>> --- /dev/null
> >>> +++ b/configs/Colombus_defconfig
> >>> @@ -0,0 +1,4 @@
> >>> +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
> >>
> >> Does this do anything other than define an unused #define?
> >>
> >> Ah, I suppose eventually it will cause the inclusion of a suitable dram
> >> file. Really ought to start moving things out of SYS_EXTRA though, but I
> >> don't think you need to shave that yakk just to get this patch in, so:
> >>
> >> Acked-by: Ian Campbell <ijc@hellion.org.uk>
> > 
> > Although I've just noticed that lacks a board/sunxi/MAINTAINERS entry.
> > 
> > I think there is no need to resend the whole series, just this one
> > patch. With this minor tweak I think it's time add this to
> > u-boot-sunxi#next.
> 
> Before you do that, note that I've just added 2 patches there, which I would
> like to get into v2014.10. Specifically I'm hoping that I can get some
> positive testing feedback on the bananapi gmac patch I've send (off-list),
> and I believe we really should try to get the bananapi fix into v2014.10,
> and if we're going todo a pull-req for v2014.10, we might as well include
> the 2 patches I've just added to next. Do you agree ?

You mean these two?
        sun7i: Add support for Olimex A20-OLinuXino-LIME2
        mmc: sunxi: add SDHC support for sun6i/sun7i/sun8i

The latter seems like a feature to me, or at least the changelog doesn't
give any rationale why it should go in now rather than waiting for the
next merge window (i.e. why it's a bugfix, what the upside is to justify
its inclusion now). How much testing has it had and what are the
potential downsides?

WRT the new board (and new boards generally), I'm in two minds. On the
one hand they are pretty low risk (can't regress anything else, at least
not in this case), on the other we are 6 weeks past the close of the
merge window and 2 from the release date, so we are pretty far along.
Where do we draw the line?

The gmac fix is a clear bug fix and once it is properly posted publicly
I will ack and then I agree it should go in.

> Still feel free to merge the sun6i series into next, I can just cherry pick
> the 3 patches in question directly into master when I'm ready to send the
> pull-req.

Ack, that's what I expected to happen.

Ian.

[U-Boot] [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Maxime Ripard]

On Sun, Sep 28, 2014 at 04:43:30PM +0100, Ian Campbell wrote:
> > Actually I don't have this board. I think Maxime has one. Not sure
> > if anyone else does. It was kind of a placeholder for all A31 boards.
> > 
> > I suppose you could just drop this patch. I can send another one
> > for the A31 Hummingbird, which I do have and can maintain.
> 
> Unless Maxime agrees to having his name in the MAINTAINERS file I think
> that would be best, actually if he does agree I see no reason not to
> have both ;-)

That's something I could live with :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [linux-sunxi] Re: [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Iain Paton]

On 28/09/14 17:20, Ian Campbell wrote:

> You mean these two?
>         sun7i: Add support for Olimex A20-OLinuXino-LIME2
>         mmc: sunxi: add SDHC support for sun6i/sun7i/sun8i
> 
> The latter seems like a feature to me, or at least the changelog doesn't
> give any rationale why it should go in now rather than waiting for the
> next merge window (i.e. why it's a bugfix, what the upside is to justify
> its inclusion now). How much testing has it had and what are the
> potential downsides?
> 
> WRT the new board (and new boards generally), I'm in two minds. On the
> one hand they are pretty low risk (can't regress anything else, at least
> not in this case), on the other we are 6 weeks past the close of the
> merge window and 2 from the release date, so we are pretty far along.
> Where do we draw the line?

FWIW, the Lime2 is very new, I had no expectations it would make it 
into 2014.10 - although I'd not complain if it does!

Seems unlikely the dts will make it into 3.17 either, so there's probably 
no rush. 
Anyone needing either can pick up the patches themselves until next 
release.

[U-Boot] [linux-sunxi] Re: [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Hans de Goede]

Hi,

On 09/28/2014 06:20 PM, Ian Campbell wrote:
> On Sun, 2014-09-28 at 17:40 +0200, Hans de Goede wrote:
>> Hi Ian,
>>
>> On 09/28/2014 05:33 PM, Ian Campbell wrote:
>>> On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
>>>> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
>>>>> The Colombus board is an A31 evaluation board from WITS Technology.
>>>>>
>>>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>>>
>>>>> ---
>>>>>  configs/Colombus_defconfig | 4 ++++
>>>>>  1 file changed, 4 insertions(+)
>>>>>  create mode 100644 configs/Colombus_defconfig
>>>>>
>>>>> diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
>>>>> new file mode 100644
>>>>> index 0000000..16800de
>>>>> --- /dev/null
>>>>> +++ b/configs/Colombus_defconfig
>>>>> @@ -0,0 +1,4 @@
>>>>> +CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
>>>>
>>>> Does this do anything other than define an unused #define?
>>>>
>>>> Ah, I suppose eventually it will cause the inclusion of a suitable dram
>>>> file. Really ought to start moving things out of SYS_EXTRA though, but I
>>>> don't think you need to shave that yakk just to get this patch in, so:
>>>>
>>>> Acked-by: Ian Campbell <ijc@hellion.org.uk>
>>>
>>> Although I've just noticed that lacks a board/sunxi/MAINTAINERS entry.
>>>
>>> I think there is no need to resend the whole series, just this one
>>> patch. With this minor tweak I think it's time add this to
>>> u-boot-sunxi#next.
>>
>> Before you do that, note that I've just added 2 patches there, which I would
>> like to get into v2014.10. Specifically I'm hoping that I can get some
>> positive testing feedback on the bananapi gmac patch I've send (off-list),
>> and I believe we really should try to get the bananapi fix into v2014.10,
>> and if we're going todo a pull-req for v2014.10, we might as well include
>> the 2 patches I've just added to next. Do you agree ?
> 
> You mean these two?
>         sun7i: Add support for Olimex A20-OLinuXino-LIME2
>         mmc: sunxi: add SDHC support for sun6i/sun7i/sun8i

Yes.

> The latter seems like a feature to me, or at least the changelog doesn't
> give any rationale why it should go in now rather than waiting for the
> next merge window (i.e. why it's a bugfix, what the upside is to justify
> its inclusion now). How much testing has it had and what are the
> potential downsides?

AFAIK the downside is that High Capacity cards will not work without it.

Looking at the code if this bit is set, then for some commands
drivers/mmc/mmc.c or-s in OCR_HCS into the mmc cmdarg, so I guess you're
right that this may cause some undesirable side effects, so lets delay
this one.

> WRT the new board (and new boards generally), I'm in two minds. On the
> one hand they are pretty low risk (can't regress anything else, at least
> not in this case), on the other we are 6 weeks past the close of the
> merge window and 2 from the release date, so we are pretty far along.
> Where do we draw the line?

Normally I would not include new boards at this moment in the cycle, but
since we need to do a pull-req for the gmac anyways I thought it would
be nice to have it included, esp. since many distros only spin things
like sdcard boot images once, so if we do not include it now, many distros
will not get it for a significant amount of time.

Either way let me know how you want to proceed, if you think we should not
include this, then I'll send a pull-req with only the gmac fix.

> The gmac fix is a clear bug fix and once it is properly posted publicly
> I will ack and then I agree it should go in.

I was hoping for Stephen to get around to testing it today, and then I wanted
to send it out with his Tested-by. I'll just go and send it as is for now.

>> Still feel free to merge the sun6i series into next, I can just cherry pick
>> the 3 patches in question directly into master when I'm ready to send the
>> pull-req.
> 
> Ack, that's what I expected to happen.

Regards,

Hans

[U-Boot] [linux-sunxi] Re: [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Ian Campbell]

On Sun, 2014-09-28 at 20:10 +0200, Hans de Goede wrote:
> On 09/28/2014 06:20 PM, Ian Campbell wrote:
> > On Sun, 2014-09-28 at 17:40 +0200, Hans de Goede wrote:

> >> Before you do that, note that I've just added 2 patches there, which I would
> >> like to get into v2014.10. Specifically I'm hoping that I can get some
> >> positive testing feedback on the bananapi gmac patch I've send (off-list),
> >> and I believe we really should try to get the bananapi fix into v2014.10,
> >> and if we're going todo a pull-req for v2014.10, we might as well include
> >> the 2 patches I've just added to next. Do you agree ?
> > 
> > You mean these two?
> >         sun7i: Add support for Olimex A20-OLinuXino-LIME2
> >         mmc: sunxi: add SDHC support for sun6i/sun7i/sun8i
> 
> Yes.
> 
> > The latter seems like a feature to me, or at least the changelog doesn't
> > give any rationale why it should go in now rather than waiting for the
> > next merge window (i.e. why it's a bugfix, what the upside is to justify
> > its inclusion now). How much testing has it had and what are the
> > potential downsides?
> 
> AFAIK the downside is that High Capacity cards will not work without it.
> 
> Looking at the code if this bit is set, then for some commands
> drivers/mmc/mmc.c or-s in OCR_HCS into the mmc cmdarg, so I guess you're
> right that this may cause some undesirable side effects, so lets delay
> this one.

OK.

> > WRT the new board (and new boards generally), I'm in two minds. On the
> > one hand they are pretty low risk (can't regress anything else, at least
> > not in this case), on the other we are 6 weeks past the close of the
> > merge window and 2 from the release date, so we are pretty far along.
> > Where do we draw the line?
> 
> Normally I would not include new boards at this moment in the cycle, but
> since we need to do a pull-req for the gmac anyways I thought it would
> be nice to have it included, esp. since many distros only spin things
> like sdcard boot images once, so if we do not include it now, many distros
> will not get it for a significant amount of time.

There's always Just One More Board(tm) ;-)

> Either way let me know how you want to proceed, if you think we should not
> include this, then I'll send a pull-req with only the gmac fix.

As I say I'm in two minds. I'm not really sure what the u-boot norm is
on this, I was hoping someone might chime in (although it's not been
very long and the thread topic doesn't exactly scream for attention).
Maybe run it by Albert/Tom and see how they feel about such things in
general?

Where run it by might be two alternate PRs? Or a PR structured so the
new board can trivially be dropped?

> > The gmac fix is a clear bug fix and once it is properly posted publicly
> > I will ack and then I agree it should go in.
> 
> I was hoping for Stephen to get around to testing it today, and then I wanted
> to send it out with his Tested-by. I'll just go and send it as is for now.

s/Stephen/Karsten/?

Ian.

[U-Boot] [linux-sunxi] Re: [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Hans de Goede]

Hi,

On 09/28/2014 11:36 PM, Ian Campbell wrote:
> On Sun, 2014-09-28 at 20:10 +0200, Hans de Goede wrote:
>> On 09/28/2014 06:20 PM, Ian Campbell wrote:
>>> On Sun, 2014-09-28 at 17:40 +0200, Hans de Goede wrote:
> 
>>>> Before you do that, note that I've just added 2 patches there, which I would
>>>> like to get into v2014.10. Specifically I'm hoping that I can get some
>>>> positive testing feedback on the bananapi gmac patch I've send (off-list),
>>>> and I believe we really should try to get the bananapi fix into v2014.10,
>>>> and if we're going todo a pull-req for v2014.10, we might as well include
>>>> the 2 patches I've just added to next. Do you agree ?
>>>
>>> You mean these two?
>>>         sun7i: Add support for Olimex A20-OLinuXino-LIME2
>>>         mmc: sunxi: add SDHC support for sun6i/sun7i/sun8i
>>
>> Yes.
>>
>>> The latter seems like a feature to me, or at least the changelog doesn't
>>> give any rationale why it should go in now rather than waiting for the
>>> next merge window (i.e. why it's a bugfix, what the upside is to justify
>>> its inclusion now). How much testing has it had and what are the
>>> potential downsides?
>>
>> AFAIK the downside is that High Capacity cards will not work without it.
>>
>> Looking at the code if this bit is set, then for some commands
>> drivers/mmc/mmc.c or-s in OCR_HCS into the mmc cmdarg, so I guess you're
>> right that this may cause some undesirable side effects, so lets delay
>> this one.
> 
> OK.
> 
>>> WRT the new board (and new boards generally), I'm in two minds. On the
>>> one hand they are pretty low risk (can't regress anything else, at least
>>> not in this case), on the other we are 6 weeks past the close of the
>>> merge window and 2 from the release date, so we are pretty far along.
>>> Where do we draw the line?
>>
>> Normally I would not include new boards at this moment in the cycle, but
>> since we need to do a pull-req for the gmac anyways I thought it would
>> be nice to have it included, esp. since many distros only spin things
>> like sdcard boot images once, so if we do not include it now, many distros
>> will not get it for a significant amount of time.
> 
> There's always Just One More Board(tm) ;-)

Right, so lets just drop the board and I'll do a pull-req with only the
bananapi gmac fix, can I have your Reviewed-by for that one please?

>> Either way let me know how you want to proceed, if you think we should not
>> include this, then I'll send a pull-req with only the gmac fix.
> 
> As I say I'm in two minds. I'm not really sure what the u-boot norm is
> on this, I was hoping someone might chime in (although it's not been
> very long and the thread topic doesn't exactly scream for attention).
> Maybe run it by Albert/Tom and see how they feel about such things in
> general?
> 
> Where run it by might be two alternate PRs? Or a PR structured so the
> new board can trivially be dropped?
> 
>>> The gmac fix is a clear bug fix and once it is properly posted publicly
>>> I will ack and then I agree it should go in.
>>
>> I was hoping for Stephen to get around to testing it today, and then I wanted
>> to send it out with his Tested-by. I'll just go and send it as is for now.
> 
> s/Stephen/Karsten/?

Yes, my bad.

Regards,

Hans

[U-Boot] [linux-sunxi] Re: [PATCH v2 10/10] ARM: sun6i: Add Colombus board defconfig

[Ian Campbell]

On Mon, 2014-09-29 at 20:08 +0200, Hans de Goede wrote:
> 
> Right, so lets just drop the board and I'll do a pull-req with only
> the
> bananapi gmac fix, can I have your Reviewed-by for that one please?

Done.

[U-Boot] [PATCH v2 06/10] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Pantelis Antoniou]

Hi Ian,

> On Sep 25, 2014, at 21:52 , Ian Campbell <ijc@hellion.org.uk> wrote:
> 
> On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
>> From: Hans de Goede <hdegoede@redhat.com>
>> 
>> The mmc hardware on sun6i has an extra reset control that needs to
>> be de-asserted prior to usage. Also the FIFO address is different.
>> 
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> [wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
>> 		rewrite different FIFO address handling, add commit message]
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> 
> Acked-by: Ian Campbell <ijc@hellion.org.uk>
> 
> Pantelis, unless you object I'd like to eventually take this into
> u-boot-sunxi.git#next and merge for v2015.04.
> 

Be my guest.

[holly misplaced emails due to change of mailer batman]

? Pantelis