[PATCH 00/17] Netlogic XLP updates

[PATCH 00/17] Netlogic XLP updates

[Jayachandran C]

This patchset is a collection of fixes and updates to the Netlogic
platform support.

Comments/suggestions welcome.

JC.

Ganesan Ramalingam (5):
  MIPS: Netlogic: Fix cop0 prid check in AHCI init
  MIPS: Netlogic: Fix for SATA PHY init
  MIPS: Netlogic: Fix frequency calculation register
  MIPS: Netlogic: Add irq mapping and setup for XHCI port 3
  MIPS: Netlogic: Add built-in dts for XLP5xx boards

Jayachandran C (8):
  MIPS: Netlogic: Disable writing IRT for disabled blocks
  MIPS: MSI: Update MSI handling for XLP
  MIPS: Netlogic: Use MIPS topology.h
  MIPS: Netlogic: Move cores per node out of multi-node.h
  MIPS: Netlogic: nlm_core_id for xlp9xx
  MIPS: Netlogic: Update function to read DRAM BARs
  MIPS: Netlogic: Handle XLP hardware errata
  MIPS: Netlogic: Do not enable SUE for core

Prem Mallappa (1):
  MIPS: Netlogic: Added HugeTLB as default

Qingmin Liu (1):
  MIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_div

Shanghui Liu (1):
  MIPS: Netlogic: Fix wait for slave CPUs

Subhendu Sekhar Behera (1):
  MIPS: Netlogic: i2c IRQ mappings for XLP9XX

 arch/mips/Kconfig                                  |  1 +
 arch/mips/boot/dts/Makefile                        |  1 +
 arch/mips/boot/dts/xlp_rvp.dts                     | 77 ++++++++++++++++++++++
 arch/mips/include/asm/mach-netlogic/multi-node.h   |  9 ---
 arch/mips/include/asm/mach-netlogic/topology.h     | 15 -----
 arch/mips/include/asm/netlogic/common.h            | 21 +++++-
 arch/mips/include/asm/netlogic/mips-extns.h        |  8 ++-
 .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h |  2 +
 arch/mips/include/asm/netlogic/xlp-hal/sys.h       |  3 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h       |  3 +-
 arch/mips/netlogic/Kconfig                         |  9 +++
 arch/mips/netlogic/common/irq.c                    | 10 +--
 arch/mips/netlogic/common/reset.S                  | 20 +++++-
 arch/mips/netlogic/common/smp.c                    | 25 +++----
 arch/mips/netlogic/xlp/ahci-init-xlp2.c            | 13 ++++
 arch/mips/netlogic/xlp/ahci-init.c                 |  2 +-
 arch/mips/netlogic/xlp/dt.c                        | 10 ++-
 arch/mips/netlogic/xlp/nlm_hal.c                   | 57 ++++++++++------
 arch/mips/netlogic/xlp/setup.c                     |  7 +-
 arch/mips/netlogic/xlp/usb-init-xlp2.c             | 10 ++-
 arch/mips/netlogic/xlp/wakeup.c                    | 10 +--
 arch/mips/pci/msi-xlp.c                            | 19 +++---
 22 files changed, 244 insertions(+), 88 deletions(-)
 create mode 100644 arch/mips/boot/dts/xlp_rvp.dts
 delete mode 100644 arch/mips/include/asm/mach-netlogic/topology.h

-- 
1.9.1

[PATCH 00/17] Netlogic XLP updates

[Jayachandran C]

This patchset is a collection of fixes and updates to the Netlogic
platform support.

Comments/suggestions welcome.

JC.

Ganesan Ramalingam (5):
  MIPS: Netlogic: Fix cop0 prid check in AHCI init
  MIPS: Netlogic: Fix for SATA PHY init
  MIPS: Netlogic: Fix frequency calculation register
  MIPS: Netlogic: Add irq mapping and setup for XHCI port 3
  MIPS: Netlogic: Add built-in dts for XLP5xx boards

Jayachandran C (8):
  MIPS: Netlogic: Disable writing IRT for disabled blocks
  MIPS: MSI: Update MSI handling for XLP
  MIPS: Netlogic: Use MIPS topology.h
  MIPS: Netlogic: Move cores per node out of multi-node.h
  MIPS: Netlogic: nlm_core_id for xlp9xx
  MIPS: Netlogic: Update function to read DRAM BARs
  MIPS: Netlogic: Handle XLP hardware errata
  MIPS: Netlogic: Do not enable SUE for core

Prem Mallappa (1):
  MIPS: Netlogic: Added HugeTLB as default

Qingmin Liu (1):
  MIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_div

Shanghui Liu (1):
  MIPS: Netlogic: Fix wait for slave CPUs

Subhendu Sekhar Behera (1):
  MIPS: Netlogic: i2c IRQ mappings for XLP9XX

 arch/mips/Kconfig                                  |  1 +
 arch/mips/boot/dts/Makefile                        |  1 +
 arch/mips/boot/dts/xlp_rvp.dts                     | 77 ++++++++++++++++++++++
 arch/mips/include/asm/mach-netlogic/multi-node.h   |  9 ---
 arch/mips/include/asm/mach-netlogic/topology.h     | 15 -----
 arch/mips/include/asm/netlogic/common.h            | 21 +++++-
 arch/mips/include/asm/netlogic/mips-extns.h        |  8 ++-
 .../mips/include/asm/netlogic/xlp-hal/cpucontrol.h |  2 +
 arch/mips/include/asm/netlogic/xlp-hal/sys.h       |  3 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h       |  3 +-
 arch/mips/netlogic/Kconfig                         |  9 +++
 arch/mips/netlogic/common/irq.c                    | 10 +--
 arch/mips/netlogic/common/reset.S                  | 20 +++++-
 arch/mips/netlogic/common/smp.c                    | 25 +++----
 arch/mips/netlogic/xlp/ahci-init-xlp2.c            | 13 ++++
 arch/mips/netlogic/xlp/ahci-init.c                 |  2 +-
 arch/mips/netlogic/xlp/dt.c                        | 10 ++-
 arch/mips/netlogic/xlp/nlm_hal.c                   | 57 ++++++++++------
 arch/mips/netlogic/xlp/setup.c                     |  7 +-
 arch/mips/netlogic/xlp/usb-init-xlp2.c             | 10 ++-
 arch/mips/netlogic/xlp/wakeup.c                    | 10 +--
 arch/mips/pci/msi-xlp.c                            | 19 +++---
 22 files changed, 244 insertions(+), 88 deletions(-)
 create mode 100644 arch/mips/boot/dts/xlp_rvp.dts
 delete mode 100644 arch/mips/include/asm/mach-netlogic/topology.h

-- 
1.9.1

[PATCH 01/17] MIPS: Netlogic: Fix wait for slave CPUs

[Jayachandran C]

From: Shanghui Liu <shliu@broadcom.com>

For core 0, the condition of "cpu == bootcpu" is always true, so it
does not wait for other three threads to become ready. Fix this by
using correct check.

Signed-off-by: Shanghui Liu <shliu@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/wakeup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index e5f44d2..26d82f7 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -99,7 +99,7 @@ static int wait_for_cpus(int cpu, int bootcpu)
 	do {
 		notready = nlm_threads_per_core;
 		for (i = 0; i < nlm_threads_per_core; i++)
-			if (cpu_ready[cpu + i] || cpu == bootcpu)
+			if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
 				--notready;
 	} while (notready != 0 && --count > 0);
 
-- 
1.9.1

[PATCH 01/17] MIPS: Netlogic: Fix wait for slave CPUs

[Jayachandran C]

From: Shanghui Liu <shliu@broadcom.com>

For core 0, the condition of "cpu == bootcpu" is always true, so it
does not wait for other three threads to become ready. Fix this by
using correct check.

Signed-off-by: Shanghui Liu <shliu@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/wakeup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index e5f44d2..26d82f7 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -99,7 +99,7 @@ static int wait_for_cpus(int cpu, int bootcpu)
 	do {
 		notready = nlm_threads_per_core;
 		for (i = 0; i < nlm_threads_per_core; i++)
-			if (cpu_ready[cpu + i] || cpu == bootcpu)
+			if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
 				--notready;
 	} while (notready != 0 && --count > 0);
 
-- 
1.9.1

[PATCH 02/17] MIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_div

[Jayachandran C]

From: Qingmin Liu <qingmin@broadcom.com>

The variable ref_div is initialized to the correct divisor but not
used in the frequency calculation. This caused incorrect frequency
to be reported when the clock divisor is not 3.

Signed-off-by: Qingmin Liu <qingmin@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/nlm_hal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index bc24beb..7e0d224 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -410,7 +410,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 
 	fdiv = fdiv/(1 << 13);
 	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
-	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
+	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div;
 
 	if (pll_out_freq_den > 0)
 		do_div(pll_out_freq_num, pll_out_freq_den);
-- 
1.9.1

[PATCH 02/17] MIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_div

[Jayachandran C]

From: Qingmin Liu <qingmin@broadcom.com>

The variable ref_div is initialized to the correct divisor but not
used in the frequency calculation. This caused incorrect frequency
to be reported when the clock divisor is not 3.

Signed-off-by: Qingmin Liu <qingmin@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/nlm_hal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index bc24beb..7e0d224 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -410,7 +410,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 
 	fdiv = fdiv/(1 << 13);
 	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
-	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
+	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div;
 
 	if (pll_out_freq_den > 0)
 		do_div(pll_out_freq_num, pll_out_freq_den);
-- 
1.9.1

[PATCH 03/17] MIPS: Netlogic: Fix cop0 prid check in AHCI init

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

PRID register should be masked with IMP_MASK to get processor ID.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/ahci-init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/xlp/ahci-init.c b/arch/mips/netlogic/xlp/ahci-init.c
index a9d0fae..92be1a3 100644
--- a/arch/mips/netlogic/xlp/ahci-init.c
+++ b/arch/mips/netlogic/xlp/ahci-init.c
@@ -151,7 +151,7 @@ static void nlm_sata_firmware_init(int node)
 static int __init nlm_ahci_init(void)
 {
 	int node = 0;
-	int chip = read_c0_prid() & PRID_REV_MASK;
+	int chip = read_c0_prid() & PRID_IMP_MASK;
 
 	if (chip == PRID_IMP_NETLOGIC_XLP3XX)
 		nlm_sata_firmware_init(node);
-- 
1.9.1

[PATCH 03/17] MIPS: Netlogic: Fix cop0 prid check in AHCI init

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

PRID register should be masked with IMP_MASK to get processor ID.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/ahci-init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/xlp/ahci-init.c b/arch/mips/netlogic/xlp/ahci-init.c
index a9d0fae..92be1a3 100644
--- a/arch/mips/netlogic/xlp/ahci-init.c
+++ b/arch/mips/netlogic/xlp/ahci-init.c
@@ -151,7 +151,7 @@ static void nlm_sata_firmware_init(int node)
 static int __init nlm_ahci_init(void)
 {
 	int node = 0;
-	int chip = read_c0_prid() & PRID_REV_MASK;
+	int chip = read_c0_prid() & PRID_IMP_MASK;
 
 	if (chip == PRID_IMP_NETLOGIC_XLP3XX)
 		nlm_sata_firmware_init(node);
-- 
1.9.1

[PATCH 04/17] MIPS: Netlogic: Disable writing IRT for disabled blocks

[Jayachandran C]

If the device header of a block is not present, return invalid IRT
value so that we do not program an incorrect offset.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/nlm_hal.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 7e0d224..de41fb5 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -170,16 +170,23 @@ static int xlp_irq_to_irt(int irq)
 	}
 
 	if (devoff != 0) {
+		uint32_t val;
+
 		pcibase = nlm_pcicfg_base(devoff);
-		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
-		/* HW weirdness, I2C IRT entry has to be fixed up */
-		switch (irq) {
-		case PIC_I2C_1_IRQ:
-			irt = irt + 1; break;
-		case PIC_I2C_2_IRQ:
-			irt = irt + 2; break;
-		case PIC_I2C_3_IRQ:
-			irt = irt + 3; break;
+		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
+		if (val == 0xffffffff) {
+			irt = -1;
+		} else {
+			irt = val & 0xffff;
+			/* HW weirdness, I2C IRT entry has to be fixed up */
+			switch (irq) {
+			case PIC_I2C_1_IRQ:
+				irt = irt + 1; break;
+			case PIC_I2C_2_IRQ:
+				irt = irt + 2; break;
+			case PIC_I2C_3_IRQ:
+				irt = irt + 3; break;
+			}
 		}
 	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
 			irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
-- 
1.9.1

[PATCH 04/17] MIPS: Netlogic: Disable writing IRT for disabled blocks

[Jayachandran C]

If the device header of a block is not present, return invalid IRT
value so that we do not program an incorrect offset.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/nlm_hal.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 7e0d224..de41fb5 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -170,16 +170,23 @@ static int xlp_irq_to_irt(int irq)
 	}
 
 	if (devoff != 0) {
+		uint32_t val;
+
 		pcibase = nlm_pcicfg_base(devoff);
-		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
-		/* HW weirdness, I2C IRT entry has to be fixed up */
-		switch (irq) {
-		case PIC_I2C_1_IRQ:
-			irt = irt + 1; break;
-		case PIC_I2C_2_IRQ:
-			irt = irt + 2; break;
-		case PIC_I2C_3_IRQ:
-			irt = irt + 3; break;
+		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
+		if (val == 0xffffffff) {
+			irt = -1;
+		} else {
+			irt = val & 0xffff;
+			/* HW weirdness, I2C IRT entry has to be fixed up */
+			switch (irq) {
+			case PIC_I2C_1_IRQ:
+				irt = irt + 1; break;
+			case PIC_I2C_2_IRQ:
+				irt = irt + 2; break;
+			case PIC_I2C_3_IRQ:
+				irt = irt + 3; break;
+			}
 		}
 	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
 			irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
-- 
1.9.1

Re: [PATCH 04/17] MIPS: Netlogic: Disable writing IRT for disabled blocks

[Sergei Shtylyov]

Hello.

On 01/07/2015 02:28 PM, Jayachandran C wrote:

> If the device header of a block is not present, return invalid IRT
> value so that we do not program an incorrect offset.

> Signed-off-by: Jayachandran C <jchandra@broadcom.com>
> ---
>   arch/mips/netlogic/xlp/nlm_hal.c | 25 ++++++++++++++++---------
>   1 file changed, 16 insertions(+), 9 deletions(-)

> diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
> index 7e0d224..de41fb5 100644
> --- a/arch/mips/netlogic/xlp/nlm_hal.c
> +++ b/arch/mips/netlogic/xlp/nlm_hal.c
> @@ -170,16 +170,23 @@ static int xlp_irq_to_irt(int irq)
>   	}
>
>   	if (devoff != 0) {
> +		uint32_t val;
> +
>   		pcibase = nlm_pcicfg_base(devoff);
> -		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
> -		/* HW weirdness, I2C IRT entry has to be fixed up */
> -		switch (irq) {
> -		case PIC_I2C_1_IRQ:
> -			irt = irt + 1; break;
> -		case PIC_I2C_2_IRQ:
> -			irt = irt + 2; break;
> -		case PIC_I2C_3_IRQ:
> -			irt = irt + 3; break;
> +		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
> +		if (val == 0xffffffff) {
> +			irt = -1;
> +		} else {
> +			irt = val & 0xffff;
> +			/* HW weirdness, I2C IRT entry has to be fixed up */
> +			switch (irq) {
> +			case PIC_I2C_1_IRQ:
> +				irt = irt + 1; break;
> +			case PIC_I2C_2_IRQ:
> +				irt = irt + 2; break;
> +			case PIC_I2C_3_IRQ:
> +				irt = irt + 3; break;

    Why not 'irt += n' in all 3 cases?
    And don't place *break* on the same line -- this upsets checkpatch.pl IIRC.

WBR, Sergei

Re: [PATCH 04/17] MIPS: Netlogic: Disable writing IRT for disabled blocks

[Jayachandran C.]

On Wed, Jan 07, 2015 at 08:07:59PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 01/07/2015 02:28 PM, Jayachandran C wrote:
> 
> >If the device header of a block is not present, return invalid IRT
> >value so that we do not program an incorrect offset.
> 
> >Signed-off-by: Jayachandran C <jchandra@broadcom.com>
> >---
> >  arch/mips/netlogic/xlp/nlm_hal.c | 25 ++++++++++++++++---------
> >  1 file changed, 16 insertions(+), 9 deletions(-)
> 
> >diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
> >index 7e0d224..de41fb5 100644
> >--- a/arch/mips/netlogic/xlp/nlm_hal.c
> >+++ b/arch/mips/netlogic/xlp/nlm_hal.c
> >@@ -170,16 +170,23 @@ static int xlp_irq_to_irt(int irq)
> >  	}
> >
> >  	if (devoff != 0) {
> >+		uint32_t val;
> >+
> >  		pcibase = nlm_pcicfg_base(devoff);
> >-		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
> >-		/* HW weirdness, I2C IRT entry has to be fixed up */
> >-		switch (irq) {
> >-		case PIC_I2C_1_IRQ:
> >-			irt = irt + 1; break;
> >-		case PIC_I2C_2_IRQ:
> >-			irt = irt + 2; break;
> >-		case PIC_I2C_3_IRQ:
> >-			irt = irt + 3; break;
> >+		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
> >+		if (val == 0xffffffff) {
> >+			irt = -1;
> >+		} else {
> >+			irt = val & 0xffff;
> >+			/* HW weirdness, I2C IRT entry has to be fixed up */
> >+			switch (irq) {
> >+			case PIC_I2C_1_IRQ:
> >+				irt = irt + 1; break;
> >+			case PIC_I2C_2_IRQ:
> >+				irt = irt + 2; break;
> >+			case PIC_I2C_3_IRQ:
> >+				irt = irt + 3; break;
> 
>    Why not 'irt += n' in all 3 cases?
>    And don't place *break* on the same line -- this upsets checkpatch.pl IIRC.

checkpatch did not complain, and also I did not want to mix formatting
change with actual fix. But agree that the code can cleaned up a bit.
I will sent out a patch for this next cycle.

JC.

Re: [PATCH 04/17] MIPS: Netlogic: Disable writing IRT for disabled blocks

[Jayachandran C.]

On Wed, Jan 07, 2015 at 08:07:59PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 01/07/2015 02:28 PM, Jayachandran C wrote:
> 
> >If the device header of a block is not present, return invalid IRT
> >value so that we do not program an incorrect offset.
> 
> >Signed-off-by: Jayachandran C <jchandra@broadcom.com>
> >---
> >  arch/mips/netlogic/xlp/nlm_hal.c | 25 ++++++++++++++++---------
> >  1 file changed, 16 insertions(+), 9 deletions(-)
> 
> >diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
> >index 7e0d224..de41fb5 100644
> >--- a/arch/mips/netlogic/xlp/nlm_hal.c
> >+++ b/arch/mips/netlogic/xlp/nlm_hal.c
> >@@ -170,16 +170,23 @@ static int xlp_irq_to_irt(int irq)
> >  	}
> >
> >  	if (devoff != 0) {
> >+		uint32_t val;
> >+
> >  		pcibase = nlm_pcicfg_base(devoff);
> >-		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
> >-		/* HW weirdness, I2C IRT entry has to be fixed up */
> >-		switch (irq) {
> >-		case PIC_I2C_1_IRQ:
> >-			irt = irt + 1; break;
> >-		case PIC_I2C_2_IRQ:
> >-			irt = irt + 2; break;
> >-		case PIC_I2C_3_IRQ:
> >-			irt = irt + 3; break;
> >+		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
> >+		if (val == 0xffffffff) {
> >+			irt = -1;
> >+		} else {
> >+			irt = val & 0xffff;
> >+			/* HW weirdness, I2C IRT entry has to be fixed up */
> >+			switch (irq) {
> >+			case PIC_I2C_1_IRQ:
> >+				irt = irt + 1; break;
> >+			case PIC_I2C_2_IRQ:
> >+				irt = irt + 2; break;
> >+			case PIC_I2C_3_IRQ:
> >+				irt = irt + 3; break;
> 
>    Why not 'irt += n' in all 3 cases?
>    And don't place *break* on the same line -- this upsets checkpatch.pl IIRC.

checkpatch did not complain, and also I did not want to mix formatting
change with actual fix. But agree that the code can cleaned up a bit.
I will sent out a patch for this next cycle.

JC.

Re: [PATCH 04/17] MIPS: Netlogic: Disable writing IRT for disabled blocks

[Sergei Shtylyov]

Hello.

On 1/9/2015 12:48 PM, Jayachandran C. wrote:

>>> If the device header of a block is not present, return invalid IRT
>>> value so that we do not program an incorrect offset.

>>> Signed-off-by: Jayachandran C <jchandra@broadcom.com>
>>> ---
>>>   arch/mips/netlogic/xlp/nlm_hal.c | 25 ++++++++++++++++---------
>>>   1 file changed, 16 insertions(+), 9 deletions(-)

>>> diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
>>> index 7e0d224..de41fb5 100644
>>> --- a/arch/mips/netlogic/xlp/nlm_hal.c
>>> +++ b/arch/mips/netlogic/xlp/nlm_hal.c
>>> @@ -170,16 +170,23 @@ static int xlp_irq_to_irt(int irq)
>>>   	}
>>>
>>>   	if (devoff != 0) {
>>> +		uint32_t val;
>>> +
>>>   		pcibase = nlm_pcicfg_base(devoff);
>>> -		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
>>> -		/* HW weirdness, I2C IRT entry has to be fixed up */
>>> -		switch (irq) {
>>> -		case PIC_I2C_1_IRQ:
>>> -			irt = irt + 1; break;
>>> -		case PIC_I2C_2_IRQ:
>>> -			irt = irt + 2; break;
>>> -		case PIC_I2C_3_IRQ:
>>> -			irt = irt + 3; break;
>>> +		val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
>>> +		if (val == 0xffffffff) {
>>> +			irt = -1;
>>> +		} else {
>>> +			irt = val & 0xffff;
>>> +			/* HW weirdness, I2C IRT entry has to be fixed up */
>>> +			switch (irq) {
>>> +			case PIC_I2C_1_IRQ:
>>> +				irt = irt + 1; break;
>>> +			case PIC_I2C_2_IRQ:
>>> +				irt = irt + 2; break;
>>> +			case PIC_I2C_3_IRQ:
>>> +				irt = irt + 3; break;

>>     Why not 'irt += n' in all 3 cases?
>>     And don't place *break* on the same line -- this upsets checkpatch.pl IIRC.

> checkpatch did not complain,

    Hm, perhaps this specific check was removed recently...

> and also I did not want to mix formatting
> change with actual fix.

    Ah, I didn't realize you were just moving the code.

> But agree that the code can cleaned up a bit.
> I will sent out a patch for this next cycle.

    TIA. :-)

> JC.

WBR, Sergei

[PATCH 05/17] MIPS: Netlogic: Fix for SATA PHY init

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Update to the SATA PHY initialization. This is needed for SATA detection
to succeed in all configurations.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c
index c83dbf3..7b066a4 100644
--- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/ahci-init-xlp2.c
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel)
 static void config_sata_phy(u64 regbase)
 {
 	u32 port, i, reg;
+	u8 val;
 
 	for (port = 0; port < 2; port++) {
 		for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase)
 
 		for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)
 			write_phy_reg(regbase, reg, port, sata_phy_config2[i]);
+
+		/* Fix for PHY link up failures at lower temperatures */
+		write_phy_reg(regbase, 0x800F, port, 0x1f);
+
+		val = read_phy_reg(regbase, 0x0029, port);
+		write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1));
+
+		val = read_phy_reg(regbase, 0x0056, port);
+		write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3));
+
+		val = read_phy_reg(regbase, 0x0018, port);
+		write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0));
 	}
 }
 
-- 
1.9.1

[PATCH 05/17] MIPS: Netlogic: Fix for SATA PHY init

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Update to the SATA PHY initialization. This is needed for SATA detection
to succeed in all configurations.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c
index c83dbf3..7b066a4 100644
--- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/ahci-init-xlp2.c
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel)
 static void config_sata_phy(u64 regbase)
 {
 	u32 port, i, reg;
+	u8 val;
 
 	for (port = 0; port < 2; port++) {
 		for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase)
 
 		for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)
 			write_phy_reg(regbase, reg, port, sata_phy_config2[i]);
+
+		/* Fix for PHY link up failures at lower temperatures */
+		write_phy_reg(regbase, 0x800F, port, 0x1f);
+
+		val = read_phy_reg(regbase, 0x0029, port);
+		write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1));
+
+		val = read_phy_reg(regbase, 0x0056, port);
+		write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3));
+
+		val = read_phy_reg(regbase, 0x0018, port);
+		write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0));
 	}
 }
 
-- 
1.9.1

[PATCH 06/17] MIPS: Netlogic: Fix frequency calculation register

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Change the PIC frequency calculation to use the register that has the
current configuration. The existing code used the register that is
written to change frequency, which can have an invalid value if the
firmware did not set it up correctly.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/sys.h | 3 +++
 arch/mips/netlogic/xlp/nlm_hal.c             | 8 ++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index bc7bddf..6bcf395 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -177,6 +177,9 @@
 #define SYS_9XX_CLK_DEV_DIV			0x18d
 #define SYS_9XX_CLK_DEV_CHG			0x18f
 
+#define SYS_9XX_CLK_DEV_SEL_REG			0x1a4
+#define SYS_9XX_CLK_DEV_DIV_REG			0x1a6
+
 /* Registers changed on 9XX */
 #define SYS_9XX_POWER_ON_RESET_CFG		0x00
 #define SYS_9XX_CHIP_RESET			0x01
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index de41fb5..b80d893 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -332,7 +332,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 	/* Find the clock source PLL device for PIC */
 	if (cpu_xlp9xx) {
 		reg_select = nlm_read_sys_reg(clockbase,
-				SYS_9XX_CLK_DEV_SEL) & 0x3;
+				SYS_9XX_CLK_DEV_SEL_REG) & 0x3;
 		switch (reg_select) {
 		case 0:
 			ctrl_val0 = nlm_read_sys_reg(clockbase,
@@ -361,7 +361,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 		}
 	} else {
 		reg_select = (nlm_read_sys_reg(sysbase,
-					SYS_CLK_DEV_SEL) >> 22) & 0x3;
+					SYS_CLK_DEV_SEL_REG) >> 22) & 0x3;
 		switch (reg_select) {
 		case 0:
 			ctrl_val0 = nlm_read_sys_reg(sysbase,
@@ -425,10 +425,10 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 	/* PIC post divider, which happens after PLL */
 	if (cpu_xlp9xx)
 		pic_div = nlm_read_sys_reg(clockbase,
-				SYS_9XX_CLK_DEV_DIV) & 0x3;
+				SYS_9XX_CLK_DEV_DIV_REG) & 0x3;
 	else
 		pic_div = (nlm_read_sys_reg(sysbase,
-					SYS_CLK_DEV_DIV) >> 22) & 0x3;
+					SYS_CLK_DEV_DIV_REG) >> 22) & 0x3;
 	do_div(pll_out_freq_num, 1 << pic_div);
 
 	return pll_out_freq_num;
-- 
1.9.1

[PATCH 06/17] MIPS: Netlogic: Fix frequency calculation register

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Change the PIC frequency calculation to use the register that has the
current configuration. The existing code used the register that is
written to change frequency, which can have an invalid value if the
firmware did not set it up correctly.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/sys.h | 3 +++
 arch/mips/netlogic/xlp/nlm_hal.c             | 8 ++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index bc7bddf..6bcf395 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -177,6 +177,9 @@
 #define SYS_9XX_CLK_DEV_DIV			0x18d
 #define SYS_9XX_CLK_DEV_CHG			0x18f
 
+#define SYS_9XX_CLK_DEV_SEL_REG			0x1a4
+#define SYS_9XX_CLK_DEV_DIV_REG			0x1a6
+
 /* Registers changed on 9XX */
 #define SYS_9XX_POWER_ON_RESET_CFG		0x00
 #define SYS_9XX_CHIP_RESET			0x01
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index de41fb5..b80d893 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -332,7 +332,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 	/* Find the clock source PLL device for PIC */
 	if (cpu_xlp9xx) {
 		reg_select = nlm_read_sys_reg(clockbase,
-				SYS_9XX_CLK_DEV_SEL) & 0x3;
+				SYS_9XX_CLK_DEV_SEL_REG) & 0x3;
 		switch (reg_select) {
 		case 0:
 			ctrl_val0 = nlm_read_sys_reg(clockbase,
@@ -361,7 +361,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 		}
 	} else {
 		reg_select = (nlm_read_sys_reg(sysbase,
-					SYS_CLK_DEV_SEL) >> 22) & 0x3;
+					SYS_CLK_DEV_SEL_REG) >> 22) & 0x3;
 		switch (reg_select) {
 		case 0:
 			ctrl_val0 = nlm_read_sys_reg(sysbase,
@@ -425,10 +425,10 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
 	/* PIC post divider, which happens after PLL */
 	if (cpu_xlp9xx)
 		pic_div = nlm_read_sys_reg(clockbase,
-				SYS_9XX_CLK_DEV_DIV) & 0x3;
+				SYS_9XX_CLK_DEV_DIV_REG) & 0x3;
 	else
 		pic_div = (nlm_read_sys_reg(sysbase,
-					SYS_CLK_DEV_DIV) >> 22) & 0x3;
+					SYS_CLK_DEV_DIV_REG) >> 22) & 0x3;
 	do_div(pll_out_freq_num, 1 << pic_div);
 
 	return pll_out_freq_num;
-- 
1.9.1

[PATCH 07/17] MIPS: MSI: Update MSI handling for XLP

[Jayachandran C]

The per-cpu interrupt ACK using EIRR has to be done just once after
all the bits in the status register are processed.

PIC ack has to be done once in case of MSI, and for every interrupt
in case of MSI-X

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/pci/msi-xlp.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index 6a40f24..3407495 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -178,13 +178,6 @@ static void xlp_msi_mask_ack(struct irq_data *d)
 	else
 		nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
 
-	/* Ack at eirr and PIC */
-	ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
-	if (cpu_is_xlp9xx())
-		nlm_pic_ack(md->node->picbase,
-				PIC_9XX_IRT_PCIE_LINK_INDEX(link));
-	else
-		nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
 }
 
 static struct irq_chip xlp_msi_chip = {
@@ -230,8 +223,6 @@ static void xlp_msix_mask_ack(struct irq_data *d)
 	}
 	nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
 
-	/* Ack at eirr and PIC */
-	ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
 	if (!cpu_is_xlp9xx())
 		nlm_pic_ack(md->node->picbase,
 				PIC_IRT_PCIE_MSIX_INDEX(msixvec));
@@ -541,6 +532,14 @@ void nlm_dispatch_msi(int node, int lirq)
 		do_IRQ(irqbase + i);
 		status &= status - 1;
 	}
+
+	/* Ack at eirr and PIC */
+	ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
+	if (cpu_is_xlp9xx())
+		nlm_pic_ack(md->node->picbase,
+				PIC_9XX_IRT_PCIE_LINK_INDEX(link));
+	else
+		nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
 }
 
 void nlm_dispatch_msix(int node, int lirq)
@@ -567,4 +566,6 @@ void nlm_dispatch_msix(int node, int lirq)
 		do_IRQ(irqbase + i);
 		status &= status - 1;
 	}
+	/* Ack at eirr and PIC */
+	ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
 }
-- 
1.9.1

[PATCH 07/17] MIPS: MSI: Update MSI handling for XLP

[Jayachandran C]

The per-cpu interrupt ACK using EIRR has to be done just once after
all the bits in the status register are processed.

PIC ack has to be done once in case of MSI, and for every interrupt
in case of MSI-X

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/pci/msi-xlp.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index 6a40f24..3407495 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -178,13 +178,6 @@ static void xlp_msi_mask_ack(struct irq_data *d)
 	else
 		nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
 
-	/* Ack at eirr and PIC */
-	ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
-	if (cpu_is_xlp9xx())
-		nlm_pic_ack(md->node->picbase,
-				PIC_9XX_IRT_PCIE_LINK_INDEX(link));
-	else
-		nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
 }
 
 static struct irq_chip xlp_msi_chip = {
@@ -230,8 +223,6 @@ static void xlp_msix_mask_ack(struct irq_data *d)
 	}
 	nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
 
-	/* Ack at eirr and PIC */
-	ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
 	if (!cpu_is_xlp9xx())
 		nlm_pic_ack(md->node->picbase,
 				PIC_IRT_PCIE_MSIX_INDEX(msixvec));
@@ -541,6 +532,14 @@ void nlm_dispatch_msi(int node, int lirq)
 		do_IRQ(irqbase + i);
 		status &= status - 1;
 	}
+
+	/* Ack at eirr and PIC */
+	ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
+	if (cpu_is_xlp9xx())
+		nlm_pic_ack(md->node->picbase,
+				PIC_9XX_IRT_PCIE_LINK_INDEX(link));
+	else
+		nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
 }
 
 void nlm_dispatch_msix(int node, int lirq)
@@ -567,4 +566,6 @@ void nlm_dispatch_msix(int node, int lirq)
 		do_IRQ(irqbase + i);
 		status &= status - 1;
 	}
+	/* Ack at eirr and PIC */
+	ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
 }
-- 
1.9.1

[PATCH 08/17] MIPS: Netlogic: Use MIPS topology.h

[Jayachandran C]

commit bda4584cd943 ("MIPS: Support CPU topology files in sysfs")
added topology related macros for all MIPS platforms and commit
bbbf6d8768f5 ("MIPS: NL: Fix nlm_xlp_defconfig build error")
removed most of the contents from mach-netlogic/topology.h.

The netlogic specific topology is not needed anymore, we just need
to setup the package field in current_cpu_data.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/mach-netlogic/topology.h | 15 ---------------
 arch/mips/netlogic/common/smp.c                |  1 +
 2 files changed, 1 insertion(+), 15 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-netlogic/topology.h

diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
deleted file mode 100644
index 0eb43c8..00000000
--- a/arch/mips/include/asm/mach-netlogic/topology.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2013 Broadcom Corporation
- */
-#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
-#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
-
-#include <asm/mach-netlogic/multi-node.h>
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 4fde7ac..f23fe22 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -120,6 +120,7 @@ static void nlm_init_secondary(void)
 
 	hwtid = hard_smp_processor_id();
 	current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
+	current_cpu_data.package = nlm_cpuid_to_node(hwtid);
 	nlm_percpu_init(hwtid);
 	nlm_smp_irq_init(hwtid);
 }
-- 
1.9.1

[PATCH 08/17] MIPS: Netlogic: Use MIPS topology.h

[Jayachandran C]

commit bda4584cd943 ("MIPS: Support CPU topology files in sysfs")
added topology related macros for all MIPS platforms and commit
bbbf6d8768f5 ("MIPS: NL: Fix nlm_xlp_defconfig build error")
removed most of the contents from mach-netlogic/topology.h.

The netlogic specific topology is not needed anymore, we just need
to setup the package field in current_cpu_data.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/mach-netlogic/topology.h | 15 ---------------
 arch/mips/netlogic/common/smp.c                |  1 +
 2 files changed, 1 insertion(+), 15 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-netlogic/topology.h

diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
deleted file mode 100644
index 0eb43c8..00000000
--- a/arch/mips/include/asm/mach-netlogic/topology.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2013 Broadcom Corporation
- */
-#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
-#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
-
-#include <asm/mach-netlogic/multi-node.h>
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 4fde7ac..f23fe22 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -120,6 +120,7 @@ static void nlm_init_secondary(void)
 
 	hwtid = hard_smp_processor_id();
 	current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
+	current_cpu_data.package = nlm_cpuid_to_node(hwtid);
 	nlm_percpu_init(hwtid);
 	nlm_smp_irq_init(hwtid);
 }
-- 
1.9.1

[PATCH 09/17] MIPS: Netlogic: Move cores per node out of multi-node.h

[Jayachandran C]

Use the current_cpu_data package field to get the node of the current CPU.

This allows us to remove xlp_cores_per_node and move nlm_threads_per_node()
and nlm_cores_per_node() to netlogic/common.h, which simplifies code.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/mach-netlogic/multi-node.h |  9 --------
 arch/mips/include/asm/netlogic/common.h          | 21 ++++++++++++++++++-
 arch/mips/netlogic/common/irq.c                  | 10 ++++-----
 arch/mips/netlogic/common/smp.c                  | 26 +++++++++++++-----------
 arch/mips/netlogic/xlp/setup.c                   |  5 -----
 arch/mips/netlogic/xlp/wakeup.c                  |  8 ++++----
 6 files changed, 43 insertions(+), 36 deletions(-)

diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index 9ed8dac..8bdf47e 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -48,15 +48,6 @@
 #endif
 
 #define NLM_THREADS_PER_CORE	4
-#ifdef CONFIG_CPU_XLR
-#define nlm_cores_per_node()	8
-#else
-extern unsigned int xlp_cores_per_node;
-#define nlm_cores_per_node()	xlp_cores_per_node
-#endif
-
-#define nlm_threads_per_node()	(nlm_cores_per_node() * NLM_THREADS_PER_CORE)
-#define nlm_cpuid_to_node(c)	((c) / nlm_threads_per_node())
 
 struct nlm_soc_info {
 	unsigned long	coremask;	/* cores enabled on the soc */
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index c281f03..2a4c128 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -111,6 +111,25 @@ static inline int nlm_irq_to_xirq(int node, int irq)
 	return node * NR_IRQS / NLM_NR_NODES + irq;
 }
 
-extern int nlm_cpu_ready[];
+#ifdef CONFIG_CPU_XLR
+#define nlm_cores_per_node()	8
+#else
+static inline int nlm_cores_per_node(void)
+{
+	return ((read_c0_prid() & PRID_IMP_MASK)
+				== PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
+}
 #endif
+static inline int nlm_threads_per_node(void)
+{
+	return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
+}
+
+static inline int nlm_hwtid_to_node(int hwtid)
+{
+	return hwtid / nlm_threads_per_node();
+}
+
+extern int nlm_cpu_ready[];
+#endif /* __ASSEMBLY__ */
 #endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index c100b9a..5f5d18b 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -230,16 +230,16 @@ static void nlm_init_node_irqs(int node)
 	}
 }
 
-void nlm_smp_irq_init(int hwcpuid)
+void nlm_smp_irq_init(int hwtid)
 {
-	int node, cpu;
+	int cpu, node;
 
-	node = nlm_cpuid_to_node(hwcpuid);
-	cpu  = hwcpuid % nlm_threads_per_node();
+	cpu = hwtid % nlm_threads_per_node();
+	node = hwtid / nlm_threads_per_node();
 
 	if (cpu == 0 && node != 0)
 		nlm_init_node_irqs(node);
-	write_c0_eimr(nlm_current_node()->irqmask);
+	write_c0_eimr(nlm_get_node(node)->irqmask);
 }
 
 asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index f23fe22..1f709db 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -59,17 +59,17 @@
 
 void nlm_send_ipi_single(int logical_cpu, unsigned int action)
 {
-	int cpu, node;
+	unsigned int hwtid;
 	uint64_t picbase;
 
-	cpu = cpu_logical_map(logical_cpu);
-	node = nlm_cpuid_to_node(cpu);
-	picbase = nlm_get_node(node)->picbase;
+	/* node id is part of hwtid, and needed for send_ipi */
+	hwtid = cpu_logical_map(logical_cpu);
+	picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
 
 	if (action & SMP_CALL_FUNCTION)
-		nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_FUNCTION, 0);
+		nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
 	if (action & SMP_RESCHEDULE_YOURSELF)
-		nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
+		nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
 }
 
 void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -120,7 +120,7 @@ static void nlm_init_secondary(void)
 
 	hwtid = hard_smp_processor_id();
 	current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
-	current_cpu_data.package = nlm_cpuid_to_node(hwtid);
+	current_cpu_data.package = nlm_nodeid();
 	nlm_percpu_init(hwtid);
 	nlm_smp_irq_init(hwtid);
 }
@@ -146,16 +146,18 @@ static cpumask_t phys_cpu_present_mask;
 
 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 {
-	int cpu, node;
+	uint64_t picbase;
+	int hwtid;
+
+	hwtid = cpu_logical_map(logical_cpu);
+	picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
 
-	cpu = cpu_logical_map(logical_cpu);
-	node = nlm_cpuid_to_node(logical_cpu);
 	nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
 	nlm_next_gp = (unsigned long)task_thread_info(idle);
 
 	/* barrier for sp/gp store above */
 	__sync();
-	nlm_pic_send_ipi(nlm_get_node(node)->picbase, cpu, 1, 1);  /* NMI */
+	nlm_pic_send_ipi(picbase, hwtid, 1, 1);  /* NMI */
 }
 
 void __init nlm_smp_setup(void)
@@ -184,7 +186,7 @@ void __init nlm_smp_setup(void)
 			__cpu_number_map[i] = num_cpus;
 			__cpu_logical_map[num_cpus] = i;
 			set_cpu_possible(num_cpus, true);
-			node = nlm_cpuid_to_node(i);
+			node = nlm_hwtid_to_node(i);
 			cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
 			++num_cpus;
 		}
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 4fdd9fd..27113a1 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -51,7 +51,6 @@ uint64_t nlm_io_base;
 struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 cpumask_t nlm_cpumask = CPU_MASK_CPU0;
 unsigned int nlm_threads_per_core;
-unsigned int xlp_cores_per_node;
 
 static void nlm_linux_exit(void)
 {
@@ -163,10 +162,6 @@ void __init prom_init(void)
 	void *reset_vec;
 
 	nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
-	if (cpu_is_xlp9xx())
-		xlp_cores_per_node = 32;
-	else
-		xlp_cores_per_node = 8;
 	nlm_init_boot_cpu();
 	xlp_mmu_init();
 	nlm_node_init(0);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index 26d82f7..87d7846 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -111,7 +111,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 	struct nlm_soc_info *nodep;
 	uint64_t syspcibase, fusebase;
 	uint32_t syscoremask, mask, fusemask;
-	int core, n, cpu;
+	int core, n, cpu, ncores;
 
 	for (n = 0; n < NLM_NR_NODES; n++) {
 		if (n != 0) {
@@ -168,7 +168,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 		syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
 
 		pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
-		for (core = 0; core < nlm_cores_per_node(); core++) {
+		ncores = nlm_cores_per_node();
+		for (core = 0; core < ncores; core++) {
 			/* we will be on node 0 core 0 */
 			if (n == 0 && core == 0)
 				continue;
@@ -178,8 +179,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 				continue;
 
 			/* see if at least the first hw thread is enabled */
-			cpu = (n * nlm_cores_per_node() + core)
-						* NLM_THREADS_PER_CORE;
+			cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
 			if (!cpumask_test_cpu(cpu, wakeup_mask))
 				continue;
 
-- 
1.9.1

[PATCH 09/17] MIPS: Netlogic: Move cores per node out of multi-node.h

[Jayachandran C]

Use the current_cpu_data package field to get the node of the current CPU.

This allows us to remove xlp_cores_per_node and move nlm_threads_per_node()
and nlm_cores_per_node() to netlogic/common.h, which simplifies code.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/mach-netlogic/multi-node.h |  9 --------
 arch/mips/include/asm/netlogic/common.h          | 21 ++++++++++++++++++-
 arch/mips/netlogic/common/irq.c                  | 10 ++++-----
 arch/mips/netlogic/common/smp.c                  | 26 +++++++++++++-----------
 arch/mips/netlogic/xlp/setup.c                   |  5 -----
 arch/mips/netlogic/xlp/wakeup.c                  |  8 ++++----
 6 files changed, 43 insertions(+), 36 deletions(-)

diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index 9ed8dac..8bdf47e 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -48,15 +48,6 @@
 #endif
 
 #define NLM_THREADS_PER_CORE	4
-#ifdef CONFIG_CPU_XLR
-#define nlm_cores_per_node()	8
-#else
-extern unsigned int xlp_cores_per_node;
-#define nlm_cores_per_node()	xlp_cores_per_node
-#endif
-
-#define nlm_threads_per_node()	(nlm_cores_per_node() * NLM_THREADS_PER_CORE)
-#define nlm_cpuid_to_node(c)	((c) / nlm_threads_per_node())
 
 struct nlm_soc_info {
 	unsigned long	coremask;	/* cores enabled on the soc */
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index c281f03..2a4c128 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -111,6 +111,25 @@ static inline int nlm_irq_to_xirq(int node, int irq)
 	return node * NR_IRQS / NLM_NR_NODES + irq;
 }
 
-extern int nlm_cpu_ready[];
+#ifdef CONFIG_CPU_XLR
+#define nlm_cores_per_node()	8
+#else
+static inline int nlm_cores_per_node(void)
+{
+	return ((read_c0_prid() & PRID_IMP_MASK)
+				== PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
+}
 #endif
+static inline int nlm_threads_per_node(void)
+{
+	return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
+}
+
+static inline int nlm_hwtid_to_node(int hwtid)
+{
+	return hwtid / nlm_threads_per_node();
+}
+
+extern int nlm_cpu_ready[];
+#endif /* __ASSEMBLY__ */
 #endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index c100b9a..5f5d18b 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -230,16 +230,16 @@ static void nlm_init_node_irqs(int node)
 	}
 }
 
-void nlm_smp_irq_init(int hwcpuid)
+void nlm_smp_irq_init(int hwtid)
 {
-	int node, cpu;
+	int cpu, node;
 
-	node = nlm_cpuid_to_node(hwcpuid);
-	cpu  = hwcpuid % nlm_threads_per_node();
+	cpu = hwtid % nlm_threads_per_node();
+	node = hwtid / nlm_threads_per_node();
 
 	if (cpu == 0 && node != 0)
 		nlm_init_node_irqs(node);
-	write_c0_eimr(nlm_current_node()->irqmask);
+	write_c0_eimr(nlm_get_node(node)->irqmask);
 }
 
 asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index f23fe22..1f709db 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -59,17 +59,17 @@
 
 void nlm_send_ipi_single(int logical_cpu, unsigned int action)
 {
-	int cpu, node;
+	unsigned int hwtid;
 	uint64_t picbase;
 
-	cpu = cpu_logical_map(logical_cpu);
-	node = nlm_cpuid_to_node(cpu);
-	picbase = nlm_get_node(node)->picbase;
+	/* node id is part of hwtid, and needed for send_ipi */
+	hwtid = cpu_logical_map(logical_cpu);
+	picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
 
 	if (action & SMP_CALL_FUNCTION)
-		nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_FUNCTION, 0);
+		nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
 	if (action & SMP_RESCHEDULE_YOURSELF)
-		nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
+		nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
 }
 
 void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -120,7 +120,7 @@ static void nlm_init_secondary(void)
 
 	hwtid = hard_smp_processor_id();
 	current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
-	current_cpu_data.package = nlm_cpuid_to_node(hwtid);
+	current_cpu_data.package = nlm_nodeid();
 	nlm_percpu_init(hwtid);
 	nlm_smp_irq_init(hwtid);
 }
@@ -146,16 +146,18 @@ static cpumask_t phys_cpu_present_mask;
 
 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 {
-	int cpu, node;
+	uint64_t picbase;
+	int hwtid;
+
+	hwtid = cpu_logical_map(logical_cpu);
+	picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
 
-	cpu = cpu_logical_map(logical_cpu);
-	node = nlm_cpuid_to_node(logical_cpu);
 	nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
 	nlm_next_gp = (unsigned long)task_thread_info(idle);
 
 	/* barrier for sp/gp store above */
 	__sync();
-	nlm_pic_send_ipi(nlm_get_node(node)->picbase, cpu, 1, 1);  /* NMI */
+	nlm_pic_send_ipi(picbase, hwtid, 1, 1);  /* NMI */
 }
 
 void __init nlm_smp_setup(void)
@@ -184,7 +186,7 @@ void __init nlm_smp_setup(void)
 			__cpu_number_map[i] = num_cpus;
 			__cpu_logical_map[num_cpus] = i;
 			set_cpu_possible(num_cpus, true);
-			node = nlm_cpuid_to_node(i);
+			node = nlm_hwtid_to_node(i);
 			cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
 			++num_cpus;
 		}
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 4fdd9fd..27113a1 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -51,7 +51,6 @@ uint64_t nlm_io_base;
 struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 cpumask_t nlm_cpumask = CPU_MASK_CPU0;
 unsigned int nlm_threads_per_core;
-unsigned int xlp_cores_per_node;
 
 static void nlm_linux_exit(void)
 {
@@ -163,10 +162,6 @@ void __init prom_init(void)
 	void *reset_vec;
 
 	nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
-	if (cpu_is_xlp9xx())
-		xlp_cores_per_node = 32;
-	else
-		xlp_cores_per_node = 8;
 	nlm_init_boot_cpu();
 	xlp_mmu_init();
 	nlm_node_init(0);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index 26d82f7..87d7846 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -111,7 +111,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 	struct nlm_soc_info *nodep;
 	uint64_t syspcibase, fusebase;
 	uint32_t syscoremask, mask, fusemask;
-	int core, n, cpu;
+	int core, n, cpu, ncores;
 
 	for (n = 0; n < NLM_NR_NODES; n++) {
 		if (n != 0) {
@@ -168,7 +168,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 		syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
 
 		pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
-		for (core = 0; core < nlm_cores_per_node(); core++) {
+		ncores = nlm_cores_per_node();
+		for (core = 0; core < ncores; core++) {
 			/* we will be on node 0 core 0 */
 			if (n == 0 && core == 0)
 				continue;
@@ -178,8 +179,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 				continue;
 
 			/* see if at least the first hw thread is enabled */
-			cpu = (n * nlm_cores_per_node() + core)
-						* NLM_THREADS_PER_CORE;
+			cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
 			if (!cpumask_test_cpu(cpu, wakeup_mask))
 				continue;
 
-- 
1.9.1

[PATCH 10/17] MIPS: Netlogic: nlm_core_id for xlp9xx

[Jayachandran C]

XLP9XX has 5 bits that specify the core in the EBASE register. XLP5XX
case added as well for completeness.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/mips-extns.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 06f1f75..788baf3 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -157,7 +157,13 @@ static inline int nlm_nodeid(void)
 
 static inline unsigned int nlm_core_id(void)
 {
-	return (read_c0_ebase() & 0x1c) >> 2;
+	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
+
+	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
+			(prid == PRID_IMP_NETLOGIC_XLP5XX))
+		return (read_c0_ebase() & 0x7c) >> 2;
+	else
+		return (read_c0_ebase() & 0x1c) >> 2;
 }
 
 static inline unsigned int nlm_thread_id(void)
-- 
1.9.1

[PATCH 10/17] MIPS: Netlogic: nlm_core_id for xlp9xx

[Jayachandran C]

XLP9XX has 5 bits that specify the core in the EBASE register. XLP5XX
case added as well for completeness.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/mips-extns.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 06f1f75..788baf3 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -157,7 +157,13 @@ static inline int nlm_nodeid(void)
 
 static inline unsigned int nlm_core_id(void)
 {
-	return (read_c0_ebase() & 0x1c) >> 2;
+	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
+
+	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
+			(prid == PRID_IMP_NETLOGIC_XLP5XX))
+		return (read_c0_ebase() & 0x7c) >> 2;
+	else
+		return (read_c0_ebase() & 0x1c) >> 2;
 }
 
 static inline unsigned int nlm_thread_id(void)
-- 
1.9.1

[PATCH 11/17] MIPS: Netlogic: Added HugeTLB as default

[Jayachandran C]

From: Prem Mallappa <pmallapp@broadcom.com>

Enable CPU_SUPPORTS_HUGEPAGES for XLP processors.

Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3289969..74a76da 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1532,6 +1532,7 @@ config CPU_XLP
 	select WEAK_REORDERING_BEYOND_LLSC
 	select CPU_HAS_PREFETCH
 	select CPU_MIPSR2
+	select CPU_SUPPORTS_HUGEPAGES
 	help
 	  Netlogic Microsystems XLP processors.
 endchoice
-- 
1.9.1

[PATCH 11/17] MIPS: Netlogic: Added HugeTLB as default

[Jayachandran C]

From: Prem Mallappa <pmallapp@broadcom.com>

Enable CPU_SUPPORTS_HUGEPAGES for XLP processors.

Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3289969..74a76da 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1532,6 +1532,7 @@ config CPU_XLP
 	select WEAK_REORDERING_BEYOND_LLSC
 	select CPU_HAS_PREFETCH
 	select CPU_MIPSR2
+	select CPU_SUPPORTS_HUGEPAGES
 	help
 	  Netlogic Microsystems XLP processors.
 endchoice
-- 
1.9.1

[PATCH 12/17] MIPS: Netlogic: Update function to read DRAM BARs

[Jayachandran C]

Change name of xlp_get_dram_map to nlm_get_dram_map to be consistent
with the rest of the functions in the file. Pass the the size of the
array 'dram_map' to the function, and ensure that it does not write
past the end of the array.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |  2 +-
 arch/mips/netlogic/xlp/nlm_hal.c             | 12 +++++++-----
 arch/mips/netlogic/xlp/setup.c               |  2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index a862b93..c0b2a80 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -89,7 +89,7 @@ void xlp_wakeup_secondary_cpus(void);
 
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
-int xlp_get_dram_map(int n, uint64_t *dram_map);
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
 
 struct pci_dev;
 int xlp_socdev_to_node(const struct pci_dev *dev);
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index b80d893..c6c31e3 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -449,19 +449,21 @@ unsigned int nlm_get_cpu_frequency(void)
 
 /*
  * Fills upto 8 pairs of entries containing the DRAM map of a node
- * if n < 0, get dram map for all nodes
+ * if node < 0, get dram map for all nodes
  */
-int xlp_get_dram_map(int n, uint64_t *dram_map)
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries)
 {
 	uint64_t bridgebase, base, lim;
 	uint32_t val;
 	unsigned int barreg, limreg, xlatreg;
-	int i, node, rv;
+	int i, n, rv;
 
 	/* Look only at mapping on Node 0, we don't handle crazy configs */
 	bridgebase = nlm_get_bridge_regbase(0);
 	rv = 0;
 	for (i = 0; i < 8; i++) {
+		if (rv + 1 >= nentries)
+			break;
 		if (cpu_is_xlp9xx()) {
 			barreg = BRIDGE_9XX_DRAM_BAR(i);
 			limreg = BRIDGE_9XX_DRAM_LIMIT(i);
@@ -471,10 +473,10 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
 			limreg = BRIDGE_DRAM_LIMIT(i);
 			xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
 		}
-		if (n >= 0) {
+		if (node >= 0) {
 			/* node specified, get node mapping of BAR */
 			val = nlm_read_bridge_reg(bridgebase, xlatreg);
-			node = (val >> 1) & 0x3;
+			n = (val >> 1) & 0x3;
 			if (n != node)
 				continue;
 		}
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 27113a1..f743fd9 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -81,7 +81,7 @@ static void __init xlp_init_mem_from_bars(void)
 	uint64_t map[16];
 	int i, n;
 
-	n = xlp_get_dram_map(-1, map);	/* -1: info for all nodes */
+	n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map));	/* -1 : all nodes */
 	for (i = 0; i < n; i += 2) {
 		/* exclude 0x1000_0000-0x2000_0000, u-boot device */
 		if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
-- 
1.9.1

[PATCH 12/17] MIPS: Netlogic: Update function to read DRAM BARs

[Jayachandran C]

Change name of xlp_get_dram_map to nlm_get_dram_map to be consistent
with the rest of the functions in the file. Pass the the size of the
array 'dram_map' to the function, and ensure that it does not write
past the end of the array.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |  2 +-
 arch/mips/netlogic/xlp/nlm_hal.c             | 12 +++++++-----
 arch/mips/netlogic/xlp/setup.c               |  2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index a862b93..c0b2a80 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -89,7 +89,7 @@ void xlp_wakeup_secondary_cpus(void);
 
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
-int xlp_get_dram_map(int n, uint64_t *dram_map);
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
 
 struct pci_dev;
 int xlp_socdev_to_node(const struct pci_dev *dev);
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index b80d893..c6c31e3 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -449,19 +449,21 @@ unsigned int nlm_get_cpu_frequency(void)
 
 /*
  * Fills upto 8 pairs of entries containing the DRAM map of a node
- * if n < 0, get dram map for all nodes
+ * if node < 0, get dram map for all nodes
  */
-int xlp_get_dram_map(int n, uint64_t *dram_map)
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries)
 {
 	uint64_t bridgebase, base, lim;
 	uint32_t val;
 	unsigned int barreg, limreg, xlatreg;
-	int i, node, rv;
+	int i, n, rv;
 
 	/* Look only at mapping on Node 0, we don't handle crazy configs */
 	bridgebase = nlm_get_bridge_regbase(0);
 	rv = 0;
 	for (i = 0; i < 8; i++) {
+		if (rv + 1 >= nentries)
+			break;
 		if (cpu_is_xlp9xx()) {
 			barreg = BRIDGE_9XX_DRAM_BAR(i);
 			limreg = BRIDGE_9XX_DRAM_LIMIT(i);
@@ -471,10 +473,10 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
 			limreg = BRIDGE_DRAM_LIMIT(i);
 			xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
 		}
-		if (n >= 0) {
+		if (node >= 0) {
 			/* node specified, get node mapping of BAR */
 			val = nlm_read_bridge_reg(bridgebase, xlatreg);
-			node = (val >> 1) & 0x3;
+			n = (val >> 1) & 0x3;
 			if (n != node)
 				continue;
 		}
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 27113a1..f743fd9 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -81,7 +81,7 @@ static void __init xlp_init_mem_from_bars(void)
 	uint64_t map[16];
 	int i, n;
 
-	n = xlp_get_dram_map(-1, map);	/* -1: info for all nodes */
+	n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map));	/* -1 : all nodes */
 	for (i = 0; i < n; i += 2) {
 		/* exclude 0x1000_0000-0x2000_0000, u-boot device */
 		if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
-- 
1.9.1

[PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Jayachandran C]

Core configuration register IFU_BRUB_RESERVE has to be setup to handle
a silicon errata which can result in a CPU hang.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h |  2 ++
 arch/mips/netlogic/common/reset.S                   | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 6d2e58a..a06b592 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
 #define CPU_BLOCKID_FPU		9
 #define CPU_BLOCKID_MAP		10
 
+#define IFU_BRUB_RESERVE	0x007
+
 #define ICU_DEFEATURE		0x100
 
 #define LSU_DEFEATURE		0x304
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 701c4bc..ff2673a 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -235,6 +235,24 @@ EXPORT(nlm_boot_siblings)
 	mfc0	v0, CP0_EBASE, 1
 	andi	v0, 0x3ff		/* v0 <- node/core */
 
+	/* Errata: to avoid potential live lock, only apply to 4
+	 * thread per core mode */
+	andi	v1, v0, 0x3             /* v1 <- thread id */
+	bnez	v1, 2f
+	nop
+
+	/* thread 0 of each core. */
+	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
+	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
+	subu	t1, 0x3				/* 4-thread per core mode? */
+	bnez	t1, 2f
+	nop
+
+	li	t0, IFU_BRUB_RESERVE
+	li	t1, 0x55
+	mtcr	t1, t0
+	_ehb
+2:
 	beqz	v0, 4f		/* boot cpu (cpuid == 0)? */
 	nop
 
-- 
1.9.1

[PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Jayachandran C]

Core configuration register IFU_BRUB_RESERVE has to be setup to handle
a silicon errata which can result in a CPU hang.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h |  2 ++
 arch/mips/netlogic/common/reset.S                   | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 6d2e58a..a06b592 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
 #define CPU_BLOCKID_FPU		9
 #define CPU_BLOCKID_MAP		10
 
+#define IFU_BRUB_RESERVE	0x007
+
 #define ICU_DEFEATURE		0x100
 
 #define LSU_DEFEATURE		0x304
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 701c4bc..ff2673a 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -235,6 +235,24 @@ EXPORT(nlm_boot_siblings)
 	mfc0	v0, CP0_EBASE, 1
 	andi	v0, 0x3ff		/* v0 <- node/core */
 
+	/* Errata: to avoid potential live lock, only apply to 4
+	 * thread per core mode */
+	andi	v1, v0, 0x3             /* v1 <- thread id */
+	bnez	v1, 2f
+	nop
+
+	/* thread 0 of each core. */
+	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
+	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
+	subu	t1, 0x3				/* 4-thread per core mode? */
+	bnez	t1, 2f
+	nop
+
+	li	t0, IFU_BRUB_RESERVE
+	li	t1, 0x55
+	mtcr	t1, t0
+	_ehb
+2:
 	beqz	v0, 4f		/* boot cpu (cpuid == 0)? */
 	nop
 
-- 
1.9.1

Re: [PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Sergei Shtylyov]

Hello.

On 01/07/2015 02:28 PM, Jayachandran C wrote:

> Core configuration register IFU_BRUB_RESERVE has to be setup to handle
> a silicon errata which can result in a CPU hang.

> Signed-off-by: Jayachandran C <jchandra@broadcom.com>

[...]

> diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
> index 701c4bc..ff2673a 100644
> --- a/arch/mips/netlogic/common/reset.S
> +++ b/arch/mips/netlogic/common/reset.S
> @@ -235,6 +235,24 @@ EXPORT(nlm_boot_siblings)
>   	mfc0	v0, CP0_EBASE, 1
>   	andi	v0, 0x3ff		/* v0 <- node/core */
>
> +	/* Errata: to avoid potential live lock, only apply to 4
> +	 * thread per core mode */

    The preferred multi-line comment style is:

/*
  * bla
  * bla
  */

> +	andi	v1, v0, 0x3             /* v1 <- thread id */
> +	bnez	v1, 2f
> +	nop

    If this 'nop' is in a delay slot, there's a tradition to add extra space 
before the instruction.

> +
> +	/* thread 0 of each core. */
> +	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)

    Hm, does this get auto-expanded into several instructions?

> +	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
> +	subu	t1, 0x3				/* 4-thread per core mode? */
> +	bnez	t1, 2f
> +	nop

    Same here...

WBR, Sergei

Re: [PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[David Daney]

On 01/07/2015 09:21 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/07/2015 02:28 PM, Jayachandran C wrote:
[...]
>> +
>> +    /* thread 0 of each core. */
>> +    li    t0, CKSEG1ADDR(RESET_DATA_PHYS)
>
>     Hm, does this get auto-expanded into several instructions?
>

Of course, it is a standard magic MIPS assembler macro that expands to 
the instructions necessary to load a 32-bit integer constant into the 
register.  It is perfectly normal and acceptable code.

David Daney

Re: [PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Jayachandran C.]

On Wed, Jan 07, 2015 at 08:21:29PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 01/07/2015 02:28 PM, Jayachandran C wrote:
> 
> >Core configuration register IFU_BRUB_RESERVE has to be setup to handle
> >a silicon errata which can result in a CPU hang.
> 
> >Signed-off-by: Jayachandran C <jchandra@broadcom.com>
> 
> [...]
> 
> >diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
> >index 701c4bc..ff2673a 100644
> >--- a/arch/mips/netlogic/common/reset.S
> >+++ b/arch/mips/netlogic/common/reset.S
> >@@ -235,6 +235,24 @@ EXPORT(nlm_boot_siblings)
> >  	mfc0	v0, CP0_EBASE, 1
> >  	andi	v0, 0x3ff		/* v0 <- node/core */
> >
> >+	/* Errata: to avoid potential live lock, only apply to 4
> >+	 * thread per core mode */
> 
>    The preferred multi-line comment style is:
> 
> /*
>  * bla
>  * bla
>  */

Will fix this and post a new patch.

> >+	andi	v1, v0, 0x3             /* v1 <- thread id */
> >+	bnez	v1, 2f
> >+	nop
> 
>    If this 'nop' is in a delay slot, there's a tradition to add
> extra space before the instruction.
> 
> >+
> >+	/* thread 0 of each core. */
> >+	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
> 
>    Hm, does this get auto-expanded into several instructions?
> 
> >+	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
> >+	subu	t1, 0x3				/* 4-thread per core mode? */
> >+	bnez	t1, 2f
> >+	nop
> 
>    Same here...

I did not know about this convention, so none of the Netlogic platform
files have the space before delay slot instruction. I will have to fixup
all of them in one commit if needed.

Thanks,
JC.

Re: [PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Jayachandran C.]

On Wed, Jan 07, 2015 at 08:21:29PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 01/07/2015 02:28 PM, Jayachandran C wrote:
> 
> >Core configuration register IFU_BRUB_RESERVE has to be setup to handle
> >a silicon errata which can result in a CPU hang.
> 
> >Signed-off-by: Jayachandran C <jchandra@broadcom.com>
> 
> [...]
> 
> >diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
> >index 701c4bc..ff2673a 100644
> >--- a/arch/mips/netlogic/common/reset.S
> >+++ b/arch/mips/netlogic/common/reset.S
> >@@ -235,6 +235,24 @@ EXPORT(nlm_boot_siblings)
> >  	mfc0	v0, CP0_EBASE, 1
> >  	andi	v0, 0x3ff		/* v0 <- node/core */
> >
> >+	/* Errata: to avoid potential live lock, only apply to 4
> >+	 * thread per core mode */
> 
>    The preferred multi-line comment style is:
> 
> /*
>  * bla
>  * bla
>  */

Will fix this and post a new patch.

> >+	andi	v1, v0, 0x3             /* v1 <- thread id */
> >+	bnez	v1, 2f
> >+	nop
> 
>    If this 'nop' is in a delay slot, there's a tradition to add
> extra space before the instruction.
> 
> >+
> >+	/* thread 0 of each core. */
> >+	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
> 
>    Hm, does this get auto-expanded into several instructions?
> 
> >+	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
> >+	subu	t1, 0x3				/* 4-thread per core mode? */
> >+	bnez	t1, 2f
> >+	nop
> 
>    Same here...

I did not know about this convention, so none of the Netlogic platform
files have the space before delay slot instruction. I will have to fixup
all of them in one commit if needed.

Thanks,
JC.

[PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Jayachandran C]

Core configuration register IFU_BRUB_RESERVE has to be setup to handle
a silicon errata which can result in a CPU hang.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h |  2 ++
 arch/mips/netlogic/common/reset.S                   | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 6d2e58a..a06b592 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
 #define CPU_BLOCKID_FPU		9
 #define CPU_BLOCKID_MAP		10
 
+#define IFU_BRUB_RESERVE	0x007
+
 #define ICU_DEFEATURE		0x100
 
 #define LSU_DEFEATURE		0x304
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 701c4bc..e3e5189 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -235,6 +235,26 @@ EXPORT(nlm_boot_siblings)
 	mfc0	v0, CP0_EBASE, 1
 	andi	v0, 0x3ff		/* v0 <- node/core */
 
+	/*
+	 * Errata: to avoid potential live lock, setup IFU_BRUB_RESERVE
+	 * when running 4 threads per core
+	 */
+	andi	v1, v0, 0x3             /* v1 <- thread id */
+	bnez	v1, 2f
+	nop
+
+	/* thread 0 of each core. */
+	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
+	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
+	subu	t1, 0x3				/* 4-thread per core mode? */
+	bnez	t1, 2f
+	nop
+
+	li	t0, IFU_BRUB_RESERVE
+	li	t1, 0x55
+	mtcr	t1, t0
+	_ehb
+2:
 	beqz	v0, 4f		/* boot cpu (cpuid == 0)? */
 	nop
 
-- 
1.9.1

[PATCH 13/17] MIPS: Netlogic: Handle XLP hardware errata

[Jayachandran C]

Core configuration register IFU_BRUB_RESERVE has to be setup to handle
a silicon errata which can result in a CPU hang.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h |  2 ++
 arch/mips/netlogic/common/reset.S                   | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 6d2e58a..a06b592 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
 #define CPU_BLOCKID_FPU		9
 #define CPU_BLOCKID_MAP		10
 
+#define IFU_BRUB_RESERVE	0x007
+
 #define ICU_DEFEATURE		0x100
 
 #define LSU_DEFEATURE		0x304
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 701c4bc..e3e5189 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -235,6 +235,26 @@ EXPORT(nlm_boot_siblings)
 	mfc0	v0, CP0_EBASE, 1
 	andi	v0, 0x3ff		/* v0 <- node/core */
 
+	/*
+	 * Errata: to avoid potential live lock, setup IFU_BRUB_RESERVE
+	 * when running 4 threads per core
+	 */
+	andi	v1, v0, 0x3             /* v1 <- thread id */
+	bnez	v1, 2f
+	nop
+
+	/* thread 0 of each core. */
+	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
+	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
+	subu	t1, 0x3				/* 4-thread per core mode? */
+	bnez	t1, 2f
+	nop
+
+	li	t0, IFU_BRUB_RESERVE
+	li	t1, 0x55
+	mtcr	t1, t0
+	_ehb
+2:
 	beqz	v0, 4f		/* boot cpu (cpuid == 0)? */
 	nop
 
-- 
1.9.1

[PATCH 14/17] MIPS: Netlogic: Do not enable SUE for core

[Jayachandran C]

Enabling the SUE bit for core can can result in rare cache errors
which are difficult to track down, so do not enable it. This can
cause a minor performance loss in some tests.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/common/reset.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index ff2673a..ebbd598 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -60,7 +60,7 @@
 	li	t0, LSU_DEFEATURE
 	mfcr	t1, t0
 
-	lui	t2, 0xc080	/* SUE, Enable Unaligned Access, L2HPE */
+	lui	t2, 0x4080	/* Enable Unaligned Access, L2HPE */
 	or	t1, t1, t2
 	mtcr	t1, t0
 
-- 
1.9.1

[PATCH 14/17] MIPS: Netlogic: Do not enable SUE for core

[Jayachandran C]

Enabling the SUE bit for core can can result in rare cache errors
which are difficult to track down, so do not enable it. This can
cause a minor performance loss in some tests.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/common/reset.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index ff2673a..ebbd598 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -60,7 +60,7 @@
 	li	t0, LSU_DEFEATURE
 	mfcr	t1, t0
 
-	lui	t2, 0xc080	/* SUE, Enable Unaligned Access, L2HPE */
+	lui	t2, 0x4080	/* Enable Unaligned Access, L2HPE */
 	or	t1, t1, t2
 	mtcr	t1, t0
 
-- 
1.9.1

[PATCH 15/17] MIPS: Netlogic: Add irq mapping and setup for XHCI port 3

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Add support for third XHCI port in XLPII processors.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |  1 +
 arch/mips/netlogic/xlp/nlm_hal.c             |  2 ++
 arch/mips/netlogic/xlp/usb-init-xlp2.c       | 10 +++++++++-
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index c0b2a80..feb6ed8 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -52,6 +52,7 @@
 #define PIC_2XX_XHCI_2_IRQ		25
 #define PIC_9XX_XHCI_0_IRQ		23
 #define PIC_9XX_XHCI_1_IRQ		24
+#define PIC_9XX_XHCI_2_IRQ		25
 
 #define PIC_MMC_IRQ			29
 #define PIC_I2C_0_IRQ			30
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index c6c31e3..8d743d0 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -75,6 +75,8 @@ static int xlp9xx_irq_to_irt(int irq)
 		return 114;
 	case PIC_9XX_XHCI_1_IRQ:
 		return 115;
+	case PIC_9XX_XHCI_2_IRQ:
+		return 116;
 	case PIC_UART_0_IRQ:
 		return 133;
 	case PIC_UART_1_IRQ:
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
index 17ade1c..2524939 100644
--- a/arch/mips/netlogic/xlp/usb-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -128,6 +128,9 @@ static void xlp9xx_usb_ack(struct irq_data *data)
 	case PIC_9XX_XHCI_1_IRQ:
 		port_addr = nlm_xlpii_get_usb_regbase(node, 2);
 		break;
+	case PIC_9XX_XHCI_2_IRQ:
+		port_addr = nlm_xlpii_get_usb_regbase(node, 3);
+		break;
 	default:
 		pr_err("No matching USB irq %d node  %d!\n", irq, node);
 		return;
@@ -222,14 +225,16 @@ static int __init nlm_platform_xlpii_usb_init(void)
 	}
 
 	/* XLP 9XX, multi-node */
-	pr_info("Initializing 9XX USB Interface\n");
+	pr_info("Initializing 9XX/5XX USB Interface\n");
 	for (node = 0; node < NLM_NR_NODES; node++) {
 		if (!nlm_node_present(node))
 			continue;
 		nlm_xlpii_usb_hw_reset(node, 1);
 		nlm_xlpii_usb_hw_reset(node, 2);
+		nlm_xlpii_usb_hw_reset(node, 3);
 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
+		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_2_IRQ, xlp9xx_usb_ack);
 	}
 	return 0;
 }
@@ -253,6 +258,9 @@ static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
 	case 0x22:
 		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
 		break;
+	case 0x23:
+		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_2_IRQ);
+		break;
 	}
 }
 
-- 
1.9.1

[PATCH 15/17] MIPS: Netlogic: Add irq mapping and setup for XHCI port 3

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Add support for third XHCI port in XLPII processors.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |  1 +
 arch/mips/netlogic/xlp/nlm_hal.c             |  2 ++
 arch/mips/netlogic/xlp/usb-init-xlp2.c       | 10 +++++++++-
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index c0b2a80..feb6ed8 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -52,6 +52,7 @@
 #define PIC_2XX_XHCI_2_IRQ		25
 #define PIC_9XX_XHCI_0_IRQ		23
 #define PIC_9XX_XHCI_1_IRQ		24
+#define PIC_9XX_XHCI_2_IRQ		25
 
 #define PIC_MMC_IRQ			29
 #define PIC_I2C_0_IRQ			30
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index c6c31e3..8d743d0 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -75,6 +75,8 @@ static int xlp9xx_irq_to_irt(int irq)
 		return 114;
 	case PIC_9XX_XHCI_1_IRQ:
 		return 115;
+	case PIC_9XX_XHCI_2_IRQ:
+		return 116;
 	case PIC_UART_0_IRQ:
 		return 133;
 	case PIC_UART_1_IRQ:
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
index 17ade1c..2524939 100644
--- a/arch/mips/netlogic/xlp/usb-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -128,6 +128,9 @@ static void xlp9xx_usb_ack(struct irq_data *data)
 	case PIC_9XX_XHCI_1_IRQ:
 		port_addr = nlm_xlpii_get_usb_regbase(node, 2);
 		break;
+	case PIC_9XX_XHCI_2_IRQ:
+		port_addr = nlm_xlpii_get_usb_regbase(node, 3);
+		break;
 	default:
 		pr_err("No matching USB irq %d node  %d!\n", irq, node);
 		return;
@@ -222,14 +225,16 @@ static int __init nlm_platform_xlpii_usb_init(void)
 	}
 
 	/* XLP 9XX, multi-node */
-	pr_info("Initializing 9XX USB Interface\n");
+	pr_info("Initializing 9XX/5XX USB Interface\n");
 	for (node = 0; node < NLM_NR_NODES; node++) {
 		if (!nlm_node_present(node))
 			continue;
 		nlm_xlpii_usb_hw_reset(node, 1);
 		nlm_xlpii_usb_hw_reset(node, 2);
+		nlm_xlpii_usb_hw_reset(node, 3);
 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
+		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_2_IRQ, xlp9xx_usb_ack);
 	}
 	return 0;
 }
@@ -253,6 +258,9 @@ static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
 	case 0x22:
 		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
 		break;
+	case 0x23:
+		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_2_IRQ);
+		break;
 	}
 }
 
-- 
1.9.1

[PATCH 16/17] MIPS: Netlogic: i2c IRQ mappings for XLP9XX

[Jayachandran C]

From: Subhendu Sekhar Behera <sbehera@broadcom.com>

The new I2C block in XLP9XX has 4 interrupts, add the mapping for
these in nlm_hal.c

Signed-off-by: Subhendu Sekhar Behera <sbehera@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/nlm_hal.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 8d743d0..a8f4144 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -71,6 +71,14 @@ static int xlp9xx_irq_to_irt(int irq)
 	switch (irq) {
 	case PIC_GPIO_IRQ:
 		return 12;
+	case PIC_I2C_0_IRQ:
+		return 125;
+	case PIC_I2C_1_IRQ:
+		return 126;
+	case PIC_I2C_2_IRQ:
+		return 127;
+	case PIC_I2C_3_IRQ:
+		return 128;
 	case PIC_9XX_XHCI_0_IRQ:
 		return 114;
 	case PIC_9XX_XHCI_1_IRQ:
-- 
1.9.1

[PATCH 16/17] MIPS: Netlogic: i2c IRQ mappings for XLP9XX

[Jayachandran C]

From: Subhendu Sekhar Behera <sbehera@broadcom.com>

The new I2C block in XLP9XX has 4 interrupts, add the mapping for
these in nlm_hal.c

Signed-off-by: Subhendu Sekhar Behera <sbehera@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/netlogic/xlp/nlm_hal.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 8d743d0..a8f4144 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -71,6 +71,14 @@ static int xlp9xx_irq_to_irt(int irq)
 	switch (irq) {
 	case PIC_GPIO_IRQ:
 		return 12;
+	case PIC_I2C_0_IRQ:
+		return 125;
+	case PIC_I2C_1_IRQ:
+		return 126;
+	case PIC_I2C_2_IRQ:
+		return 127;
+	case PIC_I2C_3_IRQ:
+		return 128;
 	case PIC_9XX_XHCI_0_IRQ:
 		return 114;
 	case PIC_9XX_XHCI_1_IRQ:
-- 
1.9.1

[PATCH 17/17] MIPS: Netlogic: Add built-in dts for XLP5xx boards

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/boot/dts/Makefile    |  1 +
 arch/mips/boot/dts/xlp_rvp.dts | 77 ++++++++++++++++++++++++++++++++++++++++++
 arch/mips/netlogic/Kconfig     |  9 +++++
 arch/mips/netlogic/xlp/dt.c    | 10 ++++--
 4 files changed, 94 insertions(+), 3 deletions(-)
 create mode 100644 arch/mips/boot/dts/xlp_rvp.dts

diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 4f49fa4..de26ec6 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_DT_XLP_EVP)		+= xlp_evp.dtb
 dtb-$(CONFIG_DT_XLP_SVP)		+= xlp_svp.dtb
 dtb-$(CONFIG_DT_XLP_FVP)		+= xlp_fvp.dtb
 dtb-$(CONFIG_DT_XLP_GVP)		+= xlp_gvp.dtb
+dtb-$(CONFIG_DT_XLP_RVP)		+= xlp_rvp.dtb
 dtb-$(CONFIG_DTB_RT2880_EVAL)		+= rt2880_eval.dtb
 dtb-$(CONFIG_DTB_RT305X_EVAL)		+= rt3052_eval.dtb
 dtb-$(CONFIG_DTB_RT3883_EVAL)		+= rt3883_eval.dtb
diff --git a/arch/mips/boot/dts/xlp_rvp.dts b/arch/mips/boot/dts/xlp_rvp.dts
new file mode 100644
index 00000000..7188aed
--- /dev/null
+++ b/arch/mips/boot/dts/xlp_rvp.dts
@@ -0,0 +1,77 @@
+/*
+ * XLP5XX Device Tree Source for RVP boards
+ */
+
+/dts-v1/;
+/ {
+	model = "netlogic,XLP-RVP";
+	compatible = "netlogic,xlp";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+		serial0: serial@30000 {
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0 0x112100 0xa00>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <125000000>;
+			interrupt-parent = <&pic>;
+			interrupts = <17>;
+		};
+		pic: pic@110000 {
+			compatible = "netlogic,xlp-pic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0 0x110000 0x200>;
+			interrupt-controller;
+		};
+
+		nor_flash@1,0 {
+			compatible = "cfi-flash";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			reg = <1 0 0x1000000>;
+
+			partition@0 {
+				label = "x-loader";
+				reg = <0x0 0x100000>; /* 1M */
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot";
+				reg = <0x100000 0x100000>; /* 1M */
+			};
+
+			partition@200000 {
+				label = "kernel";
+				reg = <0x200000 0x500000>; /* 5M */
+			};
+
+			partition@700000 {
+				label = "rootfs";
+				reg = <0x700000 0x800000>; /* 8M */
+			};
+
+			partition@f00000 {
+				label = "env";
+				reg = <0xf00000 0x100000>; /* 1M */
+				read-only;
+			};
+		};
+
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+	};
+};
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 0823321..fb00606 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -41,6 +41,15 @@ config DT_XLP_GVP
 	  pointer to the kernel.  The corresponding DTS file is at
 	  arch/mips/netlogic/dts/xlp_gvp.dts
 
+config DT_XLP_RVP
+	bool "Built-in device tree for XLP RVP boards"
+	default y
+	help
+	  Add an FDT blob for XLP RVP board into the kernel.
+	  This DTB will be used if the firmware does not pass in a DTB
+	  pointer to the kernel.  The corresponding DTS file is at
+	  arch/mips/netlogic/dts/xlp_rvp.dts
+
 config NLM_MULTINODE
 	bool "Support for multi-chip boards"
 	depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index 7cc4603..a625bdb 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -41,17 +41,21 @@
 
 #include <asm/prom.h>
 
-extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
-	__dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[];
+extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_xlp_fvp_begin[],
+	__dtb_xlp_gvp_begin[], __dtb_xlp_rvp_begin[];
 static void *xlp_fdt_blob;
 
 void __init *xlp_dt_init(void *fdtp)
 {
 	if (!fdtp) {
 		switch (current_cpu_data.processor_id & PRID_IMP_MASK) {
+#ifdef CONFIG_DT_XLP_RVP
+		case PRID_IMP_NETLOGIC_XLP5XX:
+			fdtp = __dtb_xlp_rvp_begin;
+			break;
+#endif
 #ifdef CONFIG_DT_XLP_GVP
 		case PRID_IMP_NETLOGIC_XLP9XX:
-		case PRID_IMP_NETLOGIC_XLP5XX:
 			fdtp = __dtb_xlp_gvp_begin;
 			break;
 #endif
-- 
1.9.1

[PATCH 17/17] MIPS: Netlogic: Add built-in dts for XLP5xx boards

[Jayachandran C]

From: Ganesan Ramalingam <ganesanr@broadcom.com>

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
 arch/mips/boot/dts/Makefile    |  1 +
 arch/mips/boot/dts/xlp_rvp.dts | 77 ++++++++++++++++++++++++++++++++++++++++++
 arch/mips/netlogic/Kconfig     |  9 +++++
 arch/mips/netlogic/xlp/dt.c    | 10 ++++--
 4 files changed, 94 insertions(+), 3 deletions(-)
 create mode 100644 arch/mips/boot/dts/xlp_rvp.dts

diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 4f49fa4..de26ec6 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_DT_XLP_EVP)		+= xlp_evp.dtb
 dtb-$(CONFIG_DT_XLP_SVP)		+= xlp_svp.dtb
 dtb-$(CONFIG_DT_XLP_FVP)		+= xlp_fvp.dtb
 dtb-$(CONFIG_DT_XLP_GVP)		+= xlp_gvp.dtb
+dtb-$(CONFIG_DT_XLP_RVP)		+= xlp_rvp.dtb
 dtb-$(CONFIG_DTB_RT2880_EVAL)		+= rt2880_eval.dtb
 dtb-$(CONFIG_DTB_RT305X_EVAL)		+= rt3052_eval.dtb
 dtb-$(CONFIG_DTB_RT3883_EVAL)		+= rt3883_eval.dtb
diff --git a/arch/mips/boot/dts/xlp_rvp.dts b/arch/mips/boot/dts/xlp_rvp.dts
new file mode 100644
index 00000000..7188aed
--- /dev/null
+++ b/arch/mips/boot/dts/xlp_rvp.dts
@@ -0,0 +1,77 @@
+/*
+ * XLP5XX Device Tree Source for RVP boards
+ */
+
+/dts-v1/;
+/ {
+	model = "netlogic,XLP-RVP";
+	compatible = "netlogic,xlp";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+		serial0: serial@30000 {
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0 0x112100 0xa00>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clock-frequency = <125000000>;
+			interrupt-parent = <&pic>;
+			interrupts = <17>;
+		};
+		pic: pic@110000 {
+			compatible = "netlogic,xlp-pic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0 0x110000 0x200>;
+			interrupt-controller;
+		};
+
+		nor_flash@1,0 {
+			compatible = "cfi-flash";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			reg = <1 0 0x1000000>;
+
+			partition@0 {
+				label = "x-loader";
+				reg = <0x0 0x100000>; /* 1M */
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot";
+				reg = <0x100000 0x100000>; /* 1M */
+			};
+
+			partition@200000 {
+				label = "kernel";
+				reg = <0x200000 0x500000>; /* 5M */
+			};
+
+			partition@700000 {
+				label = "rootfs";
+				reg = <0x700000 0x800000>; /* 8M */
+			};
+
+			partition@f00000 {
+				label = "env";
+				reg = <0xf00000 0x100000>; /* 1M */
+				read-only;
+			};
+		};
+
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+	};
+};
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 0823321..fb00606 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -41,6 +41,15 @@ config DT_XLP_GVP
 	  pointer to the kernel.  The corresponding DTS file is at
 	  arch/mips/netlogic/dts/xlp_gvp.dts
 
+config DT_XLP_RVP
+	bool "Built-in device tree for XLP RVP boards"
+	default y
+	help
+	  Add an FDT blob for XLP RVP board into the kernel.
+	  This DTB will be used if the firmware does not pass in a DTB
+	  pointer to the kernel.  The corresponding DTS file is at
+	  arch/mips/netlogic/dts/xlp_rvp.dts
+
 config NLM_MULTINODE
 	bool "Support for multi-chip boards"
 	depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index 7cc4603..a625bdb 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -41,17 +41,21 @@
 
 #include <asm/prom.h>
 
-extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
-	__dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[];
+extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_xlp_fvp_begin[],
+	__dtb_xlp_gvp_begin[], __dtb_xlp_rvp_begin[];
 static void *xlp_fdt_blob;
 
 void __init *xlp_dt_init(void *fdtp)
 {
 	if (!fdtp) {
 		switch (current_cpu_data.processor_id & PRID_IMP_MASK) {
+#ifdef CONFIG_DT_XLP_RVP
+		case PRID_IMP_NETLOGIC_XLP5XX:
+			fdtp = __dtb_xlp_rvp_begin;
+			break;
+#endif
 #ifdef CONFIG_DT_XLP_GVP
 		case PRID_IMP_NETLOGIC_XLP9XX:
-		case PRID_IMP_NETLOGIC_XLP5XX:
 			fdtp = __dtb_xlp_gvp_begin;
 			break;
 #endif
-- 
1.9.1