From: Markos Chandras <markos.chandras@imgtec.com> To: <linux-mips@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Subject: [PATCH RFC v2 65/70] MIPS: Make use of the ERETNC instruction on MIPS R6 Date: Fri, 16 Jan 2015 10:49:44 +0000 [thread overview] Message-ID: <1421405389-15512-66-git-send-email-markos.chandras@imgtec.com> (raw) In-Reply-To: <1421405389-15512-1-git-send-email-markos.chandras@imgtec.com> The ERETNC instruction, introduced in MIPS R5, is similar to the ERET one, except it does not clear the LLB bit in the LLADDR register. This feature is necessary to safely emulate R2 LL/SC instructions. However, on context switches, we need to clear the LLAddr/LLB bit in order to make sure that an SC instruction from the new thread will never succeed if it happens to interrupt an LL operation on the same address from the previous thread. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/switch_to.h | 9 ++++++--- arch/mips/include/asm/thread_info.h | 2 +- arch/mips/kernel/asm-offsets.c | 1 + arch/mips/kernel/entry.S | 18 ++++++++++++++++++ arch/mips/kernel/traps.c | 2 ++ 5 files changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h index b928b6f898cd..e92d6c4b5ed1 100644 --- a/arch/mips/include/asm/switch_to.h +++ b/arch/mips/include/asm/switch_to.h @@ -75,9 +75,12 @@ do { \ #endif #define __clear_software_ll_bit() \ -do { \ - if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ - ll_bit = 0; \ +do { if (cpu_has_rw_llb) { \ + write_c0_lladdr(0); \ + } else { \ + if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)\ + ll_bit = 0; \ + } \ } while (0) #define switch_to(prev, next, last) \ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 99eea59604e9..fb68fd2714fb 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -28,7 +28,7 @@ struct thread_info { unsigned long tp_value; /* thread pointer */ __u32 cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, <0 => BUG */ - + int r2_emul_return; /* 1 => Returning from R2 emulator */ mm_segment_t addr_limit; /* * thread address space limit: * 0x7fffffff for user-thead diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index b1d84bd4efb3..7b6c11aa1cae 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -97,6 +97,7 @@ void output_thread_info_defines(void) OFFSET(TI_TP_VALUE, thread_info, tp_value); OFFSET(TI_CPU, thread_info, cpu); OFFSET(TI_PRE_COUNT, thread_info, preempt_count); + OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return); OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); OFFSET(TI_RESTART_BLOCK, thread_info, restart_block); OFFSET(TI_REGS, thread_info, regs); diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index d5ab21c3fd12..af41ba6db960 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -46,6 +46,11 @@ resume_userspace: local_irq_disable # make sure we dont miss an # interrupt setting need_resched # between sampling and return +#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR + lw k0, TI_R2_EMUL_RET($28) + bnez k0, restore_all_from_r2_emul +#endif + LONG_L a2, TI_FLAGS($28) # current->work andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace) bnez t0, work_pending @@ -114,6 +119,19 @@ restore_partial: # restore partial frame RESTORE_SP_AND_RET .set at +#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR +restore_all_from_r2_emul: # restore full frame + .set noat + sw zero, TI_R2_EMUL_RET($28) # reset it + RESTORE_TEMP + RESTORE_AT + RESTORE_STATIC + RESTORE_SOME + LONG_L sp, PT_R29(sp) + eretnc + .set at +#endif + work_pending: andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS beqz t0, work_notifysig diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ada73d288d0b..e7ac32f3b80a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1039,12 +1039,14 @@ asmlinkage void do_ri(struct pt_regs *regs) switch (status) { case 0: case SIGEMT: + task_thread_info(current)->r2_emul_return = 1; return; case SIGILL: goto no_r2_instr; default: process_fpemu_return(status, ¤t->thread.cp0_baduaddr); + task_thread_info(current)->r2_emul_return = 1; return; } } -- 2.2.1
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <markos.chandras@imgtec.com> To: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Subject: [PATCH RFC v2 65/70] MIPS: Make use of the ERETNC instruction on MIPS R6 Date: Fri, 16 Jan 2015 10:49:44 +0000 [thread overview] Message-ID: <1421405389-15512-66-git-send-email-markos.chandras@imgtec.com> (raw) Message-ID: <20150116104944.PuDRO0BrLqrLb3AGWKiQxtagGvGWxIJgRRToJNEthEI@z> (raw) In-Reply-To: <1421405389-15512-1-git-send-email-markos.chandras@imgtec.com> The ERETNC instruction, introduced in MIPS R5, is similar to the ERET one, except it does not clear the LLB bit in the LLADDR register. This feature is necessary to safely emulate R2 LL/SC instructions. However, on context switches, we need to clear the LLAddr/LLB bit in order to make sure that an SC instruction from the new thread will never succeed if it happens to interrupt an LL operation on the same address from the previous thread. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/switch_to.h | 9 ++++++--- arch/mips/include/asm/thread_info.h | 2 +- arch/mips/kernel/asm-offsets.c | 1 + arch/mips/kernel/entry.S | 18 ++++++++++++++++++ arch/mips/kernel/traps.c | 2 ++ 5 files changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h index b928b6f898cd..e92d6c4b5ed1 100644 --- a/arch/mips/include/asm/switch_to.h +++ b/arch/mips/include/asm/switch_to.h @@ -75,9 +75,12 @@ do { \ #endif #define __clear_software_ll_bit() \ -do { \ - if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ - ll_bit = 0; \ +do { if (cpu_has_rw_llb) { \ + write_c0_lladdr(0); \ + } else { \ + if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)\ + ll_bit = 0; \ + } \ } while (0) #define switch_to(prev, next, last) \ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 99eea59604e9..fb68fd2714fb 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -28,7 +28,7 @@ struct thread_info { unsigned long tp_value; /* thread pointer */ __u32 cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, <0 => BUG */ - + int r2_emul_return; /* 1 => Returning from R2 emulator */ mm_segment_t addr_limit; /* * thread address space limit: * 0x7fffffff for user-thead diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index b1d84bd4efb3..7b6c11aa1cae 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -97,6 +97,7 @@ void output_thread_info_defines(void) OFFSET(TI_TP_VALUE, thread_info, tp_value); OFFSET(TI_CPU, thread_info, cpu); OFFSET(TI_PRE_COUNT, thread_info, preempt_count); + OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return); OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); OFFSET(TI_RESTART_BLOCK, thread_info, restart_block); OFFSET(TI_REGS, thread_info, regs); diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index d5ab21c3fd12..af41ba6db960 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -46,6 +46,11 @@ resume_userspace: local_irq_disable # make sure we dont miss an # interrupt setting need_resched # between sampling and return +#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR + lw k0, TI_R2_EMUL_RET($28) + bnez k0, restore_all_from_r2_emul +#endif + LONG_L a2, TI_FLAGS($28) # current->work andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace) bnez t0, work_pending @@ -114,6 +119,19 @@ restore_partial: # restore partial frame RESTORE_SP_AND_RET .set at +#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR +restore_all_from_r2_emul: # restore full frame + .set noat + sw zero, TI_R2_EMUL_RET($28) # reset it + RESTORE_TEMP + RESTORE_AT + RESTORE_STATIC + RESTORE_SOME + LONG_L sp, PT_R29(sp) + eretnc + .set at +#endif + work_pending: andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS beqz t0, work_notifysig diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ada73d288d0b..e7ac32f3b80a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1039,12 +1039,14 @@ asmlinkage void do_ri(struct pt_regs *regs) switch (status) { case 0: case SIGEMT: + task_thread_info(current)->r2_emul_return = 1; return; case SIGILL: goto no_r2_instr; default: process_fpemu_return(status, ¤t->thread.cp0_baduaddr); + task_thread_info(current)->r2_emul_return = 1; return; } } -- 2.2.1
next prev parent reply other threads:[~2015-01-16 11:10 UTC|newest] Thread overview: 262+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-01-16 10:48 [PATCH RFC v2 00/70] Add MIPS R6 support Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 01/70] MIPS: Add generic QEMU PRid and cpu type identifiers Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 02/70] MIPS: Add cases for CPU_QEMU_GENERIC Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 03/70] MIPS: Add MIPS generic QEMU probe support Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 04/70] MIPS: Add build support for the MIPS R6 ISA Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-19 23:56 ` Maciej W. Rozycki 2015-01-16 10:48 ` [PATCH RFC v2 05/70] MIPS: mm: uasm: Add signed 9-bit immediate related macros Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 11:29 ` Sergei Shtylyov 2015-01-19 12:35 ` Markos Chandras 2015-01-19 12:35 ` Markos Chandras 2015-01-19 12:45 ` Markos Chandras 2015-01-19 12:45 ` Markos Chandras 2015-01-19 12:50 ` Sergei Shtylyov 2015-01-16 10:48 ` [PATCH RFC v2 06/70] MIPS: mm: Add MIPS R6 instruction encodings Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 19:15 ` David Daney 2015-01-16 10:48 ` [PATCH RFC v2 07/70] MIPS: asm: asm: Add new macros to set ISA and arch asm annotations Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 08/70] MIPS: asm: module: define MODULE_PROC_FAMILY for MIPS R6 Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 09/70] MIPS: asm: stackframe: Do not preserve the HI/LO registers on " Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 10/70] MIPS: asm: asmmacro: Drop unused 'reg' argument on MIPSR2 Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-20 0:04 ` Maciej W. Rozycki 2015-01-20 9:49 ` Markos Chandras 2015-01-20 9:49 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 11/70] MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variants Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 12/70] MIPS: asm: asmmacro: Replace add instructions with "addui" Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-19 15:59 ` Maciej W. Rozycki 2015-01-19 16:39 ` Markos Chandras 2015-01-19 16:39 ` Markos Chandras 2015-01-19 19:07 ` Maciej W. Rozycki 2015-01-19 19:25 ` Maciej W. Rozycki 2015-01-20 9:52 ` Markos Chandras 2015-01-20 9:52 ` Markos Chandras 2015-01-20 14:33 ` Matthew Fortune 2015-01-16 10:48 ` [PATCH RFC v2 13/70] MIPS: Use generic checksum functions for MIPS R6 Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 14/70] MIPS: asm: cpu: Add MIPSR6 ISA definitions Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 15/70] MIPS: asm: hazards: Add MIPSR6 definitions Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 16/70] MIPS: asm: irqflags: Add MIPS R6 related definitions Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 17/70] MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 18/70] MIPS: asm: spram: Add MIPS R6 related definitions Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-20 0:13 ` Maciej W. Rozycki 2015-01-21 12:16 ` Markos Chandras 2015-01-21 12:16 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 19/70] MIPS: Use the new "ZC" constraint for MIPS R6 Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-20 0:27 ` Maciej W. Rozycki 2015-01-20 9:11 ` Matthew Fortune 2015-01-20 9:35 ` Markos Chandras 2015-01-20 10:08 ` Matthew Fortune 2015-01-20 10:08 ` Matthew Fortune 2015-01-20 10:12 ` Markos Chandras 2015-01-20 14:37 ` Maciej W. Rozycki 2015-01-20 14:46 ` Maciej W. Rozycki 2015-01-21 9:06 ` Markos Chandras 2015-01-26 13:39 ` [PATCH] MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM Markos Chandras 2015-01-26 13:39 ` Markos Chandras 2015-01-16 10:48 ` [PATCH RFC v2 20/70] MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 support Markos Chandras 2015-01-16 10:48 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 21/70] MIPS: asm: atomic: " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 22/70] MIPS: asm: bitops: " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 23/70] MIPS: asm: futex: Set the appropriate ISA level for MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 24/70] MIPS: asm: spinlock: Replace sub instruction with addiu Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-20 1:04 ` Maciej W. Rozycki 2015-01-20 11:29 ` Markos Chandras 2015-01-20 11:29 ` Markos Chandras 2015-01-20 11:47 ` Matthew Fortune 2015-02-10 16:17 ` Maciej W. Rozycki 2015-01-20 17:17 ` David Daney 2015-01-20 22:20 ` Ralf Baechle 2015-01-21 0:58 ` Maciej W. Rozycki 2015-01-16 10:49 ` [PATCH RFC v2 25/70] MIPS: asm: local: Set the appropriate ISA level for MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 26/70] MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugs Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-20 1:07 ` Maciej W. Rozycki 2015-01-16 10:49 ` [PATCH RFC v2 27/70] MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handler Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-20 1:22 ` Maciej W. Rozycki 2015-01-20 9:14 ` James Hogan 2015-01-20 9:14 ` James Hogan 2015-01-20 14:33 ` Maciej W. Rozycki 2015-01-21 9:34 ` Markos Chandras 2015-01-21 9:34 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 28/70] MIPS: kernel: cpu-probe.c: Add support for MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-20 23:32 ` Maciej W. Rozycki 2015-01-21 11:22 ` Markos Chandras 2015-01-21 11:22 ` Markos Chandras 2015-01-21 11:40 ` James Hogan 2015-01-21 11:40 ` James Hogan 2015-01-16 10:49 ` [PATCH RFC v2 29/70] MIPS: kernel: entry.S: Add MIPS R6 related definitions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 30/70] MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-20 23:42 ` Maciej W. Rozycki 2015-01-21 9:25 ` Markos Chandras 2015-01-21 9:25 ` Markos Chandras 2015-01-22 14:08 ` Maciej W. Rozycki 2015-01-22 14:43 ` Markos Chandras 2015-01-22 14:43 ` Markos Chandras 2015-01-22 15:03 ` Markos Chandras 2015-01-22 15:03 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 31/70] MIPS: kernel: traps: Add MIPS R6 related definitions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-20 23:49 ` Maciej W. Rozycki 2015-01-16 10:49 ` [PATCH RFC v2 32/70] MIPS: kernel: r4k_switch: Add support for MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 33/70] MIPS: kernel: r4k_fpu: " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 34/70] MIPS: kernel: genex: Set correct ISA level Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 35/70] MIPS: kernel: cps-vec: Replace addi with addiu Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-21 0:02 ` Maciej W. Rozycki 2015-01-16 10:49 ` [PATCH RFC v2 36/70] MIPS: kernel: unaligned: Add support for the MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 37/70] MIPS: kernel: syscall: Set the appropriate ISA level for " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 38/70] MIPS: lib: memcpy: Add MIPS R6 support Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 39/70] MIPS: lib: memset: " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 40/70] MIPS: mm: page: " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-17 11:58 ` Sergei Shtylyov 2015-01-19 12:33 ` [PATCH RFC v3 " Markos Chandras 2015-01-19 12:33 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 41/70] MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-02-23 22:03 ` David Daney 2015-02-23 22:07 ` David Daney 2015-02-24 0:33 ` Maciej W. Rozycki 2015-02-24 0:53 ` David Daney 2015-01-16 10:49 ` [PATCH RFC v2 42/70] MIPS: mm: c-r4k: Set the correct ISA level Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 43/70] MIPS: mm: scache: Add secondary cache support for MIPS R6 cores Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 44/70] MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 45/70] MIPS: kernel: branch: Prevent BLTZL emulation for " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-21 1:59 ` Maciej W. Rozycki 2015-01-21 1:59 ` Maciej W. Rozycki 2015-01-21 10:43 ` Markos Chandras 2015-01-21 10:43 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 46/70] MIPS: kernel: branch: Prevent BGEZL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-02-03 11:57 ` Maciej W. Rozycki 2015-01-16 10:49 ` [PATCH RFC v2 47/70] MIPS: kernel: branch: Prevent BLTZAL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 48/70] MIPS: kernel: branch: Prevent BGEZAL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 49/70] MIPS: kernel: branch: Prevent BEQL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 50/70] MIPS: kernel: branch: Prevent BNEL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 51/70] MIPS: kernel: branch: Prevent BLEZL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 52/70] MIPS: kernel: branch: Prevent BGTZL " Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 53/70] MIPS: Emulate the BC1{EQ,NE}Z FPU instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 54/70] MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 55/70] MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 56/70] MIPS: Emulate the new MIPS R6 branch compact (BC) instruction Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 57/70] MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-17 13:24 ` Sergei Shtylyov 2015-01-19 9:48 ` Markos Chandras 2015-01-19 9:48 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 58/70] MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 59/70] MIPS: Emulate the new MIPS R6 BALC instruction Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 60/70] MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 61/70] MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 62/70] MIPS: Add LLB bit and related feature for the Config 5 CP0 register Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 63/70] MIPS: asm: mipsregs: Add support for the LLADDR register Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 64/70] MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` Markos Chandras [this message] 2015-01-16 10:49 ` [PATCH RFC v2 65/70] MIPS: Make use of the ERETNC instruction on " Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 66/70] MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 67/70] MIPS: kernel: process: Do not allow FR=0 on MIPS R6 Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 11:54 ` Matthew Fortune 2015-01-16 15:33 ` Markos Chandras 2015-01-29 23:13 ` Paul Burton 2015-01-29 23:13 ` Paul Burton 2015-01-30 10:18 ` Markos Chandras 2015-01-30 10:18 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 68/70] MIPS: kernel: elf: Improve the overall ABI and FPU mode checks Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 12:28 ` Matthew Fortune 2015-01-19 9:29 ` Matthew Fortune 2015-01-19 12:17 ` Markos Chandras 2015-01-29 23:22 ` Paul Burton 2015-01-30 10:23 ` Markos Chandras 2015-02-03 12:41 ` Maciej W. Rozycki 2015-01-29 21:51 ` Matthew Fortune 2015-02-02 16:13 ` [PATCH v3] " Markos Chandras 2015-02-02 16:13 ` Markos Chandras 2015-02-24 13:17 ` Måns Rullgård 2015-02-24 13:17 ` Måns Rullgård 2015-02-24 13:52 ` Markos Chandras 2015-02-24 13:52 ` Markos Chandras 2015-02-24 14:06 ` Måns Rullgård 2015-02-24 14:06 ` Måns Rullgård 2015-02-24 14:26 ` Matthew Fortune 2015-02-26 8:59 ` Markos Chandras 2015-02-26 9:14 ` Måns Rullgård 2015-02-26 9:14 ` Måns Rullgård 2015-02-26 9:24 ` Markos Chandras 2015-02-26 9:31 ` Matthew Fortune 2015-02-26 9:44 ` Markos Chandras 2015-02-26 10:31 ` Måns Rullgård 2015-02-26 10:31 ` Måns Rullgård 2015-02-26 11:11 ` [PATCH] MIPS: asm: elf: Set O32 default FPU flags Markos Chandras 2015-02-26 11:11 ` Markos Chandras 2015-02-26 11:21 ` Måns Rullgård 2015-02-26 11:21 ` Måns Rullgård 2015-02-27 1:28 ` Aaro Koskinen 2015-02-27 1:46 ` Måns Rullgård 2015-04-07 16:36 ` Maciej W. Rozycki 2015-04-12 23:21 ` Aaro Koskinen 2015-04-20 11:55 ` Maciej W. Rozycki 2015-02-03 12:40 ` [PATCH RFC v2 68/70] MIPS: kernel: elf: Improve the overall ABI and FPU mode checks Maciej W. Rozycki 2015-01-16 10:49 ` [PATCH RFC v2 69/70] MIPS: Malta: Add support for building MIPS R6 kernel Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-01-16 10:49 ` [PATCH RFC v2 70/70] MIPS: Add Malta QEMU 32R6 defconfig Markos Chandras 2015-01-16 10:49 ` Markos Chandras 2015-02-12 23:12 ` [PATCH RFC v2 00/70] Add MIPS R6 support David Daney 2015-02-12 23:12 ` David Daney
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