From: Tero Kristo <t-kristo@ti.com> To: linux-omap@vger.kernel.org, tony@atomide.com, paul@pwsan.com, sakari.ailus@iki.fi Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCHv5 34/35] ARM: dts: dra7: add minimal l4 bus layout with control module support Date: Fri, 20 Mar 2015 20:44:45 +0200 [thread overview] Message-ID: <1426877086-17131-35-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1426877086-17131-1-git-send-email-t-kristo@ti.com> This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- .../devicetree/bindings/arm/omap/ctrl.txt | 1 + Documentation/devicetree/bindings/arm/omap/l4.txt | 2 + arch/arm/boot/dts/dra7.dtsi | 166 +++++++++++--------- 3 files changed, 96 insertions(+), 73 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index acb68ed..3a4e590 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -23,6 +23,7 @@ Required properties: "ti,omap4-scm-padconf-core" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" + "ti,dra7-scm-core" - reg: Contains Control Module register address range (base address and length) diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt index 2fe4211..b4f8a16 100644 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -10,6 +10,8 @@ Required properties: Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus + Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus + Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus - ranges : contains the IO map range for the bus diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5827fed..8e50ca3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -94,17 +94,101 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; - prm: prm@4ae06000 { - compatible = "ti,dra7-prm"; - reg = <0x4ae06000 0x3000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + l4_cfg: l4@4a000000 { + compatible = "ti,dra7-l4-cfg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x22c000>; - prm_clocks: clocks { + scm: scm@2000 { + compatible = "ti,dra7-scm-core", "simple-bus"; + reg = <0x2000 0x2000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x1400>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0xe00 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + dra7_pmx_core: pinmux@1400 { + compatible = "ti,dra7-padconf", + "pinctrl-single"; + reg = <0x1400 0x0464>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; + }; + + cm_core_aon: cm_core_aon@5000 { + compatible = "ti,dra7-cm-core-aon"; + reg = <0x5000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core@8000 { + compatible = "ti,dra7-cm-core"; + reg = <0x8000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; }; + }; - prm_clockdomains: clockdomains { + l4_wkup: l4@4ae00000 { + compatible = "ti,dra7-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4ae00000 0x3f000>; + + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x40>; + ti,hwmods = "counter_32k"; + }; + + prm: prm@6000 { + compatible = "ti,dra7-prm"; + reg = <0x6000 0x3000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; }; }; @@ -177,70 +261,6 @@ }; }; - cm_core_aon: cm_core_aon@4a005000 { - compatible = "ti,dra7-cm-core-aon"; - reg = <0x4a005000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@4a008000 { - compatible = "ti,dra7-cm-core"; - reg = <0x4a008000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; - }; - - dra7_ctrl_core: ctrl_core@4a002000 { - compatible = "syscon"; - reg = <0x4a002000 0x6d0>; - }; - - dra7_ctrl_general: tisyscon@4a002e00 { - compatible = "syscon"; - reg = <0x4a002e00 0x7c>; - }; - - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0 0x4>; - syscon = <&dra7_ctrl_general>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - dra7_pmx_core: pinmux@4a003400 { - compatible = "ti,dra7-padconf", "pinctrl-single"; - reg = <0x4a003400 0x0464>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -1410,7 +1430,7 @@ compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 0>; + syscon-raminit = <&scm_conf 0x558 0>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcan1_sys_clk_mux>; status = "disabled"; @@ -1420,7 +1440,7 @@ compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 1>; + syscon-raminit = <&scm_conf 0x558 1>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sys_clkin1>; status = "disabled"; -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: t-kristo@ti.com (Tero Kristo) To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv5 34/35] ARM: dts: dra7: add minimal l4 bus layout with control module support Date: Fri, 20 Mar 2015 20:44:45 +0200 [thread overview] Message-ID: <1426877086-17131-35-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1426877086-17131-1-git-send-email-t-kristo@ti.com> This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- .../devicetree/bindings/arm/omap/ctrl.txt | 1 + Documentation/devicetree/bindings/arm/omap/l4.txt | 2 + arch/arm/boot/dts/dra7.dtsi | 166 +++++++++++--------- 3 files changed, 96 insertions(+), 73 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index acb68ed..3a4e590 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -23,6 +23,7 @@ Required properties: "ti,omap4-scm-padconf-core" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" + "ti,dra7-scm-core" - reg: Contains Control Module register address range (base address and length) diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt index 2fe4211..b4f8a16 100644 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -10,6 +10,8 @@ Required properties: Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus + Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus + Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus - ranges : contains the IO map range for the bus diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5827fed..8e50ca3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -94,17 +94,101 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; - prm: prm at 4ae06000 { - compatible = "ti,dra7-prm"; - reg = <0x4ae06000 0x3000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + l4_cfg: l4 at 4a000000 { + compatible = "ti,dra7-l4-cfg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x22c000>; - prm_clocks: clocks { + scm: scm at 2000 { + compatible = "ti,dra7-scm-core", "simple-bus"; + reg = <0x2000 0x2000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + scm_conf: scm_conf at 0 { + compatible = "syscon"; + reg = <0x0 0x1400>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0xe00 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + dra7_pmx_core: pinmux at 1400 { + compatible = "ti,dra7-padconf", + "pinctrl-single"; + reg = <0x1400 0x0464>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; + }; + + cm_core_aon: cm_core_aon at 5000 { + compatible = "ti,dra7-cm-core-aon"; + reg = <0x5000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core at 8000 { + compatible = "ti,dra7-cm-core"; + reg = <0x8000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; }; + }; - prm_clockdomains: clockdomains { + l4_wkup: l4 at 4ae00000 { + compatible = "ti,dra7-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4ae00000 0x3f000>; + + counter32k: counter at 4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x40>; + ti,hwmods = "counter_32k"; + }; + + prm: prm at 6000 { + compatible = "ti,dra7-prm"; + reg = <0x6000 0x3000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; }; }; @@ -177,70 +261,6 @@ }; }; - cm_core_aon: cm_core_aon at 4a005000 { - compatible = "ti,dra7-cm-core-aon"; - reg = <0x4a005000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core at 4a008000 { - compatible = "ti,dra7-cm-core"; - reg = <0x4a008000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - - counter32k: counter at 4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; - }; - - dra7_ctrl_core: ctrl_core at 4a002000 { - compatible = "syscon"; - reg = <0x4a002000 0x6d0>; - }; - - dra7_ctrl_general: tisyscon at 4a002e00 { - compatible = "syscon"; - reg = <0x4a002e00 0x7c>; - }; - - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0 0x4>; - syscon = <&dra7_ctrl_general>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - dra7_pmx_core: pinmux at 4a003400 { - compatible = "ti,dra7-padconf", "pinctrl-single"; - reg = <0x4a003400 0x0464>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - sdma: dma-controller at 4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -1410,7 +1430,7 @@ compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 0>; + syscon-raminit = <&scm_conf 0x558 0>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcan1_sys_clk_mux>; status = "disabled"; @@ -1420,7 +1440,7 @@ compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 1>; + syscon-raminit = <&scm_conf 0x558 1>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sys_clkin1>; status = "disabled"; -- 1.7.9.5
next prev parent reply other threads:[~2015-03-20 18:46 UTC|newest] Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-03-20 18:44 [PATCHv5 00/35] ARM: OMAP2+: PRCM/SCM cleanups against 4.0-rc Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 01/35] clk: ti: fix ti_clk_get_reg_addr error handling Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-24 18:51 ` Tero Kristo 2015-03-24 18:51 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 02/35] ARM: OMAP2+: PRCM: rename of_prcm_init to omap_prcm_init Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 03/35] ARM: OMAP3: PRM: invert the wkst_mask for the prm_clear_mod_irqs Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 04/35] ARM: OMAP2+: PRM: add generic API for clear_mod_irqs Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 05/35] ARM: OMAP3+: PRM: add common APIs for prm_vp_check/clear_txdone Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 06/35] ARM: OMAP4+: PRM: move omap_prm_base_init under OMAP4 PRM driver Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 07/35] ARM: OMAP4+: CM: move omap_cm_base_init under OMAP4 CM driver Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 08/35] ARM: OMAP4: PRM: move omap4xxx_prm_init earlier in init order Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 09/35] Documentation: DT: document PRCM compatible strings for dm81x SoCs Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 10/35] ARM: OMAP2+: PRCM: add support for static clock memmap indices Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 11/35] ARM: OMAP2+: clock: move clock provider infrastructure to clock driver Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-25 15:12 ` Tero Kristo 2015-03-25 15:12 ` Tero Kristo 2015-03-25 23:17 ` Tony Lindgren 2015-03-25 23:17 ` Tony Lindgren 2015-03-26 7:24 ` Tero Kristo 2015-03-26 7:24 ` Tero Kristo 2015-03-26 10:55 ` Tero Kristo 2015-03-26 10:55 ` Tero Kristo 2015-03-26 17:30 ` Tony Lindgren 2015-03-26 17:30 ` Tony Lindgren 2015-03-26 18:49 ` Tero Kristo 2015-03-26 18:49 ` Tero Kristo 2015-03-27 13:06 ` Tero Kristo 2015-03-27 13:06 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 12/35] ARM: OMAP2+: PRCM: split PRCM module init to their own driver files Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 13/35] ARM: OMAP2+: CM: determine CM base address from device tree Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 14/35] ARM: OMAP2+: PRM: determine PRM " Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 15/35] ARM: OMAP2+: control: determine control module base address from DT Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 16/35] ARM: OMAP2+: PRM: move SoC specific init calls within a generic API Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 17/35] ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 18/35] ARM: OMAP2+: CM: move SoC specific init calls within a generic API Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 19/35] ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 20/35] ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 21/35] ARM: OMAP2+: clock: add low-level support for regmap Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 22/35] ARM: OMAP2+: control: remove API for getting control module base address Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 23/35] ARM: OMAP2+: id: cache omap_type value Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 24/35] ARM: OMAP2+: control: add syscon support for register accesses Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 25/35] ARM: dts: omap24xx: add minimal l4 bus layout with control module support Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 26/35] ARM: dts: omap3: " Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-30 22:56 ` Tony Lindgren 2015-03-30 22:56 ` Tony Lindgren 2015-03-31 14:57 ` Tero Kristo 2015-03-31 14:57 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 27/35] ARM: dts: am33xx: " Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 21:43 ` Suman Anna 2015-03-20 21:43 ` Suman Anna 2015-03-20 22:35 ` Tony Lindgren 2015-03-20 22:35 ` Tony Lindgren 2015-03-20 23:23 ` Suman Anna 2015-03-20 23:23 ` Suman Anna 2015-03-20 23:30 ` Tony Lindgren 2015-03-20 23:30 ` Tony Lindgren 2015-03-23 6:35 ` Tero Kristo 2015-03-23 6:35 ` Tero Kristo 2015-03-25 15:02 ` Tero Kristo 2015-03-25 15:02 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 28/35] ARM: dts: am43xx-epos-evm: fix pinmux node layout Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 29/35] ARM: dts: am4372: add minimal l4 bus layout with control module support Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-24 20:10 ` Suman Anna 2015-03-24 20:10 ` Suman Anna 2015-03-25 9:10 ` Tero Kristo 2015-03-25 9:10 ` Tero Kristo 2015-03-25 15:03 ` Tero Kristo 2015-03-25 15:03 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 30/35] ARM: dts: omap4: " Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-30 23:01 ` Tony Lindgren 2015-03-30 23:01 ` Tony Lindgren 2015-03-31 14:58 ` Tero Kristo 2015-03-31 14:58 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 31/35] ARM: OMAP4: display: convert display to use syscon for dsi muxing Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 32/35] ARM: OMAP4+: control: remove support for legacy pad read/write Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` [PATCHv5 33/35] ARM: dts: omap5: add minimal l4 bus layout with control module support Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-20 18:44 ` Tero Kristo [this message] 2015-03-20 18:44 ` [PATCHv5 34/35] ARM: dts: dra7: " Tero Kristo 2015-03-20 18:44 ` [PATCHv5 35/35] ARM: OMAP4+: control: add support for initializing control module via DT Tero Kristo 2015-03-20 18:44 ` Tero Kristo 2015-03-31 0:10 ` [PATCHv5 00/35] ARM: OMAP2+: PRCM/SCM cleanups against 4.0-rc Tony Lindgren 2015-03-31 0:10 ` Tony Lindgren 2015-03-31 1:25 ` Tony Lindgren 2015-03-31 1:25 ` Tony Lindgren 2015-03-31 18:28 ` Tero Kristo 2015-03-31 18:28 ` Tero Kristo 2015-03-31 14:59 ` Tero Kristo 2015-03-31 14:59 ` Tero Kristo
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