From: Marc Zyngier <marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org>, Andre Przywara <andre.przywara@arm.com>, Will Deacon <will.deacon@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Dave Martin <dave.martin@arm.com> Subject: [PATCH v3 4/5] arm64: alternative: Introduce feature for GICv3 CPU interface Date: Fri, 27 Mar 2015 13:09:24 +0000 [thread overview] Message-ID: <1427461765-14462-5-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1427461765-14462-1-git-send-email-marc.zyngier@arm.com> Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF) to indicate that we have a system register GIC CPU interface This will help KVM switching to alternative instruction patching. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/cpufeature.h | 8 +++++++- arch/arm64/kernel/cpufeature.c | 16 ++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6ae35d1..d9e57b5 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -23,8 +23,9 @@ #define ARM64_WORKAROUND_CLEAN_CACHE 0 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 +#define ARM64_HAS_SYSREG_GIC_CPUIF 2 -#define ARM64_NCAPS 2 +#define ARM64_NCAPS 3 #ifndef __ASSEMBLY__ @@ -37,6 +38,11 @@ struct arm64_cpu_capabilities { u32 midr_model; u32 midr_range_min, midr_range_max; }; + + struct { /* Feature register checking */ + u64 register_mask; + u64 register_value; + }; }; }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3d9967e..b0bea2b3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -22,7 +22,23 @@ #include <asm/cpu.h> #include <asm/cpufeature.h> +static bool +has_id_aa64pfr0_feature(const struct arm64_cpu_capabilities *entry) +{ + u64 val; + + val = read_cpuid(id_aa64pfr0_el1); + return (val & entry->register_mask) == entry->register_value; +} + static const struct arm64_cpu_capabilities arm64_features[] = { + { + .desc = "system register GIC CPU interface", + .capability = ARM64_HAS_SYSREG_GIC_CPUIF, + .matches = has_id_aa64pfr0_feature, + .register_mask = (0xf << 24), + .register_value = (1 << 24), + }, {}, }; -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/5] arm64: alternative: Introduce feature for GICv3 CPU interface Date: Fri, 27 Mar 2015 13:09:24 +0000 [thread overview] Message-ID: <1427461765-14462-5-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1427461765-14462-1-git-send-email-marc.zyngier@arm.com> Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF) to indicate that we have a system register GIC CPU interface This will help KVM switching to alternative instruction patching. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/cpufeature.h | 8 +++++++- arch/arm64/kernel/cpufeature.c | 16 ++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6ae35d1..d9e57b5 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -23,8 +23,9 @@ #define ARM64_WORKAROUND_CLEAN_CACHE 0 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 +#define ARM64_HAS_SYSREG_GIC_CPUIF 2 -#define ARM64_NCAPS 2 +#define ARM64_NCAPS 3 #ifndef __ASSEMBLY__ @@ -37,6 +38,11 @@ struct arm64_cpu_capabilities { u32 midr_model; u32 midr_range_min, midr_range_max; }; + + struct { /* Feature register checking */ + u64 register_mask; + u64 register_value; + }; }; }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3d9967e..b0bea2b3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -22,7 +22,23 @@ #include <asm/cpu.h> #include <asm/cpufeature.h> +static bool +has_id_aa64pfr0_feature(const struct arm64_cpu_capabilities *entry) +{ + u64 val; + + val = read_cpuid(id_aa64pfr0_el1); + return (val & entry->register_mask) == entry->register_value; +} + static const struct arm64_cpu_capabilities arm64_features[] = { + { + .desc = "system register GIC CPU interface", + .capability = ARM64_HAS_SYSREG_GIC_CPUIF, + .matches = has_id_aa64pfr0_feature, + .register_mask = (0xf << 24), + .register_value = (1 << 24), + }, {}, }; -- 2.1.4
next prev parent reply other threads:[~2015-03-27 13:02 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-03-27 13:09 [PATCH v3 0/5] arm64: Patching branches for fun and profit Marc Zyngier 2015-03-27 13:09 ` Marc Zyngier 2015-03-27 13:09 ` [PATCH v3 1/5] arm64: insn: Add aarch64_insn_decode_immediate Marc Zyngier 2015-03-27 13:09 ` Marc Zyngier 2015-03-27 13:09 ` [PATCH v3 2/5] arm64: alternative: Allow immediate branch as alternative instruction Marc Zyngier 2015-03-27 13:09 ` Marc Zyngier 2015-03-27 13:09 ` [PATCH v3 3/5] arm64: Extract feature parsing code from cpu_errata.c Marc Zyngier 2015-03-27 13:09 ` Marc Zyngier 2015-03-27 13:09 ` Marc Zyngier [this message] 2015-03-27 13:09 ` [PATCH v3 4/5] arm64: alternative: Introduce feature for GICv3 CPU interface Marc Zyngier 2015-05-14 11:25 ` Christoffer Dall 2015-05-14 11:25 ` Christoffer Dall 2015-05-28 9:27 ` Marc Zyngier 2015-05-28 9:27 ` Marc Zyngier 2015-05-28 13:02 ` Christoffer Dall 2015-05-28 13:02 ` Christoffer Dall 2015-05-28 13:12 ` Marc Zyngier 2015-05-28 13:12 ` Marc Zyngier 2015-03-27 13:09 ` [PATCH v3 5/5] arm64: KVM: Switch vgic save/restore to alternative_insn Marc Zyngier 2015-03-27 13:09 ` Marc Zyngier 2015-05-14 11:53 ` Christoffer Dall 2015-05-14 11:53 ` Christoffer Dall
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