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From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 07/19] drm/i915: Simplify ilk_get_aux_clock_divider
Date: Tue, 31 Mar 2015 14:11:59 +0300	[thread overview]
Message-ID: <1427800319-4928-1-git-send-email-mika.kahola@intel.com> (raw)
In-Reply-To: <20150331110535.GB3154@sorvi>

Now that we are "extracting" the cdclk frequency on ILK-IVB we
can also simplify ilk_get_aux_clock_divider() to calculate the
divider based on cdclk instead of hardcoding the values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9b741b5..e38dbd5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -696,15 +696,13 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (index)
 		return 0;
 
 	if (intel_dig_port->port == PORT_A) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
-			return 200; /* SNB & IVB eDP input clock at 400Mhz */
-		else
-			return 225; /* eDP input clock at 450Mhz */
+		return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
 	} else {
 		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 	}
-- 
1.9.1

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  parent reply	other threads:[~2015-03-31 11:12 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-31 11:05 All sort of cdclk stuff Mika Kahola
2015-03-31 11:09 ` [PATCH 01/19] drm/i915: Return more precise cdclk for gen2/3 Mika Kahola
2015-03-31 13:10   ` Damien Lespiau
2015-03-31 11:09 ` [PATCH 02/19] drm/i915: Fix i855 get_display_clock_speed Mika Kahola
2015-03-31 11:11 ` [PATCH 04/19] drm/i915: Add cdclk extraction for g33, g965gm and g4x Mika Kahola
2015-03-31 11:11 ` [PATCH 05/19] drm/i915: ILK cdclk seems to be 450MHz Mika Kahola
2015-03-31 13:12   ` Damien Lespiau
2015-03-31 11:11 ` [PATCH 06/19] drm/i915: Assume 400MHz cdclk for the rest of gen4-7 Mika Kahola
2015-03-31 13:13   ` Damien Lespiau
2015-03-31 11:11 ` Mika Kahola [this message]
2015-03-31 13:13   ` [PATCH 07/19] drm/i915: Simplify ilk_get_aux_clock_divider Damien Lespiau
2015-03-31 11:12 ` [PATCH 08/19] drm/i915: Convert the ddi cdclk code to get_display_clock_speed Mika Kahola
2015-03-31 13:15   ` Damien Lespiau
2015-03-31 13:48     ` Daniel Vetter
2015-03-31 11:14 ` [PATCH 10/19] drm/i915: Cache current cdclk frequency in dev_priv Mika Kahola
2015-03-31 11:14 ` [PATCH 11/19] drm/i915: Use cached cdclk value Mika Kahola
2015-03-31 11:14 ` [PATCH 12/19] drm/i915: Unify ilk and hsw .get_aux_clock_divider Mika Kahola
2015-03-31 11:14 ` [PATCH 13/19] drm/i915: Store max cdclk value in dev_priv Mika Kahola
2015-03-31 11:14 ` [PATCH 14/19] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk Mika Kahola
2015-03-31 11:14 ` [PATCH 15/19] drm/i915: HSW cdclk support Mika Kahola
2015-04-07  6:27   ` Sivakumar Thulasimani
2015-04-07  7:03     ` Sivakumar Thulasimani
2015-04-07  8:29       ` Ville Syrjälä
2015-04-07  8:36         ` Sivakumar Thulasimani
2015-04-07  9:29           ` Mika Kahola
2015-04-07 13:52             ` Daniel Vetter
2015-04-09  7:24               ` Mika Kahola
2015-04-09  9:32                 ` Daniel Vetter
2015-04-09 13:41                   ` Mika Kahola
2015-04-09 13:51                     ` Daniel Vetter
2015-04-09 15:17                       ` Takashi Iwai
2015-04-10 13:27                         ` Mika Kahola
2015-04-10 14:10                           ` Takashi Iwai
2015-04-13  9:43                             ` Mika Kahola
2015-04-13 10:33                               ` Ville Syrjälä
2015-04-14  6:36           ` Mika Kahola
2015-04-14  6:57             ` Sivakumar Thulasimani
2015-04-14  7:06               ` Mika Kahola
2015-04-14  7:54                 ` Sivakumar Thulasimani
2015-04-07  8:28     ` Ville Syrjälä
2015-03-31 11:14 ` [PATCH 16/19] drm/i915: Add IS_BDW_ULX Mika Kahola
2015-03-31 11:14 ` [PATCH 17/19] drm/i915: BDW clock change support Mika Kahola
2015-03-31 11:14 ` [PATCH 18/19] drm/i915: Limit CHV max cdclk Mika Kahola
2015-03-31 11:14 ` [PATCH 19/19] drm/i915: Modeset global_pipes() update Mika Kahola
2015-03-31 14:45   ` Ville Syrjälä
2015-04-02  9:17     ` Mika Kahola
2015-04-02 10:05   ` Mika Kahola
2015-04-02 10:16     ` Ville Syrjälä
2015-04-07  9:36     ` Mika Kahola
2015-03-31 13:18 ` All sort of cdclk stuff Damien Lespiau

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