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From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 19/19] drm/i915: Modeset global_pipes() update
Date: Tue,  7 Apr 2015 12:36:25 +0300	[thread overview]
Message-ID: <1428399385-3208-1-git-send-email-mika.kahola@intel.com> (raw)
In-Reply-To: <1427969131-3204-1-git-send-email-mika.kahola@intel.com>

Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'

v2:
- we don't modify 'disable_pipes', so passing this as a pointer
  is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
  routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'

v3:
- Let's take a step back and not remove the routines 'valleyview_calc_cdclk()'
  and 'haswell_calc_cdclk()' from newly introduced routine
  'intel_calc_cdclk()' (based on Ville's comment)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7b97907..f05bd12 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5225,22 +5225,6 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
 	return max_pixclk;
 }
 
-static void valleyview_modeset_global_pipes(struct drm_device *dev,
-					    unsigned *prepare_pipes)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc;
-	int max_pixclk = intel_mode_max_pixclk(dev_priv);
-
-	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
-		return;
-
-	/* disable/enable all currently active pipes while we change cdclk */
-	for_each_intel_crtc(dev, intel_crtc)
-		if (intel_crtc->base.state->enable)
-			*prepare_pipes |= (1 << intel_crtc->pipe);
-}
-
 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 {
 	unsigned int credits, default_credits;
@@ -8787,21 +8771,46 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
 	     cdclk, dev_priv->cdclk_freq);
 }
 
-static void haswell_modeset_global_pipes(struct drm_device *dev,
-					 unsigned *prepare_pipes)
+static int intel_calc_cdclk(struct drm_device *dev, int max_pixclk)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int cdclk;
+
+	if (IS_VALLEYVIEW(dev))
+		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		cdclk = haswell_calc_cdclk(dev_priv, max_pixclk);
+
+	return cdclk;
+}
+
+static void intel_modeset_global_pipes(struct drm_device *dev,
+				       unsigned *prepare_pipes,
+				       unsigned disable_pipes)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc;
-	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+	int max_pixclk;
 
-	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
-	    dev_priv->cdclk_freq)
+       /* this modeset is valid only for VLV, HSW, and BDW */
+	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
+		return;
+
+	if (IS_VALLEYVIEW(dev))
+		max_pixclk = intel_mode_max_pixclk(dev_priv);
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		max_pixclk = ilk_max_pixel_rate(dev_priv);
+
+	if (intel_calc_cdclk(dev, max_pixclk) == dev_priv->cdclk_freq)
 		return;
 
 	/* disable/enable all currently active pipes while we change cdclk */
 	for_each_intel_crtc(dev, crtc)
-		if (crtc->base.enabled)
+		if (crtc->base.state->enable)
 			*prepare_pipes |= 1 << crtc->pipe;
+
+       /* may have added more to prepare_pipes than we should */
+	*prepare_pipes &= ~disable_pipes;
 }
 
 static void haswell_modeset_global_resources(struct drm_atomic_state *state)
@@ -11933,15 +11942,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-		if (IS_VALLEYVIEW(dev))
-			valleyview_modeset_global_pipes(dev, &prepare_pipes);
-		else
-			haswell_modeset_global_pipes(dev, &prepare_pipes);
-
-		/* may have added more to prepare_pipes than we should */
-		prepare_pipes &= ~disable_pipes;
-	}
+	intel_modeset_global_pipes(dev, &prepare_pipes, disable_pipes);
 
 	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
 	if (ret)
-- 
1.9.1

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  parent reply	other threads:[~2015-04-07  9:36 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-31 11:05 All sort of cdclk stuff Mika Kahola
2015-03-31 11:09 ` [PATCH 01/19] drm/i915: Return more precise cdclk for gen2/3 Mika Kahola
2015-03-31 13:10   ` Damien Lespiau
2015-03-31 11:09 ` [PATCH 02/19] drm/i915: Fix i855 get_display_clock_speed Mika Kahola
2015-03-31 11:11 ` [PATCH 04/19] drm/i915: Add cdclk extraction for g33, g965gm and g4x Mika Kahola
2015-03-31 11:11 ` [PATCH 05/19] drm/i915: ILK cdclk seems to be 450MHz Mika Kahola
2015-03-31 13:12   ` Damien Lespiau
2015-03-31 11:11 ` [PATCH 06/19] drm/i915: Assume 400MHz cdclk for the rest of gen4-7 Mika Kahola
2015-03-31 13:13   ` Damien Lespiau
2015-03-31 11:11 ` [PATCH 07/19] drm/i915: Simplify ilk_get_aux_clock_divider Mika Kahola
2015-03-31 13:13   ` Damien Lespiau
2015-03-31 11:12 ` [PATCH 08/19] drm/i915: Convert the ddi cdclk code to get_display_clock_speed Mika Kahola
2015-03-31 13:15   ` Damien Lespiau
2015-03-31 13:48     ` Daniel Vetter
2015-03-31 11:14 ` [PATCH 10/19] drm/i915: Cache current cdclk frequency in dev_priv Mika Kahola
2015-03-31 11:14 ` [PATCH 11/19] drm/i915: Use cached cdclk value Mika Kahola
2015-03-31 11:14 ` [PATCH 12/19] drm/i915: Unify ilk and hsw .get_aux_clock_divider Mika Kahola
2015-03-31 11:14 ` [PATCH 13/19] drm/i915: Store max cdclk value in dev_priv Mika Kahola
2015-03-31 11:14 ` [PATCH 14/19] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk Mika Kahola
2015-03-31 11:14 ` [PATCH 15/19] drm/i915: HSW cdclk support Mika Kahola
2015-04-07  6:27   ` Sivakumar Thulasimani
2015-04-07  7:03     ` Sivakumar Thulasimani
2015-04-07  8:29       ` Ville Syrjälä
2015-04-07  8:36         ` Sivakumar Thulasimani
2015-04-07  9:29           ` Mika Kahola
2015-04-07 13:52             ` Daniel Vetter
2015-04-09  7:24               ` Mika Kahola
2015-04-09  9:32                 ` Daniel Vetter
2015-04-09 13:41                   ` Mika Kahola
2015-04-09 13:51                     ` Daniel Vetter
2015-04-09 15:17                       ` Takashi Iwai
2015-04-10 13:27                         ` Mika Kahola
2015-04-10 14:10                           ` Takashi Iwai
2015-04-13  9:43                             ` Mika Kahola
2015-04-13 10:33                               ` Ville Syrjälä
2015-04-14  6:36           ` Mika Kahola
2015-04-14  6:57             ` Sivakumar Thulasimani
2015-04-14  7:06               ` Mika Kahola
2015-04-14  7:54                 ` Sivakumar Thulasimani
2015-04-07  8:28     ` Ville Syrjälä
2015-03-31 11:14 ` [PATCH 16/19] drm/i915: Add IS_BDW_ULX Mika Kahola
2015-03-31 11:14 ` [PATCH 17/19] drm/i915: BDW clock change support Mika Kahola
2015-03-31 11:14 ` [PATCH 18/19] drm/i915: Limit CHV max cdclk Mika Kahola
2015-03-31 11:14 ` [PATCH 19/19] drm/i915: Modeset global_pipes() update Mika Kahola
2015-03-31 14:45   ` Ville Syrjälä
2015-04-02  9:17     ` Mika Kahola
2015-04-02 10:05   ` Mika Kahola
2015-04-02 10:16     ` Ville Syrjälä
2015-04-07  9:36     ` Mika Kahola [this message]
2015-03-31 13:18 ` All sort of cdclk stuff Damien Lespiau

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