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* [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
@ 2015-03-31 23:03 Rodrigo Vivi
  2015-04-01  5:52 ` shuang.he
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2015-03-31 23:03 UTC (permalink / raw)
  To: intel-gfx; +Cc: Mika Kuoppala, Rodrigo Vivi

Program the default initial value of the L3SqcReg1 on BDW for performance

v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.

v3: Spec shows now a different value. It tells us to set to 0x784000
    instead the 0x610000 that is there already.
    Also rebased after a long time so using WA_WRITE now.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e1a0fd9..7f8b69a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
 #define GEN7_L3SQCREG1				0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
 
+#define GEN8_L3SQCREG1				0xB100
+#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
+
 #define GEN7_L3CNTLREG1				0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
 #define  GEN7_L3AGDIS				(1<<19)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index abe062a..c02fccc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 			    GEN6_WIZ_HASHING_MASK,
 			    GEN6_WIZ_HASHING_16x4);
 
+	/* WaProgramL3SqcReg1Default:bdw */
+	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+
 	return 0;
 }
 
-- 
2.1.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default
@ 2014-09-26 19:06 Ville Syrjälä
  2014-09-30 15:11 ` [PATCH] " Rodrigo Vivi
  0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2014-09-26 19:06 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx, Rodrigo Vivi

On Fri, Sep 26, 2014 at 03:03:19PM +0300, Mika Kuoppala wrote:
> Rodrigo Vivi <rodrigo.vivi@intel.com> writes:
> 
> > Program the default initial value of the L3SqcReg1 on BDW for performance
> >
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
> >  drivers/gpu/drm/i915/intel_pm.c | 3 +++
> >  2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 124ea60..8aafa08 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4821,6 +4821,9 @@ enum punit_power_well {
> >  #define GEN7_L3SQCREG1				0xB010
> >  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
> >  
> > +#define GEN8_L3SQCREG1				0xB100
> > +#define  BDW_WA_L3SQCREG1_DEFAULT		0x00610000
> > +
> 
> This is the default after reset. I think we want 0x00810000

Digging through some attached mails in the hsd I found this number:
0x00784000

This w/a seems to be a real mess. No bspec update, no actual infromation
in the w/a db, and even the hsd stuff is more or less useless until you
notice there's some attached email dump that has the actual number :(

> 
> -Mika
> 
> >  #define GEN7_L3CNTLREG1				0xB01C
> >  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
> >  #define  GEN7_L3AGDIS				(1<<19)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 1ec3c8f..8a58565 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5811,6 +5811,9 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
> >  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >  
> > +	/* WaProgramL3SqcReg1Default:bdw */
> > +	I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> > +
> 
> Should we use intel_ring_emit_wa?
> 
> -Mika
> 
> >  	lpt_init_clock_gating(dev);
> >  }
> >  
> > -- 
> > 1.9.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-04-07  8:24 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
2015-04-01  5:52 ` shuang.he
2015-04-01  7:49 ` Jani Nikula
2015-04-01  8:31 ` Ville Syrjälä
2015-04-01 14:49   ` Vivi, Rodrigo
2015-04-01 15:41 ` Ville Syrjälä
2015-04-07  8:26   ` Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2014-09-26 19:06 [PATCH 3/5] " Ville Syrjälä
2014-09-30 15:11 ` [PATCH] " Rodrigo Vivi
2014-10-01 13:46   ` Mika Kuoppala

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