* [PATCH] drm/i915/chv: Implement WaDisableShadowRegForCpd
@ 2015-04-14 10:28 deepak.s
2015-04-14 10:59 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: deepak.s @ 2015-04-14 10:28 UTC (permalink / raw)
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
This WA disable usage of shadow register during CPD/RC6 transactions on
CHV
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..bcdb16b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
#define GTFIFOCTL 0x120008
#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
#define GT_FIFO_NUM_RESERVED_ENTRIES 20
+#define GT_FIFO_CTL_BLOCK_POLICY (3<<11)
#define HSW_IDICR 0x9008
#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dd8b41..b9d3c00 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
/* WaDisableSDEUnitClockGating:chv */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaDisableShadowRegForCpd */
+ I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+ GT_FIFO_CTL_BLOCK_POLICY);
}
static void g4x_init_clock_gating(struct drm_device *dev)
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-14 10:28 [PATCH] drm/i915/chv: Implement WaDisableShadowRegForCpd deepak.s
@ 2015-04-14 10:59 ` Ville Syrjälä
2015-04-15 8:02 ` Deepak S
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2015-04-14 10:59 UTC (permalink / raw)
To: deepak.s; +Cc: intel-gfx
On Tue, Apr 14, 2015 at 03:58:54PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> This WA disable usage of shadow register during CPD/RC6 transactions on
> CHV
I suppose is a workaround for the shadow vs. wake FIFO problem... Yeah
hsd seems to agree (after a bit of extra digging).
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..bcdb16b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
> #define GTFIFOCTL 0x120008
> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
> +#define GT_FIFO_CTL_BLOCK_POLICY (3<<11)
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
perhaps?
>
> #define HSW_IDICR 0x9008
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4dd8b41..b9d3c00 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> /* WaDisableSDEUnitClockGating:chv */
> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> + /* WaDisableShadowRegForCpd */
> + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_POLICY);
I think __intel_uncore_early_sanitize() might be a better place for
this.
> }
>
> static void g4x_init_clock_gating(struct drm_device *dev)
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-14 10:59 ` Ville Syrjälä
@ 2015-04-15 8:02 ` Deepak S
2015-04-15 8:46 ` [PATCH v2] " deepak.s
0 siblings, 1 reply; 14+ messages in thread
From: Deepak S @ 2015-04-15 8:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tuesday 14 April 2015 04:29 PM, Ville Syrjälä wrote:
> On Tue, Apr 14, 2015 at 03:58:54PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> This WA disable usage of shadow register during CPD/RC6 transactions on
>> CHV
> I suppose is a workaround for the shadow vs. wake FIFO problem... Yeah
> hsd seems to agree (after a bit of extra digging).
Yes ville, this WA is avoid problem between shadow vs wake FIFO unload problem.
I will address the comments and send new patch set
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 9c97842..bcdb16b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
>> #define GTFIFOCTL 0x120008
>> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
>> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
>> +#define GT_FIFO_CTL_BLOCK_POLICY (3<<11)
> GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
> GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>
> perhaps?
>>
>> #define HSW_IDICR 0x9008
>> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4dd8b41..b9d3c00 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>> /* WaDisableSDEUnitClockGating:chv */
>> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> +
>> + /* WaDisableShadowRegForCpd */
>> + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
>> + GT_FIFO_CTL_BLOCK_POLICY);
> I think __intel_uncore_early_sanitize() might be a better place for
> this.
>
>> }
>>
>> static void g4x_init_clock_gating(struct drm_device *dev)
>> --
>> 1.9.1
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 8:02 ` Deepak S
@ 2015-04-15 8:46 ` deepak.s
2015-04-15 11:18 ` Ville Syrjälä
2015-04-15 18:19 ` [PATCH v2] " shuang.he
0 siblings, 2 replies; 14+ messages in thread
From: deepak.s @ 2015-04-15 8:46 UTC (permalink / raw)
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
#define GTFIFOCTL 0x120008
#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
#define GT_FIFO_NUM_RESERVED_ENTRIES 20
+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
#define HSW_IDICR 0x9008
#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dd8b41..2b86915 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
/* WaDisableSDEUnitClockGating:chv */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaDisableShadowRegForCpd */
+ I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+ GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
}
static void g4x_init_clock_gating(struct drm_device *dev)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 8:46 ` [PATCH v2] " deepak.s
@ 2015-04-15 11:18 ` Ville Syrjälä
2015-04-15 13:39 ` Deepak S
2015-04-15 18:19 ` [PATCH v2] " shuang.he
1 sibling, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2015-04-15 11:18 UTC (permalink / raw)
To: deepak.s; +Cc: intel-gfx
On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..a642a58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
> #define GTFIFOCTL 0x120008
> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>
> #define HSW_IDICR 0x9008
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4dd8b41..2b86915 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> /* WaDisableSDEUnitClockGating:chv */
> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> + /* WaDisableShadowRegForCpd */
> + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> + GT_FIFO_CTL_RC6_POLICY_STALL);
uncore early sanitize would still seem like the better place for this.
> }
>
> static void g4x_init_clock_gating(struct drm_device *dev)
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 11:18 ` Ville Syrjälä
@ 2015-04-15 13:39 ` Deepak S
2015-04-15 14:11 ` [PATCH v3] " deepak.s
0 siblings, 1 reply; 14+ messages in thread
From: Deepak S @ 2015-04-15 13:39 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wednesday 15 April 2015 04:48 PM, Ville Syrjälä wrote:
> On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> This WA is avoid problem between shadow vs wake FIFO unload
>> problem during CPD/RC6 transactions on CHV.
>>
>> v2: Define individual bits GTFIFOCTL (Ville)
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>> 2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 9c97842..a642a58 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
>> #define GTFIFOCTL 0x120008
>> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
>> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
>> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
>> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>>
>> #define HSW_IDICR 0x9008
>> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4dd8b41..2b86915 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>> /* WaDisableSDEUnitClockGating:chv */
>> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> +
>> + /* WaDisableShadowRegForCpd */
>> + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
>> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
>> + GT_FIFO_CTL_RC6_POLICY_STALL);
> uncore early sanitize would still seem like the better place for this.
you mean intel_uncore_early_sanitize(). But func is called during early resume right?
Since GTFIFOCTL will be saved and resorted by gunit. I think programming reg in
cherryview_init_clock_gating should be good enough?
>> }
>>
>> static void g4x_init_clock_gating(struct drm_device *dev)
>> --
>> 1.9.1
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 13:39 ` Deepak S
@ 2015-04-15 14:11 ` deepak.s
2015-04-15 18:39 ` Ville Syrjälä
2015-04-16 2:36 ` [PATCH v3] " shuang.he
0 siblings, 2 replies; 14+ messages in thread
From: deepak.s @ 2015-04-15 14:11 UTC (permalink / raw)
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
#define GTFIFOCTL 0x120008
#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
#define GT_FIFO_NUM_RESERVED_ENTRIES 20
+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
#define HSW_IDICR 0x9008
#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..26d6dda 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
__raw_i915_read32(dev_priv, GTFIFODBG));
+ /* WaDisableShadowRegForCpd */
+ if (IS_CHERRYVIEW(dev)) {
+ __raw_i915_write32(dev_priv, GTFIFOCTL,
+ __raw_i915_read32(dev_priv, GTFIFOCTL) |
+ GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
+ }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 8:46 ` [PATCH v2] " deepak.s
2015-04-15 11:18 ` Ville Syrjälä
@ 2015-04-15 18:19 ` shuang.he
1 sibling, 0 replies; 14+ messages in thread
From: shuang.he @ 2015-04-15 18:19 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, deepak.s
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6196
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 318/318 318/318
IVB 341/341 341/341
BYT 287/287 287/287
HSW -1 395/395 394/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*HSW igt@gem_pwrite_pread@snooped-copy-performance PASS(2) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 14:11 ` [PATCH v3] " deepak.s
@ 2015-04-15 18:39 ` Ville Syrjälä
2015-04-16 3:19 ` Deepak S
2015-04-16 2:36 ` [PATCH v3] " shuang.he
1 sibling, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2015-04-15 18:39 UTC (permalink / raw)
To: deepak.s; +Cc: intel-gfx
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> v3: move WA to uncore_early_sanitize (ville)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..a642a58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
> #define GTFIFOCTL 0x120008
> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>
> #define HSW_IDICR 0x9008
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d96d15f..26d6dda 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
> __raw_i915_write32(dev_priv, GTFIFODBG,
> __raw_i915_read32(dev_priv, GTFIFODBG));
>
> + /* WaDisableShadowRegForCpd */
I couldn't find this w/a name anywhere official, but I guess it's fine.
Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + if (IS_CHERRYVIEW(dev)) {
> + __raw_i915_write32(dev_priv, GTFIFOCTL,
> + __raw_i915_read32(dev_priv, GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> + GT_FIFO_CTL_RC6_POLICY_STALL);
> + }
> +
> intel_uncore_forcewake_reset(dev, restore_forcewake);
> }
>
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 14:11 ` [PATCH v3] " deepak.s
2015-04-15 18:39 ` Ville Syrjälä
@ 2015-04-16 2:36 ` shuang.he
1 sibling, 0 replies; 14+ messages in thread
From: shuang.he @ 2015-04-16 2:36 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, deepak.s
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6201
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK -1 302/302 301/302
SNB 318/318 318/318
IVB 341/341 341/341
BYT 287/287 287/287
HSW -1 395/395 394/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*ILK igt@gem_fenced_exec_thrash@no-spare-fences-busy PASS(2) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck timer elapsed... bsd ring idle
*HSW igt@gem_pwrite_pread@snooped-pwrite-blt-cpu_mmap-performance PASS(5) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-15 18:39 ` Ville Syrjälä
@ 2015-04-16 3:19 ` Deepak S
2015-04-16 3:21 ` [PATCH v4] " deepak.s
0 siblings, 1 reply; 14+ messages in thread
From: Deepak S @ 2015-04-16 3:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thursday 16 April 2015 12:09 AM, Ville Syrjälä wrote:
> On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> This WA is avoid problem between shadow vs wake FIFO unload
>> problem during CPD/RC6 transactions on CHV.
>>
>> v2: Define individual bits GTFIFOCTL (Ville)
>>
>> v3: move WA to uncore_early_sanitize (ville)
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
>> 2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 9c97842..a642a58 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
>> #define GTFIFOCTL 0x120008
>> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
>> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
>> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
>> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>>
>> #define HSW_IDICR 0x9008
>> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index d96d15f..26d6dda 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
>> __raw_i915_write32(dev_priv, GTFIFODBG,
>> __raw_i915_read32(dev_priv, GTFIFODBG));
>>
>> + /* WaDisableShadowRegForCpd */
> I couldn't find this w/a name anywhere official, but I guess it's fine.
> Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks Ville for reviewing. I this the WA still not added to the chv list.
>> + if (IS_CHERRYVIEW(dev)) {
>> + __raw_i915_write32(dev_priv, GTFIFOCTL,
>> + __raw_i915_read32(dev_priv, GTFIFOCTL) |
>> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
>> + GT_FIFO_CTL_RC6_POLICY_STALL);
>> + }
>> +
>> intel_uncore_forcewake_reset(dev, restore_forcewake);
>> }
>>
>> --
>> 1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-16 3:19 ` Deepak S
@ 2015-04-16 3:21 ` deepak.s
2015-04-16 21:05 ` shuang.he
2015-04-28 14:41 ` Jani Nikula
0 siblings, 2 replies; 14+ messages in thread
From: deepak.s @ 2015-04-16 3:21 UTC (permalink / raw)
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
#define GTFIFOCTL 0x120008
#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
#define GT_FIFO_NUM_RESERVED_ENTRIES 20
+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
#define HSW_IDICR 0x9008
#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..d7cfd0c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
__raw_i915_read32(dev_priv, GTFIFODBG));
+ /* WaDisableShadowRegForCpd:chv */
+ if (IS_CHERRYVIEW(dev)) {
+ __raw_i915_write32(dev_priv, GTFIFOCTL,
+ __raw_i915_read32(dev_priv, GTFIFOCTL) |
+ GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
+ }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v4] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-16 3:21 ` [PATCH v4] " deepak.s
@ 2015-04-16 21:05 ` shuang.he
2015-04-28 14:41 ` Jani Nikula
1 sibling, 0 replies; 14+ messages in thread
From: shuang.he @ 2015-04-16 21:05 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, deepak.s
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6210
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 318/318 318/318
IVB 341/341 341/341
BYT 287/287 287/287
HSW -1 395/395 394/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*HSW igt@gem_pwrite_pread@uncached-copy-performance PASS(3) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4] drm/i915/chv: Implement WaDisableShadowRegForCpd
2015-04-16 3:21 ` [PATCH v4] " deepak.s
2015-04-16 21:05 ` shuang.he
@ 2015-04-28 14:41 ` Jani Nikula
1 sibling, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2015-04-28 14:41 UTC (permalink / raw)
To: deepak.s, intel-gfx
On Thu, 16 Apr 2015, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> v3: move WA to uncore_early_sanitize (ville)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pushed to drm-intel-fixes, thanks for the patch and review.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..a642a58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
> #define GTFIFOCTL 0x120008
> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>
> #define HSW_IDICR 0x9008
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d96d15f..d7cfd0c 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
> __raw_i915_write32(dev_priv, GTFIFODBG,
> __raw_i915_read32(dev_priv, GTFIFODBG));
>
> + /* WaDisableShadowRegForCpd:chv */
> + if (IS_CHERRYVIEW(dev)) {
> + __raw_i915_write32(dev_priv, GTFIFOCTL,
> + __raw_i915_read32(dev_priv, GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> + GT_FIFO_CTL_RC6_POLICY_STALL);
> + }
> +
> intel_uncore_forcewake_reset(dev, restore_forcewake);
> }
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2015-04-28 14:39 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-14 10:28 [PATCH] drm/i915/chv: Implement WaDisableShadowRegForCpd deepak.s
2015-04-14 10:59 ` Ville Syrjälä
2015-04-15 8:02 ` Deepak S
2015-04-15 8:46 ` [PATCH v2] " deepak.s
2015-04-15 11:18 ` Ville Syrjälä
2015-04-15 13:39 ` Deepak S
2015-04-15 14:11 ` [PATCH v3] " deepak.s
2015-04-15 18:39 ` Ville Syrjälä
2015-04-16 3:19 ` Deepak S
2015-04-16 3:21 ` [PATCH v4] " deepak.s
2015-04-16 21:05 ` shuang.he
2015-04-28 14:41 ` Jani Nikula
2015-04-16 2:36 ` [PATCH v3] " shuang.he
2015-04-15 18:19 ` [PATCH v2] " shuang.he
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