[U-Boot] [PATCH 1/4] drivers:usb:dwc3: Add DWC3 controller driver support

[U-Boot] [PATCH 1/4] drivers:usb:dwc3: Add DWC3 controller driver support

[Ramneek Mehresh]

Add support for DWC3 XHCI controller driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
 drivers/usb/host/Makefile    |  1 +
 drivers/usb/host/xhci-dwc3.c | 75 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/dwc3.h     |  4 +++
 3 files changed, 80 insertions(+)
 create mode 100644 drivers/usb/host/xhci-dwc3.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7658f87..c0d95cf 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
new file mode 100644
index 0000000..c875851
--- /dev/null
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * DWC3 controller driver
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/usb/dwc3.h>
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+	clrsetbits_le32(&dwc3_reg->g_ctl,
+			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+			DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+	/* Before Resetting PHY, put Core in Reset */
+	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+	/* reset USB3 phy - if required */
+	usb_phy_reset(dwc3_reg);
+
+	/* After PHYs are stable we can take Core out of reset state */
+	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+	u32 reg;
+	u32 revision;
+	unsigned int dwc3_hwparams1;
+
+	revision = readl(&dwc3_reg->g_snpsid);
+	/* This should read as U3 followed by revision number */
+	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+		puts("this is not a DesignWare USB3 DRD Core\n");
+		return -1;
+	}
+
+	dwc3_core_soft_reset(dwc3_reg);
+
+	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+	reg = readl(&dwc3_reg->g_ctl);
+	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+	reg &= ~DWC3_GCTL_DISSCRAMBLE;
+	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+		break;
+	default:
+		debug("No power optimization available\n");
+	}
+
+	/*
+	 * WORKAROUND: DWC3 revisions <1.90a have a bug
+	 * where the device can fail to connect@SuperSpeed
+	 * and falls back to high-speed mode which causes
+	 * the device to enter a Connect/Disconnect loop
+	 */
+	if ((revision & DWC3_REVISION_MASK) < 0x190a)
+		reg |= DWC3_GCTL_U2RSTECN;
+
+	writel(reg, &dwc3_reg->g_ctl);
+
+	return 0;
+}
+
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..c21878c 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -191,4 +191,8 @@ struct dwc3 {					/* offset: 0xC100 */
 #define DWC3_DCTL_CSFTRST			(1 << 30)
 #define DWC3_DCTL_LSFTRST			(1 << 29)
 
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
 #endif /* __DWC3_H_ */
-- 
1.8.3.1

[U-Boot] [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support

[Ramneek Mehresh]

Add xhci driver support for all FSL socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
 drivers/usb/host/Makefile    |   1 +
 drivers/usb/host/xhci-fsl.c  | 110 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/xhci-fsl.h |  58 +++++++++++++++++++++++
 3 files changed, 169 insertions(+)
 create mode 100644 drivers/usb/host/xhci-fsl.c
 create mode 100644 include/linux/usb/xhci-fsl.h

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c0d95cf..7c94439 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 0000000..9d89313
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+/*#include <asm/arch/cpu.h>*/
+/*#include <asm/arch/sys_proto.h>*/
+#include <linux/compat.h>
+#include <linux/usb/xhci-fsl.h>
+#include <linux/usb/dwc3.h>
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
+inline int __board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+	__attribute__((weak, alias("__board_usb_init")));
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+	/* Assert USB3 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Assert USB2 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	mdelay(200);
+
+	/* Clear USB3 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Clear USB2 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+	int ret = 0;
+
+	ret = dwc3_core_init(fsl_xhci->dwc3_reg);
+	if (ret) {
+		debug("%s:failed to initialize core\n", __func__);
+		return ret;
+	}
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+	/* Currently fsl socs do not support PHY shutdown from
+	 * sw. But this support may be added in future socs */
+	return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+	struct fsl_xhci *ctx = &fsl_xhci;
+	int ret = 0;
+
+	ctx->hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+	ctx->dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
+
+	ret = board_usb_init(index, USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+	ret = fsl_xhci_core_init(ctx);
+	if (ret < 0) {
+		puts("Failed to initialize xhci\n");
+		return ret;
+	}
+
+	*hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n",
+	      (uint32_t)*hccr, (uint32_t)*hcor,
+	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+	struct fsl_xhci *ctx = &fsl_xhci;
+
+	fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 0000000..1751c7a
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define FSL_XHCI_BASE 0x3100000
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A020000
+
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     BIT(6)
+#define USB3_PHY_RX_POWERON		BIT(14)
+#define USB3_PHY_TX_POWERON		BIT(15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	BIT(17)
+#define USBOTGSS_DMADISABLE BIT(16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
+#define USBOTGSS_STANDBYMODE_SMRT		BIT(5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
+#define USBOTGSS_IDLEMODE_SMRT BIT(3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	BIT(1)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	BIT(1)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	BIT(3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	BIT(4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	BIT(5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	BIT(8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	BIT(11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	BIT(12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	BIT(13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN		BIT(16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	BIT(17)
+
+struct fsl_xhci {
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+#endif /* _ASM_ARCH_XHCI_FSL_H_ */
-- 
1.8.3.1

[U-Boot] [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support

[Marek Vasut]

On Wednesday, April 22, 2015 at 08:49:41 AM, Ramneek Mehresh wrote:
> Add xhci driver support for all FSL socs
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

Hi!

[...]

> diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
> new file mode 100644
> index 0000000..9d89313
> --- /dev/null
> +++ b/drivers/usb/host/xhci-fsl.c
> @@ -0,0 +1,110 @@
> +/*
> + * Copyright 2015 Freescale Semiconductor, Inc.
> + *
> + * FSL USB HOST xHCI Controller
> + *
> + * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <usb.h>
> +#include <asm-generic/errno.h>
> +/*#include <asm/arch/cpu.h>*/
> +/*#include <asm/arch/sys_proto.h>*/

Remove these please .

> +#include <linux/compat.h>
> +#include <linux/usb/xhci-fsl.h>
> +#include <linux/usb/dwc3.h>
> +#include "xhci.h"
> +
> +/* Declare global data pointer */
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct fsl_xhci fsl_xhci;
> +

This will do:

__weak int board_usb_init(...)
{
	return 0;
}

> +inline int __board_usb_init(int index, enum usb_init_type init)
> +{
> +	return 0;
> +}
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +	__attribute__((weak, alias("__board_usb_init")));

Drop the above, just use __weak .

> +void usb_phy_reset(struct dwc3 *dwc3_reg)
> +{
> +	/* Assert USB3 PHY reset */
> +	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
> +
> +	/* Assert USB2 PHY reset */
> +	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
> +
> +	mdelay(200);
> +
> +	/* Clear USB3 PHY reset */
> +	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
> +
> +	/* Clear USB2 PHY reset */
> +	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
> +}
> +
> +static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
> +{
> +	int ret = 0;
> +
> +	ret = dwc3_core_init(fsl_xhci->dwc3_reg);
> +	if (ret) {
> +		debug("%s:failed to initialize core\n", __func__);
> +		return ret;
> +	}
> +
> +	/* We are hard-coding DWC3 core to Host Mode */
> +	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> +
> +	return ret;
> +}
> +
> +static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
> +{
> +	/* Currently fsl socs do not support PHY shutdown from
> +	 * sw. But this support may be added in future socs */

Multiline comment should be in this form:

/*
 * foo
 * bar
 */

> +	return 0;
> +}
> +
> +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor
> **hcor) +{
> +	struct fsl_xhci *ctx = &fsl_xhci;
> +	int ret = 0;
> +
> +	ctx->hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
> +	ctx->dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
> +
> +	ret = board_usb_init(index, USB_INIT_HOST);
> +	if (ret != 0) {
> +		puts("Failed to initialize board for USB\n");
> +		return ret;
> +	}
> +
> +	ret = fsl_xhci_core_init(ctx);
> +	if (ret < 0) {
> +		puts("Failed to initialize xhci\n");
> +		return ret;
> +	}
> +
> +	*hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
> +	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
> +				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> +
> +	debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n",
> +	      (uint32_t)*hccr, (uint32_t)*hcor,
> +	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> +
> +	return ret;
> +}
> +
> +void xhci_hcd_stop(int index)
> +{
> +	struct fsl_xhci *ctx = &fsl_xhci;
> +
> +	fsl_xhci_core_exit(ctx);
> +}
> diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
> new file mode 100644
> index 0000000..1751c7a
> --- /dev/null
> +++ b/include/linux/usb/xhci-fsl.h
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright 2015 Freescale Semiconductor, Inc.
> + *
> + * FSL USB HOST xHCI Controller
> + *
> + * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_XHCI_FSL_H_
> +#define _ASM_ARCH_XHCI_FSL_H_
> +
> +/* Default to the FSL XHCI defines */
> +#define FSL_XHCI_BASE 0x3100000
> +#define FSL_OCP1_SCP_BASE 0x4a084c00
> +#define FSL_OTG_WRAPPER_BASE 0x4A020000

This should be in CPU-specific file I guess, not in IP-specific one.

[...]

[U-Boot] [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support

[Ramneek Mehresh]

> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Wednesday, April 22, 2015 5:17 PM
> To: Mehresh Ramneek-B31383
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support
> 
> On Wednesday, April 22, 2015 at 08:49:41 AM, Ramneek Mehresh wrote:
> > Add xhci driver support for all FSL socs
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> 
> Hi!
> 
> [...]
> 
> > diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
> > new file mode 100644 index 0000000..9d89313
> > --- /dev/null
> > +++ b/drivers/usb/host/xhci-fsl.c
> > @@ -0,0 +1,110 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * FSL USB HOST xHCI Controller
> > + *
> > + * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +
> > +#include <common.h>
> > +#include <usb.h>
> > +#include <asm-generic/errno.h>
> > +/*#include <asm/arch/cpu.h>*/
> > +/*#include <asm/arch/sys_proto.h>*/
> 
> Remove these please .
> 
Oops, my bad, will do

> > +#include <linux/compat.h>
> > +#include <linux/usb/xhci-fsl.h>
> > +#include <linux/usb/dwc3.h>
> > +#include "xhci.h"
> > +
> > +/* Declare global data pointer */
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static struct fsl_xhci fsl_xhci;
> > +
> 
> This will do:
> 
agreed
> __weak int board_usb_init(...)
> {
> 	return 0;
> }
> 
> > +inline int __board_usb_init(int index, enum usb_init_type init) {
> > +	return 0;
> > +}
> > +
> > +int board_usb_init(int index, enum usb_init_type init)
> > +	__attribute__((weak, alias("__board_usb_init")));
> 
> Drop the above, just use __weak .
> 
> > +void usb_phy_reset(struct dwc3 *dwc3_reg) {
> > +	/* Assert USB3 PHY reset */
> > +	setbits_le32(&dwc3_reg->g_usb3pipectl[0],
> > +DWC3_GUSB3PIPECTL_PHYSOFTRST);
> > +
> > +	/* Assert USB2 PHY reset */
> > +	setbits_le32(&dwc3_reg->g_usb2phycfg,
> DWC3_GUSB2PHYCFG_PHYSOFTRST);
> > +
> > +	mdelay(200);
> > +
> > +	/* Clear USB3 PHY reset */
> > +	clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
> > +DWC3_GUSB3PIPECTL_PHYSOFTRST);
> > +
> > +	/* Clear USB2 PHY reset */
> > +	clrbits_le32(&dwc3_reg->g_usb2phycfg,
> DWC3_GUSB2PHYCFG_PHYSOFTRST);
> > +}
> > +
> > +static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) {
> > +	int ret = 0;
> > +
> > +	ret = dwc3_core_init(fsl_xhci->dwc3_reg);
> > +	if (ret) {
> > +		debug("%s:failed to initialize core\n", __func__);
> > +		return ret;
> > +	}
> > +
> > +	/* We are hard-coding DWC3 core to Host Mode */
> > +	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> > +
> > +	return ret;
> > +}
> > +
> > +static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) {
> > +	/* Currently fsl socs do not support PHY shutdown from
> > +	 * sw. But this support may be added in future socs */
> 
> Multiline comment should be in this form:
> 
Will correct
> /*
>  * foo
>  * bar
>  */
> 
> > +	return 0;
> > +}
> > +
> > +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct
> > +xhci_hcor
> > **hcor) +{
> > +	struct fsl_xhci *ctx = &fsl_xhci;
> > +	int ret = 0;
> > +
> > +	ctx->hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
> > +	ctx->dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE +
> DWC3_REG_OFFSET);
> > +
> > +	ret = board_usb_init(index, USB_INIT_HOST);
> > +	if (ret != 0) {
> > +		puts("Failed to initialize board for USB\n");
> > +		return ret;
> > +	}
> > +
> > +	ret = fsl_xhci_core_init(ctx);
> > +	if (ret < 0) {
> > +		puts("Failed to initialize xhci\n");
> > +		return ret;
> > +	}
> > +
> > +	*hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
> > +	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
> > +				+ HC_LENGTH(xhci_readl(&(*hccr)-
> >cr_capbase)));
> > +
> > +	debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n",
> > +	      (uint32_t)*hccr, (uint32_t)*hcor,
> > +	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> > +
> > +	return ret;
> > +}
> > +
> > +void xhci_hcd_stop(int index)
> > +{
> > +	struct fsl_xhci *ctx = &fsl_xhci;
> > +
> > +	fsl_xhci_core_exit(ctx);
> > +}
> > diff --git a/include/linux/usb/xhci-fsl.h
> > b/include/linux/usb/xhci-fsl.h new file mode 100644 index
> > 0000000..1751c7a
> > --- /dev/null
> > +++ b/include/linux/usb/xhci-fsl.h
> > @@ -0,0 +1,58 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * FSL USB HOST xHCI Controller
> > + *
> > + * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +
> > +#ifndef _ASM_ARCH_XHCI_FSL_H_
> > +#define _ASM_ARCH_XHCI_FSL_H_
> > +
> > +/* Default to the FSL XHCI defines */ #define FSL_XHCI_BASE 0x3100000
> > +#define FSL_OCP1_SCP_BASE 0x4a084c00 #define
> FSL_OTG_WRAPPER_BASE
> > +0x4A020000
> 
> This should be in CPU-specific file I guess, not in IP-specific one.
> 
Agreed, let me check which file can be used for this
> [...]

[U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support

[Ramneek Mehresh]

Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
 include/configs/ls1021atwr.h | 29 +++++++++++++++++++++++++++++
 include/linux/usb/xhci-fsl.h |  5 +++++
 2 files changed, 34 insertions(+)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..0f59b3c 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,35 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 /*
+ * USB
+ */
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
  * Generic Timer Definitions
  */
 #define GENERIC_TIMER_CLK		12500000
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 1751c7a..dc82151 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -50,6 +50,11 @@
 #define USBOTGSS_IRQ_SET_1_OEVT_EN		BIT(16)
 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	BIT(17)
 
+#ifdef CONFIG_LS102XA
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#endif
+
 struct fsl_xhci {
 	struct xhci_hccr *hcd;
 	struct dwc3 *dwc3_reg;
-- 
1.8.3.1

[U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support

[Marek Vasut]

On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote:
> Enable USB IP support for both EHCI and XHCI for
> ls1021atwr platform
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> ---
>  include/configs/ls1021atwr.h | 29 +++++++++++++++++++++++++++++
>  include/linux/usb/xhci-fsl.h |  5 +++++
>  2 files changed, 34 insertions(+)
> 
> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
> index a13876b..0f59b3c 100644
> --- a/include/configs/ls1021atwr.h
> +++ b/include/configs/ls1021atwr.h
> @@ -28,6 +28,35 @@
>  #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
> 
>  /*
> + * USB
> + */
> +/* EHCI Support - disbaled by default */

'disabled'

> +/*#define CONFIG_HAS_FSL_DR_USB*/

Why is this disabled ?

[...]

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support

[Ramneek Mehresh]

> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Wednesday, April 22, 2015 5:18 PM
> To: Mehresh Ramneek-B31383
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support
> 
> On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote:
> > Enable USB IP support for both EHCI and XHCI for ls1021atwr platform
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> > ---
> >  include/configs/ls1021atwr.h | 29 +++++++++++++++++++++++++++++
> > include/linux/usb/xhci-fsl.h |  5 +++++
> >  2 files changed, 34 insertions(+)
> >
> > diff --git a/include/configs/ls1021atwr.h
> > b/include/configs/ls1021atwr.h index a13876b..0f59b3c 100644
> > --- a/include/configs/ls1021atwr.h
> > +++ b/include/configs/ls1021atwr.h
> > @@ -28,6 +28,35 @@
> >  #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
> >
> >  /*
> > + * USB
> > + */
> > +/* EHCI Support - disbaled by default */
> 
> 'disabled'
> 
> > +/*#define CONFIG_HAS_FSL_DR_USB*/
> 
> Why is this disabled ?
> 
EHCI is disabled because this controller is not exposed via any connector
on the board. However, the silicon still has this controller, and anyone can
use this controller by taking signals out on their board.
XHCI can be used on the board via micro-A usb host connector
> [...]
> 
> Best regards,
> Marek Vasut

[U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support

[Marek Vasut]

On Thursday, April 23, 2015 at 08:51:14 AM, Ramneek Mehresh wrote:
> > -----Original Message-----
> > From: Marek Vasut [mailto:marex at denx.de]
> > Sent: Wednesday, April 22, 2015 5:18 PM
> > To: Mehresh Ramneek-B31383
> > Cc: u-boot at lists.denx.de
> > Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP
> > support
> > 
> > On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote:
> > > Enable USB IP support for both EHCI and XHCI for ls1021atwr platform
> > > 
> > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> > > ---
> > > 
> > >  include/configs/ls1021atwr.h | 29 +++++++++++++++++++++++++++++
> > > 
> > > include/linux/usb/xhci-fsl.h |  5 +++++
> > > 
> > >  2 files changed, 34 insertions(+)
> > > 
> > > diff --git a/include/configs/ls1021atwr.h
> > > b/include/configs/ls1021atwr.h index a13876b..0f59b3c 100644
> > > --- a/include/configs/ls1021atwr.h
> > > +++ b/include/configs/ls1021atwr.h
> > > @@ -28,6 +28,35 @@
> > > 
> > >  #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
> > >  
> > >  /*
> > > 
> > > + * USB
> > > + */
> > > +/* EHCI Support - disbaled by default */
> > 
> > 'disabled'
> > 
> > > +/*#define CONFIG_HAS_FSL_DR_USB*/
> > 
> > Why is this disabled ?
> 
> EHCI is disabled because this controller is not exposed via any connector
> on the board. However, the silicon still has this controller, and anyone
> can use this controller by taking signals out on their board.
> XHCI can be used on the board via micro-A usb host connector

Oki, please document it a bit better. The thing you just wrote would be exactly
the nice piece of documentation/comment which should be in the code.

Thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support

[Ramneek Mehresh]

> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Thursday, April 23, 2015 5:26 PM
> To: Mehresh Ramneek-B31383
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support
> 
> On Thursday, April 23, 2015 at 08:51:14 AM, Ramneek Mehresh wrote:
> > > -----Original Message-----
> > > From: Marek Vasut [mailto:marex at denx.de]
> > > Sent: Wednesday, April 22, 2015 5:18 PM
> > > To: Mehresh Ramneek-B31383
> > > Cc: u-boot at lists.denx.de
> > > Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP
> > > support
> > >
> > > On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote:
> > > > Enable USB IP support for both EHCI and XHCI for ls1021atwr
> > > > platform
> > > >
> > > > Signed-off-by: Ramneek Mehresh
> <ramneek.mehresh@freescale.com>
> > > > ---
> > > >
> > > >  include/configs/ls1021atwr.h | 29
> +++++++++++++++++++++++++++++
> > > >
> > > > include/linux/usb/xhci-fsl.h |  5 +++++
> > > >
> > > >  2 files changed, 34 insertions(+)
> > > >
> > > > diff --git a/include/configs/ls1021atwr.h
> > > > b/include/configs/ls1021atwr.h index a13876b..0f59b3c 100644
> > > > --- a/include/configs/ls1021atwr.h
> > > > +++ b/include/configs/ls1021atwr.h
> > > > @@ -28,6 +28,35 @@
> > > >
> > > >  #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
> > > >
> > > >  /*
> > > >
> > > > + * USB
> > > > + */
> > > > +/* EHCI Support - disbaled by default */
> > >
> > > 'disabled'
> > >
> > > > +/*#define CONFIG_HAS_FSL_DR_USB*/
> > >
> > > Why is this disabled ?
> >
> > EHCI is disabled because this controller is not exposed via any
> > connector on the board. However, the silicon still has this
> > controller, and anyone can use this controller by taking signals out on their
> board.
> > XHCI can be used on the board via micro-A usb host connector
> 
> Oki, please document it a bit better. The thing you just wrote would be
> exactly the nice piece of documentation/comment which should be in the
> code.
> 
Understood, will do
> Thanks!
> 
> Best regards,
> Marek Vasut

[U-Boot] [PATCH 4/4] include:configs:ls1021aqds: Enable USB IP support

[Ramneek Mehresh]

Enable USB IP support for both EHCI and XHCI for
ls1021aqds platform

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
 include/configs/ls1021aqds.h | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5de416d..1aa2f94 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -423,19 +423,31 @@ unsigned long get_board_ddr_clk(void);
 /*
  * USB
  */
-#define CONFIG_HAS_FSL_DR_USB
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
 
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
 
-#ifdef CONFIG_USB_EHCI
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
 #endif
-#endif
 
 /*
  * Video
-- 
1.8.3.1