* [PATCH 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-06-19 8:43 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-19 8:43 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a boolean to the core spi-dw driver to indicate to the core that 16 bit data register access is appropriate, implements the code that respects that flag and updates the dw-spi-mmio driver to allow setting this boolean from the device tree. A binding documentation fix is included in this series. Prior to applying this change the following error presents on a picoCell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Describe 16 bit data register usage limitations spi: dw: Allow interface drivers to limit data I/O to word sizes Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 +++ drivers/spi/spi-dw-mmio.c | 5 +++++ drivers/spi/spi-dw.c | 13 +++++++++++-- drivers/spi/spi-dw.h | 11 +++++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-06-19 8:43 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-19 8:43 UTC (permalink / raw) To: linux-arm-kernel The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a boolean to the core spi-dw driver to indicate to the core that 16 bit data register access is appropriate, implements the code that respects that flag and updates the dw-spi-mmio driver to allow setting this boolean from the device tree. A binding documentation fix is included in this series. Prior to applying this change the following error presents on a picoCell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Describe 16 bit data register usage limitations spi: dw: Allow interface drivers to limit data I/O to word sizes Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 +++ drivers/spi/spi-dw-mmio.c | 5 +++++ drivers/spi/spi-dw.c | 13 +++++++++++-- drivers/spi/spi-dw.h | 11 +++++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) -- 2.1.4 ^ permalink raw reply [flat|nested] 41+ messages in thread
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* [PATCH 2/2] dt: snps,dw-apb-ssi: Describe 16 bit data register usage limitations 2015-06-19 8:43 ` Michael van der Westhuizen @ 2015-06-19 8:43 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-19 8:43 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to interact with the SPI controller data register in 16 bit mode only. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..3b2a86f 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,9 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- snps,data-io-16bit : A boolean property that, when present, causes + the driver to interact with the data register using 16 bit I/O instead + of the default 32 bit I/O. Child nodes as per the generic SPI binding. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 2/2] dt: snps, dw-apb-ssi: Describe 16 bit data register usage limitations @ 2015-06-19 8:43 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-19 8:43 UTC (permalink / raw) To: linux-arm-kernel This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to interact with the SPI controller data register in 16 bit mode only. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..3b2a86f 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,9 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- snps,data-io-16bit : A boolean property that, when present, causes + the driver to interact with the data register using 16 bit I/O instead + of the default 32 bit I/O. Child nodes as per the generic SPI binding. -- 2.1.4 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-06-19 8:43 ` Michael van der Westhuizen @ 2015-06-19 8:43 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-19 8:43 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> --- drivers/spi/spi-dw-mmio.c | 5 +++++ drivers/spi/spi-dw.c | 13 +++++++++++-- drivers/spi/spi-dw.h | 11 +++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..1397424 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,11 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + dws->data_io_16bit = + of_property_read_bool(pdev->dev.of_node, + "snps,data-io-16bit"); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..862b001 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,12 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + + if (dws->data_io_16bit) + dw_writew(dws, DW_SPI_DR, txw); + else + dw_writel(dws, DW_SPI_DR, txw); + dws->tx += dws->n_bytes; } } @@ -205,7 +210,11 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + if (dws->data_io_16bit) + rxw = dw_readw(dws, DW_SPI_DR); + else + rxw = dw_readl(dws, DW_SPI_DR); + /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..ced276a 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + bool data_io_16bit; /* DR is only 16 bits wide */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,21 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes @ 2015-06-19 8:43 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-19 8:43 UTC (permalink / raw) To: linux-arm-kernel The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> --- drivers/spi/spi-dw-mmio.c | 5 +++++ drivers/spi/spi-dw.c | 13 +++++++++++-- drivers/spi/spi-dw.h | 11 +++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..1397424 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,11 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + dws->data_io_16bit = + of_property_read_bool(pdev->dev.of_node, + "snps,data-io-16bit"); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..862b001 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,12 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + + if (dws->data_io_16bit) + dw_writew(dws, DW_SPI_DR, txw); + else + dw_writel(dws, DW_SPI_DR, txw); + dws->tx += dws->n_bytes; } } @@ -205,7 +210,11 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + if (dws->data_io_16bit) + rxw = dw_readw(dws, DW_SPI_DR); + else + rxw = dw_readl(dws, DW_SPI_DR); + /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..ced276a 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + bool data_io_16bit; /* DR is only 16 bits wide */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,21 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- 2.1.4 ^ permalink raw reply related [flat|nested] 41+ messages in thread
[parent not found: <1434703435-25198-3-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org>]
* Re: [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-06-19 8:43 ` Michael van der Westhuizen @ 2015-06-24 11:57 ` Andy Shevchenko -1 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-06-24 11:57 UTC (permalink / raw) To: Michael van der Westhuizen, linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Fri, 2015-06-19 at 10:43 +0200, Michael van der Westhuizen wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to > 32bit > accesses") changed all 16bit accesses in the DW_apb_ssi driver to > 32bit. > This, unfortunately, breaks data register access on picoXcell, where > the > DW IP needs data register accesses to be word accesses (all other > accesses appear to be OK). Thanks for the patch. My comments below. > > This change introduces a new master variable to allow interface > drivers > to specify that 16bit data transfer I/O is required. This change > also > introduces the ability to set this variable via device tree bindings > in > the MMIO interface driver. > > Before this change, on a picoXcell pc3x3: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > After this change: > m25p80 spi32766.0: m25p40 (512 Kbytes) > Please, add Fixes: tag as well. > Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> > --- > drivers/spi/spi-dw-mmio.c | 5 +++++ > drivers/spi/spi-dw.c | 13 +++++++++++-- > drivers/spi/spi-dw.h | 11 +++++++++++ > 3 files changed, 27 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c > index eb03e12..1397424 100644 > --- a/drivers/spi/spi-dw-mmio.c > +++ b/drivers/spi/spi-dw-mmio.c > @@ -74,6 +74,11 @@ static int dw_spi_mmio_probe(struct > platform_device *pdev) > > dws->max_freq = clk_get_rate(dwsmmio->clk); > > + if (pdev->dev.of_node) > + dws->data_io_16bit = I don't like "flexibility" in the DeviceTree data base and thus I would prefer to see what we already have in naming there, i.e. reg-io-width = 2 or 4. > + of_property_read_bool(pdev->dev.of_node, > + "snps,data-io-16bit"); > + > num_cs = 4; > > if (pdev->dev.of_node) > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 8d67d03..862b001 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -194,7 +194,12 @@ static void dw_writer(struct dw_spi *dws) > else > txw = *(u16 *)(dws->tx); > } > - dw_writel(dws, DW_SPI_DR, txw); > + > + if (dws->data_io_16bit) > + dw_writew(dws, DW_SPI_DR, txw); > + else > + dw_writel(dws, DW_SPI_DR, txw); > + > dws->tx += dws->n_bytes; > } > } > @@ -205,7 +210,11 @@ static void dw_reader(struct dw_spi *dws) > u16 rxw; > > while (max--) { > - rxw = dw_readl(dws, DW_SPI_DR); > + if (dws->data_io_16bit) > + rxw = dw_readw(dws, DW_SPI_DR); > + else > + rxw = dw_readl(dws, DW_SPI_DR); > + > /* Care rx only if the transfer's original "rx" is > not null */ > if (dws->rx_end - dws->len) { > if (dws->n_bytes == 1) > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index 6c91391..ced276a 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -109,6 +109,7 @@ struct dw_spi { > u32 fifo_len; /* depth of the FIFO > buffer */ > u32 max_freq; /* max bus freq > supported */ > > + bool data_io_16bit; /* DR is only 16 > bits wide */ > u16 bus_num; > u16 num_cs; /* supported > slave numbers */ > > @@ -145,11 +146,21 @@ static inline u32 dw_readl(struct dw_spi *dws, > u32 offset) > return __raw_readl(dws->regs + offset); > } > > +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) > +{ > + return __raw_readw(dws->regs + offset); > +} > + > static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 > val) > { > __raw_writel(val, dws->regs + offset); > } > > +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 > val) > +{ > + __raw_writew(val, dws->regs + offset); > +} > + > static inline void spi_enable_chip(struct dw_spi *dws, int enable) > { > dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); Regarding to above comment what about something like static inline u32 dw_read_reg(dws, offset) { switch (reg_io_width) case 2: return dw_readw(); case 4: default: return dw_readl(); } -- Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes @ 2015-06-24 11:57 ` Andy Shevchenko 0 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-06-24 11:57 UTC (permalink / raw) To: linux-arm-kernel On Fri, 2015-06-19 at 10:43 +0200, Michael van der Westhuizen wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to > 32bit > accesses") changed all 16bit accesses in the DW_apb_ssi driver to > 32bit. > This, unfortunately, breaks data register access on picoXcell, where > the > DW IP needs data register accesses to be word accesses (all other > accesses appear to be OK). Thanks for the patch. My comments below. > > This change introduces a new master variable to allow interface > drivers > to specify that 16bit data transfer I/O is required. This change > also > introduces the ability to set this variable via device tree bindings > in > the MMIO interface driver. > > Before this change, on a picoXcell pc3x3: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > After this change: > m25p80 spi32766.0: m25p40 (512 Kbytes) > Please, add Fixes: tag as well. > Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> > --- > drivers/spi/spi-dw-mmio.c | 5 +++++ > drivers/spi/spi-dw.c | 13 +++++++++++-- > drivers/spi/spi-dw.h | 11 +++++++++++ > 3 files changed, 27 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c > index eb03e12..1397424 100644 > --- a/drivers/spi/spi-dw-mmio.c > +++ b/drivers/spi/spi-dw-mmio.c > @@ -74,6 +74,11 @@ static int dw_spi_mmio_probe(struct > platform_device *pdev) > > dws->max_freq = clk_get_rate(dwsmmio->clk); > > + if (pdev->dev.of_node) > + dws->data_io_16bit = I don't like "flexibility" in the DeviceTree data base and thus I would prefer to see what we already have in naming there, i.e. reg-io-width = 2 or 4. > + of_property_read_bool(pdev->dev.of_node, > + "snps,data-io-16bit"); > + > num_cs = 4; > > if (pdev->dev.of_node) > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 8d67d03..862b001 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -194,7 +194,12 @@ static void dw_writer(struct dw_spi *dws) > else > txw = *(u16 *)(dws->tx); > } > - dw_writel(dws, DW_SPI_DR, txw); > + > + if (dws->data_io_16bit) > + dw_writew(dws, DW_SPI_DR, txw); > + else > + dw_writel(dws, DW_SPI_DR, txw); > + > dws->tx += dws->n_bytes; > } > } > @@ -205,7 +210,11 @@ static void dw_reader(struct dw_spi *dws) > u16 rxw; > > while (max--) { > - rxw = dw_readl(dws, DW_SPI_DR); > + if (dws->data_io_16bit) > + rxw = dw_readw(dws, DW_SPI_DR); > + else > + rxw = dw_readl(dws, DW_SPI_DR); > + > /* Care rx only if the transfer's original "rx" is > not null */ > if (dws->rx_end - dws->len) { > if (dws->n_bytes == 1) > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index 6c91391..ced276a 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -109,6 +109,7 @@ struct dw_spi { > u32 fifo_len; /* depth of the FIFO > buffer */ > u32 max_freq; /* max bus freq > supported */ > > + bool data_io_16bit; /* DR is only 16 > bits wide */ > u16 bus_num; > u16 num_cs; /* supported > slave numbers */ > > @@ -145,11 +146,21 @@ static inline u32 dw_readl(struct dw_spi *dws, > u32 offset) > return __raw_readl(dws->regs + offset); > } > > +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) > +{ > + return __raw_readw(dws->regs + offset); > +} > + > static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 > val) > { > __raw_writel(val, dws->regs + offset); > } > > +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 > val) > +{ > + __raw_writew(val, dws->regs + offset); > +} > + > static inline void spi_enable_chip(struct dw_spi *dws, int enable) > { > dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); Regarding to above comment what about something like static inline u32 dw_read_reg(dws, offset) { switch (reg_io_width) case 2: return dw_readw(); case 4: default: return dw_readl(); } -- Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-06-24 11:57 ` Andy Shevchenko (?) @ 2015-06-24 16:11 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:11 UTC (permalink / raw) To: Andy Shevchenko Cc: linux-spi, devicetree, linux-arm-kernel, Steffen Trumtrar, Thor Thayer, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala [-- Attachment #1: Type: text/plain, Size: 3150 bytes --] > On 24 Jun 2015, at 1:57 PM, Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > > On Fri, 2015-06-19 at 10:43 +0200, Michael van der Westhuizen wrote: >> The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to >> 32bit >> accesses") changed all 16bit accesses in the DW_apb_ssi driver to >> 32bit. >> This, unfortunately, breaks data register access on picoXcell, where >> the >> DW IP needs data register accesses to be word accesses (all other >> accesses appear to be OK). > > Thanks for the patch. My comments below. > >> >> This change introduces a new master variable to allow interface >> drivers >> to specify that 16bit data transfer I/O is required. This change >> also >> introduces the ability to set this variable via device tree bindings >> in >> the MMIO interface driver. >> >> Before this change, on a picoXcell pc3x3: >> spi_master spi32766: interrupt_transfer: fifo overrun/underrun >> m25p80 spi32766.0: error -5 reading 9f >> m25p80: probe of spi32766.0 failed with error -5 >> >> After this change: >> m25p80 spi32766.0: m25p40 (512 Kbytes) >> > > Please, add Fixes: tag as well. OK. > >> Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> >> --- >> drivers/spi/spi-dw-mmio.c | 5 +++++ >> drivers/spi/spi-dw.c | 13 +++++++++++-- >> drivers/spi/spi-dw.h | 11 +++++++++++ >> 3 files changed, 27 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c >> index eb03e12..1397424 100644 >> --- a/drivers/spi/spi-dw-mmio.c >> +++ b/drivers/spi/spi-dw-mmio.c >> @@ -74,6 +74,11 @@ static int dw_spi_mmio_probe(struct >> platform_device *pdev) >> >> dws->max_freq = clk_get_rate(dwsmmio->clk); >> >> + if (pdev->dev.of_node) >> + dws->data_io_16bit = > > I don't like "flexibility" in the DeviceTree data base and thus I > would prefer to see what we already have in naming there, i.e. > reg-io-width = 2 or 4. Will update. <snip> >> @@ -145,11 +146,21 @@ static inline u32 dw_readl(struct dw_spi *dws, >> u32 offset) >> return __raw_readl(dws->regs + offset); >> } >> >> +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) >> +{ >> + return __raw_readw(dws->regs + offset); >> +} >> + >> static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 >> val) >> { >> __raw_writel(val, dws->regs + offset); >> } >> >> +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 >> val) >> +{ >> + __raw_writew(val, dws->regs + offset); >> +} >> + >> static inline void spi_enable_chip(struct dw_spi *dws, int enable) >> { >> dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); > > Regarding to above comment what about something like > > static inline u32 dw_read_reg(dws, offset) > { > switch (reg_io_width) > case 2: > return dw_readw(); > case 4: > default: > return dw_readl(); > } Yes, that would be better. Note that this will only be used for data register access, as the other registers seem fine with 32 bit access. I’ll update the series and resend. Michael [-- Attachment #2: Type: text/html, Size: 20765 bytes --] ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-06-19 8:43 ` Michael van der Westhuizen @ 2015-06-24 16:34 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:34 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a boolean to the core spi-dw driver to indicate to the core that 16 bit data register access is appropriate, implements the code that respects that flag and updates the dw-spi-mmio driver to allow setting this boolean from the device tree. A binding documentation fix is included in this series. Prior to applying this change the following error presents on a picoCell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice and adjusting the driver to suit. - Add a wrapper inline function for accessing the data register using the configured with. Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Document new I/O data register width property spi: dw: Allow interface drivers to limit data I/O to word sizes drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-06-24 16:34 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:34 UTC (permalink / raw) To: linux-arm-kernel The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a boolean to the core spi-dw driver to indicate to the core that 16 bit data register access is appropriate, implements the code that respects that flag and updates the dw-spi-mmio driver to allow setting this boolean from the device tree. A binding documentation fix is included in this series. Prior to applying this change the following error presents on a picoCell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice and adjusting the driver to suit. - Add a wrapper inline function for accessing the data register using the configured with. Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Document new I/O data register width property spi: dw: Allow interface drivers to limit data I/O to word sizes drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) -- 2.1.4 ^ permalink raw reply [flat|nested] 41+ messages in thread
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* [PATCH v2 1/2] dt: snps,dw-apb-ssi: Document new I/O data register width property 2015-06-24 16:34 ` Michael van der Westhuizen @ 2015-06-24 16:34 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:34 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to specify either four byte or two bytes access to the SPI controller data register. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice. Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..b4f1086 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,8 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- snps,reg-io-width : The I/O register width (in bytes) implemented by + this device. Supported values are 2 or 4 (the default). Child nodes as per the generic SPI binding. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 1/2] dt: snps, dw-apb-ssi: Document new I/O data register width property @ 2015-06-24 16:34 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:34 UTC (permalink / raw) To: linux-arm-kernel This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to specify either four byte or two bytes access to the SPI controller data register. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice. Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..b4f1086 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,8 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- snps,reg-io-width : The I/O register width (in bytes) implemented by + this device. Supported values are 2 or 4 (the default). Child nodes as per the generic SPI binding. -- 2.1.4 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-06-24 16:34 ` Michael van der Westhuizen @ 2015-06-24 16:34 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:34 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko - Rework the DT bindings to accept an I/O register width as a number of bytes rather than using a boolean spefifying the width preference to be 16 bits. - Add data register access wrapper functions and use them when reading and writing the data register. drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..e76bf72 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + of_property_read_u32(pdev->dev.of_node, "snps,reg-io-width", + &dws->reg_io_width); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..4fbfcdc 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + dw_write_io_reg(dws, DW_SPI_DR, txw); dws->tx += dws->n_bytes; } } @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + rxw = dw_read_io_reg(dws, DW_SPI_DR); /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..b75ed32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + u32 reg_io_width; /* DR I/O width in bytes */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) +{ + switch (dws->reg_io_width) { + case 2: + return dw_readw(dws, offset); + case 4: + default: + return dw_readl(dws, offset); + } +} + +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) +{ + switch (dws->reg_io_width) { + case 2: + dw_writew(dws, offset, val); + break; + case 4: + default: + dw_writel(dws, offset, val); + break; + } +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes @ 2015-06-24 16:34 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-06-24 16:34 UTC (permalink / raw) To: linux-arm-kernel The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko - Rework the DT bindings to accept an I/O register width as a number of bytes rather than using a boolean spefifying the width preference to be 16 bits. - Add data register access wrapper functions and use them when reading and writing the data register. drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..e76bf72 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + of_property_read_u32(pdev->dev.of_node, "snps,reg-io-width", + &dws->reg_io_width); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..4fbfcdc 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + dw_write_io_reg(dws, DW_SPI_DR, txw); dws->tx += dws->n_bytes; } } @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + rxw = dw_read_io_reg(dws, DW_SPI_DR); /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..b75ed32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + u32 reg_io_width; /* DR I/O width in bytes */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) +{ + switch (dws->reg_io_width) { + case 2: + return dw_readw(dws, offset); + case 4: + default: + return dw_readl(dws, offset); + } +} + +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) +{ + switch (dws->reg_io_width) { + case 2: + dw_writew(dws, offset, val); + break; + case 4: + default: + dw_writel(dws, offset, val); + break; + } +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- 2.1.4 ^ permalink raw reply related [flat|nested] 41+ messages in thread
[parent not found: <1435163696-14767-3-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org>]
* Re: [PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-06-24 16:34 ` Michael van der Westhuizen @ 2015-06-25 14:41 ` Andy Shevchenko -1 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-06-25 14:41 UTC (permalink / raw) To: Michael van der Westhuizen, linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to > 32bit > accesses") changed all 16bit accesses in the DW_apb_ssi driver to > 32bit. > This, unfortunately, breaks data register access on picoXcell, where > the > DW IP needs data register accesses to be word accesses (all other > accesses appear to be OK). > > This change introduces a new master variable to allow interface > drivers > to specify that 16bit data transfer I/O is required. This change > also > introduces the ability to set this variable via device tree bindings > in > the MMIO interface driver. > > Before this change, on a picoXcell pc3x3: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > After this change: > m25p80 spi32766.0: m25p40 (512 Kbytes) Reviewed-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> > > Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit > accesses") > Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> > --- > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko > - Rework the DT bindings to accept an I/O register width as a > number of bytes rather than using a boolean spefifying the > width preference to be 16 bits. > - Add data register access wrapper functions and use them when > reading and writing the data register. > > drivers/spi/spi-dw-mmio.c | 4 ++++ > drivers/spi/spi-dw.c | 4 ++-- > drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c > index eb03e12..e76bf72 100644 > --- a/drivers/spi/spi-dw-mmio.c > +++ b/drivers/spi/spi-dw-mmio.c > @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct > platform_device *pdev) > > dws->max_freq = clk_get_rate(dwsmmio->clk); > > + if (pdev->dev.of_node) > + of_property_read_u32(pdev->dev.of_node, "snps,reg-io > -width", > + &dws->reg_io_width); > + > num_cs = 4; > > if (pdev->dev.of_node) > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 8d67d03..4fbfcdc 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) > else > txw = *(u16 *)(dws->tx); > } > - dw_writel(dws, DW_SPI_DR, txw); > + dw_write_io_reg(dws, DW_SPI_DR, txw); > dws->tx += dws->n_bytes; > } > } > @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) > u16 rxw; > > while (max--) { > - rxw = dw_readl(dws, DW_SPI_DR); > + rxw = dw_read_io_reg(dws, DW_SPI_DR); > /* Care rx only if the transfer's original "rx" is > not null */ > if (dws->rx_end - dws->len) { > if (dws->n_bytes == 1) > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index 6c91391..b75ed32 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -109,6 +109,7 @@ struct dw_spi { > u32 fifo_len; /* depth of the FIFO > buffer */ > u32 max_freq; /* max bus freq > supported */ > > + u32 reg_io_width; /* DR I/O width in > bytes */ > u16 bus_num; > u16 num_cs; /* supported > slave numbers */ > > @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, > u32 offset) > return __raw_readl(dws->regs + offset); > } > > +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) > +{ > + return __raw_readw(dws->regs + offset); > +} > + > static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 > val) > { > __raw_writel(val, dws->regs + offset); > } > > +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 > val) > +{ > + __raw_writew(val, dws->regs + offset); > +} > + > +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) > +{ > + switch (dws->reg_io_width) { > + case 2: > + return dw_readw(dws, offset); > + case 4: > + default: > + return dw_readl(dws, offset); > + } > +} > + > +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, > u32 val) > +{ > + switch (dws->reg_io_width) { > + case 2: > + dw_writew(dws, offset, val); > + break; > + case 4: > + default: > + dw_writel(dws, offset, val); > + break; > + } > +} > + > static inline void spi_enable_chip(struct dw_spi *dws, int enable) > { > dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes @ 2015-06-25 14:41 ` Andy Shevchenko 0 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-06-25 14:41 UTC (permalink / raw) To: linux-arm-kernel On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to > 32bit > accesses") changed all 16bit accesses in the DW_apb_ssi driver to > 32bit. > This, unfortunately, breaks data register access on picoXcell, where > the > DW IP needs data register accesses to be word accesses (all other > accesses appear to be OK). > > This change introduces a new master variable to allow interface > drivers > to specify that 16bit data transfer I/O is required. This change > also > introduces the ability to set this variable via device tree bindings > in > the MMIO interface driver. > > Before this change, on a picoXcell pc3x3: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > After this change: > m25p80 spi32766.0: m25p40 (512 Kbytes) Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit > accesses") > Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> > --- > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko > - Rework the DT bindings to accept an I/O register width as a > number of bytes rather than using a boolean spefifying the > width preference to be 16 bits. > - Add data register access wrapper functions and use them when > reading and writing the data register. > > drivers/spi/spi-dw-mmio.c | 4 ++++ > drivers/spi/spi-dw.c | 4 ++-- > drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c > index eb03e12..e76bf72 100644 > --- a/drivers/spi/spi-dw-mmio.c > +++ b/drivers/spi/spi-dw-mmio.c > @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct > platform_device *pdev) > > dws->max_freq = clk_get_rate(dwsmmio->clk); > > + if (pdev->dev.of_node) > + of_property_read_u32(pdev->dev.of_node, "snps,reg-io > -width", > + &dws->reg_io_width); > + > num_cs = 4; > > if (pdev->dev.of_node) > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 8d67d03..4fbfcdc 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) > else > txw = *(u16 *)(dws->tx); > } > - dw_writel(dws, DW_SPI_DR, txw); > + dw_write_io_reg(dws, DW_SPI_DR, txw); > dws->tx += dws->n_bytes; > } > } > @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) > u16 rxw; > > while (max--) { > - rxw = dw_readl(dws, DW_SPI_DR); > + rxw = dw_read_io_reg(dws, DW_SPI_DR); > /* Care rx only if the transfer's original "rx" is > not null */ > if (dws->rx_end - dws->len) { > if (dws->n_bytes == 1) > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index 6c91391..b75ed32 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -109,6 +109,7 @@ struct dw_spi { > u32 fifo_len; /* depth of the FIFO > buffer */ > u32 max_freq; /* max bus freq > supported */ > > + u32 reg_io_width; /* DR I/O width in > bytes */ > u16 bus_num; > u16 num_cs; /* supported > slave numbers */ > > @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, > u32 offset) > return __raw_readl(dws->regs + offset); > } > > +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) > +{ > + return __raw_readw(dws->regs + offset); > +} > + > static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 > val) > { > __raw_writel(val, dws->regs + offset); > } > > +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 > val) > +{ > + __raw_writew(val, dws->regs + offset); > +} > + > +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) > +{ > + switch (dws->reg_io_width) { > + case 2: > + return dw_readw(dws, offset); > + case 4: > + default: > + return dw_readl(dws, offset); > + } > +} > + > +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, > u32 val) > +{ > + switch (dws->reg_io_width) { > + case 2: > + dw_writew(dws, offset, val); > + break; > + case 4: > + default: > + dw_writel(dws, offset, val); > + break; > + } > +} > + > static inline void spi_enable_chip(struct dw_spi *dws, int enable) > { > dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-06-24 16:34 ` Michael van der Westhuizen @ 2015-07-24 15:30 ` Andy Shevchenko -1 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-07-24 15:30 UTC (permalink / raw) To: Michael van der Westhuizen, linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to > 32bit > accesses") globally changed all register access in the dw_apb_ssi > driver > to 32 bit access, which breaks data register (FIFO) access on > picoXcell > platforms. > > This series introduces a boolean to the core spi-dw driver to > indicate > to the core that 16 bit data register access is appropriate, > implements > the code that respects that flag and updates the dw-spi-mmio driver > to > allow setting this boolean from the device tree. > > A binding documentation fix is included in this series. > > Prior to applying this change the following error presents on > a picoCell pc3x3 platform: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > With this series applied: > m25p80 spi32766.0: m25p40 (512 Kbytes) Mark, what do you think about this? For me it looks okay. > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko, reworking the > bindings to reflect common practice and adjusting the driver > to suit. > - Add a wrapper inline function for accessing the data register > using the configured with. > > Michael van der Westhuizen (2): > dt: snps,dw-apb-ssi: Document new I/O data register width property > spi: dw: Allow interface drivers to limit data I/O to word sizes > > drivers/spi/spi-dw-mmio.c | 4 ++++ > drivers/spi/spi-dw.c | 4 ++-- > drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > -- Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-24 15:30 ` Andy Shevchenko 0 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-07-24 15:30 UTC (permalink / raw) To: linux-arm-kernel On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to > 32bit > accesses") globally changed all register access in the dw_apb_ssi > driver > to 32 bit access, which breaks data register (FIFO) access on > picoXcell > platforms. > > This series introduces a boolean to the core spi-dw driver to > indicate > to the core that 16 bit data register access is appropriate, > implements > the code that respects that flag and updates the dw-spi-mmio driver > to > allow setting this boolean from the device tree. > > A binding documentation fix is included in this series. > > Prior to applying this change the following error presents on > a picoCell pc3x3 platform: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > With this series applied: > m25p80 spi32766.0: m25p40 (512 Kbytes) Mark, what do you think about this? For me it looks okay. > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko, reworking the > bindings to reflect common practice and adjusting the driver > to suit. > - Add a wrapper inline function for accessing the data register > using the configured with. > > Michael van der Westhuizen (2): > dt: snps,dw-apb-ssi: Document new I/O data register width property > spi: dw: Allow interface drivers to limit data I/O to word sizes > > drivers/spi/spi-dw-mmio.c | 4 ++++ > drivers/spi/spi-dw.c | 4 ++-- > drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > -- Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy ^ permalink raw reply [flat|nested] 41+ messages in thread
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* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-07-24 15:30 ` Andy Shevchenko @ 2015-07-24 15:37 ` Mark Brown -1 siblings, 0 replies; 41+ messages in thread From: Mark Brown @ 2015-07-24 15:37 UTC (permalink / raw) To: Andy Shevchenko Cc: Michael van der Westhuizen, linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala [-- Attachment #1: Type: text/plain, Size: 371 bytes --] On Fri, Jul 24, 2015 at 06:30:12PM +0300, Andy Shevchenko wrote: > On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote: > > With this series applied: > > m25p80 spi32766.0: m25p40 (512 Kbytes) > Mark, what do you think about this? For me it looks okay. Please don't send content free pings, if you want me to review a patch please send me the patch. [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 473 bytes --] ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-24 15:37 ` Mark Brown 0 siblings, 0 replies; 41+ messages in thread From: Mark Brown @ 2015-07-24 15:37 UTC (permalink / raw) To: linux-arm-kernel On Fri, Jul 24, 2015 at 06:30:12PM +0300, Andy Shevchenko wrote: > On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote: > > With this series applied: > > m25p80 spi32766.0: m25p40 (512 Kbytes) > Mark, what do you think about this? For me it looks okay. Please don't send content free pings, if you want me to review a patch please send me the patch. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150724/c746fd8c/attachment.sig> ^ permalink raw reply [flat|nested] 41+ messages in thread
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* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-07-24 15:37 ` Mark Brown @ 2015-07-27 10:58 ` Andy Shevchenko -1 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-07-27 10:58 UTC (permalink / raw) To: Mark Brown Cc: Michael van der Westhuizen, linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Fri, 2015-07-24 at 16:37 +0100, Mark Brown wrote: > On Fri, Jul 24, 2015 at 06:30:12PM +0300, Andy Shevchenko wrote: > > On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen > > wrote: > > > > With this series applied: > > > m25p80 spi32766.0: m25p40 (512 Kbytes) > > > Mark, what do you think about this? For me it looks okay. > > Please don't send content free pings, if you want me to review a > patch > please send me the patch. Hmm… It's strange since patch series was sent to mailing list (Cc'ed to you) on 24.06 [1]. [1] https://www.mail-archive.com/linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg05530.html P.S. It has not mine authorship, though I can resend the series if needed. -- Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-27 10:58 ` Andy Shevchenko 0 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-07-27 10:58 UTC (permalink / raw) To: linux-arm-kernel On Fri, 2015-07-24 at 16:37 +0100, Mark Brown wrote: > On Fri, Jul 24, 2015 at 06:30:12PM +0300, Andy Shevchenko wrote: > > On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen > > wrote: > > > > With this series applied: > > > m25p80 spi32766.0: m25p40 (512 Kbytes) > > > Mark, what do you think about this? For me it looks okay. > > Please don't send content free pings, if you want me to review a > patch > please send me the patch. Hmm? It's strange since patch series was sent to mailing list (Cc'ed to you) on 24.06 [1]. [1] https://www.mail-archive.com/linux-spi at vger.kernel.org/msg05530.html P.S. It has not mine authorship, though I can resend the series if needed. -- Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy ^ permalink raw reply [flat|nested] 41+ messages in thread
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* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-07-27 10:58 ` Andy Shevchenko @ 2015-07-27 11:19 ` Mark Brown -1 siblings, 0 replies; 41+ messages in thread From: Mark Brown @ 2015-07-27 11:19 UTC (permalink / raw) To: Andy Shevchenko Cc: Michael van der Westhuizen, linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala [-- Attachment #1: Type: text/plain, Size: 826 bytes --] On Mon, Jul 27, 2015 at 01:58:11PM +0300, Andy Shevchenko wrote: > On Fri, 2015-07-24 at 16:37 +0100, Mark Brown wrote: > > Please don't send content free pings, if you want me to review a > > patch > > please send me the patch. > Hmm… It's strange since patch series was sent to mailing list (Cc'ed to > you) on 24.06 [1]. > [1] > https://www.mail-archive.com/linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg05530.html > P.S. It has not mine authorship, though I can resend the series if > needed. It's possible there was some discussion of the patch that made it look it needed a resubmit, or that it was buried as reply in the middle of discussion of some other patches (eg, a previous version). Either way to repeat what I said if you want me to review a patch please send me the patch. [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 473 bytes --] ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-27 11:19 ` Mark Brown 0 siblings, 0 replies; 41+ messages in thread From: Mark Brown @ 2015-07-27 11:19 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jul 27, 2015 at 01:58:11PM +0300, Andy Shevchenko wrote: > On Fri, 2015-07-24 at 16:37 +0100, Mark Brown wrote: > > Please don't send content free pings, if you want me to review a > > patch > > please send me the patch. > Hmm? It's strange since patch series was sent to mailing list (Cc'ed to > you) on 24.06 [1]. > [1] > https://www.mail-archive.com/linux-spi at vger.kernel.org/msg05530.html > P.S. It has not mine authorship, though I can resend the series if > needed. It's possible there was some discussion of the patch that made it look it needed a resubmit, or that it was buried as reply in the middle of discussion of some other patches (eg, a previous version). Either way to repeat what I said if you want me to review a patch please send me the patch. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150727/bf80ac6f/attachment.sig> ^ permalink raw reply [flat|nested] 41+ messages in thread
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* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-07-27 11:19 ` Mark Brown @ 2015-07-27 11:38 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:38 UTC (permalink / raw) To: Mark Brown Cc: Andy Shevchenko, linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala Hi Mark, > On 27 Jul 2015, at 1:19 PM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: > > On Mon, Jul 27, 2015 at 01:58:11PM +0300, Andy Shevchenko wrote: >> On Fri, 2015-07-24 at 16:37 +0100, Mark Brown wrote: > >>> Please don't send content free pings, if you want me to review a >>> patch >>> please send me the patch. > >> Hmm… It's strange since patch series was sent to mailing list (Cc'ed to >> you) on 24.06 [1]. > >> [1] >> https://www.mail-archive.com/linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg05530.html > >> P.S. It has not mine authorship, though I can resend the series if >> needed. > > It's possible there was some discussion of the patch that made > it look it needed a resubmit, or that it was buried as reply in the > middle of discussion of some other patches (eg, a previous version). > Either way to repeat what I said if you want me to review a patch please > send me the patch. I’ve just resent the series. Michael -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-27 11:38 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:38 UTC (permalink / raw) To: linux-arm-kernel Hi Mark, > On 27 Jul 2015, at 1:19 PM, Mark Brown <broonie@kernel.org> wrote: > > On Mon, Jul 27, 2015 at 01:58:11PM +0300, Andy Shevchenko wrote: >> On Fri, 2015-07-24 at 16:37 +0100, Mark Brown wrote: > >>> Please don't send content free pings, if you want me to review a >>> patch >>> please send me the patch. > >> Hmm? It's strange since patch series was sent to mailing list (Cc'ed to >> you) on 24.06 [1]. > >> [1] >> https://www.mail-archive.com/linux-spi at vger.kernel.org/msg05530.html > >> P.S. It has not mine authorship, though I can resend the series if >> needed. > > It's possible there was some discussion of the patch that made > it look it needed a resubmit, or that it was buried as reply in the > middle of discussion of some other patches (eg, a previous version). > Either way to repeat what I said if you want me to review a patch please > send me the patch. I?ve just resent the series. Michael ^ permalink raw reply [flat|nested] 41+ messages in thread
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* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-07-27 11:38 ` Michael van der Westhuizen @ 2015-07-27 13:59 ` Mark Brown -1 siblings, 0 replies; 41+ messages in thread From: Mark Brown @ 2015-07-27 13:59 UTC (permalink / raw) To: Michael van der Westhuizen Cc: Andy Shevchenko, linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala [-- Attachment #1: Type: text/plain, Size: 819 bytes --] On Mon, Jul 27, 2015 at 01:38:57PM +0200, Michael van der Westhuizen wrote: > > It's possible there was some discussion of the patch that made > > it look it needed a resubmit, or that it was buried as reply in the > > middle of discussion of some other patches (eg, a previous version). > > Either way to repeat what I said if you want me to review a patch please > > send me the patch. > I’ve just resent the series. You've sent them as a reply in the middle of another thread which is something I just indicated above was a bad idea in the message you're replying to here (it's a great way to either make it hard to figure out what the current version of the code is or get your message deleted along with the rest of the thread) and you've decided to label them as [RESEND instead of [PATCH :( [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 473 bytes --] ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-27 13:59 ` Mark Brown 0 siblings, 0 replies; 41+ messages in thread From: Mark Brown @ 2015-07-27 13:59 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jul 27, 2015 at 01:38:57PM +0200, Michael van der Westhuizen wrote: > > It's possible there was some discussion of the patch that made > > it look it needed a resubmit, or that it was buried as reply in the > > middle of discussion of some other patches (eg, a previous version). > > Either way to repeat what I said if you want me to review a patch please > > send me the patch. > I?ve just resent the series. You've sent them as a reply in the middle of another thread which is something I just indicated above was a bad idea in the message you're replying to here (it's a great way to either make it hard to figure out what the current version of the code is or get your message deleted along with the rest of the thread) and you've decided to label them as [RESEND instead of [PATCH :( -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150727/b2e3ca89/attachment-0001.sig> ^ permalink raw reply [flat|nested] 41+ messages in thread
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* Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-07-27 13:59 ` Mark Brown @ 2015-08-18 10:29 ` Andy Shevchenko -1 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-08-18 10:29 UTC (permalink / raw) To: Mark Brown Cc: Michael van der Westhuizen, Andy Shevchenko, linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree, linux-arm Mailing List, Steffen Trumtrar, Thor Thayer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Mon, Jul 27, 2015 at 4:59 PM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: > On Mon, Jul 27, 2015 at 01:38:57PM +0200, Michael van der Westhuizen wrote: > >> > It's possible there was some discussion of the patch that made >> > it look it needed a resubmit, or that it was buried as reply in the >> > middle of discussion of some other patches (eg, a previous version). >> > Either way to repeat what I said if you want me to review a patch please >> > send me the patch. > >> I’ve just resent the series. > > You've sent them as a reply in the middle of another thread which is > something I just indicated above was a bad idea in the message you're > replying to here (it's a great way to either make it hard to figure out > what the current version of the code is or get your message deleted > along with the rest of the thread) and you've decided to label them as > [RESEND instead of [PATCH :( Michael, I believe you need to resend as a v3 in a separate thread if you aware of this code. (Though it seems already late for v4.3) -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-08-18 10:29 ` Andy Shevchenko 0 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-08-18 10:29 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jul 27, 2015 at 4:59 PM, Mark Brown <broonie@kernel.org> wrote: > On Mon, Jul 27, 2015 at 01:38:57PM +0200, Michael van der Westhuizen wrote: > >> > It's possible there was some discussion of the patch that made >> > it look it needed a resubmit, or that it was buried as reply in the >> > middle of discussion of some other patches (eg, a previous version). >> > Either way to repeat what I said if you want me to review a patch please >> > send me the patch. > >> I?ve just resent the series. > > You've sent them as a reply in the middle of another thread which is > something I just indicated above was a bad idea in the message you're > replying to here (it's a great way to either make it hard to figure out > what the current version of the code is or get your message deleted > along with the rest of the thread) and you've decided to label them as > [RESEND instead of [PATCH :( Michael, I believe you need to resend as a v3 in a separate thread if you aware of this code. (Though it seems already late for v4.3) -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O 2015-06-24 16:34 ` Michael van der Westhuizen @ 2015-07-27 11:37 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:37 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a boolean to the core spi-dw driver to indicate to the core that 16 bit data register access is appropriate, implements the code that respects that flag and updates the dw-spi-mmio driver to allow setting this boolean from the device tree. A binding documentation fix is included in this series. Prior to applying this change the following error presents on a picoCell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) (Resend requested by Mark Brown) Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice and adjusting the driver to suit. - Add a wrapper inline function for accessing the data register using the configured with. Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Document new I/O data register width property spi: dw: Allow interface drivers to limit data I/O to word sizes drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O @ 2015-07-27 11:37 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:37 UTC (permalink / raw) To: linux-arm-kernel The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a boolean to the core spi-dw driver to indicate to the core that 16 bit data register access is appropriate, implements the code that respects that flag and updates the dw-spi-mmio driver to allow setting this boolean from the device tree. A binding documentation fix is included in this series. Prior to applying this change the following error presents on a picoCell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) (Resend requested by Mark Brown) Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice and adjusting the driver to suit. - Add a wrapper inline function for accessing the data register using the configured with. Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Document new I/O data register width property spi: dw: Allow interface drivers to limit data I/O to word sizes drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) -- 2.1.4 ^ permalink raw reply [flat|nested] 41+ messages in thread
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* [RESEND PATCH v2 1/2] dt: snps,dw-apb-ssi: Document new I/O data register width property 2015-07-27 11:37 ` Michael van der Westhuizen @ 2015-07-27 11:37 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:37 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to specify either four byte or two bytes access to the SPI controller data register. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice. Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..b4f1086 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,8 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- snps,reg-io-width : The I/O register width (in bytes) implemented by + this device. Supported values are 2 or 4 (the default). Child nodes as per the generic SPI binding. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 1/2] dt: snps, dw-apb-ssi: Document new I/O data register width property @ 2015-07-27 11:37 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:37 UTC (permalink / raw) To: linux-arm-kernel This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to specify either four byte or two bytes access to the SPI controller data register. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice. Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..b4f1086 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,8 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- snps,reg-io-width : The I/O register width (in bytes) implemented by + this device. Supported values are 2 or 4 (the default). Child nodes as per the generic SPI binding. -- 2.1.4 ^ permalink raw reply related [flat|nested] 41+ messages in thread
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* Re: [RESEND PATCH v2 1/2] dt: snps,dw-apb-ssi: Document new I/O data register width property 2015-07-27 11:37 ` [RESEND PATCH v2 1/2] dt: snps, dw-apb-ssi: " Michael van der Westhuizen @ 2015-07-27 13:35 ` Rob Herring -1 siblings, 0 replies; 41+ messages in thread From: Rob Herring @ 2015-07-27 13:35 UTC (permalink / raw) To: Michael van der Westhuizen Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Mon, Jul 27, 2015 at 6:37 AM, Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> wrote: > This change documents a new property for the snps,dw-apb-ssi device, > allowing an implementer to specify either four byte or two bytes > access to the SPI controller data register. > > This supports a change that unbreaks this driver on picoXcell > platforms. > > Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> > --- > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko, reworking the > bindings to reflect common practice. > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > index bd99193..b4f1086 100644 > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > @@ -10,6 +10,8 @@ Required properties: > Optional properties: > - cs-gpios : Specifies the gpio pis to be used for chipselects. > - num-cs : The number of chipselects. If omitted, this will default to 4. > +- snps,reg-io-width : The I/O register width (in bytes) implemented by > + this device. Supported values are 2 or 4 (the default). Drop the snps as this is already a common property (at least for UARTs). Rob -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 1/2] dt: snps, dw-apb-ssi: Document new I/O data register width property @ 2015-07-27 13:35 ` Rob Herring 0 siblings, 0 replies; 41+ messages in thread From: Rob Herring @ 2015-07-27 13:35 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jul 27, 2015 at 6:37 AM, Michael van der Westhuizen <michael@smart-africa.com> wrote: > This change documents a new property for the snps,dw-apb-ssi device, > allowing an implementer to specify either four byte or two bytes > access to the SPI controller data register. > > This supports a change that unbreaks this driver on picoXcell > platforms. > > Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> > --- > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko, reworking the > bindings to reflect common practice. > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > index bd99193..b4f1086 100644 > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > @@ -10,6 +10,8 @@ Required properties: > Optional properties: > - cs-gpios : Specifies the gpio pis to be used for chipselects. > - num-cs : The number of chipselects. If omitted, this will default to 4. > +- snps,reg-io-width : The I/O register width (in bytes) implemented by > + this device. Supported values are 2 or 4 (the default). Drop the snps as this is already a common property (at least for UARTs). Rob ^ permalink raw reply [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-07-27 11:37 ` Michael van der Westhuizen @ 2015-07-27 11:37 ` Michael van der Westhuizen -1 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:37 UTC (permalink / raw) To: linux-spi-u79uwXL29TY76Z2rM5mHXA Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Michael van der Westhuizen The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko - Rework the DT bindings to accept an I/O register width as a number of bytes rather than using a boolean spefifying the width preference to be 16 bits. - Add data register access wrapper functions and use them when reading and writing the data register. drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..e76bf72 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + of_property_read_u32(pdev->dev.of_node, "snps,reg-io-width", + &dws->reg_io_width); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..4fbfcdc 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + dw_write_io_reg(dws, DW_SPI_DR, txw); dws->tx += dws->n_bytes; } } @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + rxw = dw_read_io_reg(dws, DW_SPI_DR); /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..b75ed32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + u32 reg_io_width; /* DR I/O width in bytes */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) +{ + switch (dws->reg_io_width) { + case 2: + return dw_readw(dws, offset); + case 4: + default: + return dw_readl(dws, offset); + } +} + +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) +{ + switch (dws->reg_io_width) { + case 2: + dw_writew(dws, offset, val); + break; + case 4: + default: + dw_writel(dws, offset, val); + break; + } +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes @ 2015-07-27 11:37 ` Michael van der Westhuizen 0 siblings, 0 replies; 41+ messages in thread From: Michael van der Westhuizen @ 2015-07-27 11:37 UTC (permalink / raw) To: linux-arm-kernel The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- Changes in v2: - Incorporate review feedback from Andy Shevchenko - Rework the DT bindings to accept an I/O register width as a number of bytes rather than using a boolean spefifying the width preference to be 16 bits. - Add data register access wrapper functions and use them when reading and writing the data register. drivers/spi/spi-dw-mmio.c | 4 ++++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..e76bf72 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + of_property_read_u32(pdev->dev.of_node, "snps,reg-io-width", + &dws->reg_io_width); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..4fbfcdc 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + dw_write_io_reg(dws, DW_SPI_DR, txw); dws->tx += dws->n_bytes; } } @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + rxw = dw_read_io_reg(dws, DW_SPI_DR); /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..b75ed32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + u32 reg_io_width; /* DR I/O width in bytes */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) +{ + switch (dws->reg_io_width) { + case 2: + return dw_readw(dws, offset); + case 4: + default: + return dw_readl(dws, offset); + } +} + +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) +{ + switch (dws->reg_io_width) { + case 2: + dw_writew(dws, offset, val); + break; + case 4: + default: + dw_writel(dws, offset, val); + break; + } +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); -- 2.1.4 ^ permalink raw reply related [flat|nested] 41+ messages in thread
[parent not found: <1437997035-3046-3-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org>]
* Re: [RESEND PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes 2015-07-27 11:37 ` Michael van der Westhuizen @ 2015-08-18 10:36 ` Andy Shevchenko -1 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-08-18 10:36 UTC (permalink / raw) To: Michael van der Westhuizen Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA, devicetree, linux-arm Mailing List, Steffen Trumtrar, Thor Thayer, Andy Shevchenko, Mark Brown, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Mon, Jul 27, 2015 at 2:37 PM, Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit > accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. > This, unfortunately, breaks data register access on picoXcell, where the > DW IP needs data register accesses to be word accesses (all other > accesses appear to be OK). > > This change introduces a new master variable to allow interface drivers > to specify that 16bit data transfer I/O is required. This change also > introduces the ability to set this variable via device tree bindings in > the MMIO interface driver. > > Before this change, on a picoXcell pc3x3: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > After this change: > m25p80 spi32766.0: m25p40 (512 Kbytes) > > Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") > Signed-off-by: Michael van der Westhuizen <michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> > Reviewed-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> One minor comment below. > --- > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko > - Rework the DT bindings to accept an I/O register width as a > number of bytes rather than using a boolean spefifying the > width preference to be 16 bits. > - Add data register access wrapper functions and use them when > reading and writing the data register. > > drivers/spi/spi-dw-mmio.c | 4 ++++ > drivers/spi/spi-dw.c | 4 ++-- > drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c > index eb03e12..e76bf72 100644 > --- a/drivers/spi/spi-dw-mmio.c > +++ b/drivers/spi/spi-dw-mmio.c > @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) > > dws->max_freq = clk_get_rate(dwsmmio->clk); > > + if (pdev->dev.of_node) of_property_read_u32() is NULL-aware. Since the option is optional we may drop the condition. > + of_property_read_u32(pdev->dev.of_node, "snps,reg-io-width", Like Rob said, drop 'snps,' prefix as it is a generic property name. > + &dws->reg_io_width); > + > num_cs = 4; > > if (pdev->dev.of_node) > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 8d67d03..4fbfcdc 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) > else > txw = *(u16 *)(dws->tx); > } > - dw_writel(dws, DW_SPI_DR, txw); > + dw_write_io_reg(dws, DW_SPI_DR, txw); > dws->tx += dws->n_bytes; > } > } > @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) > u16 rxw; > > while (max--) { > - rxw = dw_readl(dws, DW_SPI_DR); > + rxw = dw_read_io_reg(dws, DW_SPI_DR); > /* Care rx only if the transfer's original "rx" is not null */ > if (dws->rx_end - dws->len) { > if (dws->n_bytes == 1) > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index 6c91391..b75ed32 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -109,6 +109,7 @@ struct dw_spi { > u32 fifo_len; /* depth of the FIFO buffer */ > u32 max_freq; /* max bus freq supported */ > > + u32 reg_io_width; /* DR I/O width in bytes */ > u16 bus_num; > u16 num_cs; /* supported slave numbers */ > > @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) > return __raw_readl(dws->regs + offset); > } > > +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) > +{ > + return __raw_readw(dws->regs + offset); > +} > + > static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) > { > __raw_writel(val, dws->regs + offset); > } > > +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) > +{ > + __raw_writew(val, dws->regs + offset); > +} > + > +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) > +{ > + switch (dws->reg_io_width) { > + case 2: > + return dw_readw(dws, offset); > + case 4: > + default: > + return dw_readl(dws, offset); > + } > +} > + > +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) > +{ > + switch (dws->reg_io_width) { > + case 2: > + dw_writew(dws, offset, val); > + break; > + case 4: > + default: > + dw_writel(dws, offset, val); > + break; > + } > +} > + > static inline void spi_enable_chip(struct dw_spi *dws, int enable) > { > dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); > -- > 2.1.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-spi" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 41+ messages in thread
* [RESEND PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes @ 2015-08-18 10:36 ` Andy Shevchenko 0 siblings, 0 replies; 41+ messages in thread From: Andy Shevchenko @ 2015-08-18 10:36 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jul 27, 2015 at 2:37 PM, Michael van der Westhuizen <michael@smart-africa.com> wrote: > The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit > accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. > This, unfortunately, breaks data register access on picoXcell, where the > DW IP needs data register accesses to be word accesses (all other > accesses appear to be OK). > > This change introduces a new master variable to allow interface drivers > to specify that 16bit data transfer I/O is required. This change also > introduces the ability to set this variable via device tree bindings in > the MMIO interface driver. > > Before this change, on a picoXcell pc3x3: > spi_master spi32766: interrupt_transfer: fifo overrun/underrun > m25p80 spi32766.0: error -5 reading 9f > m25p80: probe of spi32766.0 failed with error -5 > > After this change: > m25p80 spi32766.0: m25p40 (512 Kbytes) > > Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") > Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> One minor comment below. > --- > > Changes in v2: > - Incorporate review feedback from Andy Shevchenko > - Rework the DT bindings to accept an I/O register width as a > number of bytes rather than using a boolean spefifying the > width preference to be 16 bits. > - Add data register access wrapper functions and use them when > reading and writing the data register. > > drivers/spi/spi-dw-mmio.c | 4 ++++ > drivers/spi/spi-dw.c | 4 ++-- > drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c > index eb03e12..e76bf72 100644 > --- a/drivers/spi/spi-dw-mmio.c > +++ b/drivers/spi/spi-dw-mmio.c > @@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) > > dws->max_freq = clk_get_rate(dwsmmio->clk); > > + if (pdev->dev.of_node) of_property_read_u32() is NULL-aware. Since the option is optional we may drop the condition. > + of_property_read_u32(pdev->dev.of_node, "snps,reg-io-width", Like Rob said, drop 'snps,' prefix as it is a generic property name. > + &dws->reg_io_width); > + > num_cs = 4; > > if (pdev->dev.of_node) > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 8d67d03..4fbfcdc 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) > else > txw = *(u16 *)(dws->tx); > } > - dw_writel(dws, DW_SPI_DR, txw); > + dw_write_io_reg(dws, DW_SPI_DR, txw); > dws->tx += dws->n_bytes; > } > } > @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) > u16 rxw; > > while (max--) { > - rxw = dw_readl(dws, DW_SPI_DR); > + rxw = dw_read_io_reg(dws, DW_SPI_DR); > /* Care rx only if the transfer's original "rx" is not null */ > if (dws->rx_end - dws->len) { > if (dws->n_bytes == 1) > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index 6c91391..b75ed32 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -109,6 +109,7 @@ struct dw_spi { > u32 fifo_len; /* depth of the FIFO buffer */ > u32 max_freq; /* max bus freq supported */ > > + u32 reg_io_width; /* DR I/O width in bytes */ > u16 bus_num; > u16 num_cs; /* supported slave numbers */ > > @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) > return __raw_readl(dws->regs + offset); > } > > +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) > +{ > + return __raw_readw(dws->regs + offset); > +} > + > static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) > { > __raw_writel(val, dws->regs + offset); > } > > +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) > +{ > + __raw_writew(val, dws->regs + offset); > +} > + > +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) > +{ > + switch (dws->reg_io_width) { > + case 2: > + return dw_readw(dws, offset); > + case 4: > + default: > + return dw_readl(dws, offset); > + } > +} > + > +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) > +{ > + switch (dws->reg_io_width) { > + case 2: > + dw_writew(dws, offset, val); > + break; > + case 4: > + default: > + dw_writel(dws, offset, val); > + break; > + } > +} > + > static inline void spi_enable_chip(struct dw_spi *dws, int enable) > { > dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); > -- > 2.1.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-spi" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2015-08-18 10:36 UTC | newest] Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-06-19 8:43 [PATCH 0/2] spi: dw: Reintroduce optional 16 bit data register I/O Michael van der Westhuizen 2015-06-19 8:43 ` Michael van der Westhuizen [not found] ` <1434703435-25198-1-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-06-19 8:43 ` [PATCH 2/2] dt: snps,dw-apb-ssi: Describe 16 bit data register usage limitations Michael van der Westhuizen 2015-06-19 8:43 ` [PATCH 2/2] dt: snps, dw-apb-ssi: " Michael van der Westhuizen 2015-06-19 8:43 ` [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes Michael van der Westhuizen 2015-06-19 8:43 ` Michael van der Westhuizen [not found] ` <1434703435-25198-3-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-06-24 11:57 ` Andy Shevchenko 2015-06-24 11:57 ` Andy Shevchenko 2015-06-24 16:11 ` Michael van der Westhuizen 2015-06-24 16:34 ` [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O Michael van der Westhuizen 2015-06-24 16:34 ` Michael van der Westhuizen [not found] ` <1435163696-14767-1-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-06-24 16:34 ` [PATCH v2 1/2] dt: snps,dw-apb-ssi: Document new I/O data register width property Michael van der Westhuizen 2015-06-24 16:34 ` [PATCH v2 1/2] dt: snps, dw-apb-ssi: " Michael van der Westhuizen 2015-06-24 16:34 ` [PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes Michael van der Westhuizen 2015-06-24 16:34 ` Michael van der Westhuizen [not found] ` <1435163696-14767-3-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-06-25 14:41 ` Andy Shevchenko 2015-06-25 14:41 ` Andy Shevchenko 2015-07-24 15:30 ` [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O Andy Shevchenko 2015-07-24 15:30 ` Andy Shevchenko [not found] ` <1437751812.29746.74.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2015-07-24 15:37 ` Mark Brown 2015-07-24 15:37 ` Mark Brown [not found] ` <20150724153704.GM11162-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2015-07-27 10:58 ` Andy Shevchenko 2015-07-27 10:58 ` Andy Shevchenko [not found] ` <1437994691.29746.80.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2015-07-27 11:19 ` Mark Brown 2015-07-27 11:19 ` Mark Brown [not found] ` <20150727111944.GW11162-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2015-07-27 11:38 ` Michael van der Westhuizen 2015-07-27 11:38 ` Michael van der Westhuizen [not found] ` <CCC70BC0-E1D0-4C27-A44D-2D16ED9B3049-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-07-27 13:59 ` Mark Brown 2015-07-27 13:59 ` Mark Brown [not found] ` <20150727135915.GY11162-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2015-08-18 10:29 ` Andy Shevchenko 2015-08-18 10:29 ` Andy Shevchenko 2015-07-27 11:37 ` [RESEND PATCH " Michael van der Westhuizen 2015-07-27 11:37 ` Michael van der Westhuizen [not found] ` <1437997035-3046-1-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-07-27 11:37 ` [RESEND PATCH v2 1/2] dt: snps,dw-apb-ssi: Document new I/O data register width property Michael van der Westhuizen 2015-07-27 11:37 ` [RESEND PATCH v2 1/2] dt: snps, dw-apb-ssi: " Michael van der Westhuizen [not found] ` <1437997035-3046-2-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-07-27 13:35 ` [RESEND PATCH v2 1/2] dt: snps,dw-apb-ssi: " Rob Herring 2015-07-27 13:35 ` [RESEND PATCH v2 1/2] dt: snps, dw-apb-ssi: " Rob Herring 2015-07-27 11:37 ` [RESEND PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes Michael van der Westhuizen 2015-07-27 11:37 ` Michael van der Westhuizen [not found] ` <1437997035-3046-3-git-send-email-michael-XrNoQAPr3WXM9gW82pYGhQ@public.gmane.org> 2015-08-18 10:36 ` Andy Shevchenko 2015-08-18 10:36 ` Andy Shevchenko
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