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From: Zhen Lei <thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
To: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
	Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>,
	linux-arm-kernel
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	iommu
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>
Cc: Xinwei Hu <huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
	Zhen Lei
	<thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
	Zefan Li <lizefan-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
	Tianhong Ding
	<dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Subject: [PATCH 4/8] iommu/arm-smmu: set EPD1 to disable TT1 translation table walk
Date: Fri, 26 Jun 2015 16:33:00 +0800	[thread overview]
Message-ID: <1435307584-9812-5-git-send-email-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <1435307584-9812-1-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>

Now we only use TT0 translation, disable TT1 translation will safer.

Signed-off-by: Zhen Lei <thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/iommu/arm-smmu-v3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 43120ad..6d6712e 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -285,6 +285,7 @@
 #define ARM64_TCR_EPD1_MASK		0x1UL

 #define CTXDESC_CD_0_ENDI		(1UL << 15)
+#define CTXDESC_CD_0_EPD1		(1UL << 30)
 #define CTXDESC_CD_0_V			(1UL << 31)

 #define CTXDESC_CD_0_TCR_IPS_SHIFT	32
@@ -893,7 +894,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
 #endif
 	      CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE |
 	      CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |
-	      CTXDESC_CD_0_V;
+	      CTXDESC_CD_0_EPD1 | CTXDESC_CD_0_V;
 	cfg->cdptr[0] = cpu_to_le64(val);

 	val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;
--
1.8.0

WARNING: multiple messages have this Message-ID (diff)
From: thunder.leizhen@huawei.com (Zhen Lei)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/8] iommu/arm-smmu: set EPD1 to disable TT1 translation table walk
Date: Fri, 26 Jun 2015 16:33:00 +0800	[thread overview]
Message-ID: <1435307584-9812-5-git-send-email-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <1435307584-9812-1-git-send-email-thunder.leizhen@huawei.com>

Now we only use TT0 translation, disable TT1 translation will safer.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 drivers/iommu/arm-smmu-v3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 43120ad..6d6712e 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -285,6 +285,7 @@
 #define ARM64_TCR_EPD1_MASK		0x1UL

 #define CTXDESC_CD_0_ENDI		(1UL << 15)
+#define CTXDESC_CD_0_EPD1		(1UL << 30)
 #define CTXDESC_CD_0_V			(1UL << 31)

 #define CTXDESC_CD_0_TCR_IPS_SHIFT	32
@@ -893,7 +894,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
 #endif
 	      CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE |
 	      CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |
-	      CTXDESC_CD_0_V;
+	      CTXDESC_CD_0_EPD1 | CTXDESC_CD_0_V;
 	cfg->cdptr[0] = cpu_to_le64(val);

 	val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;
--
1.8.0

  parent reply	other threads:[~2015-06-26  8:33 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-26  8:32 [PATCH 0/8] iommu/arm-smmu: bugfixs and add support for non-pci devices Zhen Lei
2015-06-26  8:32 ` Zhen Lei
     [not found] ` <1435307584-9812-1-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-26  8:32   ` [PATCH 1/8] iommu/arm-smmu: fix the assignment of log2size field Zhen Lei
2015-06-26  8:32     ` Zhen Lei
     [not found]     ` <1435307584-9812-2-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:05       ` Will Deacon
2015-06-29 17:05         ` Will Deacon
     [not found]         ` <20150629170517.GH17474-5wv7dgnIgG8@public.gmane.org>
2015-06-30  3:47           ` leizhen
2015-06-30  3:47             ` leizhen
2015-06-26  8:32   ` [PATCH 2/8] iommu/arm-smmu: fix the index calculation of strtab Zhen Lei
2015-06-26  8:32     ` Zhen Lei
     [not found]     ` <1435307584-9812-3-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:17       ` Will Deacon
2015-06-29 17:17         ` Will Deacon
2015-06-26  8:32   ` [PATCH 3/8] iommu/arm-smmu: fix the values of ARM64_TCR_IRGN0_SHIFT and ARM64_TCR_ORGN0_SHIFT Zhen Lei
2015-06-26  8:32     ` Zhen Lei
     [not found]     ` <1435307584-9812-4-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:25       ` Will Deacon
2015-06-29 17:25         ` Will Deacon
     [not found]         ` <20150629172531.GJ17474-5wv7dgnIgG8@public.gmane.org>
2015-06-30  3:57           ` leizhen
2015-06-30  3:57             ` leizhen
     [not found]             ` <559213AE.6060206-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-30 14:11               ` Will Deacon
2015-06-30 14:11                 ` Will Deacon
2015-06-26  8:33   ` Zhen Lei [this message]
2015-06-26  8:33     ` [PATCH 4/8] iommu/arm-smmu: set EPD1 to disable TT1 translation table walk Zhen Lei
     [not found]     ` <1435307584-9812-5-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:26       ` Will Deacon
2015-06-29 17:26         ` Will Deacon
     [not found]         ` <20150629172622.GK17474-5wv7dgnIgG8@public.gmane.org>
2015-06-30  4:40           ` leizhen
2015-06-30  4:40             ` leizhen
2015-06-26  8:33   ` [PATCH 5/8] iommu/arm-smmu: rename __arm_smmu_get_pci_sid Zhen Lei
2015-06-26  8:33     ` Zhen Lei
2015-06-26  8:33   ` [PATCH 6/8] iommu/arm-smmu: add support for non-pci devices Zhen Lei
2015-06-26  8:33     ` Zhen Lei
     [not found]     ` <1435307584-9812-7-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:28       ` Will Deacon
2015-06-29 17:28         ` Will Deacon
     [not found]         ` <20150629172831.GL17474-5wv7dgnIgG8@public.gmane.org>
2015-06-30  8:51           ` leizhen
2015-06-30  8:51             ` leizhen
2015-06-30 11:26       ` Robin Murphy
2015-06-30 11:26         ` Robin Murphy
     [not found]         ` <55927CEC.4090900-5wv7dgnIgG8@public.gmane.org>
2015-07-01  2:16           ` leizhen
2015-07-01  2:16             ` leizhen
2015-06-26  8:33   ` [PATCH 7/8] iommu/arm-smmu: enlarge STRTAB_L1_SZ_SHIFT to support larger sidsize Zhen Lei
2015-06-26  8:33     ` Zhen Lei
     [not found]     ` <1435307584-9812-8-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:35       ` Will Deacon
2015-06-29 17:35         ` Will Deacon
     [not found]         ` <20150629173539.GM17474-5wv7dgnIgG8@public.gmane.org>
2015-06-30  8:57           ` leizhen
2015-06-30  8:57             ` leizhen
2015-06-26  8:33   ` [PATCH 8/8] iommu/arm-smmu: suppress fault information about CMD_PREFETCH_CONFIG execution Zhen Lei
2015-06-26  8:33     ` Zhen Lei
     [not found]     ` <1435307584-9812-9-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-06-29 17:49       ` Will Deacon
2015-06-29 17:49         ` Will Deacon
     [not found]         ` <20150629174909.GN17474-5wv7dgnIgG8@public.gmane.org>
2015-06-30  9:18           ` leizhen
2015-06-30  9:18             ` leizhen

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