From: leizhen <thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> To: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> Cc: "huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org" <huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>, iommu <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Zefan Li <lizefan-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>, Tianhong Ding <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>, linux-arm-kernel <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> Subject: Re: [PATCH 3/8] iommu/arm-smmu: fix the values of ARM64_TCR_IRGN0_SHIFT and ARM64_TCR_ORGN0_SHIFT Date: Tue, 30 Jun 2015 11:57:34 +0800 [thread overview] Message-ID: <559213AE.6060206@huawei.com> (raw) In-Reply-To: <20150629172531.GJ17474-5wv7dgnIgG8@public.gmane.org> On 2015/6/30 1:25, Will Deacon wrote: > On Fri, Jun 26, 2015 at 09:32:59AM +0100, Zhen Lei wrote: >> In context descriptor, the offset of IR0 is 8, the offset of OR0 is 10. >> >> Signed-off-by: Zhen Lei <thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> >> --- >> drivers/iommu/arm-smmu-v3.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c >> index 2a5f810..43120ad 100644 >> --- a/drivers/iommu/arm-smmu-v3.c >> +++ b/drivers/iommu/arm-smmu-v3.c >> @@ -269,10 +269,10 @@ >> #define ARM64_TCR_TG0_SHIFT 14 >> #define ARM64_TCR_TG0_MASK 0x3UL >> #define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8 >> -#define ARM64_TCR_IRGN0_SHIFT 24 >> +#define ARM64_TCR_IRGN0_SHIFT 8 >> #define ARM64_TCR_IRGN0_MASK 0x3UL >> #define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10 >> -#define ARM64_TCR_ORGN0_SHIFT 26 >> +#define ARM64_TCR_ORGN0_SHIFT 10 >> #define ARM64_TCR_ORGN0_MASK 0x3UL >> #define CTXDESC_CD_0_TCR_SH0_SHIFT 12 >> #define ARM64_TCR_SH0_SHIFT 12 > > I don't understand this patch. > > The ARM64_* definitions correspond to the CPU architecture, whilst the > CTXDESC_* definitions correspond to the SMMUv3 CD description. > > What problem are you seeing? Oh, I'm sorry. My description was incorrect. In io-pgtable-arm.c: #define ARM_LPAE_TCR_ORGN0_SHIFT 10 #define ARM_LPAE_TCR_IRGN0_SHIFT 8 So, the description should be modified as below: In SMMU_CBn_TCR when LPAE enabled, the offset of IRGN0 is 8, the offset of ORGN0 is 10. > > Will > > . >
WARNING: multiple messages have this Message-ID (diff)
From: thunder.leizhen@huawei.com (leizhen) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/8] iommu/arm-smmu: fix the values of ARM64_TCR_IRGN0_SHIFT and ARM64_TCR_ORGN0_SHIFT Date: Tue, 30 Jun 2015 11:57:34 +0800 [thread overview] Message-ID: <559213AE.6060206@huawei.com> (raw) In-Reply-To: <20150629172531.GJ17474@arm.com> On 2015/6/30 1:25, Will Deacon wrote: > On Fri, Jun 26, 2015 at 09:32:59AM +0100, Zhen Lei wrote: >> In context descriptor, the offset of IR0 is 8, the offset of OR0 is 10. >> >> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> >> --- >> drivers/iommu/arm-smmu-v3.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c >> index 2a5f810..43120ad 100644 >> --- a/drivers/iommu/arm-smmu-v3.c >> +++ b/drivers/iommu/arm-smmu-v3.c >> @@ -269,10 +269,10 @@ >> #define ARM64_TCR_TG0_SHIFT 14 >> #define ARM64_TCR_TG0_MASK 0x3UL >> #define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8 >> -#define ARM64_TCR_IRGN0_SHIFT 24 >> +#define ARM64_TCR_IRGN0_SHIFT 8 >> #define ARM64_TCR_IRGN0_MASK 0x3UL >> #define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10 >> -#define ARM64_TCR_ORGN0_SHIFT 26 >> +#define ARM64_TCR_ORGN0_SHIFT 10 >> #define ARM64_TCR_ORGN0_MASK 0x3UL >> #define CTXDESC_CD_0_TCR_SH0_SHIFT 12 >> #define ARM64_TCR_SH0_SHIFT 12 > > I don't understand this patch. > > The ARM64_* definitions correspond to the CPU architecture, whilst the > CTXDESC_* definitions correspond to the SMMUv3 CD description. > > What problem are you seeing? Oh, I'm sorry. My description was incorrect. In io-pgtable-arm.c: #define ARM_LPAE_TCR_ORGN0_SHIFT 10 #define ARM_LPAE_TCR_IRGN0_SHIFT 8 So, the description should be modified as below: In SMMU_CBn_TCR when LPAE enabled, the offset of IRGN0 is 8, the offset of ORGN0 is 10. > > Will > > . >
next prev parent reply other threads:[~2015-06-30 3:57 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-26 8:32 [PATCH 0/8] iommu/arm-smmu: bugfixs and add support for non-pci devices Zhen Lei 2015-06-26 8:32 ` Zhen Lei [not found] ` <1435307584-9812-1-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-26 8:32 ` [PATCH 1/8] iommu/arm-smmu: fix the assignment of log2size field Zhen Lei 2015-06-26 8:32 ` Zhen Lei [not found] ` <1435307584-9812-2-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:05 ` Will Deacon 2015-06-29 17:05 ` Will Deacon [not found] ` <20150629170517.GH17474-5wv7dgnIgG8@public.gmane.org> 2015-06-30 3:47 ` leizhen 2015-06-30 3:47 ` leizhen 2015-06-26 8:32 ` [PATCH 2/8] iommu/arm-smmu: fix the index calculation of strtab Zhen Lei 2015-06-26 8:32 ` Zhen Lei [not found] ` <1435307584-9812-3-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:17 ` Will Deacon 2015-06-29 17:17 ` Will Deacon 2015-06-26 8:32 ` [PATCH 3/8] iommu/arm-smmu: fix the values of ARM64_TCR_IRGN0_SHIFT and ARM64_TCR_ORGN0_SHIFT Zhen Lei 2015-06-26 8:32 ` Zhen Lei [not found] ` <1435307584-9812-4-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:25 ` Will Deacon 2015-06-29 17:25 ` Will Deacon [not found] ` <20150629172531.GJ17474-5wv7dgnIgG8@public.gmane.org> 2015-06-30 3:57 ` leizhen [this message] 2015-06-30 3:57 ` leizhen [not found] ` <559213AE.6060206-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-30 14:11 ` Will Deacon 2015-06-30 14:11 ` Will Deacon 2015-06-26 8:33 ` [PATCH 4/8] iommu/arm-smmu: set EPD1 to disable TT1 translation table walk Zhen Lei 2015-06-26 8:33 ` Zhen Lei [not found] ` <1435307584-9812-5-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:26 ` Will Deacon 2015-06-29 17:26 ` Will Deacon [not found] ` <20150629172622.GK17474-5wv7dgnIgG8@public.gmane.org> 2015-06-30 4:40 ` leizhen 2015-06-30 4:40 ` leizhen 2015-06-26 8:33 ` [PATCH 5/8] iommu/arm-smmu: rename __arm_smmu_get_pci_sid Zhen Lei 2015-06-26 8:33 ` Zhen Lei 2015-06-26 8:33 ` [PATCH 6/8] iommu/arm-smmu: add support for non-pci devices Zhen Lei 2015-06-26 8:33 ` Zhen Lei [not found] ` <1435307584-9812-7-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:28 ` Will Deacon 2015-06-29 17:28 ` Will Deacon [not found] ` <20150629172831.GL17474-5wv7dgnIgG8@public.gmane.org> 2015-06-30 8:51 ` leizhen 2015-06-30 8:51 ` leizhen 2015-06-30 11:26 ` Robin Murphy 2015-06-30 11:26 ` Robin Murphy [not found] ` <55927CEC.4090900-5wv7dgnIgG8@public.gmane.org> 2015-07-01 2:16 ` leizhen 2015-07-01 2:16 ` leizhen 2015-06-26 8:33 ` [PATCH 7/8] iommu/arm-smmu: enlarge STRTAB_L1_SZ_SHIFT to support larger sidsize Zhen Lei 2015-06-26 8:33 ` Zhen Lei [not found] ` <1435307584-9812-8-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:35 ` Will Deacon 2015-06-29 17:35 ` Will Deacon [not found] ` <20150629173539.GM17474-5wv7dgnIgG8@public.gmane.org> 2015-06-30 8:57 ` leizhen 2015-06-30 8:57 ` leizhen 2015-06-26 8:33 ` [PATCH 8/8] iommu/arm-smmu: suppress fault information about CMD_PREFETCH_CONFIG execution Zhen Lei 2015-06-26 8:33 ` Zhen Lei [not found] ` <1435307584-9812-9-git-send-email-thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2015-06-29 17:49 ` Will Deacon 2015-06-29 17:49 ` Will Deacon [not found] ` <20150629174909.GN17474-5wv7dgnIgG8@public.gmane.org> 2015-06-30 9:18 ` leizhen 2015-06-30 9:18 ` leizhen
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