Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations

[Tim Chen <tim.c.chen@linux.intel.com>]

On Thu, 2015-08-20 at 22:02 +0200, Thomas Gleixner wrote:
> On Thu, 20 Aug 2015, Tim Chen wrote:
> > From: Tim Chen <tim.c.chen@linux.intel.com>
> > Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
> 
>    sha: is not a proper subsystem name
> 
>    x86/cpufeatures: is the correct one
> 
> >  Enable cpuid check for Intel SHA extensions implementations
> 
> This patch does not enable any checks. It merily adds the feature bit.
>  
> > The Intel Secure Hash Algorithm Extensions are designed to improve the performance
> > of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit.
> 
> Again there is no check.
> 
> > This will allow the feature to be shown in the /proc/cpuinfo.
> > 
> > The SHA extension programming guide is found in chapter 8 of the Intel
> > Architecture Instruction Set Extensions Programming reference:
> > https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
> > 
> > Originally-by: Chandramouli Narayanan <mouli@linux.intel.com>
> 
> So Mouli left the company. What's the point of having his Intel mail
> address here and in the Cc list?

Thomas,

Thanks for your input.  Hopefully the attached patch below
addresses issues you've raised.  Mouli was copied on his new 
email address too. 

Tim

--->8---
From: Tim Chen <tim.c.chen@linux.intel.com>
Subject: [PATCH] x86/cpufeatures: Enable cpuid for Intel SHA extensions

Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature
provides new instructions for accelerated computation of SHA-1 and SHA-256.
This allows the feature to be shown in the /proc/cpuinfo for cpus that
support it.

Refer to SHA extension programming guide in chapter 8.2 of the Intel
Architecture Instruction Set Extensions Programming reference
for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf

Originally-by: Chandramouli Narayanan <mouli_7982@yahoo.com>
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..a94f83d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -239,6 +239,7 @@
 #define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
 #define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
 #define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
 
 /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
 #define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
-- 
1.8.3.1