* [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations @ 2015-08-17 20:44 Tim Chen 2015-08-17 21:19 ` Dave Hansen 0 siblings, 1 reply; 10+ messages in thread From: Tim Chen @ 2015-08-17 20:44 UTC (permalink / raw) To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin Cc: Herbert Xu, Chandramouli Narayanan, x86, linux-kernel The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. The SHA extension guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Signed-off-by: Chandramouli Narayanan <mouli@linux.intel.com> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> --- arch/x86/include/asm/cpufeature.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..7f85580 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) #if __GNUC__ >= 4 extern void warn_pre_alternatives(void); -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-17 20:44 [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations Tim Chen @ 2015-08-17 21:19 ` Dave Hansen 2015-08-17 22:33 ` Tim Chen 0 siblings, 1 reply; 10+ messages in thread From: Dave Hansen @ 2015-08-17 21:19 UTC (permalink / raw) To: Tim Chen, Thomas Gleixner, Ingo Molnar, H. Peter Anvin Cc: Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, Borislav Petkov On 08/17/2015 01:44 PM, Tim Chen wrote: > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) > #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) > #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) > +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) I think we're trying not to add these cpu_has_* macros any more. For MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. In the patch description, it might also be nice to remind folks that this will feature will also show up as "sha_ni" in /proc/cpuinfo. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-17 21:19 ` Dave Hansen @ 2015-08-17 22:33 ` Tim Chen 2015-08-18 16:46 ` Thomas Gleixner 0 siblings, 1 reply; 10+ messages in thread From: Tim Chen @ 2015-08-17 22:33 UTC (permalink / raw) To: Dave Hansen Cc: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, Borislav Petkov, mouli_7982 On Mon, 2015-08-17 at 14:19 -0700, Dave Hansen wrote: > On 08/17/2015 01:44 PM, Tim Chen wrote: > > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > > #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) > > #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) > > #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) > > +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) > > I think we're trying not to add these cpu_has_* macros any more. For > MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. > > In the patch description, it might also be nice to remind folks that > this will feature will also show up as "sha_ni" in /proc/cpuinfo. Okay, in that case, I've modified the patch to below: Tim --->8--- Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, H. Peter Anvin <hpa@zytor.com> Cc: Herbert Xu <herbert@gondor.apana.org.au>, Chandramouli Narayanan <mouli@linux.intel.com>, x86@kernel.org, linux-kernel@vger.kernel.org The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown as sha_ni in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Signed-off-by: Chandramouli Narayanan <mouli@linux.intel.com> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-17 22:33 ` Tim Chen @ 2015-08-18 16:46 ` Thomas Gleixner 2015-08-19 16:49 ` Tim Chen 0 siblings, 1 reply; 10+ messages in thread From: Thomas Gleixner @ 2015-08-18 16:46 UTC (permalink / raw) To: Tim Chen Cc: Dave Hansen, Ingo Molnar, H. Peter Anvin, Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, Borislav Petkov, mouli_7982 On Mon, 17 Aug 2015, Tim Chen wrote: > Signed-off-by: Chandramouli Narayanan <mouli@linux.intel.com> > Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> And now the question who authored this complex one liner .... > --- > arch/x86/include/asm/cpufeature.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > index 3d6606f..a94f83d 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -239,6 +239,7 @@ > #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ > #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ > #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ > +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ > > /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ > #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ > -- > 1.8.3.1 > > > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-18 16:46 ` Thomas Gleixner @ 2015-08-19 16:49 ` Tim Chen 2015-08-20 4:08 ` Borislav Petkov 0 siblings, 1 reply; 10+ messages in thread From: Tim Chen @ 2015-08-19 16:49 UTC (permalink / raw) To: Thomas Gleixner Cc: Dave Hansen, Ingo Molnar, H. Peter Anvin, Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, Borislav Petkov, mouli_7982 On Tue, 2015-08-18 at 18:46 +0200, Thomas Gleixner wrote: > On Mon, 17 Aug 2015, Tim Chen wrote: > > Signed-off-by: Chandramouli Narayanan <mouli@linux.intel.com> > > Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> > > And now the question who authored this complex one liner .... > Mouli did the patch originally but he left the company. So I'm picking it up. Tim > > --- > > arch/x86/include/asm/cpufeature.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > > index 3d6606f..a94f83d 100644 > > --- a/arch/x86/include/asm/cpufeature.h > > +++ b/arch/x86/include/asm/cpufeature.h > > @@ -239,6 +239,7 @@ > > #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ > > #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ > > #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ > > +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ > > > > /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ > > #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ > > -- > > 1.8.3.1 > > > > > > > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-19 16:49 ` Tim Chen @ 2015-08-20 4:08 ` Borislav Petkov 2015-08-20 15:03 ` Tim Chen 0 siblings, 1 reply; 10+ messages in thread From: Borislav Petkov @ 2015-08-20 4:08 UTC (permalink / raw) To: Tim Chen Cc: Thomas Gleixner, Dave Hansen, Ingo Molnar, H. Peter Anvin, Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, Borislav Petkov, mouli_7982 On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote: > On Tue, 2015-08-18 at 18:46 +0200, Thomas Gleixner wrote: > > On Mon, 17 Aug 2015, Tim Chen wrote: > > > Signed-off-by: Chandramouli Narayanan <mouli@linux.intel.com> > > > Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> > > > > And now the question who authored this complex one liner .... > > > > Mouli did the patch originally but he left the company. So > I'm picking it up. So the SOB chain should be: From: you <commit message> Originally-by: Mouli Signed-off-by: you -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) -- ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-20 4:08 ` Borislav Petkov @ 2015-08-20 15:03 ` Tim Chen 2015-08-20 20:02 ` Thomas Gleixner 0 siblings, 1 reply; 10+ messages in thread From: Tim Chen @ 2015-08-20 15:03 UTC (permalink / raw) To: Borislav Petkov Cc: Thomas Gleixner, Dave Hansen, Ingo Molnar, H. Peter Anvin, Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, mouli_7982 On Thu, 2015-08-20 at 06:08 +0200, Borislav Petkov wrote: > On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote: > > Mouli did the patch originally but he left the company. So > > I'm picking it up. > > So the SOB chain should be: > > From: you > > <commit message> > > Originally-by: Mouli > Signed-off-by: you > Thanks. Revised patch embedded below. Tim --->8--- From: Tim Chen <tim.c.chen@linux.intel.com> Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan <mouli@linux.intel.com> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-20 15:03 ` Tim Chen @ 2015-08-20 20:02 ` Thomas Gleixner 2015-08-21 21:56 ` Tim Chen 0 siblings, 1 reply; 10+ messages in thread From: Thomas Gleixner @ 2015-08-20 20:02 UTC (permalink / raw) To: Tim Chen Cc: Borislav Petkov, Dave Hansen, Ingo Molnar, H. Peter Anvin, Herbert Xu, Chandramouli Narayanan, x86, linux-kernel, mouli_7982 On Thu, 20 Aug 2015, Tim Chen wrote: > From: Tim Chen <tim.c.chen@linux.intel.com> > Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations sha: is not a proper subsystem name x86/cpufeatures: is the correct one > Enable cpuid check for Intel SHA extensions implementations This patch does not enable any checks. It merily adds the feature bit. > The Intel Secure Hash Algorithm Extensions are designed to improve the performance > of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. Again there is no check. > This will allow the feature to be shown in the /proc/cpuinfo. > > The SHA extension programming guide is found in chapter 8 of the Intel > Architecture Instruction Set Extensions Programming reference: > https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf > > Originally-by: Chandramouli Narayanan <mouli@linux.intel.com> So Mouli left the company. What's the point of having his Intel mail address here and in the Cc list? Thanks, tglx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations 2015-08-20 20:02 ` Thomas Gleixner @ 2015-08-21 21:56 ` Tim Chen 2015-08-22 9:21 ` [tip:x86/cpufeature] x86/cpufeatures: Enable cpuid for Intel SHA extensions tip-bot for Tim Chen 0 siblings, 1 reply; 10+ messages in thread From: Tim Chen @ 2015-08-21 21:56 UTC (permalink / raw) To: Thomas Gleixner Cc: Borislav Petkov, Dave Hansen, Ingo Molnar, H. Peter Anvin, Herbert Xu, x86, linux-kernel, Chandramouli Narayanan On Thu, 2015-08-20 at 22:02 +0200, Thomas Gleixner wrote: > On Thu, 20 Aug 2015, Tim Chen wrote: > > From: Tim Chen <tim.c.chen@linux.intel.com> > > Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations > > sha: is not a proper subsystem name > > x86/cpufeatures: is the correct one > > > Enable cpuid check for Intel SHA extensions implementations > > This patch does not enable any checks. It merily adds the feature bit. > > > The Intel Secure Hash Algorithm Extensions are designed to improve the performance > > of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. > > Again there is no check. > > > This will allow the feature to be shown in the /proc/cpuinfo. > > > > The SHA extension programming guide is found in chapter 8 of the Intel > > Architecture Instruction Set Extensions Programming reference: > > https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf > > > > Originally-by: Chandramouli Narayanan <mouli@linux.intel.com> > > So Mouli left the company. What's the point of having his Intel mail > address here and in the Cc list? Thomas, Thanks for your input. Hopefully the attached patch below addresses issues you've raised. Mouli was copied on his new email address too. Tim --->8--- From: Tim Chen <tim.c.chen@linux.intel.com> Subject: [PATCH] x86/cpufeatures: Enable cpuid for Intel SHA extensions Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature provides new instructions for accelerated computation of SHA-1 and SHA-256. This allows the feature to be shown in the /proc/cpuinfo for cpus that support it. Refer to SHA extension programming guide in chapter 8.2 of the Intel Architecture Instruction Set Extensions Programming reference for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1 https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan <mouli_7982@yahoo.com> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [tip:x86/cpufeature] x86/cpufeatures: Enable cpuid for Intel SHA extensions 2015-08-21 21:56 ` Tim Chen @ 2015-08-22 9:21 ` tip-bot for Tim Chen 0 siblings, 0 replies; 10+ messages in thread From: tip-bot for Tim Chen @ 2015-08-22 9:21 UTC (permalink / raw) To: linux-tip-commits Cc: herbert, bp, dave.hansen, mingo, tglx, mouli_7982, tim.c.chen, linux-kernel, hpa Commit-ID: 488ca7d72d974e3c00ae73ed9f947590680bdf00 Gitweb: http://git.kernel.org/tip/488ca7d72d974e3c00ae73ed9f947590680bdf00 Author: Tim Chen <tim.c.chen@linux.intel.com> AuthorDate: Fri, 21 Aug 2015 14:56:46 -0700 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sat, 22 Aug 2015 11:17:31 +0200 x86/cpufeatures: Enable cpuid for Intel SHA extensions Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature provides new instructions for accelerated computation of SHA-1 and SHA-256. This allows the feature to be shown in the /proc/cpuinfo for cpus that support it. Refer to SHA extension programming guide in chapter 8.2 of the Intel Architecture Instruction Set Extensions Programming reference for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1 https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan <mouli_7982@yahoo.com> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Cc: Borislav Petkov <bp@suse.de> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Link: http://lkml.kernel.org/r/1440194206.3940.6.camel@schen9-mobl2 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-08-22 9:21 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-08-17 20:44 [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations Tim Chen 2015-08-17 21:19 ` Dave Hansen 2015-08-17 22:33 ` Tim Chen 2015-08-18 16:46 ` Thomas Gleixner 2015-08-19 16:49 ` Tim Chen 2015-08-20 4:08 ` Borislav Petkov 2015-08-20 15:03 ` Tim Chen 2015-08-20 20:02 ` Thomas Gleixner 2015-08-21 21:56 ` Tim Chen 2015-08-22 9:21 ` [tip:x86/cpufeature] x86/cpufeatures: Enable cpuid for Intel SHA extensions tip-bot for Tim Chen
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