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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, proljc@gmail.com
Subject: [Qemu-devel] [PATCH 00/17] target-openrisc improvements
Date: Wed,  2 Sep 2015 17:17:26 -0700	[thread overview]
Message-ID: <1441239463-18981-1-git-send-email-rth@twiddle.net> (raw)

This is a refresh of a branch I worked on in February, but I don't
believe was ever posted.  I'm doing so now in order to flush my set
of uncommitted branches.

The openrisc target is in terrible shape and, as far as I can tell
from the opencores mailing list, no one uses it.  The fact that it's
missing so many of the instructions in the ISA, so many that we
cannot execute the musl libc, is proof of that.

This patch set should probably be reviewed and merged, or we should
drop the whole target.


r~


Richard Henderson (17):
  target-openrisc: Always enable OPENRISC_DISAS
  target-openrisc: Streamline arithmetic and OVE
  target-openrisc: Invert the decoding in dec_calc
  target-openrisc: Keep SR_F in a separate variable
  target-openrisc: Use movcond where appropriate
  target-openrisc: Put SR[OVE] in TB flags
  target-openrisc: Keep SR_CY and SR_OV in a separate variables
  target-openrisc: Set flags on helpers
  target-openrisc: Implement ff1 and fl1 for 64-bit
  target-openrisc: Represent MACHI:MACLO as a single unit
  target-openrisc: Rationalize immediate extraction
  target-openrisc: Enable m[tf]spr from user mode
  target-openrisc: Enable trap, csync, msync, psync for user mode
  target-openrisc: Implement muld, muldu, macu, msbu
  target-openrisc: Fix madd
  target-openrisc: Write back result before FPE exception
  target-openrisc: Implement lwa, swa

 linux-user/main.c                  |   45 ++
 target-openrisc/cpu.c              |    1 +
 target-openrisc/cpu.h              |   41 +-
 target-openrisc/exception_helper.c |   31 +
 target-openrisc/fpu_helper.c       |  286 ++-----
 target-openrisc/gdbstub.c          |    4 +-
 target-openrisc/helper.h           |   42 +-
 target-openrisc/int_helper.c       |   57 +-
 target-openrisc/interrupt.c        |    3 +-
 target-openrisc/interrupt_helper.c |    3 +-
 target-openrisc/mmu.c              |    1 +
 target-openrisc/sys_helper.c       |   69 +-
 target-openrisc/translate.c        | 1443 ++++++++++++++++--------------------
 13 files changed, 883 insertions(+), 1143 deletions(-)

-- 
2.4.3

             reply	other threads:[~2015-09-03  0:17 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-03  0:17 Richard Henderson [this message]
2015-09-03  0:17 ` [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS Richard Henderson
2015-09-03 14:15   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE Richard Henderson
2015-09-03 14:16   ` Bastian Koppelmann
2015-09-03 14:44     ` Richard Henderson
2015-09-04 13:12       ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc Richard Henderson
2015-09-03 14:48   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable Richard Henderson
2015-09-03 15:09   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate Richard Henderson
2015-09-03 16:04   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags Richard Henderson
2015-09-04 13:05   ` Bastian Koppelmann
2015-09-04 14:29     ` Richard Henderson
2015-09-03  0:17 ` [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2015-09-04 13:33   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers Richard Henderson
2015-09-04 13:58   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit Richard Henderson
2015-09-04 13:59   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2015-09-04 15:04   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction Richard Henderson
2015-09-04 15:24   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode Richard Henderson
2015-09-05 21:35   ` Bastian Koppelmann
2015-09-06 20:36     ` Richard Henderson
2015-09-13  8:34       ` Bastian Koppelmann
2015-09-14 17:11         ` Richard Henderson
2015-09-15  7:22           ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for " Richard Henderson
2015-09-06  9:30   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2015-09-06 11:38   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd Richard Henderson
2015-09-13  8:21   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception Richard Henderson
2015-09-15 13:02   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa Richard Henderson
2015-09-15 13:04   ` Bastian Koppelmann

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