From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, proljc@gmail.com
Subject: [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception
Date: Wed, 2 Sep 2015 17:17:42 -0700 [thread overview]
Message-ID: <1441239463-18981-17-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1441239463-18981-1-git-send-email-rth@twiddle.net>
The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in half, with the exception raised by the second.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-openrisc/fpu_helper.c | 252 +++++++++----------------------------------
target-openrisc/helper.h | 25 +++--
target-openrisc/translate.c | 118 +++++++++++---------
3 files changed, 129 insertions(+), 266 deletions(-)
diff --git a/target-openrisc/fpu_helper.c b/target-openrisc/fpu_helper.c
index d612012..05b1077 100644
--- a/target-openrisc/fpu_helper.c
+++ b/target-openrisc/fpu_helper.c
@@ -22,121 +22,70 @@
#include "exec/helper-proto.h"
#include "exception.h"
-static inline uint32_t ieee_ex_to_openrisc(OpenRISCCPU *cpu, int fexcp)
+static int ieee_ex_to_openrisc(int fexcp)
{
int ret = 0;
- if (fexcp) {
- if (fexcp & float_flag_invalid) {
- cpu->env.fpcsr |= FPCSR_IVF;
- ret = 1;
- }
- if (fexcp & float_flag_overflow) {
- cpu->env.fpcsr |= FPCSR_OVF;
- ret = 1;
- }
- if (fexcp & float_flag_underflow) {
- cpu->env.fpcsr |= FPCSR_UNF;
- ret = 1;
- }
- if (fexcp & float_flag_divbyzero) {
- cpu->env.fpcsr |= FPCSR_DZF;
- ret = 1;
- }
- if (fexcp & float_flag_inexact) {
- cpu->env.fpcsr |= FPCSR_IXF;
- ret = 1;
- }
+ if (fexcp & float_flag_invalid) {
+ ret |= FPCSR_IVF;
+ }
+ if (fexcp & float_flag_overflow) {
+ ret |= FPCSR_OVF;
+ }
+ if (fexcp & float_flag_underflow) {
+ ret |= FPCSR_UNF;
+ }
+ if (fexcp & float_flag_divbyzero) {
+ ret |= FPCSR_DZF;
+ }
+ if (fexcp & float_flag_inexact) {
+ ret |= FPCSR_IXF;
}
-
return ret;
}
-static inline void update_fpcsr(OpenRISCCPU *cpu)
+void HELPER(update_fpcsr)(CPUOpenRISCState *env)
{
- int tmp = ieee_ex_to_openrisc(cpu,
- get_float_exception_flags(&cpu->env.fp_status));
-
- SET_FP_CAUSE(cpu->env.fpcsr, tmp);
- if ((GET_FP_ENABLE(cpu->env.fpcsr) & tmp) &&
- (cpu->env.fpcsr & FPCSR_FPEE)) {
- helper_exception(&cpu->env, EXCP_FPE);
- } else {
- UPDATE_FP_FLAGS(cpu->env.fpcsr, tmp);
+ int tmp = get_float_exception_flags(&env->fp_status);
+
+ if (tmp) {
+ set_float_exception_flags(0, &env->fp_status);
+ tmp = ieee_ex_to_openrisc(tmp);
+ if (tmp) {
+ env->fpcsr |= tmp;
+ if (env->fpcsr & FPCSR_FPEE) {
+ helper_exception(env, EXCP_FPE);
+ }
+ }
}
}
uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
{
- uint64_t itofd;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
-
- set_float_exception_flags(0, &cpu->env.fp_status);
- itofd = int32_to_float64(val, &cpu->env.fp_status);
- update_fpcsr(cpu);
-
- return itofd;
+ return int32_to_float64(val, &env->fp_status);
}
uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
{
- uint32_t itofs;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
-
- set_float_exception_flags(0, &cpu->env.fp_status);
- itofs = int32_to_float32(val, &cpu->env.fp_status);
- update_fpcsr(cpu);
-
- return itofs;
+ return int32_to_float32(val, &env->fp_status);
}
uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
{
- uint64_t ftoid;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
-
- set_float_exception_flags(0, &cpu->env.fp_status);
- ftoid = float32_to_int64(val, &cpu->env.fp_status);
- update_fpcsr(cpu);
-
- return ftoid;
+ return float32_to_int64(val, &env->fp_status);
}
uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
{
- uint32_t ftois;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
-
- set_float_exception_flags(0, &cpu->env.fp_status);
- ftois = float32_to_int32(val, &cpu->env.fp_status);
- update_fpcsr(cpu);
-
- return ftois;
+ return float32_to_int32(val, &env->fp_status);
}
-#define FLOAT_OP(name, p) void helper_float_##_##p(void)
-
#define FLOAT_CALC(name) \
uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint64_t fdt0, uint64_t fdt1) \
-{ \
- uint64_t result; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return result; \
-} \
- \
+{ return float64_ ## name(fdt0, fdt1, &env->fp_status); } \
uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t fdt0, uint32_t fdt1) \
-{ \
- uint32_t result; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return result; \
-} \
+{ return float32_ ## name(fdt0, fdt1, &env->fp_status); }
FLOAT_CALC(add)
FLOAT_CALC(sub)
@@ -149,132 +98,29 @@ FLOAT_CALC(rem)
uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a,
uint64_t b, uint64_t c)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- uint64_t result;
- set_float_exception_flags(0, &cpu->env.fp_status);
- /* Note that or1ksim doesn't use merged operation. */
- result = float64_mul(b, c, &cpu->env.fp_status);
- result = float64_add(result, a, &cpu->env.fp_status);
- update_fpcsr(cpu);
- return result;
+ /* Note that or1ksim doesn't use fused operation. */
+ b = float64_mul(b, c, &env->fp_status);
+ return float64_add(a, b, &env->fp_status);
}
uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
uint32_t b, uint32_t c)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- uint32_t result;
- set_float_exception_flags(0, &cpu->env.fp_status);
- /* Note that or1ksim doesn't use merged operation. */
- result = float32_mul(b, c, &cpu->env.fp_status);
- result = float32_add(result, a, &cpu->env.fp_status);
- update_fpcsr(cpu);
- return result;
+ /* Note that or1ksim doesn't use fused operation. */
+ b = float32_mul(b, c, &env->fp_status);
+ return float32_add(a, b, &env->fp_status);
}
-#define FLOAT_CMP(name) \
-uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
- uint32_t fdt0, uint32_t fdt1)\
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-}
+#define FLOAT_CMP(name, impl) \
+target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
+{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \
+target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1) \
+{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); }
-FLOAT_CMP(le)
-FLOAT_CMP(eq)
-FLOAT_CMP(lt)
+FLOAT_CMP(le, le)
+FLOAT_CMP(lt, lt)
+FLOAT_CMP(eq, eq_quiet)
#undef FLOAT_CMP
-
-
-#define FLOAT_CMPNE(name) \
-uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = !float64_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
- uint32_t fdt0, uint32_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = !float32_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-}
-
-FLOAT_CMPNE(ne)
-#undef FLOAT_CMPNE
-
-#define FLOAT_CMPGT(name) \
-uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = !float64_le(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
- uint32_t fdt0, uint32_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = !float32_le(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-}
-FLOAT_CMPGT(gt)
-#undef FLOAT_CMPGT
-
-#define FLOAT_CMPGE(name) \
-uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = !float64_lt(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
- uint32_t fdt0, uint32_t fdt1) \
-{ \
- int res; \
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
- set_float_exception_flags(0, &cpu->env.fp_status); \
- res = !float32_lt(fdt0, fdt1, &cpu->env.fp_status); \
- update_fpcsr(cpu); \
- return res; \
-}
-
-FLOAT_CMPGE(ge)
-#undef FLOAT_CMPGE
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index 58abeb8..4bc2251 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -24,17 +24,19 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env)
DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env)
/* float */
-DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64)
-DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32)
-DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64)
-DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32)
+DEF_HELPER_FLAGS_1(update_fpcsr, TCG_CALL_NO_WG, void, env)
-DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32)
-DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32)
+DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32)
+
+DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
#define FOP_CALC(op) \
-DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \
-DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i64, env, i64, i64)
FOP_CALC(add)
FOP_CALC(sub)
FOP_CALC(mul)
@@ -43,14 +45,11 @@ FOP_CALC(rem)
#undef FOP_CALC
#define FOP_CMP(op) \
-DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \
-DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64)
FOP_CMP(eq)
FOP_CMP(lt)
FOP_CMP(le)
-FOP_CMP(ne)
-FOP_CMP(gt)
-FOP_CMP(ge)
#undef FOP_CMP
/* int */
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index ca1827e..569f4ab 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1163,175 +1163,193 @@ static void dec_float(DisasContext *dc, uint32_t insn)
rd = extract32(insn, 21, 5);
switch (op0) {
- case 0x00: /* lf.add.s */
+ case 0x00: /* lf.add.s */
LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x01: /* lf.sub.s */
+ case 0x01: /* lf.sub.s */
LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
-
- case 0x02: /* lf.mul.s */
+ case 0x02: /* lf.mul.s */
LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb);
- if (ra != 0 && rb != 0) {
- gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- } else {
- tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
- tcg_gen_movi_i32(cpu_R[rd], 0x0);
- }
+ gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x03: /* lf.div.s */
+ case 0x03: /* lf.div.s */
LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x04: /* lf.itof.s */
+ case 0x04: /* lf.itof.s */
LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x05: /* lf.ftoi.s */
+ case 0x05: /* lf.ftoi.s */
LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x06: /* lf.rem.s */
+ case 0x06: /* lf.rem.s */
LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x07: /* lf.madd.s */
+ case 0x07: /* lf.madd.s */
LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd],
cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x08: /* lf.sfeq.s */
+ case 0x08: /* lf.sfeq.s */
LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x09: /* lf.sfne.s */
+ case 0x09: /* lf.sfne.s */
LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
- gen_helper_float_ne_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x0a: /* lf.sfgt.s */
+ case 0x0a: /* lf.sfgt.s */
LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
- gen_helper_float_gt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x0b: /* lf.sfge.s */
+ case 0x0b: /* lf.sfge.s */
LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
- gen_helper_float_ge_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x0c: /* lf.sflt.s */
+ case 0x0c: /* lf.sflt.s */
LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x0d: /* lf.sfle.s */
+ case 0x0d: /* lf.sfle.s */
LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- case 0x10: lf.add.d
+#ifdef TARGET_OPENRISC64
+ case 0x10: /* lf.add.d */
LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
check_of64s(dc);
gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x11: lf.sub.d
+ case 0x11: /* lf.sub.d */
LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
check_of64s(dc);
gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x12: lf.mul.d
+ case 0x12: /* lf.mul.d */
LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
check_of64s(dc);
- if (ra != 0 && rb != 0) {
- gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- } else {
- tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
- tcg_gen_movi_i64(cpu_R[rd], 0x0);
- }
+ gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x13: lf.div.d
+ case 0x13: /* lf.div.d */
LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
check_of64s(dc);
gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x14: lf.itof.d
+ case 0x14: /* lf.itof.d */
LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
check_of64s(dc);
gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x15: lf.ftoi.d
+ case 0x15: /* lf.ftoi.d */
LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
check_of64s(dc);
gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x16: lf.rem.d
+ case 0x16: /* lf.rem.d */
LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
check_of64s(dc);
gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x17: lf.madd.d
+ case 0x17: /* lf.madd.d */
LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
check_of64s(dc);
gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd],
cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x18: lf.sfeq.d
+ case 0x18: /* lf.sfeq.d */
LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
check_of64s(dc);
gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x1a: lf.sfgt.d
+ case 0x1a: /* lf.sfgt.d */
LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_gt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x1b: lf.sfge.d
+ case 0x1b: /* lf.sfge.d */
LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_ge_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x19: lf.sfne.d
+ case 0x19: /* lf.sfne.d */
LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_ne_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x1c: lf.sflt.d
+ case 0x1c: /* lf.sflt.d */
LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
check_of64s(dc);
gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
- case 0x1d: lf.sfle.d
+ case 0x1d: /* lf.sfle.d */
LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
check_of64s(dc);
gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_update_fpcsr(cpu_env);
break;
-#endif*/
+#endif
default:
gen_illegal_exception(dc);
--
2.4.3
next prev parent reply other threads:[~2015-09-03 0:18 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-03 0:17 [Qemu-devel] [PATCH 00/17] target-openrisc improvements Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS Richard Henderson
2015-09-03 14:15 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE Richard Henderson
2015-09-03 14:16 ` Bastian Koppelmann
2015-09-03 14:44 ` Richard Henderson
2015-09-04 13:12 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc Richard Henderson
2015-09-03 14:48 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable Richard Henderson
2015-09-03 15:09 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate Richard Henderson
2015-09-03 16:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags Richard Henderson
2015-09-04 13:05 ` Bastian Koppelmann
2015-09-04 14:29 ` Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2015-09-04 13:33 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers Richard Henderson
2015-09-04 13:58 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit Richard Henderson
2015-09-04 13:59 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2015-09-04 15:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction Richard Henderson
2015-09-04 15:24 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode Richard Henderson
2015-09-05 21:35 ` Bastian Koppelmann
2015-09-06 20:36 ` Richard Henderson
2015-09-13 8:34 ` Bastian Koppelmann
2015-09-14 17:11 ` Richard Henderson
2015-09-15 7:22 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for " Richard Henderson
2015-09-06 9:30 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2015-09-06 11:38 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd Richard Henderson
2015-09-13 8:21 ` Bastian Koppelmann
2015-09-03 0:17 ` Richard Henderson [this message]
2015-09-15 13:02 ` [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa Richard Henderson
2015-09-15 13:04 ` Bastian Koppelmann
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