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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, proljc@gmail.com
Subject: [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd
Date: Wed,  2 Sep 2015 17:17:41 -0700	[thread overview]
Message-ID: <1441239463-18981-16-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1441239463-18981-1-git-send-email-rth@twiddle.net>

Note that the specification for lf.madd.s is confused.  It's
the only mention of supposed FPMADDHI/FPMADDLO special registers.
On the other hand, or1ksim implements a somewhat normal non-fused
multiply and add.  Mirror that.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-openrisc/cpu.h        |  3 --
 target-openrisc/fpu_helper.c | 68 ++++++++++++++++----------------------------
 target-openrisc/helper.h     |  7 ++---
 target-openrisc/translate.c  | 13 +++------
 4 files changed, 30 insertions(+), 61 deletions(-)

diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index adb1410..5ddf477 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -281,9 +281,6 @@ typedef struct CPUOpenRISCState {
 
     uint64_t mac;             /* Multiply registers MACHI:MACLO */
 
-    target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
-    target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */
-
     target_ulong epcr;        /* Exception PC register */
     target_ulong eear;        /* Exception EA register */
 
diff --git a/target-openrisc/fpu_helper.c b/target-openrisc/fpu_helper.c
index c94ed35..d612012 100644
--- a/target-openrisc/fpu_helper.c
+++ b/target-openrisc/fpu_helper.c
@@ -145,52 +145,32 @@ FLOAT_CALC(div)
 FLOAT_CALC(rem)
 #undef FLOAT_CALC
 
-#define FLOAT_TERNOP(name1, name2)                                        \
-uint64_t helper_float_ ## name1 ## name2 ## _d(CPUOpenRISCState *env,     \
-                                               uint64_t fdt0,             \
-                                               uint64_t fdt1)             \
-{                                                                         \
-    uint64_t result, temp, hi, lo;                                        \
-    uint32_t val1, val2;                                                  \
-    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);                         \
-    hi = env->fpmaddhi;                                                   \
-    lo = env->fpmaddlo;                                                   \
-    set_float_exception_flags(0, &cpu->env.fp_status);                    \
-    result = float64_ ## name1(fdt0, fdt1, &cpu->env.fp_status);          \
-    lo &= 0xffffffff;                                                     \
-    hi &= 0xffffffff;                                                     \
-    temp = (hi << 32) | lo;                                               \
-    result = float64_ ## name2(result, temp, &cpu->env.fp_status);        \
-    val1 = result >> 32;                                                  \
-    val2 = (uint32_t) (result & 0xffffffff);                              \
-    update_fpcsr(cpu);                                                    \
-    cpu->env.fpmaddlo = val2;                                             \
-    cpu->env.fpmaddhi = val1;                                             \
-    return 0;                                                             \
-}                                                                         \
-                                                                          \
-uint32_t helper_float_ ## name1 ## name2 ## _s(CPUOpenRISCState *env,     \
-                                            uint32_t fdt0, uint32_t fdt1) \
-{                                                                         \
-    uint64_t result, temp, hi, lo;                                        \
-    uint32_t val1, val2;                                                  \
-    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);                         \
-    hi = cpu->env.fpmaddhi;                                               \
-    lo = cpu->env.fpmaddlo;                                               \
-    set_float_exception_flags(0, &cpu->env.fp_status);                    \
-    result = float64_ ## name1(fdt0, fdt1, &cpu->env.fp_status);          \
-    temp = (hi << 32) | lo;                                               \
-    result = float64_ ## name2(result, temp, &cpu->env.fp_status);        \
-    val1 = result >> 32;                                                  \
-    val2 = (uint32_t) (result & 0xffffffff);                              \
-    update_fpcsr(cpu);                                                    \
-    cpu->env.fpmaddlo = val2;                                             \
-    cpu->env.fpmaddhi = val1;                                             \
-    return 0;                                                             \
+
+uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a,
+                             uint64_t b, uint64_t c)
+{
+    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+    uint64_t result;
+    set_float_exception_flags(0, &cpu->env.fp_status);
+    /* Note that or1ksim doesn't use merged operation.  */
+    result = float64_mul(b, c, &cpu->env.fp_status);
+    result = float64_add(result, a, &cpu->env.fp_status);
+    update_fpcsr(cpu);
+    return result;
 }
 
-FLOAT_TERNOP(mul, add)
-#undef FLOAT_TERNOP
+uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
+                             uint32_t b, uint32_t c)
+{
+    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+    uint32_t result;
+    set_float_exception_flags(0, &cpu->env.fp_status);
+    /* Note that or1ksim doesn't use merged operation.  */
+    result = float32_mul(b, c, &cpu->env.fp_status);
+    result = float32_add(result, a, &cpu->env.fp_status);
+    update_fpcsr(cpu);
+    return result;
+}
 
 
 #define FLOAT_CMP(name)                                                   \
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index ef243cd..58abeb8 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -29,11 +29,8 @@ DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32)
 DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64)
 DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32)
 
-#define FOP_MADD(op)                                             \
-DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \
-DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64)
-FOP_MADD(muladd)
-#undef FOP_MADD
+DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
 
 #define FOP_CALC(op)                                            \
 DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index cd684c7..ca1827e 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -59,7 +59,6 @@ static TCGv cpu_sr_cy;          /* carry (unsigned overflow) */
 static TCGv cpu_sr_ov;          /* signed overflow */
 static TCGv_i32 fpcsr;
 static TCGv_i64 cpu_mac;        /* MACHI:MACLO */
-static TCGv fpmaddhi, fpmaddlo;
 static TCGv_i32 env_flags;
 #include "exec/gen-icount.h"
 
@@ -99,12 +98,6 @@ void openrisc_translate_init(void)
     cpu_mac = tcg_global_mem_new_i64(TCG_AREG0,
                                      offsetof(CPUOpenRISCState, mac),
                                      "mac");
-    fpmaddhi = tcg_global_mem_new(TCG_AREG0,
-                                  offsetof(CPUOpenRISCState, fpmaddhi),
-                                  "fpmaddhi");
-    fpmaddlo = tcg_global_mem_new(TCG_AREG0,
-                                  offsetof(CPUOpenRISCState, fpmaddlo),
-                                  "fpmaddlo");
     for (i = 0; i < 32; i++) {
         cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
                                       offsetof(CPUOpenRISCState, gpr[i]),
@@ -1213,7 +1206,8 @@ static void dec_float(DisasContext *dc, uint32_t insn)
 
     case 0x07:    /* lf.madd.s */
         LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
-        gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd],
+                                cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x08:    /* lf.sfeq.s */
@@ -1298,7 +1292,8 @@ static void dec_float(DisasContext *dc, uint32_t insn)
     case 0x17:     lf.madd.d
         LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
         check_of64s(dc);
-        gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd],
+                                cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x18:     lf.sfeq.d
-- 
2.4.3

  parent reply	other threads:[~2015-09-03  0:18 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-03  0:17 [Qemu-devel] [PATCH 00/17] target-openrisc improvements Richard Henderson
2015-09-03  0:17 ` [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS Richard Henderson
2015-09-03 14:15   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE Richard Henderson
2015-09-03 14:16   ` Bastian Koppelmann
2015-09-03 14:44     ` Richard Henderson
2015-09-04 13:12       ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc Richard Henderson
2015-09-03 14:48   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable Richard Henderson
2015-09-03 15:09   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate Richard Henderson
2015-09-03 16:04   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags Richard Henderson
2015-09-04 13:05   ` Bastian Koppelmann
2015-09-04 14:29     ` Richard Henderson
2015-09-03  0:17 ` [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2015-09-04 13:33   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers Richard Henderson
2015-09-04 13:58   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit Richard Henderson
2015-09-04 13:59   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2015-09-04 15:04   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction Richard Henderson
2015-09-04 15:24   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode Richard Henderson
2015-09-05 21:35   ` Bastian Koppelmann
2015-09-06 20:36     ` Richard Henderson
2015-09-13  8:34       ` Bastian Koppelmann
2015-09-14 17:11         ` Richard Henderson
2015-09-15  7:22           ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for " Richard Henderson
2015-09-06  9:30   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2015-09-06 11:38   ` Bastian Koppelmann
2015-09-03  0:17 ` Richard Henderson [this message]
2015-09-13  8:21   ` [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception Richard Henderson
2015-09-15 13:02   ` Bastian Koppelmann
2015-09-03  0:17 ` [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa Richard Henderson
2015-09-15 13:04   ` Bastian Koppelmann

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