[PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Inspired by the recent misplaced parenthesis fix from Damien, I decided to try
and see what it would take to make our register access type safe. By that mean
you shouldn't be able to pass in anything by a proper register offset in. After
a couple of days of hacking, this series is the result.

I managed to split out all the cleanup stuff upfront, but there is quite a bit
of it. I did include a few random patches no strictly needed, but as long as I
was going through the register macros I tried to fix whatever was wrong.

The actual type safe stuff is in the last patch, and I'm posting that on as an
RFC to see what other people think about the idea. I think most of the prep
work would be nice to have even if we decide against the type safety. Oh, turns
out I couldn't find any new "passing crap as the register offset" type of bugs
with this work, but this would prevent them from sneaking in. As mentioned in
the patch, I limited this only for mmio regs for now, but we could expand it
cover other register types.

I've only smoke tested this on IVB, HSW and BSW.

The whole thing is available in my git repo:
git://github.com/vsyrjala/linux.git type_safe_reg_access_3

Ville Syrjälä (43):
  drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc,i2c}_bus()
  drm/i915: Parametrize LRC registers
  drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
  drm/i915: Parametrize fence registers
  drm/i915: Parametrize FBC_TAG registers
  drm/i915: Parametrize ILK turbo registers
  drm/i915: Replace raw numbers with the approproate register name in
    ILK turbo code
  drm/i915: Parametrize TV luma/chroma filter registers
  drm/i915: Parametrize DDI_BUF_TRANS registers
  drm/i915: Parametrize CSR_PROGRAM registers
  drm/i915: Parametrize UOS_RSA_SCRATCH
  drm/i915: Add LO/HI PRIVATE_PAT registers
  drm/i915: Always use GEN8_RING_PDP_{LDW,UDW} instead of hand rolling
    the register offsets
  drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR
  drm/i915: Parametrize PALETTE and LGC_PALETTE
  drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/
  drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/
  drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
  drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
  drm/i915: Use paramtrized WRPLL_CTL()
  drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE
  drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/
  drm/i915: Eliminate weird parameter inversion from BXT PPS registers
  drm/i915: Parametrize HSW video DIP data registers
  drm/i915: Include gpio_mmio_base in GMBUS reg defines
  drm/i915: Protect register macro arguments
  drm/i915: Fix a few bad hex numbers in register defines
  drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
  drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
  drm/i915: Parametrize and fix SWF registers
  drm/i915: Throw out some useless variables
  drm/i915: Clean up LVDS register handling
  drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
  drm/i915: Turn __raw_i915_read8() & co. in to inline functions
  drm/i915: Move __raw_i915_read8() & co. into i915_drv.h
  drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
  drm/i915: Replace the aux ddc name switch statement with a table
  drm/i915: Parametrize AUX registes
  drm/i915: Add dev_priv->psr_mmio_base
  drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]
  drm/i915: Model PSR AUX register selection more like the normal AUX
    code
  drm/i915: Prefix raw register defines with underscore
  WIP: drm/i915: Type safe register read/write

 drivers/gpu/drm/i915/dvo.h                 |    2 +-
 drivers/gpu/drm/i915/i915_cmd_parser.c     |   17 +-
 drivers/gpu/drm/i915/i915_debugfs.c        |   26 +-
 drivers/gpu/drm/i915/i915_drv.c            |    8 +-
 drivers/gpu/drm/i915/i915_drv.h            |   66 +-
 drivers/gpu/drm/i915/i915_gem_context.c    |    4 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |    2 +-
 drivers/gpu/drm/i915/i915_gem_fence.c      |   41 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        |   35 +-
 drivers/gpu/drm/i915/i915_gpu_error.c      |   25 +-
 drivers/gpu/drm/i915/i915_guc_reg.h        |   50 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |    2 +-
 drivers/gpu/drm/i915/i915_irq.c            |   68 +-
 drivers/gpu/drm/i915/i915_reg.h            | 2768 ++++++++++++++--------------
 drivers/gpu/drm/i915/i915_suspend.c        |   45 +-
 drivers/gpu/drm/i915/i915_sysfs.c          |    6 +-
 drivers/gpu/drm/i915/i915_trace.h          |    4 +-
 drivers/gpu/drm/i915/i915_vgpu.c           |    6 +-
 drivers/gpu/drm/i915/i915_vgpu.h           |    2 +-
 drivers/gpu/drm/i915/intel_audio.c         |   14 +-
 drivers/gpu/drm/i915/intel_crt.c           |   16 +-
 drivers/gpu/drm/i915/intel_csr.c           |   17 +-
 drivers/gpu/drm/i915/intel_ddi.c           |  117 +-
 drivers/gpu/drm/i915/intel_display.c       |  260 ++-
 drivers/gpu/drm/i915/intel_dp.c            |  220 ++-
 drivers/gpu/drm/i915/intel_drv.h           |   14 +-
 drivers/gpu/drm/i915/intel_dsi.c           |    9 +-
 drivers/gpu/drm/i915/intel_dvo.c           |   14 +-
 drivers/gpu/drm/i915/intel_fbc.c           |    2 +-
 drivers/gpu/drm/i915/intel_fifo_underrun.c |    4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c    |    2 +-
 drivers/gpu/drm/i915/intel_hdmi.c          |   71 +-
 drivers/gpu/drm/i915/intel_i2c.c           |   64 +-
 drivers/gpu/drm/i915/intel_lrc.c           |   52 +-
 drivers/gpu/drm/i915/intel_lrc.h           |   10 -
 drivers/gpu/drm/i915/intel_lvds.c          |   36 +-
 drivers/gpu/drm/i915/intel_pm.c            |   29 +-
 drivers/gpu/drm/i915/intel_psr.c           |   63 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c    |   15 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c          |   23 +-
 drivers/gpu/drm/i915/intel_tv.c            |    8 +-
 drivers/gpu/drm/i915/intel_uncore.c        |  133 +-
 drivers/pci/quirks.c                       |    8 +-
 44 files changed, 2189 insertions(+), 2191 deletions(-)

-- 
2.4.6

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[PATCH 01/43] drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_sdvo_select_ddc_bus() and intel_sdvo_select_i2c_bus() have no used
for the passed in 'reg', so just drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index ca3dd7c..05521b5 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2222,7 +2222,7 @@ intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  */
 static void
 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
-			  struct intel_sdvo *sdvo, u32 reg)
+			  struct intel_sdvo *sdvo)
 {
 	struct sdvo_device_mapping *mapping;
 
@@ -2239,7 +2239,7 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
 
 static void
 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
-			  struct intel_sdvo *sdvo, u32 reg)
+			  struct intel_sdvo *sdvo)
 {
 	struct sdvo_device_mapping *mapping;
 	u8 pin;
@@ -2925,7 +2925,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
 	intel_sdvo->sdvo_reg = sdvo_reg;
 	intel_sdvo->is_sdvob = is_sdvob;
 	intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
-	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
+	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
 	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
 		goto err_i2c_bus;
 
@@ -2987,7 +2987,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
 	 */
 	intel_sdvo->base.cloneable = 0;
 
-	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
+	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
 
 	/* Set the input timing to the screen. Assume always input 0. */
 	if (!intel_sdvo_set_target_input(intel_sdvo))
-- 
2.4.6

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Re: [PATCH 01/43] drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus()

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_sdvo_select_ddc_bus() and intel_sdvo_select_i2c_bus() have no used
> for the passed in 'reg', so just drop it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index ca3dd7c..05521b5 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -2222,7 +2222,7 @@ intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
>   */
>  static void
>  intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
> -			  struct intel_sdvo *sdvo, u32 reg)
> +			  struct intel_sdvo *sdvo)
>  {
>  	struct sdvo_device_mapping *mapping;
>  
> @@ -2239,7 +2239,7 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
>  
>  static void
>  intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
> -			  struct intel_sdvo *sdvo, u32 reg)
> +			  struct intel_sdvo *sdvo)
>  {
>  	struct sdvo_device_mapping *mapping;
>  	u8 pin;
> @@ -2925,7 +2925,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
>  	intel_sdvo->sdvo_reg = sdvo_reg;
>  	intel_sdvo->is_sdvob = is_sdvob;
>  	intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
> -	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
> +	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
>  	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
>  		goto err_i2c_bus;
>  
> @@ -2987,7 +2987,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
>  	 */
>  	intel_sdvo->base.cloneable = 0;
>  
> -	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
> +	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
>  
>  	/* Set the input timing to the screen. Assume always input 0. */
>  	if (!intel_sdvo_set_target_input(intel_sdvo))
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 02/43] drm/i915: Parametrize LRC registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++----
 drivers/gpu/drm/i915/intel_lrc.c    | 8 +++-----
 drivers/gpu/drm/i915/intel_lrc.h    | 6 ++++--
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 72ae347..5615d3d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2069,8 +2069,8 @@ static int i915_execlists(struct seq_file *m, void *data)
 
 		seq_printf(m, "%s\n", ring->name);
 
-		status = I915_READ(RING_EXECLIST_STATUS(ring));
-		ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
+		status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
+		ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
 		seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
 			   status, ctx_id);
 
@@ -2085,8 +2085,8 @@ static int i915_execlists(struct seq_file *m, void *data)
 			   read_pointer, write_pointer);
 
 		for (i = 0; i < 6; i++) {
-			status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
-			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
+			status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
+			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
 
 			seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
 				   i, status, ctx_id);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fe06accb0..ca9f161 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -349,7 +349,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
 	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
 
 	/* ELSP is a wo register, use another nearby reg for posting */
-	POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
+	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
 	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
 	spin_unlock(&dev_priv->uncore.lock);
 }
@@ -519,10 +519,8 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 
 	while (read_pointer < write_pointer) {
 		read_pointer++;
-		status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
-				(read_pointer % 6) * 8);
-		status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
-				(read_pointer % 6) * 8 + 4);
+		status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % 6));
+		status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % 6));
 
 		if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
 			continue;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 69d99f0..8a08a27 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -28,12 +28,14 @@
 
 /* Execlists regs */
 #define RING_ELSP(ring)			((ring)->mmio_base+0x230)
-#define RING_EXECLIST_STATUS(ring)	((ring)->mmio_base+0x234)
+#define RING_EXECLIST_STATUS_LO(ring)	((ring)->mmio_base+0x234)
+#define RING_EXECLIST_STATUS_HI(ring)	((ring)->mmio_base+0x234 + 4)
 #define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
 #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
-#define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
+#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	((ring)->mmio_base+0x370 + (i) * 8)
+#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	((ring)->mmio_base+0x370 + (i) * 8 + 4)
 #define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
 
 /* Logical Rings */
-- 
2.4.6

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Re: [PATCH 02/43] drm/i915: Parametrize LRC registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++----
>  drivers/gpu/drm/i915/intel_lrc.c    | 8 +++-----
>  drivers/gpu/drm/i915/intel_lrc.h    | 6 ++++--
>  3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 72ae347..5615d3d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2069,8 +2069,8 @@ static int i915_execlists(struct seq_file *m, void *data)
>  
>  		seq_printf(m, "%s\n", ring->name);
>  
> -		status = I915_READ(RING_EXECLIST_STATUS(ring));
> -		ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
> +		status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
> +		ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
>  		seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
>  			   status, ctx_id);
>  
> @@ -2085,8 +2085,8 @@ static int i915_execlists(struct seq_file *m, void *data)
>  			   read_pointer, write_pointer);
>  
>  		for (i = 0; i < 6; i++) {
> -			status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
> -			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
> +			status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
> +			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
>  
>  			seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
>  				   i, status, ctx_id);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fe06accb0..ca9f161 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -349,7 +349,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
>  	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
>  
>  	/* ELSP is a wo register, use another nearby reg for posting */
> -	POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
> +	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
>  	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
>  	spin_unlock(&dev_priv->uncore.lock);
>  }
> @@ -519,10 +519,8 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
>  
>  	while (read_pointer < write_pointer) {
>  		read_pointer++;
> -		status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
> -				(read_pointer % 6) * 8);
> -		status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
> -				(read_pointer % 6) * 8 + 4);
> +		status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % 6));
> +		status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % 6));
>  
>  		if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
>  			continue;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 69d99f0..8a08a27 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -28,12 +28,14 @@
>  
>  /* Execlists regs */
>  #define RING_ELSP(ring)			((ring)->mmio_base+0x230)
> -#define RING_EXECLIST_STATUS(ring)	((ring)->mmio_base+0x234)
> +#define RING_EXECLIST_STATUS_LO(ring)	((ring)->mmio_base+0x234)
> +#define RING_EXECLIST_STATUS_HI(ring)	((ring)->mmio_base+0x234 + 4)
>  #define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
>  #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
>  #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
>  #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
> -#define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
> +#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	((ring)->mmio_base+0x370 + (i) * 8)
> +#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	((ring)->mmio_base+0x370 + (i) * 8 + 4)
>  #define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
>  
>  /* Logical Rings */
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e2bf9e2..e6d7a69 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);
 
 	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
+		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
 
 	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
 	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
@@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	s->pm_ier		= I915_READ(GEN6_PMIER);
 
 	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
+		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
 
 	/* GT SA CZ domain, 0x100000-0x138124 */
 	s->tilectl		= I915_READ(TILECTL);
@@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);
 
 	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
+		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
 
 	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
 	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
@@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_PMIER,		s->pm_ier);
 
 	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
+		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
 
 	/* GT SA CZ domain, 0x100000-0x138124 */
 	I915_WRITE(TILECTL,			s->tilectl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67bf205..44cedbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1527,7 +1527,7 @@ enum skl_disp_power_wells {
 #define GEN7_GFX_PEND_TLB0	0x4034
 #define GEN7_GFX_PEND_TLB1	0x4038
 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
-#define GEN7_LRA_LIMITS_BASE	0x403C
+#define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
 #define GEN7_LRA_LIMITS_REG_NUM	13
 #define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
 #define GEN7_GFX_MAX_REQ_COUNT		0x4074
@@ -6808,7 +6808,7 @@ enum skl_disp_power_wells {
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
-#define GEN7_GT_SCRATCH_BASE			0x4F100
+#define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
 #define GEN7_GT_SCRATCH_REG_NUM			8
 
 #define VLV_GTLC_SURVIVABILITY_REG              0x130098
-- 
2.4.6

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e2bf9e2..e6d7a69 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> -		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
> +		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
>  
>  	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
>  	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
> @@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	s->pm_ier		= I915_READ(GEN6_PMIER);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> -		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
> +		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
>  
>  	/* GT SA CZ domain, 0x100000-0x138124 */
>  	s->tilectl		= I915_READ(TILECTL);
> @@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> -		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
> +		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
>  
>  	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
>  	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
> @@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN6_PMIER,		s->pm_ier);
>  
>  	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> -		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
> +		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
>  
>  	/* GT SA CZ domain, 0x100000-0x138124 */
>  	I915_WRITE(TILECTL,			s->tilectl);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 67bf205..44cedbf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1527,7 +1527,7 @@ enum skl_disp_power_wells {
>  #define GEN7_GFX_PEND_TLB0	0x4034
>  #define GEN7_GFX_PEND_TLB1	0x4038
>  /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
> -#define GEN7_LRA_LIMITS_BASE	0x403C
> +#define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
>  #define GEN7_LRA_LIMITS_REG_NUM	13
>  #define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
>  #define GEN7_GFX_MAX_REQ_COUNT		0x4074
> @@ -6808,7 +6808,7 @@ enum skl_disp_power_wells {
>  						 GEN6_PM_RP_DOWN_THRESHOLD | \
>  						 GEN6_PM_RP_DOWN_TIMEOUT)
>  
> -#define GEN7_GT_SCRATCH_BASE			0x4F100
> +#define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
>  #define GEN7_GT_SCRATCH_REG_NUM			8
>  
>  #define VLV_GTLC_SURVIVABILITY_REG              0x130098
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 04/43] drm/i915: Parametrize fence registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
 drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
 drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
 3 files changed, 37 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 6077dff..ff94560 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int fence_reg;
+	int fence_reg_lo, fence_reg_hi;
 	int fence_pitch_shift;
 
 	if (INTEL_INFO(dev)->gen >= 6) {
-		fence_reg = FENCE_REG_SANDYBRIDGE_0;
-		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
+		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
+		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
+		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
 	} else {
-		fence_reg = FENCE_REG_965_0;
+		fence_reg_lo = FENCE_REG_965_LO(reg);
+		fence_reg_hi = FENCE_REG_965_HI(reg);
 		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
 	}
 
-	fence_reg += reg * 8;
-
 	/* To w/a incoherency with non-atomic 64-bit register updates,
 	 * we split the 64-bit update into two 32-bit writes. In order
 	 * for a partial fence not to be evaluated between writes, we
@@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 	 * For extra levels of paranoia, we make sure each step lands
 	 * before applying the next step.
 	 */
-	I915_WRITE(fence_reg, 0);
-	POSTING_READ(fence_reg);
+	I915_WRITE(fence_reg_lo, 0);
+	POSTING_READ(fence_reg_lo);
 
 	if (obj) {
 		u32 size = i915_gem_obj_ggtt_size(obj);
@@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
 		val |= I965_FENCE_REG_VALID;
 
-		I915_WRITE(fence_reg + 4, val >> 32);
-		POSTING_READ(fence_reg + 4);
+		I915_WRITE(fence_reg_hi, val >> 32);
+		POSTING_READ(fence_reg_hi);
 
-		I915_WRITE(fence_reg + 0, val);
-		POSTING_READ(fence_reg);
+		I915_WRITE(fence_reg_lo, val);
+		POSTING_READ(fence_reg_lo);
 	} else {
-		I915_WRITE(fence_reg + 4, 0);
-		POSTING_READ(fence_reg + 4);
+		I915_WRITE(fence_reg_hi, 0);
+		POSTING_READ(fence_reg_hi);
 	}
 }
 
@@ -118,7 +118,7 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
+	u32 fence_reg, val;
 
 	if (obj) {
 		u32 size = i915_gem_obj_ggtt_size(obj);
@@ -150,12 +150,12 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
 		val = 0;
 
 	if (reg < 8)
-		reg = FENCE_REG_830_0 + reg * 4;
+		fence_reg = FENCE_REG_830(reg);
 	else
-		reg = FENCE_REG_945_8 + (reg - 8) * 4;
+		fence_reg = FENCE_REG_945_8(reg);
 
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
+	I915_WRITE(fence_reg, val);
+	POSTING_READ(fence_reg);
 }
 
 static void i830_write_fence_reg(struct drm_device *dev, int reg,
@@ -186,8 +186,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
 	} else
 		val = 0;
 
-	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
-	POSTING_READ(FENCE_REG_830_0 + reg * 4);
+	I915_WRITE(FENCE_REG_830(reg), val);
+	POSTING_READ(FENCE_REG_830(reg));
 }
 
 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3379f9c..e873eb4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
 
 	if (IS_GEN3(dev) || IS_GEN2(dev)) {
 		for (i = 0; i < 8; i++)
-			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-			for (i = 0; i < 8; i++)
-				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
-							      (i * 4));
-	} else if (IS_GEN5(dev) || IS_GEN4(dev))
-		for (i = 0; i < 16; i++)
-			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
-						      (i * 8));
-	else if (INTEL_INFO(dev)->gen >= 6)
+			error->fence[i] = I915_READ(FENCE_REG_830(i));
+		for (i = 8; i < dev_priv->num_fence_regs; i++)
+			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
+	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
-			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
-						      (i * 8));
+			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
+	} else if (INTEL_INFO(dev)->gen >= 6) {
+		for (i = 0; i < dev_priv->num_fence_regs; i++)
+			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
+	}
 }
 
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44cedbf..b1cf17a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
 /*
  * Fence registers
  */
-#define FENCE_REG_830_0			0x2000
-#define FENCE_REG_945_8			0x3000
+#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
+#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
 #define   I830_FENCE_START_MASK		0x07f80000
 #define   I830_FENCE_TILING_Y_SHIFT	12
 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
@@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
 #define   I915_FENCE_START_MASK		0x0ff00000
 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
 
-#define FENCE_REG_965_0			0x03000
+#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
+#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
 #define   I965_FENCE_PITCH_SHIFT	2
 #define   I965_FENCE_TILING_Y_SHIFT	1
 #define   I965_FENCE_REG_VALID		(1<<0)
 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
 
-#define FENCE_REG_SANDYBRIDGE_0		0x100000
-#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
+#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
+#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
+#define   GEN6_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
 
-- 
2.4.6

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Re: [PATCH 04/43] drm/i915: Parametrize fence registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
>  drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
>  drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
>  3 files changed, 37 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 6077dff..ff94560 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int fence_reg;
> +	int fence_reg_lo, fence_reg_hi;
>  	int fence_pitch_shift;
>  
>  	if (INTEL_INFO(dev)->gen >= 6) {
> -		fence_reg = FENCE_REG_SANDYBRIDGE_0;
> -		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
> +		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
> +		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
> +		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>  	} else {
> -		fence_reg = FENCE_REG_965_0;
> +		fence_reg_lo = FENCE_REG_965_LO(reg);
> +		fence_reg_hi = FENCE_REG_965_HI(reg);
>  		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
>  	}
>  
> -	fence_reg += reg * 8;
> -
>  	/* To w/a incoherency with non-atomic 64-bit register updates,
>  	 * we split the 64-bit update into two 32-bit writes. In order
>  	 * for a partial fence not to be evaluated between writes, we
> @@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  	 * For extra levels of paranoia, we make sure each step lands
>  	 * before applying the next step.
>  	 */
> -	I915_WRITE(fence_reg, 0);
> -	POSTING_READ(fence_reg);
> +	I915_WRITE(fence_reg_lo, 0);
> +	POSTING_READ(fence_reg_lo);
>  
>  	if (obj) {
>  		u32 size = i915_gem_obj_ggtt_size(obj);
> @@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
>  		val |= I965_FENCE_REG_VALID;
>  
> -		I915_WRITE(fence_reg + 4, val >> 32);
> -		POSTING_READ(fence_reg + 4);
> +		I915_WRITE(fence_reg_hi, val >> 32);
> +		POSTING_READ(fence_reg_hi);
>  
> -		I915_WRITE(fence_reg + 0, val);
> -		POSTING_READ(fence_reg);
> +		I915_WRITE(fence_reg_lo, val);
> +		POSTING_READ(fence_reg_lo);
>  	} else {
> -		I915_WRITE(fence_reg + 4, 0);
> -		POSTING_READ(fence_reg + 4);
> +		I915_WRITE(fence_reg_hi, 0);
> +		POSTING_READ(fence_reg_hi);
>  	}
>  }
>  
> @@ -118,7 +118,7 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 val;
> +	u32 fence_reg, val;
>  
>  	if (obj) {
>  		u32 size = i915_gem_obj_ggtt_size(obj);
> @@ -150,12 +150,12 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
>  		val = 0;
>  
>  	if (reg < 8)
> -		reg = FENCE_REG_830_0 + reg * 4;
> +		fence_reg = FENCE_REG_830(reg);
>  	else
> -		reg = FENCE_REG_945_8 + (reg - 8) * 4;
> +		fence_reg = FENCE_REG_945_8(reg);
>  
> -	I915_WRITE(reg, val);
> -	POSTING_READ(reg);
> +	I915_WRITE(fence_reg, val);
> +	POSTING_READ(fence_reg);
>  }
>  
>  static void i830_write_fence_reg(struct drm_device *dev, int reg,
> @@ -186,8 +186,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
>  	} else
>  		val = 0;
>  
> -	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
> -	POSTING_READ(FENCE_REG_830_0 + reg * 4);
> +	I915_WRITE(FENCE_REG_830(reg), val);
> +	POSTING_READ(FENCE_REG_830(reg));
>  }
>  
>  inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 3379f9c..e873eb4 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
>  
>  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
>  		for (i = 0; i < 8; i++)
> -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -			for (i = 0; i < 8; i++)
> -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> -							      (i * 4));
> -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> -		for (i = 0; i < 16; i++)
> -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> -						      (i * 8));
> -	else if (INTEL_INFO(dev)->gen >= 6)
> +			error->fence[i] = I915_READ(FENCE_REG_830(i));
> +		for (i = 8; i < dev_priv->num_fence_regs; i++)
> +			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
> +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
>  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> -						      (i * 8));
> +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
> +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> +	}
>  }
>  
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44cedbf..b1cf17a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
>  /*
>   * Fence registers
>   */
> -#define FENCE_REG_830_0			0x2000
> -#define FENCE_REG_945_8			0x3000
> +#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> +#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */

How about defining that as

#define FENCE_REG_945(i) (i < 8 ? FENCE_REG_830(i) : (0x3000 + ((i) - 8) * 4))

and changing the code to look at platforms, not reg number?


BR,
Jani.


>  #define   I830_FENCE_START_MASK		0x07f80000
>  #define   I830_FENCE_TILING_Y_SHIFT	12
>  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> @@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
>  #define   I915_FENCE_START_MASK		0x0ff00000
>  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
>  
> -#define FENCE_REG_965_0			0x03000
> +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
>  #define   I965_FENCE_PITCH_SHIFT	2
>  #define   I965_FENCE_TILING_Y_SHIFT	1
>  #define   I965_FENCE_REG_VALID		(1<<0)
>  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
>  
> -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> +#define   GEN6_FENCE_PITCH_SHIFT	32
>  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
>  
>  
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/43] drm/i915: Parametrize fence registers

[Ville Syrjälä]

On Mon, Sep 21, 2015 at 10:45:46AM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
> >  drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
> >  drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
> >  3 files changed, 37 insertions(+), 38 deletions(-)
> >
<snip>
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index 3379f9c..e873eb4 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
> >  
> >  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
> >  		for (i = 0; i < 8; i++)
> > -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> > -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> > -			for (i = 0; i < 8; i++)
> > -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> > -							      (i * 4));
> > -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> > -		for (i = 0; i < 16; i++)
> > -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> > -						      (i * 8));
> > -	else if (INTEL_INFO(dev)->gen >= 6)
> > +			error->fence[i] = I915_READ(FENCE_REG_830(i));
> > +		for (i = 8; i < dev_priv->num_fence_regs; i++)
> > +			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
> > +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> >  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> > -						      (i * 8));
> > +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> > +	} else if (INTEL_INFO(dev)->gen >= 6) {
> > +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> > +	}
> >  }
> >  
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 44cedbf..b1cf17a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
> >  /*
> >   * Fence registers
> >   */
> > -#define FENCE_REG_830_0			0x2000
> > -#define FENCE_REG_945_8			0x3000
> > +#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> > +#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
> 
> How about defining that as
> 
> #define FENCE_REG_945(i) (i < 8 ? FENCE_REG_830(i) : (0x3000 + ((i) - 8) * 4))
> 
> and changing the code to look at platforms, not reg number?

Yeah, I guess we can hide the magic entirely. In fact we wouldn't even
need any gen2 vs. gen3 platforms checks anymore with that macro.

> 
> 
> BR,
> Jani.
> 
> 
> >  #define   I830_FENCE_START_MASK		0x07f80000
> >  #define   I830_FENCE_TILING_Y_SHIFT	12
> >  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> > @@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
> >  #define   I915_FENCE_START_MASK		0x0ff00000
> >  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
> >  
> > -#define FENCE_REG_965_0			0x03000
> > +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> > +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
> >  #define   I965_FENCE_PITCH_SHIFT	2
> >  #define   I965_FENCE_TILING_Y_SHIFT	1
> >  #define   I965_FENCE_REG_VALID		(1<<0)
> >  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
> >  
> > -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> > -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> > +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> > +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> > +#define   GEN6_FENCE_PITCH_SHIFT	32
> >  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
> >  
> >  
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/43] drm/i915: Parametrize fence registers

[Ville Syrjälä]

On Mon, Sep 21, 2015 at 03:33:00PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 21, 2015 at 10:45:46AM +0300, Jani Nikula wrote:
> > On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
> > >  drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
> > >  drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
> > >  3 files changed, 37 insertions(+), 38 deletions(-)
> > >
> <snip>
> > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > index 3379f9c..e873eb4 100644
> > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > @@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
> > >  
> > >  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
> > >  		for (i = 0; i < 8; i++)
> > > -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> > > -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> > > -			for (i = 0; i < 8; i++)
> > > -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> > > -							      (i * 4));
> > > -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> > > -		for (i = 0; i < 16; i++)
> > > -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> > > -						      (i * 8));
> > > -	else if (INTEL_INFO(dev)->gen >= 6)
> > > +			error->fence[i] = I915_READ(FENCE_REG_830(i));
> > > +		for (i = 8; i < dev_priv->num_fence_regs; i++)
> > > +			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
> > > +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> > >  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > > -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> > > -						      (i * 8));
> > > +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> > > +	} else if (INTEL_INFO(dev)->gen >= 6) {
> > > +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > > +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> > > +	}
> > >  }
> > >  
> > >  
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 44cedbf..b1cf17a 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
> > >  /*
> > >   * Fence registers
> > >   */
> > > -#define FENCE_REG_830_0			0x2000
> > > -#define FENCE_REG_945_8			0x3000
> > > +#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> > > +#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
> > 
> > How about defining that as
> > 
> > #define FENCE_REG_945(i) (i < 8 ? FENCE_REG_830(i) : (0x3000 + ((i) - 8) * 4))
> > 
> > and changing the code to look at platforms, not reg number?
> 
> Yeah, I guess we can hide the magic entirely. In fact we wouldn't even
> need any gen2 vs. gen3 platforms checks anymore with that macro.

Oh I think I already considered making this even more magic with
something like this:
(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
or
(0x2000 + (((i) >> 3) * 0x1000) + ((i) & 7) * 4)

Not sure if that's too obscure for people? I suppose I could toss in a
comment in there to explain it a bit.

> 
> > 
> > 
> > BR,
> > Jani.
> > 
> > 
> > >  #define   I830_FENCE_START_MASK		0x07f80000
> > >  #define   I830_FENCE_TILING_Y_SHIFT	12
> > >  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> > > @@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
> > >  #define   I915_FENCE_START_MASK		0x0ff00000
> > >  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
> > >  
> > > -#define FENCE_REG_965_0			0x03000
> > > +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> > > +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
> > >  #define   I965_FENCE_PITCH_SHIFT	2
> > >  #define   I965_FENCE_TILING_Y_SHIFT	1
> > >  #define   I965_FENCE_REG_VALID		(1<<0)
> > >  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
> > >  
> > > -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> > > -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> > > +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> > > +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> > > +#define   GEN6_FENCE_PITCH_SHIFT	32
> > >  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
> > >  
> > >  
> > > -- 
> > > 2.4.6
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Jani Nikula, Intel Open Source Technology Center
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 04/43] drm/i915: Parametrize fence registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Hide the 945 vs. rest of gen2/3 difference in the macro

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 41 +++++++++++++++--------------------
 drivers/gpu/drm/i915/i915_gpu_error.c | 21 +++++++-----------
 drivers/gpu/drm/i915/i915_reg.h       | 18 ++++++++++-----
 3 files changed, 39 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 6077dff..1cbfd5b 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int fence_reg;
+	int fence_reg_lo, fence_reg_hi;
 	int fence_pitch_shift;
 
 	if (INTEL_INFO(dev)->gen >= 6) {
-		fence_reg = FENCE_REG_SANDYBRIDGE_0;
-		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
+		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
+		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
+		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
 	} else {
-		fence_reg = FENCE_REG_965_0;
+		fence_reg_lo = FENCE_REG_965_LO(reg);
+		fence_reg_hi = FENCE_REG_965_HI(reg);
 		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
 	}
 
-	fence_reg += reg * 8;
-
 	/* To w/a incoherency with non-atomic 64-bit register updates,
 	 * we split the 64-bit update into two 32-bit writes. In order
 	 * for a partial fence not to be evaluated between writes, we
@@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 	 * For extra levels of paranoia, we make sure each step lands
 	 * before applying the next step.
 	 */
-	I915_WRITE(fence_reg, 0);
-	POSTING_READ(fence_reg);
+	I915_WRITE(fence_reg_lo, 0);
+	POSTING_READ(fence_reg_lo);
 
 	if (obj) {
 		u32 size = i915_gem_obj_ggtt_size(obj);
@@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
 		val |= I965_FENCE_REG_VALID;
 
-		I915_WRITE(fence_reg + 4, val >> 32);
-		POSTING_READ(fence_reg + 4);
+		I915_WRITE(fence_reg_hi, val >> 32);
+		POSTING_READ(fence_reg_hi);
 
-		I915_WRITE(fence_reg + 0, val);
-		POSTING_READ(fence_reg);
+		I915_WRITE(fence_reg_lo, val);
+		POSTING_READ(fence_reg_lo);
 	} else {
-		I915_WRITE(fence_reg + 4, 0);
-		POSTING_READ(fence_reg + 4);
+		I915_WRITE(fence_reg_hi, 0);
+		POSTING_READ(fence_reg_hi);
 	}
 }
 
@@ -149,13 +149,8 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
 	} else
 		val = 0;
 
-	if (reg < 8)
-		reg = FENCE_REG_830_0 + reg * 4;
-	else
-		reg = FENCE_REG_945_8 + (reg - 8) * 4;
-
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
+	I915_WRITE(FENCE_REG(reg), val);
+	POSTING_READ(FENCE_REG(reg));
 }
 
 static void i830_write_fence_reg(struct drm_device *dev, int reg,
@@ -186,8 +181,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
 	} else
 		val = 0;
 
-	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
-	POSTING_READ(FENCE_REG_830_0 + reg * 4);
+	I915_WRITE(FENCE_REG(reg), val);
+	POSTING_READ(FENCE_REG(reg));
 }
 
 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3379f9c..3b574c2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -786,20 +786,15 @@ static void i915_gem_record_fences(struct drm_device *dev,
 	int i;
 
 	if (IS_GEN3(dev) || IS_GEN2(dev)) {
-		for (i = 0; i < 8; i++)
-			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-			for (i = 0; i < 8; i++)
-				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
-							      (i * 4));
-	} else if (IS_GEN5(dev) || IS_GEN4(dev))
-		for (i = 0; i < 16; i++)
-			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
-						      (i * 8));
-	else if (INTEL_INFO(dev)->gen >= 6)
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
-			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
-						      (i * 8));
+			error->fence[i] = I915_READ(FENCE_REG(i));
+	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
+		for (i = 0; i < dev_priv->num_fence_regs; i++)
+			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
+	} else if (INTEL_INFO(dev)->gen >= 6) {
+		for (i = 0; i < dev_priv->num_fence_regs; i++)
+			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
+	}
 }
 
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44cedbf..8133c7e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1436,9 +1436,15 @@ enum skl_disp_power_wells {
 
 /*
  * Fence registers
+ * [0-7]  @ 0x2000 gen2,gen3
+ * [8-15] @ 0x3000 945,g33,pnv
+ *
+ * [0-15] @ 0x3000 gen4,gen5
+ *
+ * [0-15] @ 0x100000 gen6,vlv,chv
+ * [0-31] @ 0x100000 gen7+
  */
-#define FENCE_REG_830_0			0x2000
-#define FENCE_REG_945_8			0x3000
+#define FENCE_REG(i)			(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
 #define   I830_FENCE_START_MASK		0x07f80000
 #define   I830_FENCE_TILING_Y_SHIFT	12
 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
@@ -1451,14 +1457,16 @@ enum skl_disp_power_wells {
 #define   I915_FENCE_START_MASK		0x0ff00000
 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
 
-#define FENCE_REG_965_0			0x03000
+#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
+#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
 #define   I965_FENCE_PITCH_SHIFT	2
 #define   I965_FENCE_TILING_Y_SHIFT	1
 #define   I965_FENCE_REG_VALID		(1<<0)
 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
 
-#define FENCE_REG_SANDYBRIDGE_0		0x100000
-#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
+#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
+#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
+#define   GEN6_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
 
-- 
2.4.6

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Re: [PATCH v2 04/43] drm/i915: Parametrize fence registers

[Jani Nikula]

On Mon, 21 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> v2: Hide the 945 vs. rest of gen2/3 difference in the macro
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_fence.c | 41 +++++++++++++++--------------------
>  drivers/gpu/drm/i915/i915_gpu_error.c | 21 +++++++-----------
>  drivers/gpu/drm/i915/i915_reg.h       | 18 ++++++++++-----
>  3 files changed, 39 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 6077dff..1cbfd5b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int fence_reg;
> +	int fence_reg_lo, fence_reg_hi;
>  	int fence_pitch_shift;
>  
>  	if (INTEL_INFO(dev)->gen >= 6) {
> -		fence_reg = FENCE_REG_SANDYBRIDGE_0;
> -		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
> +		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
> +		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
> +		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>  	} else {
> -		fence_reg = FENCE_REG_965_0;
> +		fence_reg_lo = FENCE_REG_965_LO(reg);
> +		fence_reg_hi = FENCE_REG_965_HI(reg);
>  		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
>  	}
>  
> -	fence_reg += reg * 8;
> -
>  	/* To w/a incoherency with non-atomic 64-bit register updates,
>  	 * we split the 64-bit update into two 32-bit writes. In order
>  	 * for a partial fence not to be evaluated between writes, we
> @@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  	 * For extra levels of paranoia, we make sure each step lands
>  	 * before applying the next step.
>  	 */
> -	I915_WRITE(fence_reg, 0);
> -	POSTING_READ(fence_reg);
> +	I915_WRITE(fence_reg_lo, 0);
> +	POSTING_READ(fence_reg_lo);
>  
>  	if (obj) {
>  		u32 size = i915_gem_obj_ggtt_size(obj);
> @@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
>  		val |= I965_FENCE_REG_VALID;
>  
> -		I915_WRITE(fence_reg + 4, val >> 32);
> -		POSTING_READ(fence_reg + 4);
> +		I915_WRITE(fence_reg_hi, val >> 32);
> +		POSTING_READ(fence_reg_hi);
>  
> -		I915_WRITE(fence_reg + 0, val);
> -		POSTING_READ(fence_reg);
> +		I915_WRITE(fence_reg_lo, val);
> +		POSTING_READ(fence_reg_lo);
>  	} else {
> -		I915_WRITE(fence_reg + 4, 0);
> -		POSTING_READ(fence_reg + 4);
> +		I915_WRITE(fence_reg_hi, 0);
> +		POSTING_READ(fence_reg_hi);
>  	}
>  }
>  
> @@ -149,13 +149,8 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
>  	} else
>  		val = 0;
>  
> -	if (reg < 8)
> -		reg = FENCE_REG_830_0 + reg * 4;
> -	else
> -		reg = FENCE_REG_945_8 + (reg - 8) * 4;
> -
> -	I915_WRITE(reg, val);
> -	POSTING_READ(reg);
> +	I915_WRITE(FENCE_REG(reg), val);
> +	POSTING_READ(FENCE_REG(reg));
>  }
>  
>  static void i830_write_fence_reg(struct drm_device *dev, int reg,
> @@ -186,8 +181,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
>  	} else
>  		val = 0;
>  
> -	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
> -	POSTING_READ(FENCE_REG_830_0 + reg * 4);
> +	I915_WRITE(FENCE_REG(reg), val);
> +	POSTING_READ(FENCE_REG(reg));
>  }
>  
>  inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 3379f9c..3b574c2 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -786,20 +786,15 @@ static void i915_gem_record_fences(struct drm_device *dev,
>  	int i;
>  
>  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
> -		for (i = 0; i < 8; i++)
> -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -			for (i = 0; i < 8; i++)
> -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> -							      (i * 4));
> -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> -		for (i = 0; i < 16; i++)
> -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> -						      (i * 8));
> -	else if (INTEL_INFO(dev)->gen >= 6)
>  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> -						      (i * 8));
> +			error->fence[i] = I915_READ(FENCE_REG(i));
> +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
> +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> +	}
>  }
>  
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44cedbf..8133c7e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1436,9 +1436,15 @@ enum skl_disp_power_wells {
>  
>  /*
>   * Fence registers
> + * [0-7]  @ 0x2000 gen2,gen3
> + * [8-15] @ 0x3000 945,g33,pnv
> + *
> + * [0-15] @ 0x3000 gen4,gen5
> + *
> + * [0-15] @ 0x100000 gen6,vlv,chv
> + * [0-31] @ 0x100000 gen7+
>   */
> -#define FENCE_REG_830_0			0x2000
> -#define FENCE_REG_945_8			0x3000
> +#define FENCE_REG(i)			(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)

I'd have appreciated the more obvious (i < 8 ? 0x2000 + i * 4 : 0x3000 +
(i - 8) * 4) but meh.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>




>  #define   I830_FENCE_START_MASK		0x07f80000
>  #define   I830_FENCE_TILING_Y_SHIFT	12
>  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> @@ -1451,14 +1457,16 @@ enum skl_disp_power_wells {
>  #define   I915_FENCE_START_MASK		0x0ff00000
>  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
>  
> -#define FENCE_REG_965_0			0x03000
> +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
>  #define   I965_FENCE_PITCH_SHIFT	2
>  #define   I965_FENCE_TILING_Y_SHIFT	1
>  #define   I965_FENCE_REG_VALID		(1<<0)
>  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
>  
> -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> +#define   GEN6_FENCE_PITCH_SHIFT	32
>  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
>  
>  
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH v2 04/43] drm/i915: Parametrize fence registers

[Daniel Vetter]

On Fri, Sep 25, 2015 at 03:02:37PM +0300, Jani Nikula wrote:
> On Mon, 21 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > v2: Hide the 945 vs. rest of gen2/3 difference in the macro
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_fence.c | 41 +++++++++++++++--------------------
> >  drivers/gpu/drm/i915/i915_gpu_error.c | 21 +++++++-----------
> >  drivers/gpu/drm/i915/i915_reg.h       | 18 ++++++++++-----
> >  3 files changed, 39 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> > index 6077dff..1cbfd5b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> > @@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
> >  				 struct drm_i915_gem_object *obj)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	int fence_reg;
> > +	int fence_reg_lo, fence_reg_hi;
> >  	int fence_pitch_shift;
> >  
> >  	if (INTEL_INFO(dev)->gen >= 6) {
> > -		fence_reg = FENCE_REG_SANDYBRIDGE_0;
> > -		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
> > +		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
> > +		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
> > +		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
> >  	} else {
> > -		fence_reg = FENCE_REG_965_0;
> > +		fence_reg_lo = FENCE_REG_965_LO(reg);
> > +		fence_reg_hi = FENCE_REG_965_HI(reg);
> >  		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
> >  	}
> >  
> > -	fence_reg += reg * 8;
> > -
> >  	/* To w/a incoherency with non-atomic 64-bit register updates,
> >  	 * we split the 64-bit update into two 32-bit writes. In order
> >  	 * for a partial fence not to be evaluated between writes, we
> > @@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
> >  	 * For extra levels of paranoia, we make sure each step lands
> >  	 * before applying the next step.
> >  	 */
> > -	I915_WRITE(fence_reg, 0);
> > -	POSTING_READ(fence_reg);
> > +	I915_WRITE(fence_reg_lo, 0);
> > +	POSTING_READ(fence_reg_lo);
> >  
> >  	if (obj) {
> >  		u32 size = i915_gem_obj_ggtt_size(obj);
> > @@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
> >  			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
> >  		val |= I965_FENCE_REG_VALID;
> >  
> > -		I915_WRITE(fence_reg + 4, val >> 32);
> > -		POSTING_READ(fence_reg + 4);
> > +		I915_WRITE(fence_reg_hi, val >> 32);
> > +		POSTING_READ(fence_reg_hi);
> >  
> > -		I915_WRITE(fence_reg + 0, val);
> > -		POSTING_READ(fence_reg);
> > +		I915_WRITE(fence_reg_lo, val);
> > +		POSTING_READ(fence_reg_lo);
> >  	} else {
> > -		I915_WRITE(fence_reg + 4, 0);
> > -		POSTING_READ(fence_reg + 4);
> > +		I915_WRITE(fence_reg_hi, 0);
> > +		POSTING_READ(fence_reg_hi);
> >  	}
> >  }
> >  
> > @@ -149,13 +149,8 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
> >  	} else
> >  		val = 0;
> >  
> > -	if (reg < 8)
> > -		reg = FENCE_REG_830_0 + reg * 4;
> > -	else
> > -		reg = FENCE_REG_945_8 + (reg - 8) * 4;
> > -
> > -	I915_WRITE(reg, val);
> > -	POSTING_READ(reg);
> > +	I915_WRITE(FENCE_REG(reg), val);
> > +	POSTING_READ(FENCE_REG(reg));
> >  }
> >  
> >  static void i830_write_fence_reg(struct drm_device *dev, int reg,
> > @@ -186,8 +181,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
> >  	} else
> >  		val = 0;
> >  
> > -	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
> > -	POSTING_READ(FENCE_REG_830_0 + reg * 4);
> > +	I915_WRITE(FENCE_REG(reg), val);
> > +	POSTING_READ(FENCE_REG(reg));
> >  }
> >  
> >  inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index 3379f9c..3b574c2 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -786,20 +786,15 @@ static void i915_gem_record_fences(struct drm_device *dev,
> >  	int i;
> >  
> >  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
> > -		for (i = 0; i < 8; i++)
> > -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> > -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> > -			for (i = 0; i < 8; i++)
> > -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> > -							      (i * 4));
> > -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> > -		for (i = 0; i < 16; i++)
> > -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> > -						      (i * 8));
> > -	else if (INTEL_INFO(dev)->gen >= 6)
> >  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> > -						      (i * 8));
> > +			error->fence[i] = I915_READ(FENCE_REG(i));
> > +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> > +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> > +	} else if (INTEL_INFO(dev)->gen >= 6) {
> > +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> > +	}
> >  }
> >  
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 44cedbf..8133c7e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1436,9 +1436,15 @@ enum skl_disp_power_wells {
> >  
> >  /*
> >   * Fence registers
> > + * [0-7]  @ 0x2000 gen2,gen3
> > + * [8-15] @ 0x3000 945,g33,pnv
> > + *
> > + * [0-15] @ 0x3000 gen4,gen5
> > + *
> > + * [0-15] @ 0x100000 gen6,vlv,chv
> > + * [0-31] @ 0x100000 gen7+
> >   */
> > -#define FENCE_REG_830_0			0x2000
> > -#define FENCE_REG_945_8			0x3000
> > +#define FENCE_REG(i)			(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
> 
> I'd have appreciated the more obvious (i < 8 ? 0x2000 + i * 4 : 0x3000 +
> (i - 8) * 4) but meh.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> 
> 
> 
> >  #define   I830_FENCE_START_MASK		0x07f80000
> >  #define   I830_FENCE_TILING_Y_SHIFT	12
> >  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> > @@ -1451,14 +1457,16 @@ enum skl_disp_power_wells {
> >  #define   I915_FENCE_START_MASK		0x0ff00000
> >  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
> >  
> > -#define FENCE_REG_965_0			0x03000
> > +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> > +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
> >  #define   I965_FENCE_PITCH_SHIFT	2
> >  #define   I965_FENCE_TILING_Y_SHIFT	1
> >  #define   I965_FENCE_REG_VALID		(1<<0)
> >  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
> >  
> > -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> > -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> > +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> > +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> > +#define   GEN6_FENCE_PITCH_SHIFT	32
> >  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
> >  
> >  
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 05/43] drm/i915: Parametrize FBC_TAG registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 +-
 drivers/gpu/drm/i915/intel_fbc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b1cf17a..fcd1e81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2013,7 +2013,7 @@ enum skl_disp_power_wells {
 #define   FBC_CTL_CPU_FENCE	(1<<1)
 #define   FBC_CTL_PLANE(plane)	((plane)<<0)
 #define FBC_FENCE_OFF		0x03218 /* BSpec typo has 321Bh */
-#define FBC_TAG			0x03300
+#define FBC_TAG(i)		(0x03300 + (i) * 4)
 
 #define FBC_STATUS2		0x43214
 #define  FBC_COMPRESSION_MASK	0x7ff
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 1f97fb5..f8c527f 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -88,7 +88,7 @@ static void i8xx_fbc_enable(struct intel_crtc *crtc)
 
 	/* Clear old tags */
 	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
-		I915_WRITE(FBC_TAG + (i * 4), 0);
+		I915_WRITE(FBC_TAG(i), 0);
 
 	if (IS_GEN4(dev_priv)) {
 		u32 fbc_ctl2;
-- 
2.4.6

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Re: [PATCH 05/43] drm/i915: Parametrize FBC_TAG registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 2 +-
>  drivers/gpu/drm/i915/intel_fbc.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b1cf17a..fcd1e81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2013,7 +2013,7 @@ enum skl_disp_power_wells {
>  #define   FBC_CTL_CPU_FENCE	(1<<1)
>  #define   FBC_CTL_PLANE(plane)	((plane)<<0)
>  #define FBC_FENCE_OFF		0x03218 /* BSpec typo has 321Bh */
> -#define FBC_TAG			0x03300
> +#define FBC_TAG(i)		(0x03300 + (i) * 4)
>  
>  #define FBC_STATUS2		0x43214
>  #define  FBC_COMPRESSION_MASK	0x7ff
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 1f97fb5..f8c527f 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -88,7 +88,7 @@ static void i8xx_fbc_enable(struct intel_crtc *crtc)
>  
>  	/* Clear old tags */
>  	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
> -		I915_WRITE(FBC_TAG + (i * 4), 0);
> +		I915_WRITE(FBC_TAG(i), 0);
>  
>  	if (IS_GEN4(dev_priv)) {
>  		u32 fbc_ctl2;
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 06/43] drm/i915: Parametrize ILK turbo registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
 drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fcd1e81..b95f7f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2576,7 +2576,7 @@ enum skl_disp_power_wells {
 #define   TSFS_INTR_MASK	0x000000ff
 
 #define CRSTANDVID		0x11100
-#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
+#define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
 #define   PXVFREQ_PX_MASK	0x7f000000
 #define   PXVFREQ_PX_SHIFT	24
 #define VIDFREQ_BASE		0x11110
@@ -2760,8 +2760,8 @@ enum skl_disp_power_wells {
 #define CSIEW0			0x11250
 #define CSIEW1			0x11254
 #define CSIEW2			0x11258
-#define PEW			0x1125c
-#define DEW			0x11270
+#define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */
+#define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */
 #define MCHAFE			0x112c0
 #define CSIEC			0x112e0
 #define DMIEC			0x112e4
@@ -2785,8 +2785,8 @@ enum skl_disp_power_wells {
 #define EG5			0x11624
 #define EG6			0x11628
 #define EG7			0x1162c
-#define PXW			0x11664
-#define PXWL			0x11680
+#define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */
+#define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */
 #define LCFUSE02		0x116c0
 #define   LCFUSE_HIV_MASK	0x000000ff
 #define CSIPLL0			0x12c10
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62de97e..0320675 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4274,7 +4274,7 @@ static void ironlake_enable_drps(struct drm_device *dev)
 	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
 		MEMMODE_FSTART_SHIFT;
 
-	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
+	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
 		PXVFREQ_PX_SHIFT;
 
 	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
@@ -5877,7 +5877,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
 
 	assert_spin_locked(&mchdev_lock);
 
-	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
+	pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
 	pxvid = (pxvid >> 24) & 0x7f;
 	ext_v = pvid_to_extvid(dev_priv, pxvid);
 
@@ -6120,13 +6120,13 @@ static void intel_init_emon(struct drm_device *dev)
 	I915_WRITE(CSIEW2, 0x04000004);
 
 	for (i = 0; i < 5; i++)
-		I915_WRITE(PEW + (i * 4), 0);
+		I915_WRITE(PEW(i), 0);
 	for (i = 0; i < 3; i++)
-		I915_WRITE(DEW + (i * 4), 0);
+		I915_WRITE(DEW(i), 0);
 
 	/* Program P-state weights to account for frequency power adjustment */
 	for (i = 0; i < 16; i++) {
-		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
+		u32 pxvidfreq = I915_READ(PXVFREQ(i));
 		unsigned long freq = intel_pxfreq(pxvidfreq);
 		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
 			PXVFREQ_PX_SHIFT;
@@ -6147,7 +6147,7 @@ static void intel_init_emon(struct drm_device *dev)
 	for (i = 0; i < 4; i++) {
 		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
 			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
-		I915_WRITE(PXW + (i * 4), val);
+		I915_WRITE(PXW(i), val);
 	}
 
 	/* Adjust magic regs to magic values (more experimental results) */
@@ -6163,7 +6163,7 @@ static void intel_init_emon(struct drm_device *dev)
 	I915_WRITE(EG7, 0);
 
 	for (i = 0; i < 8; i++)
-		I915_WRITE(PXWL + (i * 4), 0);
+		I915_WRITE(PXWL(i), 0);
 
 	/* Enable PMON + select events */
 	I915_WRITE(ECR, 0x80000019);
-- 
2.4.6

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Re: [PATCH 06/43] drm/i915: Parametrize ILK turbo registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
>  drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
>  2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fcd1e81..b95f7f1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2576,7 +2576,7 @@ enum skl_disp_power_wells {
>  #define   TSFS_INTR_MASK	0x000000ff
>  
>  #define CRSTANDVID		0x11100
> -#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
> +#define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
>  #define   PXVFREQ_PX_MASK	0x7f000000
>  #define   PXVFREQ_PX_SHIFT	24
>  #define VIDFREQ_BASE		0x11110
> @@ -2760,8 +2760,8 @@ enum skl_disp_power_wells {
>  #define CSIEW0			0x11250
>  #define CSIEW1			0x11254
>  #define CSIEW2			0x11258
> -#define PEW			0x1125c
> -#define DEW			0x11270
> +#define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */
> +#define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */
>  #define MCHAFE			0x112c0
>  #define CSIEC			0x112e0
>  #define DMIEC			0x112e4
> @@ -2785,8 +2785,8 @@ enum skl_disp_power_wells {
>  #define EG5			0x11624
>  #define EG6			0x11628
>  #define EG7			0x1162c
> -#define PXW			0x11664
> -#define PXWL			0x11680
> +#define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */
> +#define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */
>  #define LCFUSE02		0x116c0
>  #define   LCFUSE_HIV_MASK	0x000000ff
>  #define CSIPLL0			0x12c10
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 62de97e..0320675 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4274,7 +4274,7 @@ static void ironlake_enable_drps(struct drm_device *dev)
>  	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
>  		MEMMODE_FSTART_SHIFT;
>  
> -	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
> +	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
>  		PXVFREQ_PX_SHIFT;
>  
>  	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
> @@ -5877,7 +5877,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
>  
>  	assert_spin_locked(&mchdev_lock);
>  
> -	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
> +	pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
>  	pxvid = (pxvid >> 24) & 0x7f;
>  	ext_v = pvid_to_extvid(dev_priv, pxvid);
>  
> @@ -6120,13 +6120,13 @@ static void intel_init_emon(struct drm_device *dev)
>  	I915_WRITE(CSIEW2, 0x04000004);
>  
>  	for (i = 0; i < 5; i++)
> -		I915_WRITE(PEW + (i * 4), 0);
> +		I915_WRITE(PEW(i), 0);
>  	for (i = 0; i < 3; i++)
> -		I915_WRITE(DEW + (i * 4), 0);
> +		I915_WRITE(DEW(i), 0);
>  
>  	/* Program P-state weights to account for frequency power adjustment */
>  	for (i = 0; i < 16; i++) {
> -		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
> +		u32 pxvidfreq = I915_READ(PXVFREQ(i));
>  		unsigned long freq = intel_pxfreq(pxvidfreq);
>  		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
>  			PXVFREQ_PX_SHIFT;
> @@ -6147,7 +6147,7 @@ static void intel_init_emon(struct drm_device *dev)
>  	for (i = 0; i < 4; i++) {
>  		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
>  			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
> -		I915_WRITE(PXW + (i * 4), val);
> +		I915_WRITE(PXW(i), val);
>  	}
>  
>  	/* Adjust magic regs to magic values (more experimental results) */
> @@ -6163,7 +6163,7 @@ static void intel_init_emon(struct drm_device *dev)
>  	I915_WRITE(EG7, 0);
>  
>  	for (i = 0; i < 8; i++)
> -		I915_WRITE(PXWL + (i * 4), 0);
> +		I915_WRITE(PXWL(i), 0);
>  
>  	/* Enable PMON + select events */
>  	I915_WRITE(ECR, 0x80000019);
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 07/43] drm/i915: Replace raw numbers with the approproate register name in ILK turbo code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0320675..dc765eb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4305,10 +4305,10 @@ static void ironlake_enable_drps(struct drm_device *dev)
 
 	ironlake_set_drps(dev, fstart);
 
-	dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
-		I915_READ(0x112e0);
+	dev_priv->ips.last_count1 = I915_READ(DMIEC) +
+		I915_READ(DDREC) + I915_READ(CSIEC);
 	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
-	dev_priv->ips.last_count2 = I915_READ(0x112f4);
+	dev_priv->ips.last_count2 = I915_READ(GFXEC);
 	dev_priv->ips.last_time2 = ktime_get_raw_ns();
 
 	spin_unlock_irq(&mchdev_lock);
-- 
2.4.6

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Re: [PATCH 07/43] drm/i915: Replace raw numbers with the approproate register name in ILK turbo code

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0320675..dc765eb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4305,10 +4305,10 @@ static void ironlake_enable_drps(struct drm_device *dev)
>  
>  	ironlake_set_drps(dev, fstart);
>  
> -	dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
> -		I915_READ(0x112e0);
> +	dev_priv->ips.last_count1 = I915_READ(DMIEC) +
> +		I915_READ(DDREC) + I915_READ(CSIEC);
>  	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
> -	dev_priv->ips.last_count2 = I915_READ(0x112f4);
> +	dev_priv->ips.last_count2 = I915_READ(GFXEC);
>  	dev_priv->ips.last_time2 = ktime_get_raw_ns();
>  
>  	spin_unlock_irq(&mchdev_lock);
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 08/43] drm/i915: Parametrize TV luma/chroma filter registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 12 ++++--------
 drivers/gpu/drm/i915/intel_tv.c |  8 ++++----
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b95f7f1..13b52f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4079,14 +4079,10 @@ enum skl_disp_power_wells {
 # define TV_CC_DATA_1_MASK		0x0000007f
 # define TV_CC_DATA_1_SHIFT		0
 
-#define TV_H_LUMA_0		0x68100
-#define TV_H_LUMA_59		0x681ec
-#define TV_H_CHROMA_0		0x68200
-#define TV_H_CHROMA_59		0x682ec
-#define TV_V_LUMA_0		0x68300
-#define TV_V_LUMA_42		0x683a8
-#define TV_V_CHROMA_0		0x68400
-#define TV_V_CHROMA_42		0x684a8
+#define TV_H_LUMA(i)		(0x68100 + (i) * 4) /* 60 registers */
+#define TV_H_CHROMA(i)		(0x68200 + (i) * 4) /* 60 registers */
+#define TV_V_LUMA(i)		(0x68300 + (i) * 4) /* 43 registers */
+#define TV_V_CHROMA(i)		(0x68400 + (i) * 4) /* 43 registers */
 
 /* Display Port */
 #define DP_A				0x64000 /* eDP */
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 29983cba..6bea789 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1138,13 +1138,13 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder)
 
 	j = 0;
 	for (i = 0; i < 60; i++)
-		I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
+		I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
 	for (i = 0; i < 60; i++)
-		I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
+		I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
 	for (i = 0; i < 43; i++)
-		I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
+		I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
 	for (i = 0; i < 43; i++)
-		I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
+		I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
 	I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
 	I915_WRITE(TV_CTL, tv_ctl);
 }
-- 
2.4.6

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Re: [PATCH 08/43] drm/i915: Parametrize TV luma/chroma filter registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 12 ++++--------
>  drivers/gpu/drm/i915/intel_tv.c |  8 ++++----
>  2 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b95f7f1..13b52f7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4079,14 +4079,10 @@ enum skl_disp_power_wells {
>  # define TV_CC_DATA_1_MASK		0x0000007f
>  # define TV_CC_DATA_1_SHIFT		0
>  
> -#define TV_H_LUMA_0		0x68100
> -#define TV_H_LUMA_59		0x681ec
> -#define TV_H_CHROMA_0		0x68200
> -#define TV_H_CHROMA_59		0x682ec
> -#define TV_V_LUMA_0		0x68300
> -#define TV_V_LUMA_42		0x683a8
> -#define TV_V_CHROMA_0		0x68400
> -#define TV_V_CHROMA_42		0x684a8
> +#define TV_H_LUMA(i)		(0x68100 + (i) * 4) /* 60 registers */
> +#define TV_H_CHROMA(i)		(0x68200 + (i) * 4) /* 60 registers */
> +#define TV_V_LUMA(i)		(0x68300 + (i) * 4) /* 43 registers */
> +#define TV_V_CHROMA(i)		(0x68400 + (i) * 4) /* 43 registers */
>  
>  /* Display Port */
>  #define DP_A				0x64000 /* eDP */
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index 29983cba..6bea789 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -1138,13 +1138,13 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder)
>  
>  	j = 0;
>  	for (i = 0; i < 60; i++)
> -		I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
> +		I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
>  	for (i = 0; i < 60; i++)
> -		I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
> +		I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
>  	for (i = 0; i < 43; i++)
> -		I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
> +		I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
>  	for (i = 0; i < 43; i++)
> -		I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
> +		I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
>  	I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
>  	I915_WRITE(TV_CTL, tv_ctl);
>  }
> -- 
> 2.4.6
>
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 09/43] drm/i915: Parametrize DDI_BUF_TRANS registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

FIXME: Should there be a WARN(i != 9) or something, or what does the
entry 9 comment mean?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 ++-
 drivers/gpu/drm/i915/intel_ddi.c | 19 +++++++++----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13b52f7..61414c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7194,7 +7194,8 @@ enum skl_disp_power_wells {
 /* DDI Buffer Translations */
 #define DDI_BUF_TRANS_A				0x64E00
 #define DDI_BUF_TRANS_B				0x64E60
-#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
+#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8)
+#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5b600bf..9e640ea 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -414,7 +414,6 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
 				      bool supports_hdmi)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg;
 	u32 iboost_bit = 0;
 	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 	    size;
@@ -505,11 +504,11 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
 		BUG();
 	}
 
-	for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
-		I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit);
-		reg += 4;
-		I915_WRITE(reg, ddi_translations[i].trans2);
-		reg += 4;
+	for (i = 0; i < size; i++) {
+		I915_WRITE(DDI_BUF_TRANS_LO(port, i),
+			   ddi_translations[i].trans1 | iboost_bit);
+		I915_WRITE(DDI_BUF_TRANS_HI(port, i),
+			   ddi_translations[i].trans2);
 	}
 
 	if (!supports_hdmi)
@@ -521,10 +520,10 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
 		hdmi_level = hdmi_default_entry;
 
 	/* Entry 9 is for HDMI: */
-	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
-	reg += 4;
-	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
-	reg += 4;
+	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
+		   ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
+	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
+		   ddi_translations_hdmi[hdmi_level].trans2);
 }
 
 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
-- 
2.4.6

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Re: [PATCH 09/43] drm/i915: Parametrize DDI_BUF_TRANS registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> FIXME: Should there be a WARN(i != 9) or something, or what does the
> entry 9 comment mean?

Either the code, the comment, or both are bust. Needs to be checked.

However, this patch does not change that part for the better or for
worse, so

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 ++-
>  drivers/gpu/drm/i915/intel_ddi.c | 19 +++++++++----------
>  2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 13b52f7..61414c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7194,7 +7194,8 @@ enum skl_disp_power_wells {
>  /* DDI Buffer Translations */
>  #define DDI_BUF_TRANS_A				0x64E00
>  #define DDI_BUF_TRANS_B				0x64E60
> -#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
> +#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8)
> +#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4)
>  
>  /* Sideband Interface (SBI) is programmed indirectly, via
>   * SBI_ADDR, which contains the register offset; and SBI_DATA,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5b600bf..9e640ea 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -414,7 +414,6 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
>  				      bool supports_hdmi)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg;
>  	u32 iboost_bit = 0;
>  	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
>  	    size;
> @@ -505,11 +504,11 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
>  		BUG();
>  	}
>  
> -	for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
> -		I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit);
> -		reg += 4;
> -		I915_WRITE(reg, ddi_translations[i].trans2);
> -		reg += 4;
> +	for (i = 0; i < size; i++) {
> +		I915_WRITE(DDI_BUF_TRANS_LO(port, i),
> +			   ddi_translations[i].trans1 | iboost_bit);
> +		I915_WRITE(DDI_BUF_TRANS_HI(port, i),
> +			   ddi_translations[i].trans2);
>  	}
>  
>  	if (!supports_hdmi)
> @@ -521,10 +520,10 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
>  		hdmi_level = hdmi_default_entry;
>  
>  	/* Entry 9 is for HDMI: */
> -	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
> -	reg += 4;
> -	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
> -	reg += 4;
> +	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
> +		   ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
> +	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
> +		   ddi_translations_hdmi[hdmi_level].trans2);
>  }
>  
>  /* Program DDI buffers translations for DP. By default, program ports A-D in DP
> -- 
> 2.4.6
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index b69264d..8174335 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -48,7 +48,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
 /*
 * SKL CSR registers for DC5 and DC6
 */
-#define CSR_PROGRAM_BASE		0x80000
+#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
 #define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
 #define CSR_HTP_ADDR_SKL		0x00500034
 #define CSR_SSP_BASE			0x8F074
@@ -255,8 +255,7 @@ void intel_csr_load_program(struct drm_device *dev)
 	mutex_lock(&dev_priv->csr_lock);
 	fw_size = dev_priv->csr.dmc_fw_size;
 	for (i = 0; i < fw_size; i++)
-		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
-			payload[i]);
+		I915_WRITE(CSR_PROGRAM(i), payload[i]);
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
@@ -456,7 +455,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
 {
 	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
 		  "CSR is not loaded.\n");
-	WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
+	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 		  "CSR program storage start is NULL\n");
 	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
-- 
2.4.6

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Re: [PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers

[Mika Kuoppala]

ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_csr.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index b69264d..8174335 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -48,7 +48,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
>  /*
>  * SKL CSR registers for DC5 and DC6
>  */
> -#define CSR_PROGRAM_BASE		0x80000
> +#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
>  #define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
>  #define CSR_HTP_ADDR_SKL		0x00500034
>  #define CSR_SSP_BASE			0x8F074
> @@ -255,8 +255,7 @@ void intel_csr_load_program(struct drm_device *dev)
>  	mutex_lock(&dev_priv->csr_lock);
>  	fw_size = dev_priv->csr.dmc_fw_size;
>  	for (i = 0; i < fw_size; i++)
> -		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
> -			payload[i]);
> +		I915_WRITE(CSR_PROGRAM(i), payload[i]);
>  
>  	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
>  		I915_WRITE(dev_priv->csr.mmioaddr[i],
> @@ -456,7 +455,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
>  {
>  	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
>  		  "CSR is not loaded.\n");
> -	WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
> +	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
>  		  "CSR program storage start is NULL\n");
>  	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
>  	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
> -- 
> 2.4.6
>
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Re: [PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers

[Daniel Vetter]

On Wed, Sep 23, 2015 at 05:15:55PM +0300, Mika Kuoppala wrote:
> ville.syrjala@linux.intel.com writes:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Merged the reviewed patches up to this one to dinq, thanks.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_csr.c | 7 +++----
> >  1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > index b69264d..8174335 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -48,7 +48,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
> >  /*
> >  * SKL CSR registers for DC5 and DC6
> >  */
> > -#define CSR_PROGRAM_BASE		0x80000
> > +#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
> >  #define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
> >  #define CSR_HTP_ADDR_SKL		0x00500034
> >  #define CSR_SSP_BASE			0x8F074
> > @@ -255,8 +255,7 @@ void intel_csr_load_program(struct drm_device *dev)
> >  	mutex_lock(&dev_priv->csr_lock);
> >  	fw_size = dev_priv->csr.dmc_fw_size;
> >  	for (i = 0; i < fw_size; i++)
> > -		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
> > -			payload[i]);
> > +		I915_WRITE(CSR_PROGRAM(i), payload[i]);
> >  
> >  	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
> >  		I915_WRITE(dev_priv->csr.mmioaddr[i],
> > @@ -456,7 +455,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
> >  {
> >  	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
> >  		  "CSR is not loaded.\n");
> > -	WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
> > +	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
> >  		  "CSR program storage start is NULL\n");
> >  	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
> >  	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h     | 2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 8c8e574..848a563 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -40,7 +40,7 @@
 
 #define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
 
-#define UOS_RSA_SCRATCH_0		0xc200
+#define UOS_RSA_SCRATCH(i)		(0xc200 + (i) * 4)
 #define DMA_ADDR_0_LOW			0xc300
 #define DMA_ADDR_0_HIGH			0xc304
 #define DMA_ADDR_1_LOW			0xc308
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index e0601cc..7432832 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -257,7 +257,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 	/* Copy RSA signature from the fw image to HW for verification */
 	sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
 	for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
-		I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
+		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 
 	/* Set the source address for the new blob */
 	offset = i915_gem_obj_ggtt_offset(fw_obj);
-- 
2.4.6

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Re: [PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_guc_reg.h     | 2 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 8c8e574..848a563 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -40,7 +40,7 @@
>  
>  #define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
>  
> -#define UOS_RSA_SCRATCH_0		0xc200
> +#define UOS_RSA_SCRATCH(i)		(0xc200 + (i) * 4)
>  #define DMA_ADDR_0_LOW			0xc300
>  #define DMA_ADDR_0_HIGH			0xc304
>  #define DMA_ADDR_1_LOW			0xc308
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index e0601cc..7432832 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -257,7 +257,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
>  	/* Copy RSA signature from the fw image to HW for verification */
>  	sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
>  	for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
> -		I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
> +		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
>  
>  	/* Set the source address for the new blob */
>  	offset = i915_gem_obj_ggtt_offset(fw_obj);
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8786281..2b6dd70 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2879,8 +2879,8 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
-	I915_WRITE(GEN8_PRIVATE_PAT, pat);
-	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
 }
 
 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
@@ -2914,8 +2914,8 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
 	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
 
-	I915_WRITE(GEN8_PRIVATE_PAT, pat);
-	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
 }
 
 static int gen8_gmch_probe(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61414c8..a04fa2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1544,7 +1544,8 @@ enum skl_disp_power_wells {
 #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
 #define   RING_FAULT_VALID	(1<<0)
 #define DONE_REG		0x40b0
-#define GEN8_PRIVATE_PAT	0x40e0
+#define GEN8_PRIVATE_PAT_LO	0x40e0
+#define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
 #define BSD_HWS_PGA_GEN7	(0x04180)
 #define BLT_HWS_PGA_GEN7	(0x04280)
 #define VEBOX_HWS_PGA_GEN7	(0x04380)
-- 
2.4.6

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Re: [PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
>  2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8786281..2b6dd70 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2879,8 +2879,8 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
>  
>  	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
>  	 * write would work. */
> -	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> -	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
> +	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
>  }
>  
>  static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
> @@ -2914,8 +2914,8 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
>  	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
>  	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
>  
> -	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> -	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
> +	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
>  }
>  
>  static int gen8_gmch_probe(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 61414c8..a04fa2a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1544,7 +1544,8 @@ enum skl_disp_power_wells {
>  #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
>  #define   RING_FAULT_VALID	(1<<0)
>  #define DONE_REG		0x40b0
> -#define GEN8_PRIVATE_PAT	0x40e0
> +#define GEN8_PRIVATE_PAT_LO	0x40e0
> +#define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
>  #define BSD_HWS_PGA_GEN7	(0x04180)
>  #define BLT_HWS_PGA_GEN7	(0x04280)
>  #define VEBOX_HWS_PGA_GEN7	(0x04380)
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5615d3d..24baa5a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2231,10 +2231,9 @@ static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
 	for_each_ring(ring, dev_priv, unused) {
 		seq_printf(m, "%s\n", ring->name);
 		for (i = 0; i < 4; i++) {
-			u32 offset = 0x270 + i * 8;
-			u64 pdp = I915_READ(ring->mmio_base + offset + 4);
+			u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
 			pdp <<= 32;
-			pdp |= I915_READ(ring->mmio_base + offset);
+			pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
 			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
 		}
 	}
-- 
2.4.6

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Re: [PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5615d3d..24baa5a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2231,10 +2231,9 @@ static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
>  	for_each_ring(ring, dev_priv, unused) {
>  		seq_printf(m, "%s\n", ring->name);
>  		for (i = 0; i < 4; i++) {
> -			u32 offset = 0x270 + i * 8;
> -			u64 pdp = I915_READ(ring->mmio_base + offset + 4);
> +			u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
>  			pdp <<= 32;
> -			pdp |= I915_READ(ring->mmio_base + offset);
> +			pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
>  			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
>  		}
>  	}
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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_______________________________________________
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[PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a04fa2a..610ce25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -105,7 +105,7 @@
 #define  GRDOM_RESET_STATUS (1<<1)
 #define  GRDOM_RESET_ENABLE (1<<0)
 
-#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
+#define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
 #define  ILK_GRDOM_FULL		(0<<1)
 #define  ILK_GRDOM_RENDER	(1<<1)
 #define  ILK_GRDOM_MEDIA	(3<<1)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 440e2a5..3294f63 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1429,21 +1429,21 @@ static int ironlake_do_reset(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+	I915_WRITE(ILK_GDSR,
 		   ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
-	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+	ret = wait_for((I915_READ(ILK_GDSR) &
 			ILK_GRDOM_RESET_ENABLE) == 0, 500);
 	if (ret)
 		return ret;
 
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+	I915_WRITE(ILK_GDSR,
 		   ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
-	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+	ret = wait_for((I915_READ(ILK_GDSR) &
 			ILK_GRDOM_RESET_ENABLE) == 0, 500);
 	if (ret)
 		return ret;
 
-	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
+	I915_WRITE(ILK_GDSR, 0);
 
 	return 0;
 }
-- 
2.4.6

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Re: [PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
>  drivers/gpu/drm/i915/intel_uncore.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a04fa2a..610ce25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -105,7 +105,7 @@
>  #define  GRDOM_RESET_STATUS (1<<1)
>  #define  GRDOM_RESET_ENABLE (1<<0)
>  
> -#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
> +#define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
>  #define  ILK_GRDOM_FULL		(0<<1)
>  #define  ILK_GRDOM_RENDER	(1<<1)
>  #define  ILK_GRDOM_MEDIA	(3<<1)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 440e2a5..3294f63 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1429,21 +1429,21 @@ static int ironlake_do_reset(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int ret;
>  
> -	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> +	I915_WRITE(ILK_GDSR,
>  		   ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> -	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> +	ret = wait_for((I915_READ(ILK_GDSR) &
>  			ILK_GRDOM_RESET_ENABLE) == 0, 500);
>  	if (ret)
>  		return ret;
>  
> -	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> +	I915_WRITE(ILK_GDSR,
>  		   ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> -	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> +	ret = wait_for((I915_READ(ILK_GDSR) &
>  			ILK_GRDOM_RESET_ENABLE) == 0, 500);
>  	if (ret)
>  		return ret;
>  
> -	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
> +	I915_WRITE(ILK_GDSR, 0);
>  
>  	return 0;
>  }
> -- 
> 2.4.6
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  6 +++---
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++++------
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 610ce25..93cb6ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2478,8 +2478,8 @@ enum skl_disp_power_wells {
 #define PALETTE_A_OFFSET 0xa000
 #define PALETTE_B_OFFSET 0xa800
 #define CHV_PALETTE_C_OFFSET 0xc000
-#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
-		       dev_priv->info.display_mmio_offset)
+#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
+			  dev_priv->info.display_mmio_offset + (i) * 4)
 
 /* MCH MMIO space */
 
@@ -5629,7 +5629,7 @@ enum skl_disp_power_wells {
 /* legacy palette */
 #define _LGC_PALETTE_A           0x4a000
 #define _LGC_PALETTE_B           0x4a800
-#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
+#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
 
 #define _GAMMA_MODE_A		0x4a480
 #define _GAMMA_MODE_B		0x4ac80
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc00867..f385dd3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4558,7 +4558,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
-	int palreg = PALETTE(pipe);
 	int i;
 	bool reenable_ips = false;
 
@@ -4573,10 +4572,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
 			assert_pll_enabled(dev_priv, pipe);
 	}
 
-	/* use legacy palette for Ironlake */
-	if (!HAS_GMCH_DISPLAY(dev))
-		palreg = LGC_PALETTE(pipe);
-
 	/* Workaround : Do not read or write the pipe palette/gamma data while
 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 	 */
@@ -4588,7 +4583,14 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
 	}
 
 	for (i = 0; i < 256; i++) {
-		I915_WRITE(palreg + 4 * i,
+		u32 palreg;
+
+		if (HAS_GMCH_DISPLAY(dev))
+			palreg = PALETTE(pipe, i);
+		else
+			palreg = LGC_PALETTE(pipe, i);
+
+		I915_WRITE(palreg,
 			   (intel_crtc->lut_r[i] << 16) |
 			   (intel_crtc->lut_g[i] << 8) |
 			   intel_crtc->lut_b[i]);
-- 
2.4.6

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Re: [PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  6 +++---
>  drivers/gpu/drm/i915/intel_display.c | 14 ++++++++------
>  2 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 610ce25..93cb6ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2478,8 +2478,8 @@ enum skl_disp_power_wells {
>  #define PALETTE_A_OFFSET 0xa000
>  #define PALETTE_B_OFFSET 0xa800
>  #define CHV_PALETTE_C_OFFSET 0xc000
> -#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
> -		       dev_priv->info.display_mmio_offset)
> +#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
> +			  dev_priv->info.display_mmio_offset + (i) * 4)
>  
>  /* MCH MMIO space */
>  
> @@ -5629,7 +5629,7 @@ enum skl_disp_power_wells {
>  /* legacy palette */
>  #define _LGC_PALETTE_A           0x4a000
>  #define _LGC_PALETTE_B           0x4a800
> -#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
> +#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
>  
>  #define _GAMMA_MODE_A		0x4a480
>  #define _GAMMA_MODE_B		0x4ac80
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fc00867..f385dd3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4558,7 +4558,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	enum pipe pipe = intel_crtc->pipe;
> -	int palreg = PALETTE(pipe);
>  	int i;
>  	bool reenable_ips = false;
>  
> @@ -4573,10 +4572,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
>  			assert_pll_enabled(dev_priv, pipe);
>  	}
>  
> -	/* use legacy palette for Ironlake */
> -	if (!HAS_GMCH_DISPLAY(dev))
> -		palreg = LGC_PALETTE(pipe);
> -
>  	/* Workaround : Do not read or write the pipe palette/gamma data while
>  	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
>  	 */
> @@ -4588,7 +4583,14 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
>  	}
>  
>  	for (i = 0; i < 256; i++) {
> -		I915_WRITE(palreg + 4 * i,
> +		u32 palreg;
> +
> +		if (HAS_GMCH_DISPLAY(dev))
> +			palreg = PALETTE(pipe, i);
> +		else
> +			palreg = LGC_PALETTE(pipe, i);
> +
> +		I915_WRITE(palreg,
>  			   (intel_crtc->lut_r[i] << 16) |
>  			   (intel_crtc->lut_g[i] << 8) |
>  			   intel_crtc->lut_b[i]);
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24baa5a..47ef007 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2905,7 +2905,7 @@ static bool cursor_active(struct drm_device *dev, int pipe)
 	u32 state;
 
 	if (IS_845G(dev) || IS_I865G(dev))
-		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 	else
 		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f385dd3..7343e14 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1295,7 +1295,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
 	bool cur_state;
 
 	if (IS_845G(dev) || IS_I865G(dev))
-		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 	else
 		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
@@ -9850,8 +9850,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 		/* On these chipsets we can only modify the base/size/stride
 		 * whilst the cursor is disabled.
 		 */
-		I915_WRITE(_CURACNTR, 0);
-		POSTING_READ(_CURACNTR);
+		I915_WRITE(CURCNTR(PIPE_A), 0);
+		POSTING_READ(CURCNTR(PIPE_A));
 		intel_crtc->cursor_cntl = 0;
 	}
 
@@ -9866,8 +9866,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 	}
 
 	if (intel_crtc->cursor_cntl != cntl) {
-		I915_WRITE(_CURACNTR, cntl);
-		POSTING_READ(_CURACNTR);
+		I915_WRITE(CURCNTR(PIPE_A), cntl);
+		POSTING_READ(CURCNTR(PIPE_A));
 		intel_crtc->cursor_cntl = cntl;
 	}
 }
-- 
2.4.6

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[PATCH v2 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Deal with _CURABASE too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24baa5a..47ef007 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2905,7 +2905,7 @@ static bool cursor_active(struct drm_device *dev, int pipe)
 	u32 state;
 
 	if (IS_845G(dev) || IS_I865G(dev))
-		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 	else
 		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f385dd3..6732733 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1295,7 +1295,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
 	bool cur_state;
 
 	if (IS_845G(dev) || IS_I865G(dev))
-		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 	else
 		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
@@ -9850,13 +9850,13 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 		/* On these chipsets we can only modify the base/size/stride
 		 * whilst the cursor is disabled.
 		 */
-		I915_WRITE(_CURACNTR, 0);
-		POSTING_READ(_CURACNTR);
+		I915_WRITE(CURCNTR(PIPE_A), 0);
+		POSTING_READ(CURCNTR(PIPE_A));
 		intel_crtc->cursor_cntl = 0;
 	}
 
 	if (intel_crtc->cursor_base != base) {
-		I915_WRITE(_CURABASE, base);
+		I915_WRITE(CURBASE(PIPE_A), base);
 		intel_crtc->cursor_base = base;
 	}
 
@@ -9866,8 +9866,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 	}
 
 	if (intel_crtc->cursor_cntl != cntl) {
-		I915_WRITE(_CURACNTR, cntl);
-		POSTING_READ(_CURACNTR);
+		I915_WRITE(CURCNTR(PIPE_A), cntl);
+		POSTING_READ(CURCNTR(PIPE_A));
 		intel_crtc->cursor_cntl = cntl;
 	}
 }
-- 
2.4.6

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Re: [PATCH v2 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

[Jani Nikula]

On Tue, 22 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> v2: Deal with _CURABASE too

Yeah better, though I was happy with v1 too. :)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
>  2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 24baa5a..47ef007 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2905,7 +2905,7 @@ static bool cursor_active(struct drm_device *dev, int pipe)
>  	u32 state;
>  
>  	if (IS_845G(dev) || IS_I865G(dev))
> -		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
> +		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
>  	else
>  		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f385dd3..6732733 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1295,7 +1295,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
>  	bool cur_state;
>  
>  	if (IS_845G(dev) || IS_I865G(dev))
> -		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
> +		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
>  	else
>  		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
>  
> @@ -9850,13 +9850,13 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
>  		/* On these chipsets we can only modify the base/size/stride
>  		 * whilst the cursor is disabled.
>  		 */
> -		I915_WRITE(_CURACNTR, 0);
> -		POSTING_READ(_CURACNTR);
> +		I915_WRITE(CURCNTR(PIPE_A), 0);
> +		POSTING_READ(CURCNTR(PIPE_A));
>  		intel_crtc->cursor_cntl = 0;
>  	}
>  
>  	if (intel_crtc->cursor_base != base) {
> -		I915_WRITE(_CURABASE, base);
> +		I915_WRITE(CURBASE(PIPE_A), base);
>  		intel_crtc->cursor_base = base;
>  	}
>  
> @@ -9866,8 +9866,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
>  	}
>  
>  	if (intel_crtc->cursor_cntl != cntl) {
> -		I915_WRITE(_CURACNTR, cntl);
> -		POSTING_READ(_CURACNTR);
> +		I915_WRITE(CURCNTR(PIPE_A), cntl);
> +		POSTING_READ(CURCNTR(PIPE_A));
>  		intel_crtc->cursor_cntl = cntl;
>  	}
>  }
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v2 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

[Daniel Vetter]

On Mon, Sep 28, 2015 at 02:50:01PM +0300, Jani Nikula wrote:
> On Tue, 22 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > v2: Deal with _CURABASE too
> 
> Yeah better, though I was happy with v1 too. :)
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Merged up to this patch to dinq, thanks.
-Daniel

> 
> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
> >  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> >  2 files changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 24baa5a..47ef007 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2905,7 +2905,7 @@ static bool cursor_active(struct drm_device *dev, int pipe)
> >  	u32 state;
> >  
> >  	if (IS_845G(dev) || IS_I865G(dev))
> > -		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
> > +		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> >  	else
> >  		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f385dd3..6732733 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1295,7 +1295,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
> >  	bool cur_state;
> >  
> >  	if (IS_845G(dev) || IS_I865G(dev))
> > -		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
> > +		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> >  	else
> >  		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> >  
> > @@ -9850,13 +9850,13 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
> >  		/* On these chipsets we can only modify the base/size/stride
> >  		 * whilst the cursor is disabled.
> >  		 */
> > -		I915_WRITE(_CURACNTR, 0);
> > -		POSTING_READ(_CURACNTR);
> > +		I915_WRITE(CURCNTR(PIPE_A), 0);
> > +		POSTING_READ(CURCNTR(PIPE_A));
> >  		intel_crtc->cursor_cntl = 0;
> >  	}
> >  
> >  	if (intel_crtc->cursor_base != base) {
> > -		I915_WRITE(_CURABASE, base);
> > +		I915_WRITE(CURBASE(PIPE_A), base);
> >  		intel_crtc->cursor_base = base;
> >  	}
> >  
> > @@ -9866,8 +9866,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
> >  	}
> >  
> >  	if (intel_crtc->cursor_cntl != cntl) {
> > -		I915_WRITE(_CURACNTR, cntl);
> > -		POSTING_READ(_CURACNTR);
> > +		I915_WRITE(CURCNTR(PIPE_A), cntl);
> > +		POSTING_READ(CURCNTR(PIPE_A));
> >  		intel_crtc->cursor_cntl = cntl;
> >  	}
> >  }
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 24baa5a..47ef007 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2905,7 +2905,7 @@ static bool cursor_active(struct drm_device *dev, int pipe)
>  	u32 state;
>  
>  	if (IS_845G(dev) || IS_I865G(dev))
> -		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
> +		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
>  	else
>  		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f385dd3..7343e14 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1295,7 +1295,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
>  	bool cur_state;
>  
>  	if (IS_845G(dev) || IS_I865G(dev))
> -		cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
> +		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
>  	else
>  		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
>  
> @@ -9850,8 +9850,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
>  		/* On these chipsets we can only modify the base/size/stride
>  		 * whilst the cursor is disabled.
>  		 */
> -		I915_WRITE(_CURACNTR, 0);
> -		POSTING_READ(_CURACNTR);
> +		I915_WRITE(CURCNTR(PIPE_A), 0);
> +		POSTING_READ(CURCNTR(PIPE_A));
>  		intel_crtc->cursor_cntl = 0;
>  	}
>  
> @@ -9866,8 +9866,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
>  	}
>  
>  	if (intel_crtc->cursor_cntl != cntl) {
> -		I915_WRITE(_CURACNTR, cntl);
> -		POSTING_READ(_CURACNTR);
> +		I915_WRITE(CURCNTR(PIPE_A), cntl);
> +		POSTING_READ(CURCNTR(PIPE_A));
>  		intel_crtc->cursor_cntl = cntl;
>  	}
>  }
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 17/43] drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c | 46 ++++++++++++++++++++--------------------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index af5e43b..086b5c5 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -891,7 +891,7 @@ void intel_crt_init(struct drm_device *dev)
 		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 				 FDI_RX_LINK_REVERSAL_OVERRIDE;
 
-		dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
+		dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
 	}
 
 	intel_crt_reset(connector);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9e640ea..b885b70 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -592,7 +592,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 	 *
 	 * WaFDIAutoLinkSetTimingOverrride:hsw
 	 */
-	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
+	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 				  FDI_RX_PWRDN_LANE0_VAL(2) |
 				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 
@@ -600,13 +600,13 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 		     FDI_RX_PLL_ENABLE |
 		     FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
-	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-	POSTING_READ(_FDI_RXA_CTL);
+	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
+	POSTING_READ(FDI_RX_CTL(PIPE_A));
 	udelay(220);
 
 	/* Switch from Rawclk to PCDclk */
 	rx_ctl_val |= FDI_PCDCLK;
-	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 
 	/* Configure Port Clock Select */
 	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
@@ -635,21 +635,21 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		udelay(600);
 
 		/* Program PCH FDI Receiver TU */
-		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
+		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 
 		/* Enable PCH FDI Receiver with auto-training */
 		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
-		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-		POSTING_READ(_FDI_RXA_CTL);
+		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
+		POSTING_READ(FDI_RX_CTL(PIPE_A));
 
 		/* Wait for FDI receiver lane calibration */
 		udelay(30);
 
 		/* Unset FDI_RX_MISC pwrdn lanes */
-		temp = I915_READ(_FDI_RXA_MISC);
+		temp = I915_READ(FDI_RX_MISC(PIPE_A));
 		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
-		I915_WRITE(_FDI_RXA_MISC, temp);
-		POSTING_READ(_FDI_RXA_MISC);
+		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
+		POSTING_READ(FDI_RX_MISC(PIPE_A));
 
 		/* Wait for FDI auto training time */
 		udelay(5);
@@ -683,15 +683,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 
 		rx_ctl_val &= ~FDI_RX_ENABLE;
-		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-		POSTING_READ(_FDI_RXA_CTL);
+		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
+		POSTING_READ(FDI_RX_CTL(PIPE_A));
 
 		/* Reset FDI_RX_MISC pwrdn lanes */
-		temp = I915_READ(_FDI_RXA_MISC);
+		temp = I915_READ(FDI_RX_MISC(PIPE_A));
 		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
-		I915_WRITE(_FDI_RXA_MISC, temp);
-		POSTING_READ(_FDI_RXA_MISC);
+		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
+		POSTING_READ(FDI_RX_MISC(PIPE_A));
 	}
 
 	DRM_ERROR("FDI link training failed!\n");
@@ -2999,22 +2999,22 @@ void intel_ddi_fdi_disable(struct drm_crtc *crtc)
 
 	intel_ddi_post_disable(intel_encoder);
 
-	val = I915_READ(_FDI_RXA_CTL);
+	val = I915_READ(FDI_RX_CTL(PIPE_A));
 	val &= ~FDI_RX_ENABLE;
-	I915_WRITE(_FDI_RXA_CTL, val);
+	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
 
-	val = I915_READ(_FDI_RXA_MISC);
+	val = I915_READ(FDI_RX_MISC(PIPE_A));
 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
-	I915_WRITE(_FDI_RXA_MISC, val);
+	I915_WRITE(FDI_RX_MISC(PIPE_A), val);
 
-	val = I915_READ(_FDI_RXA_CTL);
+	val = I915_READ(FDI_RX_CTL(PIPE_A));
 	val &= ~FDI_PCDCLK;
-	I915_WRITE(_FDI_RXA_CTL, val);
+	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
 
-	val = I915_READ(_FDI_RXA_CTL);
+	val = I915_READ(FDI_RX_CTL(PIPE_A));
 	val &= ~FDI_RX_PLL_ENABLE;
-	I915_WRITE(_FDI_RXA_CTL, val);
+	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
 }
 
 void intel_ddi_get_config(struct intel_encoder *encoder,
-- 
2.4.6

_______________________________________________
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Re: [PATCH 17/43] drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_crt.c |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c | 46 ++++++++++++++++++++--------------------
>  2 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index af5e43b..086b5c5 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -891,7 +891,7 @@ void intel_crt_init(struct drm_device *dev)
>  		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
>  				 FDI_RX_LINK_REVERSAL_OVERRIDE;
>  
> -		dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
> +		dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
>  	}
>  
>  	intel_crt_reset(connector);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9e640ea..b885b70 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -592,7 +592,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	 *
>  	 * WaFDIAutoLinkSetTimingOverrride:hsw
>  	 */
> -	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> +	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
>  				  FDI_RX_PWRDN_LANE0_VAL(2) |
>  				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
>  
> @@ -600,13 +600,13 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
>  		     FDI_RX_PLL_ENABLE |
>  		     FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> -	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -	POSTING_READ(_FDI_RXA_CTL);
> +	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
> +	POSTING_READ(FDI_RX_CTL(PIPE_A));
>  	udelay(220);
>  
>  	/* Switch from Rawclk to PCDclk */
>  	rx_ctl_val |= FDI_PCDCLK;
> -	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
>  
>  	/* Configure Port Clock Select */
>  	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
> @@ -635,21 +635,21 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  		udelay(600);
>  
>  		/* Program PCH FDI Receiver TU */
> -		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
> +		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
>  
>  		/* Enable PCH FDI Receiver with auto-training */
>  		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> -		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -		POSTING_READ(_FDI_RXA_CTL);
> +		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
> +		POSTING_READ(FDI_RX_CTL(PIPE_A));
>  
>  		/* Wait for FDI receiver lane calibration */
>  		udelay(30);
>  
>  		/* Unset FDI_RX_MISC pwrdn lanes */
> -		temp = I915_READ(_FDI_RXA_MISC);
> +		temp = I915_READ(FDI_RX_MISC(PIPE_A));
>  		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> -		I915_WRITE(_FDI_RXA_MISC, temp);
> -		POSTING_READ(_FDI_RXA_MISC);
> +		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
> +		POSTING_READ(FDI_RX_MISC(PIPE_A));
>  
>  		/* Wait for FDI auto training time */
>  		udelay(5);
> @@ -683,15 +683,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
>  
>  		rx_ctl_val &= ~FDI_RX_ENABLE;
> -		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -		POSTING_READ(_FDI_RXA_CTL);
> +		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
> +		POSTING_READ(FDI_RX_CTL(PIPE_A));
>  
>  		/* Reset FDI_RX_MISC pwrdn lanes */
> -		temp = I915_READ(_FDI_RXA_MISC);
> +		temp = I915_READ(FDI_RX_MISC(PIPE_A));
>  		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>  		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> -		I915_WRITE(_FDI_RXA_MISC, temp);
> -		POSTING_READ(_FDI_RXA_MISC);
> +		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
> +		POSTING_READ(FDI_RX_MISC(PIPE_A));
>  	}
>  
>  	DRM_ERROR("FDI link training failed!\n");
> @@ -2999,22 +2999,22 @@ void intel_ddi_fdi_disable(struct drm_crtc *crtc)
>  
>  	intel_ddi_post_disable(intel_encoder);
>  
> -	val = I915_READ(_FDI_RXA_CTL);
> +	val = I915_READ(FDI_RX_CTL(PIPE_A));
>  	val &= ~FDI_RX_ENABLE;
> -	I915_WRITE(_FDI_RXA_CTL, val);
> +	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
>  
> -	val = I915_READ(_FDI_RXA_MISC);
> +	val = I915_READ(FDI_RX_MISC(PIPE_A));
>  	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
>  	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> -	I915_WRITE(_FDI_RXA_MISC, val);
> +	I915_WRITE(FDI_RX_MISC(PIPE_A), val);
>  
> -	val = I915_READ(_FDI_RXA_CTL);
> +	val = I915_READ(FDI_RX_CTL(PIPE_A));
>  	val &= ~FDI_PCDCLK;
> -	I915_WRITE(_FDI_RXA_CTL, val);
> +	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
>  
> -	val = I915_READ(_FDI_RXA_CTL);
> +	val = I915_READ(FDI_RX_CTL(PIPE_A));
>  	val &= ~FDI_RX_PLL_ENABLE;
> -	I915_WRITE(_FDI_RXA_CTL, val);
> +	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
>  }
>  
>  void intel_ddi_get_config(struct intel_encoder *encoder,
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c      | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7343e14..63cf5eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2003,9 +2003,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
 
 	/* Workaround: set timing override bit. */
-	val = I915_READ(_TRANSA_CHICKEN2);
+	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
 	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
-	I915_WRITE(_TRANSA_CHICKEN2, val);
+	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 
 	val = TRANS_ENABLE;
 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
@@ -2063,9 +2063,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 		DRM_ERROR("Failed to disable PCH transcoder\n");
 
 	/* Workaround: clear timing override bit. */
-	val = I915_READ(_TRANSA_CHICKEN2);
+	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
 	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
-	I915_WRITE(_TRANSA_CHICKEN2, val);
+	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dc765eb..0d43d51 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6623,8 +6623,8 @@ static void lpt_init_clock_gating(struct drm_device *dev)
 			   PCH_LP_PARTITION_LEVEL_DISABLE);
 
 	/* WADPOClockGatingDisable:hsw */
-	I915_WRITE(_TRANSA_CHICKEN1,
-		   I915_READ(_TRANSA_CHICKEN1) |
+	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
+		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
 		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
 }
 
-- 
2.4.6

_______________________________________________
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Re: [PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++----
>  drivers/gpu/drm/i915/intel_pm.c      | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7343e14..63cf5eb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2003,9 +2003,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
>  
>  	/* Workaround: set timing override bit. */
> -	val = I915_READ(_TRANSA_CHICKEN2);
> +	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
>  	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> -	I915_WRITE(_TRANSA_CHICKEN2, val);
> +	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>  
>  	val = TRANS_ENABLE;
>  	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
> @@ -2063,9 +2063,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
>  		DRM_ERROR("Failed to disable PCH transcoder\n");
>  
>  	/* Workaround: clear timing override bit. */
> -	val = I915_READ(_TRANSA_CHICKEN2);
> +	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
>  	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> -	I915_WRITE(_TRANSA_CHICKEN2, val);
> +	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index dc765eb..0d43d51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6623,8 +6623,8 @@ static void lpt_init_clock_gating(struct drm_device *dev)
>  			   PCH_LP_PARTITION_LEVEL_DISABLE);
>  
>  	/* WADPOClockGatingDisable:hsw */
> -	I915_WRITE(_TRANSA_CHICKEN1,
> -		   I915_READ(_TRANSA_CHICKEN1) |
> +	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
> +		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
>  		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>  }
>  
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
 drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93cb6ed..25864ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7401,8 +7401,8 @@ enum skl_disp_power_wells {
 #define  DPLL_CFGCR2_PDIV_7 (4<<2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
 
-#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
-#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
+#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
+#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			0x6d000
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b885b70..399e70e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -953,8 +953,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 	uint32_t cfgcr1_val, cfgcr2_val;
 	uint32_t p0, p1, p2, dco_freq;
 
-	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
-	cfgcr2_reg = GET_CFG_CR2_REG(dpll);
+	cfgcr1_reg = DPLL_CFGCR1(dpll);
+	cfgcr2_reg = DPLL_CFGCR2(dpll);
 
 	cfgcr1_val = I915_READ(cfgcr1_reg);
 	cfgcr2_val = I915_READ(cfgcr2_reg);
@@ -2480,20 +2480,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
 	{
 		/* DPLL 1 */
 		.ctl = LCPLL2_CTL,
-		.cfgcr1 = DPLL1_CFGCR1,
-		.cfgcr2 = DPLL1_CFGCR2,
+		.cfgcr1 = DPLL_CFGCR1(1),
+		.cfgcr2 = DPLL_CFGCR2(1),
 	},
 	{
 		/* DPLL 2 */
 		.ctl = WRPLL_CTL1,
-		.cfgcr1 = DPLL2_CFGCR1,
-		.cfgcr2 = DPLL2_CFGCR2,
+		.cfgcr1 = DPLL_CFGCR1(2),
+		.cfgcr2 = DPLL_CFGCR2(2),
 	},
 	{
 		/* DPLL 3 */
 		.ctl = WRPLL_CTL2,
-		.cfgcr1 = DPLL3_CFGCR1,
-		.cfgcr2 = DPLL3_CFGCR2,
+		.cfgcr1 = DPLL_CFGCR1(3),
+		.cfgcr2 = DPLL_CFGCR2(3),
 	},
 };
 
-- 
2.4.6

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Re: [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
>  drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
>  2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 93cb6ed..25864ae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7401,8 +7401,8 @@ enum skl_disp_power_wells {
>  #define  DPLL_CFGCR2_PDIV_7 (4<<2)
>  #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
>  
> -#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
> -#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
> +#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
> +#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
>  
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL			0x6d000
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index b885b70..399e70e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -953,8 +953,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>  	uint32_t cfgcr1_val, cfgcr2_val;
>  	uint32_t p0, p1, p2, dco_freq;
>  
> -	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
> -	cfgcr2_reg = GET_CFG_CR2_REG(dpll);
> +	cfgcr1_reg = DPLL_CFGCR1(dpll);
> +	cfgcr2_reg = DPLL_CFGCR2(dpll);
>  
>  	cfgcr1_val = I915_READ(cfgcr1_reg);
>  	cfgcr2_val = I915_READ(cfgcr2_reg);
> @@ -2480,20 +2480,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
>  	{
>  		/* DPLL 1 */
>  		.ctl = LCPLL2_CTL,
> -		.cfgcr1 = DPLL1_CFGCR1,
> -		.cfgcr2 = DPLL1_CFGCR2,
> +		.cfgcr1 = DPLL_CFGCR1(1),
> +		.cfgcr2 = DPLL_CFGCR2(1),
>  	},
>  	{
>  		/* DPLL 2 */
>  		.ctl = WRPLL_CTL1,
> -		.cfgcr1 = DPLL2_CFGCR1,
> -		.cfgcr2 = DPLL2_CFGCR2,
> +		.cfgcr1 = DPLL_CFGCR1(2),
> +		.cfgcr2 = DPLL_CFGCR2(2),
>  	},
>  	{
>  		/* DPLL 3 */
>  		.ctl = WRPLL_CTL2,
> -		.cfgcr1 = DPLL3_CFGCR1,
> -		.cfgcr2 = DPLL3_CFGCR2,
> +		.cfgcr1 = DPLL_CFGCR1(3),
> +		.cfgcr2 = DPLL_CFGCR2(3),
>  	},
>  };
>  
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Re: [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

[Ville Syrjälä]

On Wed, Sep 30, 2015 at 04:44:21PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
> >  drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
> >  2 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 93cb6ed..25864ae 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7401,8 +7401,8 @@ enum skl_disp_power_wells {
> >  #define  DPLL_CFGCR2_PDIV_7 (4<<2)
> >  #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
> >  
> > -#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
> > -#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
> > +#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
> > +#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
> >  
> >  /* BXT display engine PLL */
> >  #define BXT_DE_PLL_CTL			0x6d000
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index b885b70..399e70e 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -953,8 +953,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >  	uint32_t cfgcr1_val, cfgcr2_val;
> >  	uint32_t p0, p1, p2, dco_freq;
> >  
> > -	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
> > -	cfgcr2_reg = GET_CFG_CR2_REG(dpll);
> > +	cfgcr1_reg = DPLL_CFGCR1(dpll);
> > +	cfgcr2_reg = DPLL_CFGCR2(dpll);
> >  
> >  	cfgcr1_val = I915_READ(cfgcr1_reg);
> >  	cfgcr2_val = I915_READ(cfgcr2_reg);
> > @@ -2480,20 +2480,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
> >  	{
> >  		/* DPLL 1 */
> >  		.ctl = LCPLL2_CTL,
> > -		.cfgcr1 = DPLL1_CFGCR1,
> > -		.cfgcr2 = DPLL1_CFGCR2,
> > +		.cfgcr1 = DPLL_CFGCR1(1),
> > +		.cfgcr2 = DPLL_CFGCR2(1),
> >  	},
> >  	{
> >  		/* DPLL 2 */
> >  		.ctl = WRPLL_CTL1,
> > -		.cfgcr1 = DPLL2_CFGCR1,
> > -		.cfgcr2 = DPLL2_CFGCR2,
> > +		.cfgcr1 = DPLL_CFGCR1(2),
> > +		.cfgcr2 = DPLL_CFGCR2(2),
> >  	},
> >  	{
> >  		/* DPLL 3 */
> >  		.ctl = WRPLL_CTL2,
> > -		.cfgcr1 = DPLL3_CFGCR1,
> > -		.cfgcr2 = DPLL3_CFGCR2,
> > +		.cfgcr1 = DPLL_CFGCR1(3),
> > +		.cfgcr2 = DPLL_CFGCR2(3),

I guess I really should have used the SKL_DPLL names here. I think it
was me who even asked for them originally. Let me respin with that small
change...

> >  	},
> >  };
> >  
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
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[PATCH v2 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Use SKL_DPLLx symbolic names instead of raw numbers

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
 drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 015d04b..67f2453 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7407,8 +7407,8 @@ enum skl_disp_power_wells {
 #define  DPLL_CFGCR2_PDIV_7 (4<<2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
 
-#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
-#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
+#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
+#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			0x6d000
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b885b70..708136c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -953,8 +953,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 	uint32_t cfgcr1_val, cfgcr2_val;
 	uint32_t p0, p1, p2, dco_freq;
 
-	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
-	cfgcr2_reg = GET_CFG_CR2_REG(dpll);
+	cfgcr1_reg = DPLL_CFGCR1(dpll);
+	cfgcr2_reg = DPLL_CFGCR2(dpll);
 
 	cfgcr1_val = I915_READ(cfgcr1_reg);
 	cfgcr2_val = I915_READ(cfgcr2_reg);
@@ -2480,20 +2480,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
 	{
 		/* DPLL 1 */
 		.ctl = LCPLL2_CTL,
-		.cfgcr1 = DPLL1_CFGCR1,
-		.cfgcr2 = DPLL1_CFGCR2,
+		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
+		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
 	},
 	{
 		/* DPLL 2 */
 		.ctl = WRPLL_CTL1,
-		.cfgcr1 = DPLL2_CFGCR1,
-		.cfgcr2 = DPLL2_CFGCR2,
+		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
+		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
 	},
 	{
 		/* DPLL 3 */
 		.ctl = WRPLL_CTL2,
-		.cfgcr1 = DPLL3_CFGCR1,
-		.cfgcr2 = DPLL3_CFGCR2,
+		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
+		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
 	},
 };
 
-- 
2.4.6

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[PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 2 +-
 drivers/gpu/drm/i915/intel_ddi.c     | 8 ++++----
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25864ae..a8fb5f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7253,7 +7253,7 @@ enum skl_disp_power_wells {
 /* WRPLL */
 #define WRPLL_CTL1			0x46040
 #define WRPLL_CTL2			0x46060
-#define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
+#define WRPLL_CTL(pll)			_PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)
 #define  WRPLL_PLL_ENABLE		(1<<31)
 #define  WRPLL_PLL_SSC			(1<<28)
 #define  WRPLL_PLL_NON_SSC		(2<<28)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 399e70e..fb456a4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1094,10 +1094,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 		link_clock = 270000;
 		break;
 	case PORT_CLK_SEL_WRPLL1:
-		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
+		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
 		break;
 	case PORT_CLK_SEL_WRPLL2:
-		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
+		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
 		break;
 	case PORT_CLK_SEL_SPLL:
 		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
@@ -2485,13 +2485,13 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
 	},
 	{
 		/* DPLL 2 */
-		.ctl = WRPLL_CTL1,
+		.ctl = WRPLL_CTL(0),
 		.cfgcr1 = DPLL_CFGCR1(2),
 		.cfgcr2 = DPLL_CFGCR2(2),
 	},
 	{
 		/* DPLL 3 */
-		.ctl = WRPLL_CTL2,
+		.ctl = WRPLL_CTL(1),
 		.cfgcr1 = DPLL_CFGCR1(3),
 		.cfgcr2 = DPLL_CFGCR2(3),
 	},
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 63cf5eb..fa7c10fa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9237,8 +9237,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 
 	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
 	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
-	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
-	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
+	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
+	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
 	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
 	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
 	     "CPU PWM1 enabled\n");
-- 
2.4.6

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Re: [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL()

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 2 +-
>  drivers/gpu/drm/i915/intel_ddi.c     | 8 ++++----
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 25864ae..a8fb5f7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7253,7 +7253,7 @@ enum skl_disp_power_wells {
>  /* WRPLL */
>  #define WRPLL_CTL1			0x46040
>  #define WRPLL_CTL2			0x46060
> -#define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
> +#define WRPLL_CTL(pll)			_PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)

I hope we never accidentally pass pll >= 2 here... I guess we'll find
out. ;)

I know we do reuse _PIPE like this, but maybe we should have a different
macro that emphasizes the parameter is really not pipe based, but rather
an ID or enumeration. There's value in self-documentating code, and
*gasp* maybe we'll eventually make this stuff type safe too! Basically
it would be an alias for _PIPE(); see _PLANE(). Or maybe _PIPE and
_PLANE could be based on the new one. Anyway, just a thought, this is

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  #define  WRPLL_PLL_ENABLE		(1<<31)
>  #define  WRPLL_PLL_SSC			(1<<28)
>  #define  WRPLL_PLL_NON_SSC		(2<<28)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 399e70e..fb456a4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1094,10 +1094,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
>  		link_clock = 270000;
>  		break;
>  	case PORT_CLK_SEL_WRPLL1:
> -		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
> +		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
>  		break;
>  	case PORT_CLK_SEL_WRPLL2:
> -		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
> +		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
>  		break;
>  	case PORT_CLK_SEL_SPLL:
>  		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
> @@ -2485,13 +2485,13 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
>  	},
>  	{
>  		/* DPLL 2 */
> -		.ctl = WRPLL_CTL1,
> +		.ctl = WRPLL_CTL(0),
>  		.cfgcr1 = DPLL_CFGCR1(2),
>  		.cfgcr2 = DPLL_CFGCR2(2),
>  	},
>  	{
>  		/* DPLL 3 */
> -		.ctl = WRPLL_CTL2,
> +		.ctl = WRPLL_CTL(1),
>  		.cfgcr1 = DPLL_CFGCR1(3),
>  		.cfgcr2 = DPLL_CFGCR2(3),
>  	},
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 63cf5eb..fa7c10fa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9237,8 +9237,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
>  
>  	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
>  	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> -	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> -	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> +	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> +	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
>  	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
>  	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
>  	     "CPU PWM1 enabled\n");
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL()

[Ville Syrjälä]

On Wed, Sep 30, 2015 at 04:58:34PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 2 +-
> >  drivers/gpu/drm/i915/intel_ddi.c     | 8 ++++----
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++--
> >  3 files changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 25864ae..a8fb5f7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7253,7 +7253,7 @@ enum skl_disp_power_wells {
> >  /* WRPLL */
> >  #define WRPLL_CTL1			0x46040
> >  #define WRPLL_CTL2			0x46060
> > -#define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
> > +#define WRPLL_CTL(pll)			_PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)
> 
> I hope we never accidentally pass pll >= 2 here... I guess we'll find
> out. ;)
> 
> I know we do reuse _PIPE like this, but maybe we should have a different
> macro that emphasizes the parameter is really not pipe based, but rather
> an ID or enumeration. There's value in self-documentating code, and
> *gasp* maybe we'll eventually make this stuff type safe too! Basically
> it would be an alias for _PIPE(); see _PLANE(). Or maybe _PIPE and
> _PLANE could be based on the new one.

Yeah, I suppose some kind of base macro would be good, and then just give it
aliases. I was also thinking of having a macro for the typical
'((base) + (n) * 4' type of stuff.

> Anyway, just a thought, this is
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> >  #define  WRPLL_PLL_ENABLE		(1<<31)
> >  #define  WRPLL_PLL_SSC			(1<<28)
> >  #define  WRPLL_PLL_NON_SSC		(2<<28)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 399e70e..fb456a4 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1094,10 +1094,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
> >  		link_clock = 270000;
> >  		break;
> >  	case PORT_CLK_SEL_WRPLL1:
> > -		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
> > +		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
> >  		break;
> >  	case PORT_CLK_SEL_WRPLL2:
> > -		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
> > +		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
> >  		break;
> >  	case PORT_CLK_SEL_SPLL:
> >  		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
> > @@ -2485,13 +2485,13 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
> >  	},
> >  	{
> >  		/* DPLL 2 */
> > -		.ctl = WRPLL_CTL1,
> > +		.ctl = WRPLL_CTL(0),
> >  		.cfgcr1 = DPLL_CFGCR1(2),
> >  		.cfgcr2 = DPLL_CFGCR2(2),
> >  	},
> >  	{
> >  		/* DPLL 3 */
> > -		.ctl = WRPLL_CTL2,
> > +		.ctl = WRPLL_CTL(1),
> >  		.cfgcr1 = DPLL_CFGCR1(3),
> >  		.cfgcr2 = DPLL_CFGCR2(3),
> >  	},
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 63cf5eb..fa7c10fa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -9237,8 +9237,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> >  
> >  	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
> >  	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> > -	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> > -	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> > +	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> > +	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> >  	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
> >  	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> >  	     "CPU PWM1 enabled\n");
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL()

[Ville Syrjälä]

On Wed, Sep 30, 2015 at 04:58:34PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 2 +-
> >  drivers/gpu/drm/i915/intel_ddi.c     | 8 ++++----
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++--
> >  3 files changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 25864ae..a8fb5f7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7253,7 +7253,7 @@ enum skl_disp_power_wells {
> >  /* WRPLL */
> >  #define WRPLL_CTL1			0x46040
> >  #define WRPLL_CTL2			0x46060
> > -#define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
> > +#define WRPLL_CTL(pll)			_PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)
> 
> I hope we never accidentally pass pll >= 2 here... I guess we'll find
> out. ;)
> 
> I know we do reuse _PIPE like this, but maybe we should have a different
> macro that emphasizes the parameter is really not pipe based, but rather
> an ID or enumeration. There's value in self-documentating code, and
> *gasp* maybe we'll eventually make this stuff type safe too! Basically
> it would be an alias for _PIPE(); see _PLANE(). Or maybe _PIPE and
> _PLANE could be based on the new one. Anyway, just a thought, this is
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Merged this one. Thanks for the review.

Note that I had to rebase it a bit due to the SKL_DPLLx change in one
of the earlier patches.

> 
> 
> >  #define  WRPLL_PLL_ENABLE		(1<<31)
> >  #define  WRPLL_PLL_SSC			(1<<28)
> >  #define  WRPLL_PLL_NON_SSC		(2<<28)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 399e70e..fb456a4 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1094,10 +1094,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
> >  		link_clock = 270000;
> >  		break;
> >  	case PORT_CLK_SEL_WRPLL1:
> > -		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
> > +		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
> >  		break;
> >  	case PORT_CLK_SEL_WRPLL2:
> > -		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
> > +		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
> >  		break;
> >  	case PORT_CLK_SEL_SPLL:
> >  		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
> > @@ -2485,13 +2485,13 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
> >  	},
> >  	{
> >  		/* DPLL 2 */
> > -		.ctl = WRPLL_CTL1,
> > +		.ctl = WRPLL_CTL(0),
> >  		.cfgcr1 = DPLL_CFGCR1(2),
> >  		.cfgcr2 = DPLL_CFGCR2(2),
> >  	},
> >  	{
> >  		/* DPLL 3 */
> > -		.ctl = WRPLL_CTL2,
> > +		.ctl = WRPLL_CTL(1),
> >  		.cfgcr1 = DPLL_CFGCR1(3),
> >  		.cfgcr2 = DPLL_CFGCR2(3),
> >  	},
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 63cf5eb..fa7c10fa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -9237,8 +9237,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> >  
> >  	I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
> >  	I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> > -	I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> > -	I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> > +	I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> > +	I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> >  	I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
> >  	I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> >  	     "CPU PWM1 enabled\n");
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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[PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  8 +++++++-
 drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++---------------
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8fb5f7..ddfcd68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3262,7 +3262,9 @@ enum skl_disp_power_wells {
 #define GEN3_SDVOC	0x61160
 #define GEN4_HDMIB	GEN3_SDVOB
 #define GEN4_HDMIC	GEN3_SDVOC
-#define CHV_HDMID	0x6116C
+#define VLV_HDMIB	(VLV_DISPLAY_BASE + GEN4_HDMIB)
+#define VLV_HDMIC	(VLV_DISPLAY_BASE + GEN4_HDMIC)
+#define CHV_HDMID	(VLV_DISPLAY_BASE + 0x6116C)
 #define PCH_SDVOB	0xe1140
 #define PCH_HDMIB	PCH_SDVOB
 #define PCH_HDMIC	0xe1150
@@ -4091,6 +4093,10 @@ enum skl_disp_power_wells {
 #define DP_C				0x64200
 #define DP_D				0x64300
 
+#define VLV_DP_B			(VLV_DISPLAY_BASE + DP_B)
+#define VLV_DP_C			(VLV_DISPLAY_BASE + DP_C)
+#define CHV_DP_D			(VLV_DISPLAY_BASE + DP_D)
+
 #define   DP_PORT_EN			(1 << 31)
 #define   DP_PIPEB_SELECT		(1 << 30)
 #define   DP_PIPE_MASK			(1 << 30)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fa7c10fa..e20abd5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14009,29 +14009,26 @@ static void intel_setup_outputs(struct drm_device *dev)
 		 * eDP ports. Consult the VBT as well as DP_DETECTED to
 		 * detect eDP ports.
 		 */
-		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
+		if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
 		    !intel_dp_is_edp(dev, PORT_B))
-			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
-					PORT_B);
-		if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
+			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
+		if (I915_READ(VLV_DP_B) & DP_DETECTED ||
 		    intel_dp_is_edp(dev, PORT_B))
-			intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
+			intel_dp_init(dev, VLV_DP_B, PORT_B);
 
-		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
+		if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
 		    !intel_dp_is_edp(dev, PORT_C))
-			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
-					PORT_C);
-		if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
+			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
+		if (I915_READ(VLV_DP_C) & DP_DETECTED ||
 		    intel_dp_is_edp(dev, PORT_C))
-			intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
+			intel_dp_init(dev, VLV_DP_C, PORT_C);
 
 		if (IS_CHERRYVIEW(dev)) {
-			if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
-				intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
-						PORT_D);
 			/* eDP not supported on port D, so don't check VBT */
-			if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
-				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
+			if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
+				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
+			if (I915_READ(CHV_DP_D) & DP_DETECTED)
+				intel_dp_init(dev, CHV_DP_D, PORT_D);
 		}
 
 		intel_dsi_init(dev);
-- 
2.4.6

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Re: [PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  8 +++++++-
>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++---------------
>  2 files changed, 19 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a8fb5f7..ddfcd68 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3262,7 +3262,9 @@ enum skl_disp_power_wells {
>  #define GEN3_SDVOC	0x61160
>  #define GEN4_HDMIB	GEN3_SDVOB
>  #define GEN4_HDMIC	GEN3_SDVOC
> -#define CHV_HDMID	0x6116C
> +#define VLV_HDMIB	(VLV_DISPLAY_BASE + GEN4_HDMIB)
> +#define VLV_HDMIC	(VLV_DISPLAY_BASE + GEN4_HDMIC)
> +#define CHV_HDMID	(VLV_DISPLAY_BASE + 0x6116C)
>  #define PCH_SDVOB	0xe1140
>  #define PCH_HDMIB	PCH_SDVOB
>  #define PCH_HDMIC	0xe1150
> @@ -4091,6 +4093,10 @@ enum skl_disp_power_wells {
>  #define DP_C				0x64200
>  #define DP_D				0x64300
>  
> +#define VLV_DP_B			(VLV_DISPLAY_BASE + DP_B)
> +#define VLV_DP_C			(VLV_DISPLAY_BASE + DP_C)
> +#define CHV_DP_D			(VLV_DISPLAY_BASE + DP_D)
> +
>  #define   DP_PORT_EN			(1 << 31)
>  #define   DP_PIPEB_SELECT		(1 << 30)
>  #define   DP_PIPE_MASK			(1 << 30)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fa7c10fa..e20abd5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14009,29 +14009,26 @@ static void intel_setup_outputs(struct drm_device *dev)
>  		 * eDP ports. Consult the VBT as well as DP_DETECTED to
>  		 * detect eDP ports.
>  		 */
> -		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
> +		if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
>  		    !intel_dp_is_edp(dev, PORT_B))
> -			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
> -					PORT_B);
> -		if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
> +			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
> +		if (I915_READ(VLV_DP_B) & DP_DETECTED ||
>  		    intel_dp_is_edp(dev, PORT_B))
> -			intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
> +			intel_dp_init(dev, VLV_DP_B, PORT_B);
>  
> -		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
> +		if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
>  		    !intel_dp_is_edp(dev, PORT_C))
> -			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
> -					PORT_C);
> -		if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
> +			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
> +		if (I915_READ(VLV_DP_C) & DP_DETECTED ||
>  		    intel_dp_is_edp(dev, PORT_C))
> -			intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
> +			intel_dp_init(dev, VLV_DP_C, PORT_C);
>  
>  		if (IS_CHERRYVIEW(dev)) {
> -			if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
> -				intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
> -						PORT_D);
>  			/* eDP not supported on port D, so don't check VBT */
> -			if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
> -				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
> +			if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
> +				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
> +			if (I915_READ(CHV_DP_D) & DP_DETECTED)
> +				intel_dp_init(dev, CHV_DP_D, PORT_D);
>  		}
>  
>  		intel_dsi_init(dev);
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e20abd5..92e624b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13948,7 +13948,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 		 * On SKL pre-D0 the strap isn't connected, so we assume
 		 * it's there.
 		 */
-		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
+		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
 		/* WaIgnoreDDIAStrap: skl */
 		if (found || IS_SKYLAKE(dev))
 			intel_ddi_init(dev, PORT_A);
-- 
2.4.6

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Re: [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e20abd5..92e624b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13948,7 +13948,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  		 * On SKL pre-D0 the strap isn't connected, so we assume
>  		 * it's there.
>  		 */
> -		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
> +		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
>  		/* WaIgnoreDDIAStrap: skl */
>  		if (found || IS_SKYLAKE(dev))
>  			intel_ddi_init(dev, PORT_A);
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/

[Daniel Vetter]

On Mon, Sep 28, 2015 at 02:53:56PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Merged patches 21&22 too, thanks.
-Daniel

> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index e20abd5..92e624b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13948,7 +13948,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  		 * On SKL pre-D0 the strap isn't connected, so we assume
> >  		 * it's there.
> >  		 */
> > -		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
> > +		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
> >  		/* WaIgnoreDDIAStrap: skl */
> >  		if (found || IS_SKYLAKE(dev))
> >  			intel_ddi_init(dev, PORT_A);
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 23/43] drm/i915: Eliminate weird parameter inversion from BXT PPS registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  8 ++++----
 drivers/gpu/drm/i915/intel_dp.c | 17 ++++++++---------
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddfcd68..134b075 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6537,10 +6537,10 @@ enum skl_disp_power_wells {
 #define _BXT_PP_ON_DELAYS2	0xc7308
 #define _BXT_PP_OFF_DELAYS2	0xc730c
 
-#define BXT_PP_STATUS(n)	((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2)
-#define BXT_PP_CONTROL(n)	((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2)
-#define BXT_PP_ON_DELAYS(n)	((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2)
-#define BXT_PP_OFF_DELAYS(n)	((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2)
+#define BXT_PP_STATUS(n)	_PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
+#define BXT_PP_CONTROL(n)	_PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
+#define BXT_PP_ON_DELAYS(n)	_PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
+#define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B		0xe4100
 #define PCH_DPB_AUX_CH_CTL	0xe4110
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a687250..7e64555 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -546,7 +546,7 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
 	if (IS_BROXTON(dev))
-		return BXT_PP_CONTROL(0);
+		return BXT_PP_CONTROL(1);
 	else if (HAS_PCH_SPLIT(dev))
 		return PCH_PP_CONTROL;
 	else
@@ -558,7 +558,7 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
 	if (IS_BROXTON(dev))
-		return BXT_PP_STATUS(0);
+		return BXT_PP_STATUS(1);
 	else if (HAS_PCH_SPLIT(dev))
 		return PCH_PP_STATUS;
 	else
@@ -5318,9 +5318,9 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 		 * Correct Register for Broxton need to be identified
 		 * using VBT. hardcoding for now
 		 */
-		pp_ctrl_reg = BXT_PP_CONTROL(0);
-		pp_on_reg = BXT_PP_ON_DELAYS(0);
-		pp_off_reg = BXT_PP_OFF_DELAYS(0);
+		pp_ctrl_reg = BXT_PP_CONTROL(1);
+		pp_on_reg = BXT_PP_ON_DELAYS(1);
+		pp_off_reg = BXT_PP_OFF_DELAYS(1);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		pp_ctrl_reg = PCH_PP_CONTROL;
 		pp_on_reg = PCH_PP_ON_DELAYS;
@@ -5438,10 +5438,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 		 * Correct Register for Broxton need to be identified
 		 * using VBT. hardcoding for now
 		 */
-		pp_ctrl_reg = BXT_PP_CONTROL(0);
-		pp_on_reg = BXT_PP_ON_DELAYS(0);
-		pp_off_reg = BXT_PP_OFF_DELAYS(0);
-
+		pp_ctrl_reg = BXT_PP_CONTROL(1);
+		pp_on_reg = BXT_PP_ON_DELAYS(1);
+		pp_off_reg = BXT_PP_OFF_DELAYS(1);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		pp_on_reg = PCH_PP_ON_DELAYS;
 		pp_off_reg = PCH_PP_OFF_DELAYS;
-- 
2.4.6

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[PATCH v2 23/43] drm/i915: Eliminate weird parameter inversion from BXT PPS registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Keep using the same registers (PCH_*) instead of accidentally
    starting to use the other ones (BXT_*)2) (Jesse)

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3dad335..7bf11f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6543,10 +6543,10 @@ enum skl_disp_power_wells {
 #define _BXT_PP_ON_DELAYS2	0xc7308
 #define _BXT_PP_OFF_DELAYS2	0xc730c
 
-#define BXT_PP_STATUS(n)	((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2)
-#define BXT_PP_CONTROL(n)	((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2)
-#define BXT_PP_ON_DELAYS(n)	((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2)
-#define BXT_PP_OFF_DELAYS(n)	((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2)
+#define BXT_PP_STATUS(n)	_PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
+#define BXT_PP_CONTROL(n)	_PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
+#define BXT_PP_ON_DELAYS(n)	_PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
+#define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B		0xe4100
 #define PCH_DPB_AUX_CH_CTL	0xe4110
-- 
2.4.9

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[PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_hdmi.c | 26 ++++++++++++++------------
 drivers/gpu/drm/i915/intel_psr.c  | 18 ++++++++++--------
 3 files changed, 32 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 134b075..b35e24f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6236,16 +6236,16 @@ enum skl_disp_power_wells {
 
 #define HSW_TVIDEO_DIP_CTL(trans) \
 	 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
-#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
-	 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
-#define HSW_TVIDEO_DIP_VS_DATA(trans) \
-	 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
-#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
-	 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
+#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
+	(_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
+#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
+	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
+#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
+	(_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
 #define HSW_TVIDEO_DIP_GCP(trans) \
 	_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
-#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
-	 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
+#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
+	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
 
 #define HSW_STEREO_3D_CTL_A	0x70020
 #define   S3D_ENABLE		(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e978c59..6b16292 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -113,17 +113,18 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 	}
 }
 
-static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
-				  enum transcoder cpu_transcoder,
-				  struct drm_i915_private *dev_priv)
+static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
+			    enum transcoder cpu_transcoder,
+			    enum hdmi_infoframe_type type,
+			    int i)
 {
 	switch (type) {
 	case HDMI_INFOFRAME_TYPE_AVI:
-		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
+		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 	case HDMI_INFOFRAME_TYPE_SPD:
-		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
+		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 	case HDMI_INFOFRAME_TYPE_VENDOR:
-		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
+		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 	default:
 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 		return 0;
@@ -365,14 +366,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
+	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 	u32 data_reg;
 	int i;
 	u32 val = I915_READ(ctl_reg);
 
-	data_reg = hsw_infoframe_data_reg(type,
-					  intel_crtc->config->cpu_transcoder,
-					  dev_priv);
+	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 	if (data_reg == 0)
 		return;
 
@@ -381,12 +381,14 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
 
 	mmiowb();
 	for (i = 0; i < len; i += 4) {
-		I915_WRITE(data_reg + i, *data);
+		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
+					    type, i >> 2), *data);
 		data++;
 	}
 	/* Write every possible data byte to force correct ECC calculation. */
 	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
-		I915_WRITE(data_reg + i, 0);
+		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
+					    type, i >> 2), 0);
 	mmiowb();
 
 	val |= hsw_infoframe_enable(type);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index a04b4dc..213581c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -73,14 +73,14 @@ static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 }
 
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
-				    struct edp_vsc_psr *vsc_psr)
+				const struct edp_vsc_psr *vsc_psr)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
-	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
+	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
+	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 	uint32_t *data = (uint32_t *) vsc_psr;
 	unsigned int i;
 
@@ -90,12 +90,14 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 	I915_WRITE(ctl_reg, 0);
 	POSTING_READ(ctl_reg);
 
-	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
-		if (i < sizeof(struct edp_vsc_psr))
-			I915_WRITE(data_reg + i, *data++);
-		else
-			I915_WRITE(data_reg + i, 0);
+	for (i = 0; i < sizeof(*vsc_psr); i += 4) {
+		I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
+						   i >> 2), *data);
+		data++;
 	}
+	for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
+		I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
+						   i >> 2), 0);
 
 	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 	POSTING_READ(ctl_reg);
-- 
2.4.6

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Re: [PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 16 ++++++++--------
>  drivers/gpu/drm/i915/intel_hdmi.c | 26 ++++++++++++++------------
>  drivers/gpu/drm/i915/intel_psr.c  | 18 ++++++++++--------
>  3 files changed, 32 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 134b075..b35e24f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6236,16 +6236,16 @@ enum skl_disp_power_wells {
>  
>  #define HSW_TVIDEO_DIP_CTL(trans) \
>  	 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
> -#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
> -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
> -#define HSW_TVIDEO_DIP_VS_DATA(trans) \
> -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
> -#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
> -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
> +#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
> +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
> +#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
> +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
> +#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
> +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
>  #define HSW_TVIDEO_DIP_GCP(trans) \
>  	_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
> -#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
> -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
> +#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
> +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
>  
>  #define HSW_STEREO_3D_CTL_A	0x70020
>  #define   S3D_ENABLE		(1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e978c59..6b16292 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -113,17 +113,18 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
>  	}
>  }
>  
> -static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
> -				  enum transcoder cpu_transcoder,
> -				  struct drm_i915_private *dev_priv)
> +static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> +			    enum transcoder cpu_transcoder,
> +			    enum hdmi_infoframe_type type,
> +			    int i)
>  {
>  	switch (type) {
>  	case HDMI_INFOFRAME_TYPE_AVI:
> -		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
> +		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
>  	case HDMI_INFOFRAME_TYPE_SPD:
> -		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
> +		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
>  	case HDMI_INFOFRAME_TYPE_VENDOR:
> -		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
> +		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
>  	default:
>  		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
>  		return 0;
> @@ -365,14 +366,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> +	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> +	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
>  	u32 data_reg;
>  	int i;
>  	u32 val = I915_READ(ctl_reg);
>  
> -	data_reg = hsw_infoframe_data_reg(type,
> -					  intel_crtc->config->cpu_transcoder,
> -					  dev_priv);
> +	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
>  	if (data_reg == 0)
>  		return;
>  
> @@ -381,12 +381,14 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
>  
>  	mmiowb();
>  	for (i = 0; i < len; i += 4) {
> -		I915_WRITE(data_reg + i, *data);
> +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
> +					    type, i >> 2), *data);
>  		data++;
>  	}
>  	/* Write every possible data byte to force correct ECC calculation. */
>  	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
> -		I915_WRITE(data_reg + i, 0);
> +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
> +					    type, i >> 2), 0);
>  	mmiowb();
>  
>  	val |= hsw_infoframe_enable(type);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index a04b4dc..213581c 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -73,14 +73,14 @@ static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>  }
>  
>  static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> -				    struct edp_vsc_psr *vsc_psr)
> +				const struct edp_vsc_psr *vsc_psr)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
> -	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
> +	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> +	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
>  	uint32_t *data = (uint32_t *) vsc_psr;
>  	unsigned int i;
>  
> @@ -90,12 +90,14 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>  	I915_WRITE(ctl_reg, 0);
>  	POSTING_READ(ctl_reg);
>  
> -	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
> -		if (i < sizeof(struct edp_vsc_psr))
> -			I915_WRITE(data_reg + i, *data++);
> -		else
> -			I915_WRITE(data_reg + i, 0);
> +	for (i = 0; i < sizeof(*vsc_psr); i += 4) {
> +		I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
> +						   i >> 2), *data);
> +		data++;
>  	}
> +	for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
> +		I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
> +						   i >> 2), 0);
>  
>  	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
>  	POSTING_READ(ctl_reg);
> 

Since you fixed the macro to use a *4 for the reg index, it might be
clearer to fix up the loop to just use i++ instead?  I guess you'd then
have to divide the condition, so meh (or maybe we need a DWORDS(bytes)
macro!).  Either way:

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers

[Ville Syrjälä]

On Mon, Oct 12, 2015 at 08:54:56AM -0700, Jesse Barnes wrote:
> On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 16 ++++++++--------
> >  drivers/gpu/drm/i915/intel_hdmi.c | 26 ++++++++++++++------------
> >  drivers/gpu/drm/i915/intel_psr.c  | 18 ++++++++++--------
> >  3 files changed, 32 insertions(+), 28 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 134b075..b35e24f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6236,16 +6236,16 @@ enum skl_disp_power_wells {
> >  
> >  #define HSW_TVIDEO_DIP_CTL(trans) \
> >  	 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
> > -#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
> > -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
> > -#define HSW_TVIDEO_DIP_VS_DATA(trans) \
> > -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
> > -#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
> > -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
> > +#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
> > +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
> > +#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
> > +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
> > +#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
> > +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
> >  #define HSW_TVIDEO_DIP_GCP(trans) \
> >  	_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
> > -#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
> > -	 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
> > +#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
> > +	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
> >  
> >  #define HSW_STEREO_3D_CTL_A	0x70020
> >  #define   S3D_ENABLE		(1<<31)
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index e978c59..6b16292 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -113,17 +113,18 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
> >  	}
> >  }
> >  
> > -static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
> > -				  enum transcoder cpu_transcoder,
> > -				  struct drm_i915_private *dev_priv)
> > +static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> > +			    enum transcoder cpu_transcoder,
> > +			    enum hdmi_infoframe_type type,
> > +			    int i)
> >  {
> >  	switch (type) {
> >  	case HDMI_INFOFRAME_TYPE_AVI:
> > -		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
> > +		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
> >  	case HDMI_INFOFRAME_TYPE_SPD:
> > -		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
> > +		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
> >  	case HDMI_INFOFRAME_TYPE_VENDOR:
> > -		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
> > +		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
> >  	default:
> >  		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
> >  		return 0;
> > @@ -365,14 +366,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
> >  	struct drm_device *dev = encoder->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> > -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> > +	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> > +	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> >  	u32 data_reg;
> >  	int i;
> >  	u32 val = I915_READ(ctl_reg);
> >  
> > -	data_reg = hsw_infoframe_data_reg(type,
> > -					  intel_crtc->config->cpu_transcoder,
> > -					  dev_priv);
> > +	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
> >  	if (data_reg == 0)
> >  		return;
> >  
> > @@ -381,12 +381,14 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
> >  
> >  	mmiowb();
> >  	for (i = 0; i < len; i += 4) {
> > -		I915_WRITE(data_reg + i, *data);
> > +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
> > +					    type, i >> 2), *data);
> >  		data++;
> >  	}
> >  	/* Write every possible data byte to force correct ECC calculation. */
> >  	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
> > -		I915_WRITE(data_reg + i, 0);
> > +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
> > +					    type, i >> 2), 0);
> >  	mmiowb();
> >  
> >  	val |= hsw_infoframe_enable(type);
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index a04b4dc..213581c 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -73,14 +73,14 @@ static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
> >  }
> >  
> >  static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> > -				    struct edp_vsc_psr *vsc_psr)
> > +				const struct edp_vsc_psr *vsc_psr)
> >  {
> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >  	struct drm_device *dev = dig_port->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> > -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
> > -	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
> > +	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> > +	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> >  	uint32_t *data = (uint32_t *) vsc_psr;
> >  	unsigned int i;
> >  
> > @@ -90,12 +90,14 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> >  	I915_WRITE(ctl_reg, 0);
> >  	POSTING_READ(ctl_reg);
> >  
> > -	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
> > -		if (i < sizeof(struct edp_vsc_psr))
> > -			I915_WRITE(data_reg + i, *data++);
> > -		else
> > -			I915_WRITE(data_reg + i, 0);
> > +	for (i = 0; i < sizeof(*vsc_psr); i += 4) {
> > +		I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
> > +						   i >> 2), *data);
> > +		data++;
> >  	}
> > +	for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
> > +		I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
> > +						   i >> 2), 0);
> >  
> >  	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
> >  	POSTING_READ(ctl_reg);
> > 
> 
> Since you fixed the macro to use a *4 for the reg index, it might be
> clearer to fix up the loop to just use i++ instead?  I guess you'd then
> have to divide the condition, so meh (or maybe we need a DWORDS(bytes)
> macro!).  Either way:

I had it both ways during development, but then I figured we should
try to do it the same way always. All other registers like this were
already indexed in dwords, and both the AUX code and the rest of the
infoframe code were counting the data in bytes, so I stuck to the
same approach in the end.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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[PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 ++++-----
 drivers/gpu/drm/i915/intel_i2c.c | 54 +++++++++++++++++-----------------------
 2 files changed, 29 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35e24f..0216771 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2114,7 +2114,7 @@ enum skl_disp_power_wells {
 # define GPIO_DATA_VAL_IN		(1 << 12)
 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
 
-#define GMBUS0			0x5100 /* clock/port select */
+#define GMBUS0			(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
 #define   GMBUS_RATE_100KHZ	(0<<8)
 #define   GMBUS_RATE_50KHZ	(1<<8)
 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
@@ -2133,7 +2133,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_2_BXT	2
 #define   GMBUS_PIN_3_BXT	3
 #define   GMBUS_NUM_PINS	7 /* including 0 */
-#define GMBUS1			0x5104 /* command/status */
+#define GMBUS1			(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
 #define   GMBUS_SW_RDY		(1<<30)
 #define   GMBUS_ENT		(1<<29) /* enable timeout */
@@ -2147,7 +2147,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ	(1<<0)
 #define   GMBUS_SLAVE_WRITE	(0<<0)
-#define GMBUS2			0x5108 /* status */
+#define GMBUS2			(dev_priv->gpio_mmio_base + 0x5108) /* status */
 #define   GMBUS_INUSE		(1<<15)
 #define   GMBUS_HW_WAIT_PHASE	(1<<14)
 #define   GMBUS_STALL_TIMEOUT	(1<<13)
@@ -2155,14 +2155,14 @@ enum skl_disp_power_wells {
 #define   GMBUS_HW_RDY		(1<<11)
 #define   GMBUS_SATOER		(1<<10)
 #define   GMBUS_ACTIVE		(1<<9)
-#define GMBUS3			0x510c /* data buffer bytes 3-0 */
-#define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
+#define GMBUS3			(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
+#define GMBUS4			(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
 #define   GMBUS_NAK_EN		(1<<3)
 #define   GMBUS_IDLE_EN		(1<<2)
 #define   GMBUS_HW_WAIT_EN	(1<<1)
 #define   GMBUS_HW_RDY_EN	(1<<0)
-#define GMBUS5			0x5120 /* byte index */
+#define GMBUS5			(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
 #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index a64f26c..1369fc4 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -114,8 +114,8 @@ intel_i2c_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
-	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
+	I915_WRITE(GMBUS0, 0);
+	I915_WRITE(GMBUS4, 0);
 }
 
 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
@@ -261,7 +261,6 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 		     u32 gmbus4_irq_en)
 {
 	int i;
-	int reg_offset = dev_priv->gpio_mmio_base;
 	u32 gmbus2 = 0;
 	DEFINE_WAIT(wait);
 
@@ -271,13 +270,13 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 	/* Important: The hw handles only the first bit, so set only one! Since
 	 * we also need to check for NAKs besides the hw ready/idle signal, we
 	 * need to wake up periodically and check that ourselves. */
-	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
+	I915_WRITE(GMBUS4, gmbus4_irq_en);
 
 	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 				TASK_UNINTERRUPTIBLE);
 
-		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
+		gmbus2 = I915_READ_NOTRACE(GMBUS2);
 		if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 			break;
 
@@ -285,7 +284,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 	}
 	finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 
-	I915_WRITE(GMBUS4 + reg_offset, 0);
+	I915_WRITE(GMBUS4, 0);
 
 	if (gmbus2 & GMBUS_SATOER)
 		return -ENXIO;
@@ -298,20 +297,19 @@ static int
 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 {
 	int ret;
-	int reg_offset = dev_priv->gpio_mmio_base;
 
-#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
+#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
 
 	if (!HAS_GMBUS_IRQ(dev_priv->dev))
 		return wait_for(C, 10);
 
 	/* Important: The hw handles only the first bit, so set only one! */
-	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
+	I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
 
 	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 				 msecs_to_jiffies_timeout(10));
 
-	I915_WRITE(GMBUS4 + reg_offset, 0);
+	I915_WRITE(GMBUS4, 0);
 
 	if (ret)
 		return 0;
@@ -325,9 +323,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
 		      u32 gmbus1_index)
 {
-	int reg_offset = dev_priv->gpio_mmio_base;
-
-	I915_WRITE(GMBUS1 + reg_offset,
+	I915_WRITE(GMBUS1,
 		   gmbus1_index |
 		   GMBUS_CYCLE_WAIT |
 		   (len << GMBUS_BYTE_COUNT_SHIFT) |
@@ -342,7 +338,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		if (ret)
 			return ret;
 
-		val = I915_READ(GMBUS3 + reg_offset);
+		val = I915_READ(GMBUS3);
 		do {
 			*buf++ = val & 0xff;
 			val >>= 8;
@@ -380,7 +376,6 @@ static int
 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 		       unsigned short addr, u8 *buf, unsigned int len)
 {
-	int reg_offset = dev_priv->gpio_mmio_base;
 	unsigned int chunk_size = len;
 	u32 val, loop;
 
@@ -390,8 +385,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 		len -= 1;
 	}
 
-	I915_WRITE(GMBUS3 + reg_offset, val);
-	I915_WRITE(GMBUS1 + reg_offset,
+	I915_WRITE(GMBUS3, val);
+	I915_WRITE(GMBUS1,
 		   GMBUS_CYCLE_WAIT |
 		   (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
 		   (addr << GMBUS_SLAVE_ADDR_SHIFT) |
@@ -404,7 +399,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 			val |= *buf++ << (8 * loop);
 		} while (--len && ++loop < 4);
 
-		I915_WRITE(GMBUS3 + reg_offset, val);
+		I915_WRITE(GMBUS3, val);
 
 		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 					   GMBUS_HW_RDY_EN);
@@ -452,7 +447,6 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 static int
 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 {
-	int reg_offset = dev_priv->gpio_mmio_base;
 	u32 gmbus1_index = 0;
 	u32 gmbus5 = 0;
 	int ret;
@@ -466,13 +460,13 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 
 	/* GMBUS5 holds 16-bit index */
 	if (gmbus5)
-		I915_WRITE(GMBUS5 + reg_offset, gmbus5);
+		I915_WRITE(GMBUS5, gmbus5);
 
 	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 
 	/* Clear GMBUS5 after each index transfer */
 	if (gmbus5)
-		I915_WRITE(GMBUS5 + reg_offset, 0);
+		I915_WRITE(GMBUS5, 0);
 
 	return ret;
 }
@@ -486,7 +480,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
 					       struct intel_gmbus,
 					       adapter);
 	struct drm_i915_private *dev_priv = bus->dev_priv;
-	int i = 0, inc, try = 0, reg_offset;
+	int i = 0, inc, try = 0;
 	int ret = 0;
 
 	intel_aux_display_runtime_get(dev_priv);
@@ -497,10 +491,8 @@ gmbus_xfer(struct i2c_adapter *adapter,
 		goto out;
 	}
 
-	reg_offset = dev_priv->gpio_mmio_base;
-
 retry:
-	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
+	I915_WRITE(GMBUS0, bus->reg0);
 
 	for (; i < num; i += inc) {
 		inc = 1;
@@ -530,7 +522,7 @@ retry:
 	 * a STOP on the very first cycle. To simplify the code we
 	 * unconditionally generate the STOP condition with an additional gmbus
 	 * cycle. */
-	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
+	I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 
 	/* Mark the GMBUS interface as disabled after waiting for idle.
 	 * We will re-enable it at the start of the next xfer,
@@ -541,7 +533,7 @@ retry:
 			 adapter->name);
 		ret = -ETIMEDOUT;
 	}
-	I915_WRITE(GMBUS0 + reg_offset, 0);
+	I915_WRITE(GMBUS0, 0);
 	ret = ret ?: i;
 	goto out;
 
@@ -570,9 +562,9 @@ clear_err:
 	 * of resetting the GMBUS controller and so clearing the
 	 * BUS_ERROR raised by the slave's NAK.
 	 */
-	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
-	I915_WRITE(GMBUS1 + reg_offset, 0);
-	I915_WRITE(GMBUS0 + reg_offset, 0);
+	I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
+	I915_WRITE(GMBUS1, 0);
+	I915_WRITE(GMBUS0, 0);
 
 	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 			 adapter->name, msgs[i].addr,
@@ -595,7 +587,7 @@ clear_err:
 timeout:
 	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 		 bus->adapter.name, bus->reg0 & 0xff);
-	I915_WRITE(GMBUS0 + reg_offset, 0);
+	I915_WRITE(GMBUS0, 0);
 
 	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 	bus->force_bit = 1;
-- 
2.4.6

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Re: [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 12 ++++-----
>  drivers/gpu/drm/i915/intel_i2c.c | 54 +++++++++++++++++-----------------------
>  2 files changed, 29 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b35e24f..0216771 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2114,7 +2114,7 @@ enum skl_disp_power_wells {
>  # define GPIO_DATA_VAL_IN		(1 << 12)
>  # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
>  
> -#define GMBUS0			0x5100 /* clock/port select */
> +#define GMBUS0			(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
>  #define   GMBUS_RATE_100KHZ	(0<<8)
>  #define   GMBUS_RATE_50KHZ	(1<<8)
>  #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
> @@ -2133,7 +2133,7 @@ enum skl_disp_power_wells {
>  #define   GMBUS_PIN_2_BXT	2
>  #define   GMBUS_PIN_3_BXT	3
>  #define   GMBUS_NUM_PINS	7 /* including 0 */
> -#define GMBUS1			0x5104 /* command/status */
> +#define GMBUS1			(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
>  #define   GMBUS_SW_CLR_INT	(1<<31)
>  #define   GMBUS_SW_RDY		(1<<30)
>  #define   GMBUS_ENT		(1<<29) /* enable timeout */
> @@ -2147,7 +2147,7 @@ enum skl_disp_power_wells {
>  #define   GMBUS_SLAVE_ADDR_SHIFT 1
>  #define   GMBUS_SLAVE_READ	(1<<0)
>  #define   GMBUS_SLAVE_WRITE	(0<<0)
> -#define GMBUS2			0x5108 /* status */
> +#define GMBUS2			(dev_priv->gpio_mmio_base + 0x5108) /* status */
>  #define   GMBUS_INUSE		(1<<15)
>  #define   GMBUS_HW_WAIT_PHASE	(1<<14)
>  #define   GMBUS_STALL_TIMEOUT	(1<<13)
> @@ -2155,14 +2155,14 @@ enum skl_disp_power_wells {
>  #define   GMBUS_HW_RDY		(1<<11)
>  #define   GMBUS_SATOER		(1<<10)
>  #define   GMBUS_ACTIVE		(1<<9)
> -#define GMBUS3			0x510c /* data buffer bytes 3-0 */
> -#define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
> +#define GMBUS3			(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
> +#define GMBUS4			(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
>  #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
>  #define   GMBUS_NAK_EN		(1<<3)
>  #define   GMBUS_IDLE_EN		(1<<2)
>  #define   GMBUS_HW_WAIT_EN	(1<<1)
>  #define   GMBUS_HW_RDY_EN	(1<<0)
> -#define GMBUS5			0x5120 /* byte index */
> +#define GMBUS5			(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
>  #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index a64f26c..1369fc4 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -114,8 +114,8 @@ intel_i2c_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
> -	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
> +	I915_WRITE(GMBUS0, 0);
> +	I915_WRITE(GMBUS4, 0);
>  }
>  
>  static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
> @@ -261,7 +261,6 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
>  		     u32 gmbus4_irq_en)
>  {
>  	int i;
> -	int reg_offset = dev_priv->gpio_mmio_base;
>  	u32 gmbus2 = 0;
>  	DEFINE_WAIT(wait);
>  
> @@ -271,13 +270,13 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
>  	/* Important: The hw handles only the first bit, so set only one! Since
>  	 * we also need to check for NAKs besides the hw ready/idle signal, we
>  	 * need to wake up periodically and check that ourselves. */
> -	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
> +	I915_WRITE(GMBUS4, gmbus4_irq_en);
>  
>  	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
>  		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
>  				TASK_UNINTERRUPTIBLE);
>  
> -		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
> +		gmbus2 = I915_READ_NOTRACE(GMBUS2);
>  		if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
>  			break;
>  
> @@ -285,7 +284,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
>  	}
>  	finish_wait(&dev_priv->gmbus_wait_queue, &wait);
>  
> -	I915_WRITE(GMBUS4 + reg_offset, 0);
> +	I915_WRITE(GMBUS4, 0);
>  
>  	if (gmbus2 & GMBUS_SATOER)
>  		return -ENXIO;
> @@ -298,20 +297,19 @@ static int
>  gmbus_wait_idle(struct drm_i915_private *dev_priv)
>  {
>  	int ret;
> -	int reg_offset = dev_priv->gpio_mmio_base;
>  
> -#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
> +#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
>  
>  	if (!HAS_GMBUS_IRQ(dev_priv->dev))
>  		return wait_for(C, 10);
>  
>  	/* Important: The hw handles only the first bit, so set only one! */
> -	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
> +	I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
>  
>  	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
>  				 msecs_to_jiffies_timeout(10));
>  
> -	I915_WRITE(GMBUS4 + reg_offset, 0);
> +	I915_WRITE(GMBUS4, 0);
>  
>  	if (ret)
>  		return 0;
> @@ -325,9 +323,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>  		      unsigned short addr, u8 *buf, unsigned int len,
>  		      u32 gmbus1_index)
>  {
> -	int reg_offset = dev_priv->gpio_mmio_base;
> -
> -	I915_WRITE(GMBUS1 + reg_offset,
> +	I915_WRITE(GMBUS1,
>  		   gmbus1_index |
>  		   GMBUS_CYCLE_WAIT |
>  		   (len << GMBUS_BYTE_COUNT_SHIFT) |
> @@ -342,7 +338,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>  		if (ret)
>  			return ret;
>  
> -		val = I915_READ(GMBUS3 + reg_offset);
> +		val = I915_READ(GMBUS3);
>  		do {
>  			*buf++ = val & 0xff;
>  			val >>= 8;
> @@ -380,7 +376,6 @@ static int
>  gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
>  		       unsigned short addr, u8 *buf, unsigned int len)
>  {
> -	int reg_offset = dev_priv->gpio_mmio_base;
>  	unsigned int chunk_size = len;
>  	u32 val, loop;
>  
> @@ -390,8 +385,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
>  		len -= 1;
>  	}
>  
> -	I915_WRITE(GMBUS3 + reg_offset, val);
> -	I915_WRITE(GMBUS1 + reg_offset,
> +	I915_WRITE(GMBUS3, val);
> +	I915_WRITE(GMBUS1,
>  		   GMBUS_CYCLE_WAIT |
>  		   (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
>  		   (addr << GMBUS_SLAVE_ADDR_SHIFT) |
> @@ -404,7 +399,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
>  			val |= *buf++ << (8 * loop);
>  		} while (--len && ++loop < 4);
>  
> -		I915_WRITE(GMBUS3 + reg_offset, val);
> +		I915_WRITE(GMBUS3, val);
>  
>  		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
>  					   GMBUS_HW_RDY_EN);
> @@ -452,7 +447,6 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
>  static int
>  gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>  {
> -	int reg_offset = dev_priv->gpio_mmio_base;
>  	u32 gmbus1_index = 0;
>  	u32 gmbus5 = 0;
>  	int ret;
> @@ -466,13 +460,13 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>  
>  	/* GMBUS5 holds 16-bit index */
>  	if (gmbus5)
> -		I915_WRITE(GMBUS5 + reg_offset, gmbus5);
> +		I915_WRITE(GMBUS5, gmbus5);
>  
>  	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
>  
>  	/* Clear GMBUS5 after each index transfer */
>  	if (gmbus5)
> -		I915_WRITE(GMBUS5 + reg_offset, 0);
> +		I915_WRITE(GMBUS5, 0);
>  
>  	return ret;
>  }
> @@ -486,7 +480,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
>  					       struct intel_gmbus,
>  					       adapter);
>  	struct drm_i915_private *dev_priv = bus->dev_priv;
> -	int i = 0, inc, try = 0, reg_offset;
> +	int i = 0, inc, try = 0;
>  	int ret = 0;
>  
>  	intel_aux_display_runtime_get(dev_priv);
> @@ -497,10 +491,8 @@ gmbus_xfer(struct i2c_adapter *adapter,
>  		goto out;
>  	}
>  
> -	reg_offset = dev_priv->gpio_mmio_base;
> -
>  retry:
> -	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
> +	I915_WRITE(GMBUS0, bus->reg0);
>  
>  	for (; i < num; i += inc) {
>  		inc = 1;
> @@ -530,7 +522,7 @@ retry:
>  	 * a STOP on the very first cycle. To simplify the code we
>  	 * unconditionally generate the STOP condition with an additional gmbus
>  	 * cycle. */
> -	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
> +	I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
>  
>  	/* Mark the GMBUS interface as disabled after waiting for idle.
>  	 * We will re-enable it at the start of the next xfer,
> @@ -541,7 +533,7 @@ retry:
>  			 adapter->name);
>  		ret = -ETIMEDOUT;
>  	}
> -	I915_WRITE(GMBUS0 + reg_offset, 0);
> +	I915_WRITE(GMBUS0, 0);
>  	ret = ret ?: i;
>  	goto out;
>  
> @@ -570,9 +562,9 @@ clear_err:
>  	 * of resetting the GMBUS controller and so clearing the
>  	 * BUS_ERROR raised by the slave's NAK.
>  	 */
> -	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
> -	I915_WRITE(GMBUS1 + reg_offset, 0);
> -	I915_WRITE(GMBUS0 + reg_offset, 0);
> +	I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
> +	I915_WRITE(GMBUS1, 0);
> +	I915_WRITE(GMBUS0, 0);
>  
>  	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
>  			 adapter->name, msgs[i].addr,
> @@ -595,7 +587,7 @@ clear_err:
>  timeout:
>  	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
>  		 bus->adapter.name, bus->reg0 & 0xff);
> -	I915_WRITE(GMBUS0 + reg_offset, 0);
> +	I915_WRITE(GMBUS0, 0);
>  
>  	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
>  	bus->force_bit = 1;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 26/43] drm/i915: Protect register macro arguments

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Always put parens around macro argument evaluations.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 92 ++++++++++++++++++++---------------------
 1 file changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0216771..21d49e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -429,7 +429,7 @@
 #define   ASYNC_FLIP                (1<<22)
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
-#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
+#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
@@ -1250,7 +1250,7 @@ enum skl_disp_power_wells {
 #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1<<27)
 #define  PORT_PLL_DCO_AMP_DEFAULT	15
 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
-#define  PORT_PLL_DCO_AMP(x)		(x<<10)
+#define  PORT_PLL_DCO_AMP(x)		((x)<<10)
 #define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
 						_PORT_PLL_0_B,		\
 						_PORT_PLL_0_C)
@@ -1540,8 +1540,8 @@ enum skl_disp_power_wells {
 #define RENDER_HWS_PGA_GEN7	(0x04080)
 #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
-#define   RING_FAULT_SRCID(x)	((x >> 3) & 0xff)
-#define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
+#define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
+#define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
 #define   RING_FAULT_VALID	(1<<0)
 #define DONE_REG		0x40b0
 #define GEN8_PRIVATE_PAT_LO	0x40e0
@@ -1626,9 +1626,9 @@ enum skl_disp_power_wells {
 #define   ERR_INT_PIPE_CRC_DONE_B	(1<<5)
 #define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
 #define   ERR_INT_PIPE_CRC_DONE_A	(1<<2)
-#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + pipe*3))
+#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + (pipe)*3))
 #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
-#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
+#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
 
 #define GEN8_FAULT_TLB_DATA0		0x04b10
 #define GEN8_FAULT_TLB_DATA1		0x04b14
@@ -1689,8 +1689,8 @@ enum skl_disp_power_wells {
 #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
 #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
-#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << (slice * 2))
-#define   GEN9_IZ_HASHING(slice, val)			((val) << (slice * 2))
+#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
+#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
 
 #define GFX_MODE	0x02520
 #define GFX_MODE_GEN7	0x0229c
@@ -2828,21 +2828,21 @@ enum skl_disp_power_wells {
  *   doesn't need saving on GT1
  */
 #define CXT_SIZE		0x21a0
-#define GEN6_CXT_POWER_SIZE(cxt_reg)	((cxt_reg >> 24) & 0x3f)
-#define GEN6_CXT_RING_SIZE(cxt_reg)	((cxt_reg >> 18) & 0x3f)
-#define GEN6_CXT_RENDER_SIZE(cxt_reg)	((cxt_reg >> 12) & 0x3f)
-#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	((cxt_reg >> 6) & 0x3f)
-#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	((cxt_reg >> 0) & 0x3f)
+#define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
+#define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
+#define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
+#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
+#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
 #define GEN7_CXT_SIZE		0x21a8
-#define GEN7_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 25) & 0x7f)
-#define GEN7_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 22) & 0x7)
-#define GEN7_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 16) & 0x3f)
-#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	((ctx_reg >> 9) & 0x7f)
-#define GEN7_CXT_GT1_SIZE(ctx_reg)	((ctx_reg >> 6) & 0x7)
-#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	((ctx_reg >> 0) & 0x3f)
+#define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
+#define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
+#define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
+#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
+#define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
+#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
 /* Haswell does have the CXT_SIZE register however it does not appear to be
@@ -5173,18 +5173,18 @@ enum skl_disp_power_wells {
 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
 
-#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
+#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
 
 /*
  * CHV pipe B sprite CSC
@@ -5530,7 +5530,7 @@ enum skl_disp_power_wells {
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
-#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
+#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK         (3 << 23)
 #define PS_FILTER_MEDIUM       (0 << 23)
 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
@@ -5695,7 +5695,7 @@ enum skl_disp_power_wells {
 #define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
 #define DE_PLANE_FLIP_DONE_IVB(plane)	(1<< (3 + 5*(plane)))
 #define DE_PIPEA_VBLANK_IVB		(1<<0)
-#define DE_PIPE_VBLANK_IVB(pipe)	(1 << (pipe * 5))
+#define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
 
 #define VLV_MASTER_IER			0x4400c /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1<<31)
@@ -5719,7 +5719,7 @@ enum skl_disp_power_wells {
 #define  GEN8_DE_PIPE_C_IRQ		(1<<18)
 #define  GEN8_DE_PIPE_B_IRQ		(1<<17)
 #define  GEN8_DE_PIPE_A_IRQ		(1<<16)
-#define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+pipe))
+#define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+(pipe)))
 #define  GEN8_GT_VECS_IRQ		(1<<6)
 #define  GEN8_GT_PM_IRQ			(1<<4)
 #define  GEN8_GT_VCS2_IRQ		(1<<3)
@@ -5763,7 +5763,7 @@ enum skl_disp_power_wells {
 #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
 #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
 #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
-#define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + p))
+#define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
 	(GEN8_PIPE_CURSOR_FAULT | \
 	 GEN8_PIPE_SPRITE_FAULT | \
@@ -6022,7 +6022,7 @@ enum skl_disp_power_wells {
 #define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
 #define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
 #define  SERR_INT_TRANS_A_FIFO_UNDERRUN	(1<<0)
-#define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
+#define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
 
 /* digital port hotplug */
 #define PCH_PORT_HOTPLUG		0xc4030	/* SHOTPLUG_CTL */
@@ -6133,9 +6133,9 @@ enum skl_disp_power_wells {
 #define PCH_SSC4_AUX_PARMS      0xc6214
 
 #define PCH_DPLL_SEL		0xc7000
-#define	 TRANS_DPLLB_SEL(pipe)		(1 << (pipe * 4))
+#define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
 #define	 TRANS_DPLLA_SEL(pipe)		0
-#define  TRANS_DPLL_ENABLE(pipe)	(1 << (pipe * 4 + 3))
+#define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
 
 /* transcoder */
 
@@ -7295,7 +7295,7 @@ enum skl_disp_power_wells {
 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
 /* For each transcoder, we need to select the corresponding port clock */
 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
-#define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
+#define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
 
 #define TRANSA_MSA_MISC			0x60410
 #define TRANSB_MSA_MISC			0x61410
@@ -7368,10 +7368,10 @@ enum skl_disp_power_wells {
 
 /* DPLL control2 */
 #define DPLL_CTRL2				0x6C05C
-#define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<(port+15))
+#define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<((port)+15))
 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
-#define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	(clk<<((port)*3+1))
+#define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk)<<((port)*3+1))
 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
 
 /* DPLL Status */
@@ -7384,23 +7384,23 @@ enum skl_disp_power_wells {
 #define DPLL3_CFGCR1	0x6C050
 #define  DPLL_CFGCR1_FREQ_ENABLE	(1<<31)
 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff<<9)
-#define  DPLL_CFGCR1_DCO_FRACTION(x)	(x<<9)
+#define  DPLL_CFGCR1_DCO_FRACTION(x)	((x)<<9)
 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
 
 #define DPLL1_CFGCR2	0x6C044
 #define DPLL2_CFGCR2	0x6C04C
 #define DPLL3_CFGCR2	0x6C054
 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff<<8)
-#define  DPLL_CFGCR2_QDIV_RATIO(x)	(x<<8)
-#define  DPLL_CFGCR2_QDIV_MODE(x)	(x<<7)
+#define  DPLL_CFGCR2_QDIV_RATIO(x)	((x)<<8)
+#define  DPLL_CFGCR2_QDIV_MODE(x)	((x)<<7)
 #define  DPLL_CFGCR2_KDIV_MASK		(3<<5)
-#define  DPLL_CFGCR2_KDIV(x)		(x<<5)
+#define  DPLL_CFGCR2_KDIV(x)		((x)<<5)
 #define  DPLL_CFGCR2_KDIV_5 (0<<5)
 #define  DPLL_CFGCR2_KDIV_2 (1<<5)
 #define  DPLL_CFGCR2_KDIV_3 (2<<5)
 #define  DPLL_CFGCR2_KDIV_1 (3<<5)
 #define  DPLL_CFGCR2_PDIV_MASK		(7<<2)
-#define  DPLL_CFGCR2_PDIV(x)		(x<<2)
+#define  DPLL_CFGCR2_PDIV(x)		((x)<<2)
 #define  DPLL_CFGCR2_PDIV_1 (0<<2)
 #define  DPLL_CFGCR2_PDIV_2 (1<<2)
 #define  DPLL_CFGCR2_PDIV_3 (2<<2)
-- 
2.4.6

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Re: [PATCH 26/43] drm/i915: Protect register macro arguments

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Always put parens around macro argument evaluations.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 92 ++++++++++++++++++++---------------------
>  1 file changed, 46 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0216771..21d49e7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -429,7 +429,7 @@
>  #define   ASYNC_FLIP                (1<<22)
>  #define   DISPLAY_PLANE_A           (0<<20)
>  #define   DISPLAY_PLANE_B           (1<<20)
> -#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> +#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
>  #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
>  #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
>  #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
> @@ -1250,7 +1250,7 @@ enum skl_disp_power_wells {
>  #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1<<27)
>  #define  PORT_PLL_DCO_AMP_DEFAULT	15
>  #define  PORT_PLL_DCO_AMP_MASK		0x3c00
> -#define  PORT_PLL_DCO_AMP(x)		(x<<10)
> +#define  PORT_PLL_DCO_AMP(x)		((x)<<10)
>  #define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
>  						_PORT_PLL_0_B,		\
>  						_PORT_PLL_0_C)
> @@ -1540,8 +1540,8 @@ enum skl_disp_power_wells {
>  #define RENDER_HWS_PGA_GEN7	(0x04080)
>  #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
>  #define   RING_FAULT_GTTSEL_MASK (1<<11)
> -#define   RING_FAULT_SRCID(x)	((x >> 3) & 0xff)
> -#define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
> +#define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
> +#define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
>  #define   RING_FAULT_VALID	(1<<0)
>  #define DONE_REG		0x40b0
>  #define GEN8_PRIVATE_PAT_LO	0x40e0
> @@ -1626,9 +1626,9 @@ enum skl_disp_power_wells {
>  #define   ERR_INT_PIPE_CRC_DONE_B	(1<<5)
>  #define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
>  #define   ERR_INT_PIPE_CRC_DONE_A	(1<<2)
> -#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + pipe*3))
> +#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + (pipe)*3))
>  #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
> -#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
> +#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
>  
>  #define GEN8_FAULT_TLB_DATA0		0x04b10
>  #define GEN8_FAULT_TLB_DATA1		0x04b14
> @@ -1689,8 +1689,8 @@ enum skl_disp_power_wells {
>  #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
>  #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
>  #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
> -#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << (slice * 2))
> -#define   GEN9_IZ_HASHING(slice, val)			((val) << (slice * 2))
> +#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
> +#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
>  
>  #define GFX_MODE	0x02520
>  #define GFX_MODE_GEN7	0x0229c
> @@ -2828,21 +2828,21 @@ enum skl_disp_power_wells {
>   *   doesn't need saving on GT1
>   */
>  #define CXT_SIZE		0x21a0
> -#define GEN6_CXT_POWER_SIZE(cxt_reg)	((cxt_reg >> 24) & 0x3f)
> -#define GEN6_CXT_RING_SIZE(cxt_reg)	((cxt_reg >> 18) & 0x3f)
> -#define GEN6_CXT_RENDER_SIZE(cxt_reg)	((cxt_reg >> 12) & 0x3f)
> -#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	((cxt_reg >> 6) & 0x3f)
> -#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	((cxt_reg >> 0) & 0x3f)
> +#define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
> +#define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
> +#define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
> +#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
> +#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
>  #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
>  					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
>  					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
>  #define GEN7_CXT_SIZE		0x21a8
> -#define GEN7_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 25) & 0x7f)
> -#define GEN7_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 22) & 0x7)
> -#define GEN7_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 16) & 0x3f)
> -#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	((ctx_reg >> 9) & 0x7f)
> -#define GEN7_CXT_GT1_SIZE(ctx_reg)	((ctx_reg >> 6) & 0x7)
> -#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	((ctx_reg >> 0) & 0x3f)
> +#define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
> +#define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
> +#define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
> +#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
> +#define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
> +#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
>  #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
>  					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
>  /* Haswell does have the CXT_SIZE register however it does not appear to be
> @@ -5173,18 +5173,18 @@ enum skl_disp_power_wells {
>  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
>  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
>  
> -#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> -#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
> +#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
>  
>  /*
>   * CHV pipe B sprite CSC
> @@ -5530,7 +5530,7 @@ enum skl_disp_power_wells {
>  #define PS_SCALER_MODE_DYN  (0 << 28)
>  #define PS_SCALER_MODE_HQ  (1 << 28)
>  #define PS_PLANE_SEL_MASK  (7 << 25)
> -#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
> +#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
>  #define PS_FILTER_MASK         (3 << 23)
>  #define PS_FILTER_MEDIUM       (0 << 23)
>  #define PS_FILTER_EDGE_ENHANCE (2 << 23)
> @@ -5695,7 +5695,7 @@ enum skl_disp_power_wells {
>  #define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
>  #define DE_PLANE_FLIP_DONE_IVB(plane)	(1<< (3 + 5*(plane)))
>  #define DE_PIPEA_VBLANK_IVB		(1<<0)
> -#define DE_PIPE_VBLANK_IVB(pipe)	(1 << (pipe * 5))
> +#define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
>  
>  #define VLV_MASTER_IER			0x4400c /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1<<31)
> @@ -5719,7 +5719,7 @@ enum skl_disp_power_wells {
>  #define  GEN8_DE_PIPE_C_IRQ		(1<<18)
>  #define  GEN8_DE_PIPE_B_IRQ		(1<<17)
>  #define  GEN8_DE_PIPE_A_IRQ		(1<<16)
> -#define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+pipe))
> +#define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+(pipe)))
>  #define  GEN8_GT_VECS_IRQ		(1<<6)
>  #define  GEN8_GT_PM_IRQ			(1<<4)
>  #define  GEN8_GT_VCS2_IRQ		(1<<3)
> @@ -5763,7 +5763,7 @@ enum skl_disp_power_wells {
>  #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
>  #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
>  #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
> -#define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + p))
> +#define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
>  #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
>  	(GEN8_PIPE_CURSOR_FAULT | \
>  	 GEN8_PIPE_SPRITE_FAULT | \
> @@ -6022,7 +6022,7 @@ enum skl_disp_power_wells {
>  #define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
>  #define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
>  #define  SERR_INT_TRANS_A_FIFO_UNDERRUN	(1<<0)
> -#define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
> +#define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
>  
>  /* digital port hotplug */
>  #define PCH_PORT_HOTPLUG		0xc4030	/* SHOTPLUG_CTL */
> @@ -6133,9 +6133,9 @@ enum skl_disp_power_wells {
>  #define PCH_SSC4_AUX_PARMS      0xc6214
>  
>  #define PCH_DPLL_SEL		0xc7000
> -#define	 TRANS_DPLLB_SEL(pipe)		(1 << (pipe * 4))
> +#define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
>  #define	 TRANS_DPLLA_SEL(pipe)		0
> -#define  TRANS_DPLL_ENABLE(pipe)	(1 << (pipe * 4 + 3))
> +#define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
>  
>  /* transcoder */
>  
> @@ -7295,7 +7295,7 @@ enum skl_disp_power_wells {
>  #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
>  /* For each transcoder, we need to select the corresponding port clock */
>  #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
> -#define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
> +#define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
>  
>  #define TRANSA_MSA_MISC			0x60410
>  #define TRANSB_MSA_MISC			0x61410
> @@ -7368,10 +7368,10 @@ enum skl_disp_power_wells {
>  
>  /* DPLL control2 */
>  #define DPLL_CTRL2				0x6C05C
> -#define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<(port+15))
> +#define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<((port)+15))
>  #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
>  #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
> -#define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	(clk<<((port)*3+1))
> +#define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk)<<((port)*3+1))
>  #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
>  
>  /* DPLL Status */
> @@ -7384,23 +7384,23 @@ enum skl_disp_power_wells {
>  #define DPLL3_CFGCR1	0x6C050
>  #define  DPLL_CFGCR1_FREQ_ENABLE	(1<<31)
>  #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff<<9)
> -#define  DPLL_CFGCR1_DCO_FRACTION(x)	(x<<9)
> +#define  DPLL_CFGCR1_DCO_FRACTION(x)	((x)<<9)
>  #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
>  
>  #define DPLL1_CFGCR2	0x6C044
>  #define DPLL2_CFGCR2	0x6C04C
>  #define DPLL3_CFGCR2	0x6C054
>  #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff<<8)
> -#define  DPLL_CFGCR2_QDIV_RATIO(x)	(x<<8)
> -#define  DPLL_CFGCR2_QDIV_MODE(x)	(x<<7)
> +#define  DPLL_CFGCR2_QDIV_RATIO(x)	((x)<<8)
> +#define  DPLL_CFGCR2_QDIV_MODE(x)	((x)<<7)
>  #define  DPLL_CFGCR2_KDIV_MASK		(3<<5)
> -#define  DPLL_CFGCR2_KDIV(x)		(x<<5)
> +#define  DPLL_CFGCR2_KDIV(x)		((x)<<5)
>  #define  DPLL_CFGCR2_KDIV_5 (0<<5)
>  #define  DPLL_CFGCR2_KDIV_2 (1<<5)
>  #define  DPLL_CFGCR2_KDIV_3 (2<<5)
>  #define  DPLL_CFGCR2_KDIV_1 (3<<5)
>  #define  DPLL_CFGCR2_PDIV_MASK		(7<<2)
> -#define  DPLL_CFGCR2_PDIV(x)		(x<<2)
> +#define  DPLL_CFGCR2_PDIV(x)		((x)<<2)
>  #define  DPLL_CFGCR2_PDIV_1 (0<<2)
>  #define  DPLL_CFGCR2_PDIV_2 (1<<2)
>  #define  DPLL_CFGCR2_PDIV_3 (2<<2)
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A few register mask defines were missing the '0x' from hex numbers. Or
at least I assume those were meant to be hex numbers. Put the '0x' in
place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 21d49e7..02f0935 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4234,7 +4234,7 @@ enum skl_disp_power_wells {
 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
-#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
+#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
 
@@ -7819,7 +7819,7 @@ enum skl_disp_power_wells {
 #define  VIRTUAL_CHANNEL_SHIFT				6
 #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
 #define  DATA_TYPE_SHIFT				0
-#define  DATA_TYPE_MASK					(3f << 0)
+#define  DATA_TYPE_MASK					(0x3f << 0)
 /* data type values, see include/video/mipi_display.h */
 
 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
-- 
2.4.6

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Re: [PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> A few register mask defines were missing the '0x' from hex numbers. Or
> at least I assume those were meant to be hex numbers. Put the '0x' in
> place.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 21d49e7..02f0935 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4234,7 +4234,7 @@ enum skl_disp_power_wells {
>  #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
>  #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
>  #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
> -#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
> +#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
>  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
>  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
>  
> @@ -7819,7 +7819,7 @@ enum skl_disp_power_wells {
>  #define  VIRTUAL_CHANNEL_SHIFT				6
>  #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
>  #define  DATA_TYPE_SHIFT				0
> -#define  DATA_TYPE_MASK					(3f << 0)
> +#define  DATA_TYPE_MASK					(0x3f << 0)
>  /* data type values, see include/video/mipi_display.h */
>  
>  #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
> 

Hah!  Maybe they're supposed to be floats though!  We should use more
floats in masks in general I believe.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 16948b2..24f68de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -139,27 +139,30 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
-#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
-	u32 val = I915_READ(reg); \
-	if (val) { \
-		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
-		     (reg), val); \
-		I915_WRITE((reg), 0xffffffff); \
-		POSTING_READ(reg); \
-		I915_WRITE((reg), 0xffffffff); \
-		POSTING_READ(reg); \
-	} \
-} while (0)
+static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
+{
+	u32 val = I915_READ(reg);
+
+	if (val == 0)
+		return;
+
+	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
+	     reg, val);
+	I915_WRITE(reg, 0xffffffff);
+	POSTING_READ(reg);
+	I915_WRITE(reg, 0xffffffff);
+	POSTING_READ(reg);
+}
 
 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
-	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
+	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 	POSTING_READ(GEN8_##type##_IMR(which)); \
 } while (0)
 
 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
-	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
+	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 	I915_WRITE(type##IER, (ier_val)); \
 	I915_WRITE(type##IMR, (imr_val)); \
 	POSTING_READ(type##IMR); \
@@ -3276,7 +3279,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 	else
 		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
 
-	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
+	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
 }
 
-- 
2.4.6

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Re: [PATCH 28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++--------------
>  1 file changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 16948b2..24f68de 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -139,27 +139,30 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
>  /*
>   * We should clear IMR at preinstall/uninstall, and just check at postinstall.
>   */
> -#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
> -	u32 val = I915_READ(reg); \
> -	if (val) { \
> -		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
> -		     (reg), val); \
> -		I915_WRITE((reg), 0xffffffff); \
> -		POSTING_READ(reg); \
> -		I915_WRITE((reg), 0xffffffff); \
> -		POSTING_READ(reg); \
> -	} \
> -} while (0)
> +static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
> +{
> +	u32 val = I915_READ(reg);
> +
> +	if (val == 0)
> +		return;
> +
> +	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
> +	     reg, val);
> +	I915_WRITE(reg, 0xffffffff);
> +	POSTING_READ(reg);
> +	I915_WRITE(reg, 0xffffffff);
> +	POSTING_READ(reg);
> +}
>  
>  #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
> -	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
> +	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
>  	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
>  	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
>  	POSTING_READ(GEN8_##type##_IMR(which)); \
>  } while (0)
>  
>  #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
> -	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
> +	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
>  	I915_WRITE(type##IER, (ier_val)); \
>  	I915_WRITE(type##IMR, (imr_val)); \
>  	POSTING_READ(type##IMR); \
> @@ -3276,7 +3279,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>  	else
>  		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
>  
> -	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
> +	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
>  	I915_WRITE(SDEIMR, ~mask);
>  }
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 29/43] drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me
for a long time. The work equally well for ELK and onwards, so let's
s/GM45/G4X/.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |  6 +++---
 drivers/gpu/drm/i915/i915_reg.h      | 12 ++++++------
 drivers/gpu/drm/i915/intel_display.c |  4 ++--
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 24f68de..4b61a42 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -671,10 +671,10 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 }
 
-static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
+static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int reg = PIPE_FRMCOUNT_GM45(pipe);
+	int reg = PIPE_FRMCOUNT_G4X(pipe);
 
 	return I915_READ(reg);
 }
@@ -4311,7 +4311,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
 	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
-		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
 	} else {
 		dev->driver->get_vblank_counter = i915_get_vblank_counter;
 		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02f0935..0cc41e4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4796,10 +4796,10 @@ enum skl_disp_power_wells {
 #define   PIPE_PIXEL_MASK         0x00ffffff
 #define   PIPE_PIXEL_SHIFT        0
 /* GM45+ just has to be different */
-#define _PIPEA_FRMCOUNT_GM45	0x70040
-#define _PIPEA_FLIPCOUNT_GM45	0x70044
-#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
-#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
+#define _PIPEA_FRMCOUNT_G4X	0x70040
+#define _PIPEA_FLIPCOUNT_G4X	0x70044
+#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
+#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
 
 /* Cursor A & B regs */
 #define _CURACNTR		0x70080
@@ -4962,8 +4962,8 @@ enum skl_disp_power_wells {
 #define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
-#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
 
 
 /* Display B control */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 92e624b..0074781 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10769,7 +10769,7 @@ static bool page_flip_finished(struct intel_crtc *crtc)
 	 */
 	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
 		crtc->unpin_work->gtt_offset &&
-		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
+		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
 				    crtc->unpin_work->flip_count);
 }
 
@@ -11374,7 +11374,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
 
 	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
-		work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
+		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
 
 	if (IS_VALLEYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
-- 
2.4.6

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Re: [PATCH 29/43] drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me
> for a long time. The work equally well for ELK and onwards, so let's
> s/GM45/G4X/.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c      |  6 +++---
>  drivers/gpu/drm/i915/i915_reg.h      | 12 ++++++------
>  drivers/gpu/drm/i915/intel_display.c |  4 ++--
>  3 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 24f68de..4b61a42 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -671,10 +671,10 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
>  	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
>  }
>  
> -static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
> +static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int reg = PIPE_FRMCOUNT_GM45(pipe);
> +	int reg = PIPE_FRMCOUNT_G4X(pipe);
>  
>  	return I915_READ(reg);
>  }
> @@ -4311,7 +4311,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
>  	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
>  		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
> -		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
> +		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
>  	} else {
>  		dev->driver->get_vblank_counter = i915_get_vblank_counter;
>  		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02f0935..0cc41e4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4796,10 +4796,10 @@ enum skl_disp_power_wells {
>  #define   PIPE_PIXEL_MASK         0x00ffffff
>  #define   PIPE_PIXEL_SHIFT        0
>  /* GM45+ just has to be different */
> -#define _PIPEA_FRMCOUNT_GM45	0x70040
> -#define _PIPEA_FLIPCOUNT_GM45	0x70044
> -#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
> -#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
> +#define _PIPEA_FRMCOUNT_G4X	0x70040
> +#define _PIPEA_FLIPCOUNT_G4X	0x70044
> +#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
> +#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
>  
>  /* Cursor A & B regs */
>  #define _CURACNTR		0x70080
> @@ -4962,8 +4962,8 @@ enum skl_disp_power_wells {
>  #define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
> -#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)
> -#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)
> +#define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
> +#define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
>  
>  
>  /* Display B control */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 92e624b..0074781 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10769,7 +10769,7 @@ static bool page_flip_finished(struct intel_crtc *crtc)
>  	 */
>  	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
>  		crtc->unpin_work->gtt_offset &&
> -		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
> +		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
>  				    crtc->unpin_work->flip_count);
>  }
>  
> @@ -11374,7 +11374,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
>  
>  	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> -		work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
> +		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		ring = &dev_priv->ring[BCS];
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 30/43] drm/i915: Parametrize and fix SWF registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Parametrize the SWF registers. This also fixes the register offsets,
which were mostly garbage in the old defines.

Also save/restore only as many SWF registers that each platform has.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     |  2 +-
 drivers/gpu/drm/i915/i915_reg.h     | 28 +++++++++++------------
 drivers/gpu/drm/i915/i915_suspend.c | 45 ++++++++++++++++++++++++++++---------
 3 files changed, 50 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3bf8a9b..3e35e08 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1041,7 +1041,7 @@ struct i915_suspend_saved_registers {
 	u32 saveMI_ARB_STATE;
 	u32 saveSWF0[16];
 	u32 saveSWF1[16];
-	u32 saveSWF2[3];
+	u32 saveSWF3[3];
 	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 	u32 savePCH_PORT_HOTPLUG;
 	u16 saveGCDGMBUS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cc41e4b..57b9469 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4941,20 +4941,20 @@ enum skl_disp_power_wells {
 #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
 #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
 
-/* VBIOS flags */
-#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
-#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
-#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
-#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
-#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
-#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
-#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
-#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
-#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
-#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
-#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
-#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
-#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
+/*
+ * VBIOS flags
+ * gen2:
+ * [00:06] alm,mgm
+ * [10:16] all
+ * [30:32] alm,mgm
+ * gen3+:
+ * [00:0f] all
+ * [10:1f] all
+ * [30:32] all
+ */
+#define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
 
 /* Pipe B */
 #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 1ccac61..2d91821 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -122,12 +122,24 @@ int i915_save_state(struct drm_device *dev)
 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 
 	/* Scratch space */
-	for (i = 0; i < 16; i++) {
-		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
-		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
+	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
+		for (i = 0; i < 7; i++) {
+			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
+			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+		}
+		for (i = 0; i < 3; i++)
+			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
+	} else if (IS_GEN2(dev_priv)) {
+		for (i = 0; i < 7; i++)
+			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
+		for (i = 0; i < 16; i++) {
+			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
+			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+		}
+		for (i = 0; i < 3; i++)
+			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
 	}
-	for (i = 0; i < 3; i++)
-		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 
 	mutex_unlock(&dev->struct_mutex);
 
@@ -156,12 +168,25 @@ int i915_restore_state(struct drm_device *dev)
 	/* Memory arbitration state */
 	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
 
-	for (i = 0; i < 16; i++) {
-		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
-		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
+	/* Scratch space */
+	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
+		for (i = 0; i < 7; i++) {
+			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
+			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+		}
+		for (i = 0; i < 3; i++)
+			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
+	} else if (IS_GEN2(dev_priv)) {
+		for (i = 0; i < 7; i++)
+			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
+		for (i = 0; i < 16; i++) {
+			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
+			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+		}
+		for (i = 0; i < 3; i++)
+			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
 	}
-	for (i = 0; i < 3; i++)
-		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
 
 	mutex_unlock(&dev->struct_mutex);
 
-- 
2.4.6

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Re: [PATCH 30/43] drm/i915: Parametrize and fix SWF registers

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Parametrize the SWF registers. This also fixes the register offsets,
> which were mostly garbage in the old defines.
> 
> Also save/restore only as many SWF registers that each platform has.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h     |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h     | 28 +++++++++++------------
>  drivers/gpu/drm/i915/i915_suspend.c | 45 ++++++++++++++++++++++++++++---------
>  3 files changed, 50 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3bf8a9b..3e35e08 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1041,7 +1041,7 @@ struct i915_suspend_saved_registers {
>  	u32 saveMI_ARB_STATE;
>  	u32 saveSWF0[16];
>  	u32 saveSWF1[16];
> -	u32 saveSWF2[3];
> +	u32 saveSWF3[3];
>  	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
>  	u32 savePCH_PORT_HOTPLUG;
>  	u16 saveGCDGMBUS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0cc41e4b..57b9469 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4941,20 +4941,20 @@ enum skl_disp_power_wells {
>  #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
>  #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
>  
> -/* VBIOS flags */
> -#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
> -#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
> -#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
> -#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
> -#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
> -#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
> -#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
> -#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
> -#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
> -#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
> -#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
> -#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
> -#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
> +/*
> + * VBIOS flags
> + * gen2:
> + * [00:06] alm,mgm
> + * [10:16] all
> + * [30:32] alm,mgm
> + * gen3+:
> + * [00:0f] all
> + * [10:1f] all
> + * [30:32] all
> + */
> +#define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> +#define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> +#define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
>  
>  /* Pipe B */
>  #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 1ccac61..2d91821 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -122,12 +122,24 @@ int i915_save_state(struct drm_device *dev)
>  	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
>  
>  	/* Scratch space */
> -	for (i = 0; i < 16; i++) {
> -		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
> -		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
> +	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> +		for (i = 0; i < 7; i++) {
> +			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> +		}
> +		for (i = 0; i < 3; i++)
> +			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> +	} else if (IS_GEN2(dev_priv)) {
> +		for (i = 0; i < 7; i++)
> +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> +	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> +		for (i = 0; i < 16; i++) {
> +			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> +		}
> +		for (i = 0; i < 3; i++)
> +			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
>  	}
> -	for (i = 0; i < 3; i++)
> -		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
>  
>  	mutex_unlock(&dev->struct_mutex);
>  
> @@ -156,12 +168,25 @@ int i915_restore_state(struct drm_device *dev)
>  	/* Memory arbitration state */
>  	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
>  
> -	for (i = 0; i < 16; i++) {
> -		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
> -		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
> +	/* Scratch space */
> +	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> +		for (i = 0; i < 7; i++) {
> +			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +		}
> +		for (i = 0; i < 3; i++)
> +			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> +	} else if (IS_GEN2(dev_priv)) {
> +		for (i = 0; i < 7; i++)
> +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> +		for (i = 0; i < 16; i++) {
> +			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +		}
> +		for (i = 0; i < 3; i++)
> +			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
>  	}
> -	for (i = 0; i < 3; i++)
> -		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
>  
>  	mutex_unlock(&dev->struct_mutex);
>  
> 

I think these were added speculatively in the first place.  Maybe we'd
see a bug on 8xx without these saved & restored, but I wonder if we'd
see anything else?

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 30/43] drm/i915: Parametrize and fix SWF registers

[Ville Syrjälä]

On Mon, Oct 12, 2015 at 09:07:17AM -0700, Jesse Barnes wrote:
> On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Parametrize the SWF registers. This also fixes the register offsets,
> > which were mostly garbage in the old defines.
> > 
> > Also save/restore only as many SWF registers that each platform has.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h     |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h     | 28 +++++++++++------------
> >  drivers/gpu/drm/i915/i915_suspend.c | 45 ++++++++++++++++++++++++++++---------
> >  3 files changed, 50 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 3bf8a9b..3e35e08 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1041,7 +1041,7 @@ struct i915_suspend_saved_registers {
> >  	u32 saveMI_ARB_STATE;
> >  	u32 saveSWF0[16];
> >  	u32 saveSWF1[16];
> > -	u32 saveSWF2[3];
> > +	u32 saveSWF3[3];
> >  	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
> >  	u32 savePCH_PORT_HOTPLUG;
> >  	u16 saveGCDGMBUS;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0cc41e4b..57b9469 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4941,20 +4941,20 @@ enum skl_disp_power_wells {
> >  #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
> >  #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
> >  
> > -/* VBIOS flags */
> > -#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
> > -#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
> > -#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
> > -#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
> > -#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
> > -#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
> > -#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
> > -#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
> > -#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
> > -#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
> > -#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
> > -#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
> > -#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
> > +/*
> > + * VBIOS flags
> > + * gen2:
> > + * [00:06] alm,mgm
> > + * [10:16] all
> > + * [30:32] alm,mgm
> > + * gen3+:
> > + * [00:0f] all
> > + * [10:1f] all
> > + * [30:32] all
> > + */
> > +#define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> > +#define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> > +#define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
> >  
> >  /* Pipe B */
> >  #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
> > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> > index 1ccac61..2d91821 100644
> > --- a/drivers/gpu/drm/i915/i915_suspend.c
> > +++ b/drivers/gpu/drm/i915/i915_suspend.c
> > @@ -122,12 +122,24 @@ int i915_save_state(struct drm_device *dev)
> >  	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
> >  
> >  	/* Scratch space */
> > -	for (i = 0; i < 16; i++) {
> > -		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
> > -		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
> > +	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> > +		for (i = 0; i < 7; i++) {
> > +			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> > +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> > +	} else if (IS_GEN2(dev_priv)) {
> > +		for (i = 0; i < 7; i++)
> > +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> > +	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> > +		for (i = 0; i < 16; i++) {
> > +			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> > +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> >  	}
> > -	for (i = 0; i < 3; i++)
> > -		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
> >  
> >  	mutex_unlock(&dev->struct_mutex);
> >  
> > @@ -156,12 +168,25 @@ int i915_restore_state(struct drm_device *dev)
> >  	/* Memory arbitration state */
> >  	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
> >  
> > -	for (i = 0; i < 16; i++) {
> > -		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
> > -		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
> > +	/* Scratch space */
> > +	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> > +		for (i = 0; i < 7; i++) {
> > +			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> > +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> > +	} else if (IS_GEN2(dev_priv)) {
> > +		for (i = 0; i < 7; i++)
> > +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> > +	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> > +		for (i = 0; i < 16; i++) {
> > +			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> > +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> >  	}
> > -	for (i = 0; i < 3; i++)
> > -		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
> >  
> >  	mutex_unlock(&dev->struct_mutex);
> >  
> > 
> 
> I think these were added speculatively in the first place.  Maybe we'd
> see a bug on 8xx without these saved & restored, but I wonder if we'd
> see anything else?

It's hard to know what the firmware does with these. IIRC there's a
"driver loaded" bit in there somewhere we perhaps should set to tell
the firmware to stay away.

Oh and I did eventually find the SWF registers for PCH platforms too.
Currently we don't save/restore those at all, so not sure we should
start either.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
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[PATCH 31/43] drm/i915: Throw out some useless variables

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop some useless 'reg' variables when we only use them once.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 70 +++++++++++-------------------------
 2 files changed, 21 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b61a42..d181dab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -674,9 +674,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int reg = PIPE_FRMCOUNT_G4X(pipe);
 
-	return I915_READ(reg);
+	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
 
 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0074781..16e204d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1110,12 +1110,10 @@ static const char *state_string(bool enabled)
 void assert_pll(struct drm_i915_private *dev_priv,
 		enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(DPLL(pipe));
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "PLL state assertion failure (expected %s, current %s)\n",
@@ -1172,20 +1170,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
-	int reg;
-	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 
 	if (HAS_DDI(dev_priv->dev)) {
 		/* DDI does not have a specific FDI_TX register */
-		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
-		val = I915_READ(reg);
+		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 	} else {
-		reg = FDI_TX_CTL(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(FDI_TX_CTL(pipe));
 		cur_state = !!(val & FDI_TX_ENABLE);
 	}
 	I915_STATE_WARN(cur_state != state,
@@ -1198,12 +1192,10 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
@@ -1215,7 +1207,6 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
-	int reg;
 	u32 val;
 
 	/* ILK FDI PLL is always enabled */
@@ -1226,20 +1217,17 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	if (HAS_DDI(dev_priv->dev))
 		return;
 
-	reg = FDI_TX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_TX_CTL(pipe));
 	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 
 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_PLL_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
@@ -1309,8 +1297,6 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
 void assert_pipe(struct drm_i915_private *dev_priv,
 		 enum pipe pipe, bool state)
 {
-	int reg;
-	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
@@ -1324,8 +1310,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
 		cur_state = false;
 	} else {
-		reg = PIPECONF(cpu_transcoder);
-		val = I915_READ(reg);
+		u32 val = I915_READ(PIPECONF(cpu_transcoder));
 		cur_state = !!(val & PIPECONF_ENABLE);
 	}
 
@@ -1337,12 +1322,10 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 static void assert_plane(struct drm_i915_private *dev_priv,
 			 enum plane plane, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
+	val = I915_READ(DSPCNTR(plane));
 	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "plane %c assertion failure (expected %s, current %s)\n",
@@ -1356,14 +1339,11 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int reg, i;
-	u32 val;
-	int cur_pipe;
+	int i;
 
 	/* Primary planes are fixed to pipes on gen4+ */
 	if (INTEL_INFO(dev)->gen >= 4) {
-		reg = DSPCNTR(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(DSPCNTR(pipe));
 		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
 		     "plane %c assertion failure, should be disabled but not\n",
 		     plane_name(pipe));
@@ -1372,9 +1352,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 
 	/* Need to check both planes against the pipe */
 	for_each_pipe(dev_priv, i) {
-		reg = DSPCNTR(i);
-		val = I915_READ(reg);
-		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
+		u32 val = I915_READ(DSPCNTR(i));
+		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 			DISPPLANE_SEL_PIPE_SHIFT;
 		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
@@ -1386,33 +1365,29 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int reg, sprite;
-	u32 val;
+	int sprite;
 
 	if (INTEL_INFO(dev)->gen >= 9) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			val = I915_READ(PLANE_CTL(pipe, sprite));
+			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
 			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
 			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
 			     sprite, pipe_name(pipe));
 		}
 	} else if (IS_VALLEYVIEW(dev)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			reg = SPCNTR(pipe, sprite);
-			val = I915_READ(reg);
+			u32 val = I915_READ(SPCNTR(pipe, sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
 			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 			     sprite_name(pipe, sprite), pipe_name(pipe));
 		}
 	} else if (INTEL_INFO(dev)->gen >= 7) {
-		reg = SPRCTL(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(SPRCTL(pipe));
 		I915_STATE_WARN(val & SPRITE_ENABLE,
 		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(pipe), pipe_name(pipe));
 	} else if (INTEL_INFO(dev)->gen >= 5) {
-		reg = DVSCNTR(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(DVSCNTR(pipe));
 		I915_STATE_WARN(val & DVS_ENABLE,
 		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(pipe), pipe_name(pipe));
@@ -1441,12 +1416,10 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 					   enum pipe pipe)
 {
-	int reg;
 	u32 val;
 	bool enabled;
 
-	reg = PCH_TRANSCONF(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(PCH_TRANSCONF(pipe));
 	enabled = !!(val & TRANS_ENABLE);
 	I915_STATE_WARN(enabled,
 	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
@@ -1553,21 +1526,18 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
-	int reg;
 	u32 val;
 
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
-	reg = PCH_ADPA;
-	val = I915_READ(reg);
+	val = I915_READ(PCH_ADPA);
 	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
 	     "PCH VGA enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 
-	reg = PCH_LVDS;
-	val = I915_READ(reg);
+	val = I915_READ(PCH_LVDS);
 	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
 	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
-- 
2.4.6

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[PATCH v2 31/43] drm/i915: Throw out some useless variables

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop some useless 'reg' variables when we only use them once.

v2: A few more, including a few variable moves

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 75 +++++++++++-------------------------
 drivers/gpu/drm/i915/intel_dp.c      | 10 ++---
 3 files changed, 28 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b61a42..d181dab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -674,9 +674,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int reg = PIPE_FRMCOUNT_G4X(pipe);
 
-	return I915_READ(reg);
+	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
 
 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6f538d5..dc24e22 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1110,12 +1110,10 @@ static const char *state_string(bool enabled)
 void assert_pll(struct drm_i915_private *dev_priv,
 		enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(DPLL(pipe));
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "PLL state assertion failure (expected %s, current %s)\n",
@@ -1172,20 +1170,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
-	int reg;
-	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 
 	if (HAS_DDI(dev_priv->dev)) {
 		/* DDI does not have a specific FDI_TX register */
-		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
-		val = I915_READ(reg);
+		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 	} else {
-		reg = FDI_TX_CTL(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(FDI_TX_CTL(pipe));
 		cur_state = !!(val & FDI_TX_ENABLE);
 	}
 	I915_STATE_WARN(cur_state != state,
@@ -1198,12 +1192,10 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
@@ -1215,7 +1207,6 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
-	int reg;
 	u32 val;
 
 	/* ILK FDI PLL is always enabled */
@@ -1226,20 +1217,17 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	if (HAS_DDI(dev_priv->dev))
 		return;
 
-	reg = FDI_TX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_TX_CTL(pipe));
 	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 
 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_PLL_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
@@ -1309,8 +1297,6 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
 void assert_pipe(struct drm_i915_private *dev_priv,
 		 enum pipe pipe, bool state)
 {
-	int reg;
-	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
@@ -1324,8 +1310,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
 		cur_state = false;
 	} else {
-		reg = PIPECONF(cpu_transcoder);
-		val = I915_READ(reg);
+		u32 val = I915_READ(PIPECONF(cpu_transcoder));
 		cur_state = !!(val & PIPECONF_ENABLE);
 	}
 
@@ -1337,12 +1322,10 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 static void assert_plane(struct drm_i915_private *dev_priv,
 			 enum plane plane, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
+	val = I915_READ(DSPCNTR(plane));
 	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "plane %c assertion failure (expected %s, current %s)\n",
@@ -1356,14 +1339,11 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int reg, i;
-	u32 val;
-	int cur_pipe;
+	int i;
 
 	/* Primary planes are fixed to pipes on gen4+ */
 	if (INTEL_INFO(dev)->gen >= 4) {
-		reg = DSPCNTR(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(DSPCNTR(pipe));
 		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
 		     "plane %c assertion failure, should be disabled but not\n",
 		     plane_name(pipe));
@@ -1372,9 +1352,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 
 	/* Need to check both planes against the pipe */
 	for_each_pipe(dev_priv, i) {
-		reg = DSPCNTR(i);
-		val = I915_READ(reg);
-		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
+		u32 val = I915_READ(DSPCNTR(i));
+		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 			DISPPLANE_SEL_PIPE_SHIFT;
 		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
@@ -1386,33 +1365,29 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int reg, sprite;
-	u32 val;
+	int sprite;
 
 	if (INTEL_INFO(dev)->gen >= 9) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			val = I915_READ(PLANE_CTL(pipe, sprite));
+			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
 			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
 			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
 			     sprite, pipe_name(pipe));
 		}
 	} else if (IS_VALLEYVIEW(dev)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			reg = SPCNTR(pipe, sprite);
-			val = I915_READ(reg);
+			u32 val = I915_READ(SPCNTR(pipe, sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
 			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 			     sprite_name(pipe, sprite), pipe_name(pipe));
 		}
 	} else if (INTEL_INFO(dev)->gen >= 7) {
-		reg = SPRCTL(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(SPRCTL(pipe));
 		I915_STATE_WARN(val & SPRITE_ENABLE,
 		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(pipe), pipe_name(pipe));
 	} else if (INTEL_INFO(dev)->gen >= 5) {
-		reg = DVSCNTR(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(DVSCNTR(pipe));
 		I915_STATE_WARN(val & DVS_ENABLE,
 		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(pipe), pipe_name(pipe));
@@ -1441,12 +1416,10 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 					   enum pipe pipe)
 {
-	int reg;
 	u32 val;
 	bool enabled;
 
-	reg = PCH_TRANSCONF(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(PCH_TRANSCONF(pipe));
 	enabled = !!(val & TRANS_ENABLE);
 	I915_STATE_WARN(enabled,
 	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
@@ -1553,21 +1526,18 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
-	int reg;
 	u32 val;
 
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
-	reg = PCH_ADPA;
-	val = I915_READ(reg);
+	val = I915_READ(PCH_ADPA);
 	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
 	     "PCH VGA enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 
-	reg = PCH_LVDS;
-	val = I915_READ(reg);
+	val = I915_READ(PCH_LVDS);
 	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
 	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
@@ -14864,13 +14834,12 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg, val;
+	u32 val;
 
 	if (INTEL_INFO(dev)->num_pipes == 1)
 		return true;
 
-	reg = DSPCNTR(!crtc->plane);
-	val = I915_READ(reg);
+	val = I915_READ(DSPCNTR(!crtc->plane));
 
 	if ((val & DISPLAY_PLANE_ENABLE) &&
 	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7e64555..0b9f973 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -574,8 +574,6 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 						 edp_notifier);
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 pp_div;
-	u32 pp_ctrl_reg, pp_div_reg;
 
 	if (!is_edp(intel_dp) || code != SYS_RESTART)
 		return 0;
@@ -584,6 +582,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 	if (IS_VALLEYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+		u32 pp_ctrl_reg, pp_div_reg;
+		u32 pp_div;
 
 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
@@ -5526,7 +5526,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	struct intel_dp *intel_dp = dev_priv->drrs.dp;
 	struct intel_crtc_state *config = NULL;
 	struct intel_crtc *intel_crtc = NULL;
-	u32 reg, val;
 	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
 
 	if (refresh_rate <= 0) {
@@ -5588,9 +5587,10 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 			DRM_ERROR("Unsupported refreshrate type\n");
 		}
 	} else if (INTEL_INFO(dev)->gen > 6) {
-		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
-		val = I915_READ(reg);
+		u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
+		u32 val;
 
+		val = I915_READ(reg);
 		if (index > DRRS_HIGH_RR) {
 			if (IS_VALLEYVIEW(dev))
 				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
-- 
2.4.6

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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v2 31/43] drm/i915: Throw out some useless variables

[Jesse Barnes]

On 09/22/2015 09:50 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Drop some useless 'reg' variables when we only use them once.
> 
> v2: A few more, including a few variable moves
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c      |  3 +-
>  drivers/gpu/drm/i915/intel_display.c | 75 +++++++++++-------------------------
>  drivers/gpu/drm/i915/intel_dp.c      | 10 ++---
>  3 files changed, 28 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4b61a42..d181dab 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -674,9 +674,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
>  static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int reg = PIPE_FRMCOUNT_G4X(pipe);
>  
> -	return I915_READ(reg);
> +	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
>  }
>  
>  /* raw reads, only for fast reads of display block, no need for forcewake etc. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6f538d5..dc24e22 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1110,12 +1110,10 @@ static const char *state_string(bool enabled)
>  void assert_pll(struct drm_i915_private *dev_priv,
>  		enum pipe pipe, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = DPLL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(DPLL(pipe));
>  	cur_state = !!(val & DPLL_VCO_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "PLL state assertion failure (expected %s, current %s)\n",
> @@ -1172,20 +1170,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, bool state)
>  {
> -	int reg;
> -	u32 val;
>  	bool cur_state;
>  	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
>  								      pipe);
>  
>  	if (HAS_DDI(dev_priv->dev)) {
>  		/* DDI does not have a specific FDI_TX register */
> -		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>  		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
>  	} else {
> -		reg = FDI_TX_CTL(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(FDI_TX_CTL(pipe));
>  		cur_state = !!(val & FDI_TX_ENABLE);
>  	}
>  	I915_STATE_WARN(cur_state != state,
> @@ -1198,12 +1192,10 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  static void assert_fdi_rx(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = FDI_RX_CTL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(FDI_RX_CTL(pipe));
>  	cur_state = !!(val & FDI_RX_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "FDI RX state assertion failure (expected %s, current %s)\n",
> @@ -1215,7 +1207,6 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
>  static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  				      enum pipe pipe)
>  {
> -	int reg;
>  	u32 val;
>  
>  	/* ILK FDI PLL is always enabled */
> @@ -1226,20 +1217,17 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  	if (HAS_DDI(dev_priv->dev))
>  		return;
>  
> -	reg = FDI_TX_CTL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(FDI_TX_CTL(pipe));
>  	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
>  }
>  
>  void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
>  		       enum pipe pipe, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = FDI_RX_CTL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(FDI_RX_CTL(pipe));
>  	cur_state = !!(val & FDI_RX_PLL_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
> @@ -1309,8 +1297,6 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
>  void assert_pipe(struct drm_i915_private *dev_priv,
>  		 enum pipe pipe, bool state)
>  {
> -	int reg;
> -	u32 val;
>  	bool cur_state;
>  	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
>  								      pipe);
> @@ -1324,8 +1310,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
>  				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
>  		cur_state = false;
>  	} else {
> -		reg = PIPECONF(cpu_transcoder);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(PIPECONF(cpu_transcoder));
>  		cur_state = !!(val & PIPECONF_ENABLE);
>  	}
>  
> @@ -1337,12 +1322,10 @@ void assert_pipe(struct drm_i915_private *dev_priv,
>  static void assert_plane(struct drm_i915_private *dev_priv,
>  			 enum plane plane, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = DSPCNTR(plane);
> -	val = I915_READ(reg);
> +	val = I915_READ(DSPCNTR(plane));
>  	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "plane %c assertion failure (expected %s, current %s)\n",
> @@ -1356,14 +1339,11 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
>  				   enum pipe pipe)
>  {
>  	struct drm_device *dev = dev_priv->dev;
> -	int reg, i;
> -	u32 val;
> -	int cur_pipe;
> +	int i;
>  
>  	/* Primary planes are fixed to pipes on gen4+ */
>  	if (INTEL_INFO(dev)->gen >= 4) {
> -		reg = DSPCNTR(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(DSPCNTR(pipe));
>  		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
>  		     "plane %c assertion failure, should be disabled but not\n",
>  		     plane_name(pipe));
> @@ -1372,9 +1352,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
>  
>  	/* Need to check both planes against the pipe */
>  	for_each_pipe(dev_priv, i) {
> -		reg = DSPCNTR(i);
> -		val = I915_READ(reg);
> -		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> +		u32 val = I915_READ(DSPCNTR(i));
> +		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
>  			DISPPLANE_SEL_PIPE_SHIFT;
>  		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
>  		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
> @@ -1386,33 +1365,29 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
>  				    enum pipe pipe)
>  {
>  	struct drm_device *dev = dev_priv->dev;
> -	int reg, sprite;
> -	u32 val;
> +	int sprite;
>  
>  	if (INTEL_INFO(dev)->gen >= 9) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
> -			val = I915_READ(PLANE_CTL(pipe, sprite));
> +			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
>  			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
>  			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
>  			     sprite, pipe_name(pipe));
>  		}
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
> -			reg = SPCNTR(pipe, sprite);
> -			val = I915_READ(reg);
> +			u32 val = I915_READ(SPCNTR(pipe, sprite));
>  			I915_STATE_WARN(val & SP_ENABLE,
>  			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
>  			     sprite_name(pipe, sprite), pipe_name(pipe));
>  		}
>  	} else if (INTEL_INFO(dev)->gen >= 7) {
> -		reg = SPRCTL(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(SPRCTL(pipe));
>  		I915_STATE_WARN(val & SPRITE_ENABLE,
>  		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
>  		     plane_name(pipe), pipe_name(pipe));
>  	} else if (INTEL_INFO(dev)->gen >= 5) {
> -		reg = DVSCNTR(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(DVSCNTR(pipe));
>  		I915_STATE_WARN(val & DVS_ENABLE,
>  		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
>  		     plane_name(pipe), pipe_name(pipe));
> @@ -1441,12 +1416,10 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
>  static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
>  					   enum pipe pipe)
>  {
> -	int reg;
>  	u32 val;
>  	bool enabled;
>  
> -	reg = PCH_TRANSCONF(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(PCH_TRANSCONF(pipe));
>  	enabled = !!(val & TRANS_ENABLE);
>  	I915_STATE_WARN(enabled,
>  	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
> @@ -1553,21 +1526,18 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
>  static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  				      enum pipe pipe)
>  {
> -	int reg;
>  	u32 val;
>  
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
>  
> -	reg = PCH_ADPA;
> -	val = I915_READ(reg);
> +	val = I915_READ(PCH_ADPA);
>  	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
>  	     "PCH VGA enabled on transcoder %c, should be disabled\n",
>  	     pipe_name(pipe));
>  
> -	reg = PCH_LVDS;
> -	val = I915_READ(reg);
> +	val = I915_READ(PCH_LVDS);
>  	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
>  	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
>  	     pipe_name(pipe));
> @@ -14864,13 +14834,12 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg, val;
> +	u32 val;
>  
>  	if (INTEL_INFO(dev)->num_pipes == 1)
>  		return true;
>  
> -	reg = DSPCNTR(!crtc->plane);
> -	val = I915_READ(reg);
> +	val = I915_READ(DSPCNTR(!crtc->plane));
>  
>  	if ((val & DISPLAY_PLANE_ENABLE) &&
>  	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7e64555..0b9f973 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -574,8 +574,6 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  						 edp_notifier);
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 pp_div;
> -	u32 pp_ctrl_reg, pp_div_reg;
>  
>  	if (!is_edp(intel_dp) || code != SYS_RESTART)
>  		return 0;
> @@ -584,6 +582,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
> +		u32 pp_ctrl_reg, pp_div_reg;
> +		u32 pp_div;
>  
>  		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
>  		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
> @@ -5526,7 +5526,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  	struct intel_dp *intel_dp = dev_priv->drrs.dp;
>  	struct intel_crtc_state *config = NULL;
>  	struct intel_crtc *intel_crtc = NULL;
> -	u32 reg, val;
>  	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>  
>  	if (refresh_rate <= 0) {
> @@ -5588,9 +5587,10 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  			DRM_ERROR("Unsupported refreshrate type\n");
>  		}
>  	} else if (INTEL_INFO(dev)->gen > 6) {
> -		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> -		val = I915_READ(reg);
> +		u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> +		u32 val;
>  
> +		val = I915_READ(reg);
>  		if (index > DRRS_HIGH_RR) {
>  			if (IS_VALLEYVIEW(dev))
>  				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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[PATCH 32/43] drm/i915: Clean up LVDS register handling

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Keep single 'lvds_reg' and 'lvds' variable around in
intel_lvds_init(), and read it just once at the start.

Also intel_lvds_get_config() doesn't need to figure out which reg to use
since it can just consult lvds_encoder->reg.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lvds.c | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2c2d1f0..35bad71 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -98,15 +98,11 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 lvds_reg, tmp, flags = 0;
+	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
+	u32 tmp, flags = 0;
 	int dotclock;
 
-	if (HAS_PCH_SPLIT(dev))
-		lvds_reg = PCH_LVDS;
-	else
-		lvds_reg = LVDS;
-
-	tmp = I915_READ(lvds_reg);
+	tmp = I915_READ(lvds_encoder->reg);
 	if (tmp & LVDS_HSYNC_POLARITY)
 		flags |= DRM_MODE_FLAG_NHSYNC;
 	else
@@ -944,6 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
 	struct drm_display_mode *downclock_mode = NULL;
 	struct edid *edid;
 	struct drm_crtc *crtc;
+	u32 lvds_reg;
 	u32 lvds;
 	int pipe;
 	u8 pin;
@@ -966,8 +963,15 @@ void intel_lvds_init(struct drm_device *dev)
 	if (dmi_check_system(intel_no_lvds))
 		return;
 
+	if (HAS_PCH_SPLIT(dev))
+		lvds_reg = PCH_LVDS;
+	else
+		lvds_reg = LVDS;
+
+	lvds = I915_READ(lvds_reg);
+
 	if (HAS_PCH_SPLIT(dev)) {
-		if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
+		if ((lvds & LVDS_DETECTED) == 0)
 			return;
 		if (dev_priv->vbt.edp_support) {
 			DRM_DEBUG_KMS("disable LVDS for eDP support\n");
@@ -977,8 +981,7 @@ void intel_lvds_init(struct drm_device *dev)
 
 	pin = GMBUS_PIN_PANEL;
 	if (!lvds_is_present_in_vbt(dev, &pin)) {
-		u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
-		if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
+		if ((lvds & LVDS_PORT_EN) == 0) {
 			DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 			return;
 		}
@@ -1055,11 +1058,7 @@ void intel_lvds_init(struct drm_device *dev)
 	connector->interlace_allowed = false;
 	connector->doublescan_allowed = false;
 
-	if (HAS_PCH_SPLIT(dev)) {
-		lvds_encoder->reg = PCH_LVDS;
-	} else {
-		lvds_encoder->reg = LVDS;
-	}
+	lvds_encoder->reg = lvds_reg;
 
 	/* create the scaling mode property */
 	drm_mode_create_scaling_mode_property(dev);
@@ -1140,7 +1139,6 @@ void intel_lvds_init(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev))
 		goto failed;
 
-	lvds = I915_READ(LVDS);
 	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
 	crtc = intel_get_crtc_for_pipe(dev, pipe);
 
-- 
2.4.6

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Re: [PATCH 32/43] drm/i915: Clean up LVDS register handling

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Keep single 'lvds_reg' and 'lvds' variable around in
> intel_lvds_init(), and read it just once at the start.
> 
> Also intel_lvds_get_config() doesn't need to figure out which reg to use
> since it can just consult lvds_encoder->reg.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lvds.c | 30 ++++++++++++++----------------
>  1 file changed, 14 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 2c2d1f0..35bad71 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -98,15 +98,11 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 lvds_reg, tmp, flags = 0;
> +	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
> +	u32 tmp, flags = 0;
>  	int dotclock;
>  
> -	if (HAS_PCH_SPLIT(dev))
> -		lvds_reg = PCH_LVDS;
> -	else
> -		lvds_reg = LVDS;
> -
> -	tmp = I915_READ(lvds_reg);
> +	tmp = I915_READ(lvds_encoder->reg);
>  	if (tmp & LVDS_HSYNC_POLARITY)
>  		flags |= DRM_MODE_FLAG_NHSYNC;
>  	else
> @@ -944,6 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	struct drm_display_mode *downclock_mode = NULL;
>  	struct edid *edid;
>  	struct drm_crtc *crtc;
> +	u32 lvds_reg;
>  	u32 lvds;
>  	int pipe;
>  	u8 pin;
> @@ -966,8 +963,15 @@ void intel_lvds_init(struct drm_device *dev)
>  	if (dmi_check_system(intel_no_lvds))
>  		return;
>  
> +	if (HAS_PCH_SPLIT(dev))
> +		lvds_reg = PCH_LVDS;
> +	else
> +		lvds_reg = LVDS;
> +
> +	lvds = I915_READ(lvds_reg);
> +
>  	if (HAS_PCH_SPLIT(dev)) {
> -		if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
> +		if ((lvds & LVDS_DETECTED) == 0)
>  			return;
>  		if (dev_priv->vbt.edp_support) {
>  			DRM_DEBUG_KMS("disable LVDS for eDP support\n");
> @@ -977,8 +981,7 @@ void intel_lvds_init(struct drm_device *dev)
>  
>  	pin = GMBUS_PIN_PANEL;
>  	if (!lvds_is_present_in_vbt(dev, &pin)) {
> -		u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
> -		if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
> +		if ((lvds & LVDS_PORT_EN) == 0) {
>  			DRM_DEBUG_KMS("LVDS is not present in VBT\n");
>  			return;
>  		}
> @@ -1055,11 +1058,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	connector->interlace_allowed = false;
>  	connector->doublescan_allowed = false;
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> -		lvds_encoder->reg = PCH_LVDS;
> -	} else {
> -		lvds_encoder->reg = LVDS;
> -	}
> +	lvds_encoder->reg = lvds_reg;
>  
>  	/* create the scaling mode property */
>  	drm_mode_create_scaling_mode_property(dev);
> @@ -1140,7 +1139,6 @@ void intel_lvds_init(struct drm_device *dev)
>  	if (HAS_PCH_SPLIT(dev))
>  		goto failed;
>  
> -	lvds = I915_READ(LVDS);
>  	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
>  	crtc = intel_get_crtc_for_pipe(dev, pipe);
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 32/43] drm/i915: Clean up LVDS register handling

[Lukas Wunner]

Hi Ville,

On Fri, Sep 18, 2015 at 08:03:45PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Keep single 'lvds_reg' and 'lvds' variable around in
> intel_lvds_init(), and read it just once at the start.

Hm, is it intentional that you didn't also replace this register readout
at the end of the function?

	lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
				 LVDS_A3_POWER_MASK;

(Sorry, I only noticed this today, post-merge, while rebasing my LVDS
reprobing stuff.)

Best regards,

Lukas

> 
> Also intel_lvds_get_config() doesn't need to figure out which reg to use
> since it can just consult lvds_encoder->reg.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lvds.c | 30 ++++++++++++++----------------
>  1 file changed, 14 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 2c2d1f0..35bad71 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -98,15 +98,11 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 lvds_reg, tmp, flags = 0;
> +	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
> +	u32 tmp, flags = 0;
>  	int dotclock;
>  
> -	if (HAS_PCH_SPLIT(dev))
> -		lvds_reg = PCH_LVDS;
> -	else
> -		lvds_reg = LVDS;
> -
> -	tmp = I915_READ(lvds_reg);
> +	tmp = I915_READ(lvds_encoder->reg);
>  	if (tmp & LVDS_HSYNC_POLARITY)
>  		flags |= DRM_MODE_FLAG_NHSYNC;
>  	else
> @@ -944,6 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	struct drm_display_mode *downclock_mode = NULL;
>  	struct edid *edid;
>  	struct drm_crtc *crtc;
> +	u32 lvds_reg;
>  	u32 lvds;
>  	int pipe;
>  	u8 pin;
> @@ -966,8 +963,15 @@ void intel_lvds_init(struct drm_device *dev)
>  	if (dmi_check_system(intel_no_lvds))
>  		return;
>  
> +	if (HAS_PCH_SPLIT(dev))
> +		lvds_reg = PCH_LVDS;
> +	else
> +		lvds_reg = LVDS;
> +
> +	lvds = I915_READ(lvds_reg);
> +
>  	if (HAS_PCH_SPLIT(dev)) {
> -		if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
> +		if ((lvds & LVDS_DETECTED) == 0)
>  			return;
>  		if (dev_priv->vbt.edp_support) {
>  			DRM_DEBUG_KMS("disable LVDS for eDP support\n");
> @@ -977,8 +981,7 @@ void intel_lvds_init(struct drm_device *dev)
>  
>  	pin = GMBUS_PIN_PANEL;
>  	if (!lvds_is_present_in_vbt(dev, &pin)) {
> -		u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
> -		if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
> +		if ((lvds & LVDS_PORT_EN) == 0) {
>  			DRM_DEBUG_KMS("LVDS is not present in VBT\n");
>  			return;
>  		}
> @@ -1055,11 +1058,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	connector->interlace_allowed = false;
>  	connector->doublescan_allowed = false;
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> -		lvds_encoder->reg = PCH_LVDS;
> -	} else {
> -		lvds_encoder->reg = LVDS;
> -	}
> +	lvds_encoder->reg = lvds_reg;
>  
>  	/* create the scaling mode property */
>  	drm_mode_create_scaling_mode_property(dev);
> @@ -1140,7 +1139,6 @@ void intel_lvds_init(struct drm_device *dev)
>  	if (HAS_PCH_SPLIT(dev))
>  		goto failed;
>  
> -	lvds = I915_READ(LVDS);
>  	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
>  	crtc = intel_get_crtc_for_pipe(dev, pipe);
>  
> -- 
> 2.4.6
> 
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 32/43] drm/i915: Clean up LVDS register handling

[Ville Syrjälä]

On Sun, Nov 01, 2015 at 04:33:57PM +0100, Lukas Wunner wrote:
> Hi Ville,
> 
> On Fri, Sep 18, 2015 at 08:03:45PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Keep single 'lvds_reg' and 'lvds' variable around in
> > intel_lvds_init(), and read it just once at the start.
> 
> Hm, is it intentional that you didn't also replace this register readout
> at the end of the function?
> 
> 	lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
> 				 LVDS_A3_POWER_MASK;

Simply didn't notice that bit.

> 
> (Sorry, I only noticed this today, post-merge, while rebasing my LVDS
> reprobing stuff.)
> 
> Best regards,
> 
> Lukas
> 
> > 
> > Also intel_lvds_get_config() doesn't need to figure out which reg to use
> > since it can just consult lvds_encoder->reg.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_lvds.c | 30 ++++++++++++++----------------
> >  1 file changed, 14 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> > index 2c2d1f0..35bad71 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -98,15 +98,11 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
> >  {
> >  	struct drm_device *dev = encoder->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	u32 lvds_reg, tmp, flags = 0;
> > +	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
> > +	u32 tmp, flags = 0;
> >  	int dotclock;
> >  
> > -	if (HAS_PCH_SPLIT(dev))
> > -		lvds_reg = PCH_LVDS;
> > -	else
> > -		lvds_reg = LVDS;
> > -
> > -	tmp = I915_READ(lvds_reg);
> > +	tmp = I915_READ(lvds_encoder->reg);
> >  	if (tmp & LVDS_HSYNC_POLARITY)
> >  		flags |= DRM_MODE_FLAG_NHSYNC;
> >  	else
> > @@ -944,6 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
> >  	struct drm_display_mode *downclock_mode = NULL;
> >  	struct edid *edid;
> >  	struct drm_crtc *crtc;
> > +	u32 lvds_reg;
> >  	u32 lvds;
> >  	int pipe;
> >  	u8 pin;
> > @@ -966,8 +963,15 @@ void intel_lvds_init(struct drm_device *dev)
> >  	if (dmi_check_system(intel_no_lvds))
> >  		return;
> >  
> > +	if (HAS_PCH_SPLIT(dev))
> > +		lvds_reg = PCH_LVDS;
> > +	else
> > +		lvds_reg = LVDS;
> > +
> > +	lvds = I915_READ(lvds_reg);
> > +
> >  	if (HAS_PCH_SPLIT(dev)) {
> > -		if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
> > +		if ((lvds & LVDS_DETECTED) == 0)
> >  			return;
> >  		if (dev_priv->vbt.edp_support) {
> >  			DRM_DEBUG_KMS("disable LVDS for eDP support\n");
> > @@ -977,8 +981,7 @@ void intel_lvds_init(struct drm_device *dev)
> >  
> >  	pin = GMBUS_PIN_PANEL;
> >  	if (!lvds_is_present_in_vbt(dev, &pin)) {
> > -		u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
> > -		if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
> > +		if ((lvds & LVDS_PORT_EN) == 0) {
> >  			DRM_DEBUG_KMS("LVDS is not present in VBT\n");
> >  			return;
> >  		}
> > @@ -1055,11 +1058,7 @@ void intel_lvds_init(struct drm_device *dev)
> >  	connector->interlace_allowed = false;
> >  	connector->doublescan_allowed = false;
> >  
> > -	if (HAS_PCH_SPLIT(dev)) {
> > -		lvds_encoder->reg = PCH_LVDS;
> > -	} else {
> > -		lvds_encoder->reg = LVDS;
> > -	}
> > +	lvds_encoder->reg = lvds_reg;
> >  
> >  	/* create the scaling mode property */
> >  	drm_mode_create_scaling_mode_property(dev);
> > @@ -1140,7 +1139,6 @@ void intel_lvds_init(struct drm_device *dev)
> >  	if (HAS_PCH_SPLIT(dev))
> >  		goto failed;
> >  
> > -	lvds = I915_READ(LVDS);
> >  	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
> >  	crtc = intel_get_crtc_for_pipe(dev, pipe);
> >  
> > -- 
> > 2.4.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 3294f63..197ca397 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -525,7 +525,7 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 }
 
 /* We give fast paths for the really cool registers */
-#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+#define NEEDS_FORCE_WAKE(reg) \
 	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
 
 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
@@ -727,7 +727,7 @@ static u##x \
 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	GEN6_READ_HEADER(x); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
-	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
+	if (NEEDS_FORCE_WAKE(reg)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 	val = __raw_i915_read##x(dev_priv, reg); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
@@ -761,7 +761,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	GEN6_READ_FOOTER; \
 }
 
-#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)	\
+#define SKL_NEEDS_FORCE_WAKE(reg) \
 	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 
 #define __gen9_read(x) \
@@ -770,9 +770,9 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	enum forcewake_domains fw_engine; \
 	GEN6_READ_HEADER(x); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
-	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))	\
+	if (!SKL_NEEDS_FORCE_WAKE(reg)) \
 		fw_engine = 0; \
-	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))	\
+	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 		fw_engine = FORCEWAKE_RENDER; \
 	else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 		fw_engine = FORCEWAKE_MEDIA; \
@@ -868,7 +868,7 @@ static void \
 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 	u32 __fifo_ret = 0; \
 	GEN6_WRITE_HEADER; \
-	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+	if (NEEDS_FORCE_WAKE(reg)) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
 	__raw_i915_write##x(dev_priv, reg, val); \
@@ -883,7 +883,7 @@ static void \
 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 	u32 __fifo_ret = 0; \
 	GEN6_WRITE_HEADER; \
-	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+	if (NEEDS_FORCE_WAKE(reg)) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
@@ -985,7 +985,7 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 	enum forcewake_domains fw_engine; \
 	GEN6_WRITE_HEADER; \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
-	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) ||	\
+	if (!SKL_NEEDS_FORCE_WAKE(reg) || \
 	    is_gen9_shadowed(dev_priv, reg)) \
 		fw_engine = 0; \
 	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
-- 
2.4.6

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Re: [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE

[Jesse Barnes]

On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 3294f63..197ca397 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -525,7 +525,7 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
>  }
>  
>  /* We give fast paths for the really cool registers */
> -#define NEEDS_FORCE_WAKE(dev_priv, reg) \
> +#define NEEDS_FORCE_WAKE(reg) \
>  	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
>  
>  #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
> @@ -727,7 +727,7 @@ static u##x \
>  gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	GEN6_READ_HEADER(x); \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
> -	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
> +	if (NEEDS_FORCE_WAKE(reg)) \
>  		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
>  	val = __raw_i915_read##x(dev_priv, reg); \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
> @@ -761,7 +761,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	GEN6_READ_FOOTER; \
>  }
>  
> -#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)	\
> +#define SKL_NEEDS_FORCE_WAKE(reg) \
>  	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
>  
>  #define __gen9_read(x) \
> @@ -770,9 +770,9 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	enum forcewake_domains fw_engine; \
>  	GEN6_READ_HEADER(x); \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
> -	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))	\
> +	if (!SKL_NEEDS_FORCE_WAKE(reg)) \
>  		fw_engine = 0; \
> -	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))	\
> +	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
>  		fw_engine = FORCEWAKE_RENDER; \
>  	else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
>  		fw_engine = FORCEWAKE_MEDIA; \
> @@ -868,7 +868,7 @@ static void \
>  gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
>  	u32 __fifo_ret = 0; \
>  	GEN6_WRITE_HEADER; \
> -	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> +	if (NEEDS_FORCE_WAKE(reg)) { \
>  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
>  	} \
>  	__raw_i915_write##x(dev_priv, reg, val); \
> @@ -883,7 +883,7 @@ static void \
>  hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
>  	u32 __fifo_ret = 0; \
>  	GEN6_WRITE_HEADER; \
> -	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> +	if (NEEDS_FORCE_WAKE(reg)) { \
>  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
>  	} \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
> @@ -985,7 +985,7 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
>  	enum forcewake_domains fw_engine; \
>  	GEN6_WRITE_HEADER; \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
> -	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) ||	\
> +	if (!SKL_NEEDS_FORCE_WAKE(reg) || \
>  	    is_gen9_shadowed(dev_priv, reg)) \
>  		fw_engine = 0; \
>  	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE

[Daniel Vetter]

On Mon, Oct 12, 2015 at 09:12:09AM -0700, Jesse Barnes wrote:
> On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--------
> >  1 file changed, 8 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 3294f63..197ca397 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -525,7 +525,7 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  /* We give fast paths for the really cool registers */
> > -#define NEEDS_FORCE_WAKE(dev_priv, reg) \
> > +#define NEEDS_FORCE_WAKE(reg) \
> >  	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
> >  
> >  #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
> > @@ -727,7 +727,7 @@ static u##x \
> >  gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> >  	GEN6_READ_HEADER(x); \
> >  	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
> > -	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
> > +	if (NEEDS_FORCE_WAKE(reg)) \
> >  		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
> >  	val = __raw_i915_read##x(dev_priv, reg); \
> >  	hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
> > @@ -761,7 +761,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> >  	GEN6_READ_FOOTER; \
> >  }
> >  
> > -#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)	\
> > +#define SKL_NEEDS_FORCE_WAKE(reg) \
> >  	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
> >  
> >  #define __gen9_read(x) \
> > @@ -770,9 +770,9 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> >  	enum forcewake_domains fw_engine; \
> >  	GEN6_READ_HEADER(x); \
> >  	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
> > -	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))	\
> > +	if (!SKL_NEEDS_FORCE_WAKE(reg)) \
> >  		fw_engine = 0; \
> > -	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))	\
> > +	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
> >  		fw_engine = FORCEWAKE_RENDER; \
> >  	else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
> >  		fw_engine = FORCEWAKE_MEDIA; \
> > @@ -868,7 +868,7 @@ static void \
> >  gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> >  	u32 __fifo_ret = 0; \
> >  	GEN6_WRITE_HEADER; \
> > -	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> > +	if (NEEDS_FORCE_WAKE(reg)) { \
> >  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
> >  	} \
> >  	__raw_i915_write##x(dev_priv, reg, val); \
> > @@ -883,7 +883,7 @@ static void \
> >  hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> >  	u32 __fifo_ret = 0; \
> >  	GEN6_WRITE_HEADER; \
> > -	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> > +	if (NEEDS_FORCE_WAKE(reg)) { \
> >  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
> >  	} \
> >  	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
> > @@ -985,7 +985,7 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
> >  	enum forcewake_domains fw_engine; \
> >  	GEN6_WRITE_HEADER; \
> >  	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
> > -	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) ||	\
> > +	if (!SKL_NEEDS_FORCE_WAKE(reg) || \
> >  	    is_gen9_shadowed(dev_priv, reg)) \
> >  		fw_engine = 0; \
> >  	else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
> > 
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Merged all the patches Jesse r-b'ed, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 34/43] drm/i915: Turn __raw_i915_read8() & co. in to inline functions

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There's no need for __raw_i915_read8() & co. bot be macros, so make them
inline funcitons. To avoid typo mistakes generate the inline functions
using preprocessor templates.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 32 +++++++++++++++++++++++---------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 197ca397..5b27ee1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -29,19 +29,33 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
-#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
-#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
+#define __raw_read(x, s) \
+static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
+					     uint32_t reg) \
+{ \
+	return read##s(dev_priv->regs + reg); \
+}
 
-#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
-#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
+#define __raw_write(x, s) \
+static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
+				       uint32_t reg, uint##x##_t val) \
+{ \
+	write##s(val, dev_priv->regs + reg); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
 
-#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
-#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
 
-#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
-#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
+#undef __raw_read
+#undef __raw_write
 
-#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
+#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
 
 static const char * const forcewake_domain_names[] = {
 	"render",
-- 
2.4.6

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[PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have a few users of the raw register acces functions outside
intel_uncore.c, so let's just move the functions into intel_drv.h.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h     | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.c     |  2 --
 drivers/gpu/drm/i915/intel_uncore.c | 28 ----------------------------
 4 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 47ef007..2322dac 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1516,7 +1516,7 @@ static int gen6_drpc_info(struct seq_file *m)
 		seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
 	}
 
-	gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
+	gt_core_status = __raw_i915_read32(dev_priv, GEN6_GT_CORE_STATUS);
 	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
 	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3e35e08..91ed3c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3502,4 +3502,32 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
 		i915_gem_request_assign(&ring->trace_irq_req, req);
 }
 
+#define __raw_read(x, s) \
+static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
+					     uint32_t reg) \
+{ \
+	return read##s(dev_priv->regs + reg); \
+}
+
+#define __raw_write(x, s) \
+static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
+				       uint32_t reg, uint##x##_t val) \
+{ \
+	write##s(val, dev_priv->regs + reg); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
+
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
+
+#undef __raw_read
+#undef __raw_write
+
+#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d181dab..a6c23b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -679,8 +679,6 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 }
 
 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
-#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
-
 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5b27ee1..acf9b4b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -29,34 +29,6 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
-#define __raw_read(x, s) \
-static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
-					     uint32_t reg) \
-{ \
-	return read##s(dev_priv->regs + reg); \
-}
-
-#define __raw_write(x, s) \
-static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
-				       uint32_t reg, uint##x##_t val) \
-{ \
-	write##s(val, dev_priv->regs + reg); \
-}
-__raw_read(8, b)
-__raw_read(16, w)
-__raw_read(32, l)
-__raw_read(64, q)
-
-__raw_write(8, b)
-__raw_write(16, w)
-__raw_write(32, l)
-__raw_write(64, q)
-
-#undef __raw_read
-#undef __raw_write
-
-#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
-
 static const char * const forcewake_domain_names[] = {
 	"render",
 	"blitter",
-- 
2.4.6

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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Chris Wilson]

On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have a few users of the raw register acces functions outside
> intel_uncore.c, so let's just move the functions into intel_drv.h.

I would rather see those external users converted to
I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
those _FW macro definitions over to the uncore set.

Also due to how we write and post our accesses, the raw functions can be
the _relaxed variants.
-Chris

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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > We have a few users of the raw register acces functions outside
> > intel_uncore.c, so let's just move the functions into intel_drv.h.
> 
> I would rather see those external users converted to
> I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> those _FW macro definitions over to the uncore set.
> 
> Also due to how we write and post our accesses, the raw functions can be
> the _relaxed variants.

Hmm. I think the only difference with the relaxed vs. not would be
potential compiler reordering of memory accesses vs. mmio. So if we
start using the relaxed versions we may need to start sprinkling
barriers around.

-- 
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Intel OTC
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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Chris Wilson]

On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > We have a few users of the raw register acces functions outside
> > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > 
> > I would rather see those external users converted to
> > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > those _FW macro definitions over to the uncore set.
> > 
> > Also due to how we write and post our accesses, the raw functions can be
> > the _relaxed variants.
> 
> Hmm. I think the only difference with the relaxed vs. not would be
> potential compiler reordering of memory accesses vs. mmio. So if we
> start using the relaxed versions we may need to start sprinkling
> barriers around.

Yes. We have been working under that assumption (weak ordering of writes),
or at least I hope we all have been...
-Chris

-- 
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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 07:33:50PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > We have a few users of the raw register acces functions outside
> > > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > > 
> > > I would rather see those external users converted to
> > > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > > those _FW macro definitions over to the uncore set.
> > > 
> > > Also due to how we write and post our accesses, the raw functions can be
> > > the _relaxed variants.
> > 
> > Hmm. I think the only difference with the relaxed vs. not would be
> > potential compiler reordering of memory accesses vs. mmio. So if we
> > start using the relaxed versions we may need to start sprinkling
> > barriers around.
> 
> Yes. We have been working under that assumption (weak ordering of writes),
> or at least I hope we all have been...

Well, looking at the irq code that uses the _FW, what would prevent the
compiler from eg. reorder the seqno read to happen before the IIR read?
Well in practice function calls are involved, so there's a barrier
there, but say we would want to read the seqno straight from the irq
handler...

-- 
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Intel OTC
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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Chris Wilson]

On Fri, Sep 18, 2015 at 09:37:38PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 07:33:50PM +0100, Chris Wilson wrote:
> > On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> > > On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > > > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrjala@linux.intel.com wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > 
> > > > > We have a few users of the raw register acces functions outside
> > > > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > > > 
> > > > I would rather see those external users converted to
> > > > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > > > those _FW macro definitions over to the uncore set.
> > > > 
> > > > Also due to how we write and post our accesses, the raw functions can be
> > > > the _relaxed variants.
> > > 
> > > Hmm. I think the only difference with the relaxed vs. not would be
> > > potential compiler reordering of memory accesses vs. mmio. So if we
> > > start using the relaxed versions we may need to start sprinkling
> > > barriers around.
> > 
> > Yes. We have been working under that assumption (weak ordering of writes),
> > or at least I hope we all have been...
> 
> Well, looking at the irq code that uses the _FW, what would prevent the
> compiler from eg. reorder the seqno read to happen before the IIR read?
> Well in practice function calls are involved, so there's a barrier
> there, but say we would want to read the seqno straight from the irq
> handler...

What seqno read? We definitely don't want to be doing those expensive
reads from an irq handler...

Anyway, I thought we had strongly ordered reads on x64/x32?
-Chris

-- 
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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 09:37:38PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 07:33:50PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> > > > On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > > > > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrjala@linux.intel.com wrote:
> > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > 
> > > > > > We have a few users of the raw register acces functions outside
> > > > > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > > > > 
> > > > > I would rather see those external users converted to
> > > > > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > > > > those _FW macro definitions over to the uncore set.
> > > > > 
> > > > > Also due to how we write and post our accesses, the raw functions can be
> > > > > the _relaxed variants.
> > > > 
> > > > Hmm. I think the only difference with the relaxed vs. not would be
> > > > potential compiler reordering of memory accesses vs. mmio. So if we
> > > > start using the relaxed versions we may need to start sprinkling
> > > > barriers around.
> > > 
> > > Yes. We have been working under that assumption (weak ordering of writes),
> > > or at least I hope we all have been...
> > 
> > Well, looking at the irq code that uses the _FW, what would prevent the
> > compiler from eg. reorder the seqno read to happen before the IIR read?
> > Well in practice function calls are involved, so there's a barrier
> > there, but say we would want to read the seqno straight from the irq
> > handler...
> 
> What seqno read? We definitely don't want to be doing those expensive
> reads from an irq handler...

Yeah I guess that was a crappy example. Trying to think of a better one,
I figure execlist status could be read from memory, but apparently
that's just mmio. I guess the context update + ELSP write is something
we do from the irq handler, but there are plenty of barriers between
those two it seems. Maybe there's no good example here.

> 
> Anyway, I thought we had strongly ordered reads on x64/x32?

The cpu won't reoder reads vs. reads, or writes vs. writes for that
matter if you ignore the nt stuff and whatnot. But AFAIU the whole
point of _relaxed() on x86 is that it allows the compiler to reoder
memory vs. mmio any which way it wants.

-- 
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Intel OTC
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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Jesse Barnes]

On 09/18/2015 12:26 PM, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
> Yeah I guess that was a crappy example. Trying to think of a better one,
> I figure execlist status could be read from memory, but apparently
> that's just mmio. I guess the context update + ELSP write is something
> we do from the irq handler, but there are plenty of barriers between
> those two it seems. Maybe there's no good example here.
> 
>>
>> Anyway, I thought we had strongly ordered reads on x64/x32?
> 
> The cpu won't reoder reads vs. reads, or writes vs. writes for that
> matter if you ignore the nt stuff and whatnot. But AFAIU the whole
> point of _relaxed() on x86 is that it allows the compiler to reoder
> memory vs. mmio any which way it wants.

If you mean the top level readX_relaxed() functions, those were more
about re-ordering on a large I/O fabric than compiler re-ordering.  I'm
not sure how the compiler handles things these days; I thought maybe the
volatile accesses would imply a re-order barrier as well, since they
could have side effects the compiler can't anticipate (i.e. re-ordering
even read after read could change behavior).  But it would be good to
double check...  and according to memory-barriers.txt we should be safe
there, from the readX_relaxed() section:

"Note that relaxed accesses to the same peripheral are guaranteed to be
ordered with respect to each other."

Jesse

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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Mon, Sep 21, 2015 at 09:26:11AM -0700, Jesse Barnes wrote:
> On 09/18/2015 12:26 PM, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
> > Yeah I guess that was a crappy example. Trying to think of a better one,
> > I figure execlist status could be read from memory, but apparently
> > that's just mmio. I guess the context update + ELSP write is something
> > we do from the irq handler, but there are plenty of barriers between
> > those two it seems. Maybe there's no good example here.
> > 
> >>
> >> Anyway, I thought we had strongly ordered reads on x64/x32?
> > 
> > The cpu won't reoder reads vs. reads, or writes vs. writes for that
> > matter if you ignore the nt stuff and whatnot. But AFAIU the whole
> > point of _relaxed() on x86 is that it allows the compiler to reoder
> > memory vs. mmio any which way it wants.
> 
> If you mean the top level readX_relaxed() functions, those were more
> about re-ordering on a large I/O fabric than compiler re-ordering.  I'm
> not sure how the compiler handles things these days; I thought maybe the
> volatile accesses would imply a re-order barrier as well, since they
> could have side effects the compiler can't anticipate (i.e. re-ordering
> even read after read could change behavior).  But it would be good to
> double check...  and according to memory-barriers.txt we should be safe
> there, from the readX_relaxed() section:
> 
> "Note that relaxed accesses to the same peripheral are guaranteed to be
> ordered with respect to each other."

We have
#define barrier() asm volatile("" ::: "memory")

so I take it someone definitely thinks just volatile isn't enough to
keep the compiler in check.

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Re: [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Jesse Barnes]

On 09/21/2015 09:53 AM, Ville Syrjälä wrote:
> On Mon, Sep 21, 2015 at 09:26:11AM -0700, Jesse Barnes wrote:
>> On 09/18/2015 12:26 PM, Ville Syrjälä wrote:
>>> On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
>>> Yeah I guess that was a crappy example. Trying to think of a better one,
>>> I figure execlist status could be read from memory, but apparently
>>> that's just mmio. I guess the context update + ELSP write is something
>>> we do from the irq handler, but there are plenty of barriers between
>>> those two it seems. Maybe there's no good example here.
>>>
>>>>
>>>> Anyway, I thought we had strongly ordered reads on x64/x32?
>>>
>>> The cpu won't reoder reads vs. reads, or writes vs. writes for that
>>> matter if you ignore the nt stuff and whatnot. But AFAIU the whole
>>> point of _relaxed() on x86 is that it allows the compiler to reoder
>>> memory vs. mmio any which way it wants.
>>
>> If you mean the top level readX_relaxed() functions, those were more
>> about re-ordering on a large I/O fabric than compiler re-ordering.  I'm
>> not sure how the compiler handles things these days; I thought maybe the
>> volatile accesses would imply a re-order barrier as well, since they
>> could have side effects the compiler can't anticipate (i.e. re-ordering
>> even read after read could change behavior).  But it would be good to
>> double check...  and according to memory-barriers.txt we should be safe
>> there, from the readX_relaxed() section:
>>
>> "Note that relaxed accesses to the same peripheral are guaranteed to be
>> ordered with respect to each other."
> 
> We have
> #define barrier() asm volatile("" ::: "memory")
> 
> so I take it someone definitely thinks just volatile isn't enough to
> keep the compiler in check.

Yeah, maybe with respect to other, non-I/O targeted reads & writes
things get messier...

Jesse

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[PATCH 36/43] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we determine the location of the AUX registers in a confusing
way. First we assume the PCH registers are used always, but then we
override it for everything but HSW/BDW to use DP+0x10. Very confusing.

Let's just make it straightforward and simply add a few functions to
pick the right AUX_CTL based on the DP port.

To deal with VLV/CHV we'll include the display_mmio_offset into the
AUX register defines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  54 ++++++++---------
 drivers/gpu/drm/i915/intel_dp.c | 124 ++++++++++++++++++++++++++++------------
 2 files changed, 113 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57b9469..4e97bf2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4182,33 +4182,33 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL			0x64010
-#define DPA_AUX_CH_DATA1		0x64014
-#define DPA_AUX_CH_DATA2		0x64018
-#define DPA_AUX_CH_DATA3		0x6401c
-#define DPA_AUX_CH_DATA4		0x64020
-#define DPA_AUX_CH_DATA5		0x64024
-
-#define DPB_AUX_CH_CTL			0x64110
-#define DPB_AUX_CH_DATA1		0x64114
-#define DPB_AUX_CH_DATA2		0x64118
-#define DPB_AUX_CH_DATA3		0x6411c
-#define DPB_AUX_CH_DATA4		0x64120
-#define DPB_AUX_CH_DATA5		0x64124
-
-#define DPC_AUX_CH_CTL			0x64210
-#define DPC_AUX_CH_DATA1		0x64214
-#define DPC_AUX_CH_DATA2		0x64218
-#define DPC_AUX_CH_DATA3		0x6421c
-#define DPC_AUX_CH_DATA4		0x64220
-#define DPC_AUX_CH_DATA5		0x64224
-
-#define DPD_AUX_CH_CTL			0x64310
-#define DPD_AUX_CH_DATA1		0x64314
-#define DPD_AUX_CH_DATA2		0x64318
-#define DPD_AUX_CH_DATA3		0x6431c
-#define DPD_AUX_CH_DATA4		0x64320
-#define DPD_AUX_CH_DATA5		0x64324
+#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
+#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
+#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
+#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
+#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
+#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
+
+#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
+#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
+#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
+#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
+#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
+#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
+
+#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
+#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
+#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
+#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
+#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
+#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
+
+#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
+#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
+#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
+#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
+#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
+#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
 
 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7e64555..bd8353f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -743,6 +743,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	uint32_t precharge, timeout;
 
 	if (IS_GEN6(dev))
@@ -1008,6 +1009,85 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 	return ret;
 }
 
+static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				enum port port)
+{
+	switch (port) {
+	case PORT_B:
+		return DPB_AUX_CH_CTL;
+	case PORT_C:
+		return DPC_AUX_CH_CTL;
+	case PORT_D:
+		return DPD_AUX_CH_CTL;
+	default:
+		MISSING_CASE(port);
+		return DPB_AUX_CH_CTL;
+	}
+}
+
+static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				enum port port)
+{
+	switch (port) {
+	case PORT_A:
+		return DPA_AUX_CH_CTL;
+	case PORT_B:
+		return PCH_DPB_AUX_CH_CTL;
+	case PORT_C:
+		return PCH_DPC_AUX_CH_CTL;
+	case PORT_D:
+		return PCH_DPD_AUX_CH_CTL;
+	default:
+		MISSING_CASE(port);
+		return DPA_AUX_CH_CTL;
+	}
+}
+
+/*
+ * On SKL we don't have Aux for port E so we rely
+ * on VBT to set a proper alternate aux channel.
+ */
+static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
+{
+	const struct ddi_vbt_port_info *info =
+		&dev_priv->vbt.ddi_port_info[PORT_E];
+
+	switch (info->alternate_aux_channel) {
+	case DP_AUX_A:
+		return PORT_A;
+	case DP_AUX_B:
+		return PORT_B;
+	case DP_AUX_C:
+		return PORT_C;
+	case DP_AUX_D:
+		return PORT_D;
+	default:
+		MISSING_CASE(info->alternate_aux_channel);
+		return PORT_A;
+	}
+}
+
+static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				enum port port)
+{
+	if (port == PORT_E)
+		port = skl_porte_aux_port(dev_priv);
+
+	switch (port) {
+	case PORT_A:
+		return DPA_AUX_CH_CTL;
+	case PORT_B:
+		return DPB_AUX_CH_CTL;
+	case PORT_C:
+		return DPC_AUX_CH_CTL;
+	case PORT_D:
+		return DPD_AUX_CH_CTL;
+	default:
+		MISSING_CASE(port);
+		return DPA_AUX_CH_CTL;
+	}
+}
+
 static void
 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
@@ -1015,67 +1095,35 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	enum port port = intel_dig_port->port;
-	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
 	const char *name = NULL;
-	uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
 	int ret;
 
-	/* On SKL we don't have Aux for port E so we rely on VBT to set
-	 * a proper alternate aux channel.
-	 */
-	if (IS_SKYLAKE(dev) && port == PORT_E) {
-		switch (info->alternate_aux_channel) {
-		case DP_AUX_B:
-			porte_aux_ctl_reg = DPB_AUX_CH_CTL;
-			break;
-		case DP_AUX_C:
-			porte_aux_ctl_reg = DPC_AUX_CH_CTL;
-			break;
-		case DP_AUX_D:
-			porte_aux_ctl_reg = DPD_AUX_CH_CTL;
-			break;
-		case DP_AUX_A:
-		default:
-			porte_aux_ctl_reg = DPA_AUX_CH_CTL;
-		}
-	}
-
 	switch (port) {
 	case PORT_A:
-		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 		name = "DPDDC-A";
 		break;
 	case PORT_B:
-		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 		name = "DPDDC-B";
 		break;
 	case PORT_C:
-		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 		name = "DPDDC-C";
 		break;
 	case PORT_D:
-		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 		name = "DPDDC-D";
 		break;
 	case PORT_E:
-		intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
 		name = "DPDDC-E";
 		break;
 	default:
 		BUG();
 	}
 
-	/*
-	 * The AUX_CTL register is usually DP_CTL + 0x10.
-	 *
-	 * On Haswell and Broadwell though:
-	 *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
-	 *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
-	 *
-	 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
-	 */
-	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
-		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
+	else if (HAS_PCH_SPLIT(dev_priv))
+		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
+	else
+		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
 
 	intel_dp->aux.name = name;
 	intel_dp->aux.dev = dev->dev;
-- 
2.4.6

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[PATCH 37/43] drm/i915: Replace the aux ddc name switch statement with a table

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++-------------------------
 1 file changed, 13 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bd8353f..fa4e8b1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1095,28 +1095,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	enum port port = intel_dig_port->port;
-	const char *name = NULL;
 	int ret;
-
-	switch (port) {
-	case PORT_A:
-		name = "DPDDC-A";
-		break;
-	case PORT_B:
-		name = "DPDDC-B";
-		break;
-	case PORT_C:
-		name = "DPDDC-C";
-		break;
-	case PORT_D:
-		name = "DPDDC-D";
-		break;
-	case PORT_E:
-		name = "DPDDC-E";
-		break;
-	default:
-		BUG();
-	}
+	static const char * const ddc_name[] = {
+		[PORT_A] = "DPDDC-A",
+		[PORT_B] = "DPDDC-B",
+		[PORT_C] = "DPDDC-C",
+		[PORT_D] = "DPDDC-D",
+		[PORT_E] = "DPDDC-E",
+	};
 
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
@@ -1125,17 +1111,18 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 	else
 		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
 
-	intel_dp->aux.name = name;
+	intel_dp->aux.name = ddc_name[port];
 	intel_dp->aux.dev = dev->dev;
 	intel_dp->aux.transfer = intel_dp_aux_transfer;
 
-	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
+	DRM_DEBUG_KMS("registering %s bus for %s\n",
+		      intel_dp->aux.name,
 		      connector->base.kdev->kobj.name);
 
 	ret = drm_dp_aux_register(&intel_dp->aux);
 	if (ret < 0) {
 		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
-			  name, ret);
+			  intel_dp->aux.name, ret);
 		return;
 	}
 
@@ -1143,7 +1130,8 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 				&intel_dp->aux.ddc.dev.kobj,
 				intel_dp->aux.ddc.dev.kobj.name);
 	if (ret < 0) {
-		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
+		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
+			  intel_dp->aux.name, ret);
 		drm_dp_aux_unregister(&intel_dp->aux);
 	}
 }
-- 
2.4.6

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[PATCH 38/43] drm/i915: Parametrize AUX registes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_dp.c  |  45 +++--------------
 drivers/gpu/drm/i915/intel_psr.c |   5 +-
 3 files changed, 62 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e97bf2..04b2063 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3062,11 +3062,7 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
 #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
-#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
-#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
-#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
-#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
+#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
 
 #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
@@ -4182,33 +4178,36 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
-#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
-#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
-#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
-#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
-#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
-
-#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
-#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
-#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
-#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
-#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
-#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
-
-#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
-#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
-#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
-#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
-#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
-#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
-
-#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
-#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
-#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
-#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
-#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
-#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
+
+#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
+#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
@@ -6543,28 +6542,31 @@ enum skl_disp_power_wells {
 #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B		0xe4100
-#define PCH_DPB_AUX_CH_CTL	0xe4110
-#define PCH_DPB_AUX_CH_DATA1	0xe4114
-#define PCH_DPB_AUX_CH_DATA2	0xe4118
-#define PCH_DPB_AUX_CH_DATA3	0xe411c
-#define PCH_DPB_AUX_CH_DATA4	0xe4120
-#define PCH_DPB_AUX_CH_DATA5	0xe4124
+#define _PCH_DPB_AUX_CH_CTL	0xe4110
+#define _PCH_DPB_AUX_CH_DATA1	0xe4114
+#define _PCH_DPB_AUX_CH_DATA2	0xe4118
+#define _PCH_DPB_AUX_CH_DATA3	0xe411c
+#define _PCH_DPB_AUX_CH_DATA4	0xe4120
+#define _PCH_DPB_AUX_CH_DATA5	0xe4124
 
 #define PCH_DP_C		0xe4200
-#define PCH_DPC_AUX_CH_CTL	0xe4210
-#define PCH_DPC_AUX_CH_DATA1	0xe4214
-#define PCH_DPC_AUX_CH_DATA2	0xe4218
-#define PCH_DPC_AUX_CH_DATA3	0xe421c
-#define PCH_DPC_AUX_CH_DATA4	0xe4220
-#define PCH_DPC_AUX_CH_DATA5	0xe4224
+#define _PCH_DPC_AUX_CH_CTL	0xe4210
+#define _PCH_DPC_AUX_CH_DATA1	0xe4214
+#define _PCH_DPC_AUX_CH_DATA2	0xe4218
+#define _PCH_DPC_AUX_CH_DATA3	0xe421c
+#define _PCH_DPC_AUX_CH_DATA4	0xe4220
+#define _PCH_DPC_AUX_CH_DATA5	0xe4224
 
 #define PCH_DP_D		0xe4300
-#define PCH_DPD_AUX_CH_CTL	0xe4310
-#define PCH_DPD_AUX_CH_DATA1	0xe4314
-#define PCH_DPD_AUX_CH_DATA2	0xe4318
-#define PCH_DPD_AUX_CH_DATA3	0xe431c
-#define PCH_DPD_AUX_CH_DATA4	0xe4320
-#define PCH_DPD_AUX_CH_DATA5	0xe4324
+#define _PCH_DPD_AUX_CH_CTL	0xe4310
+#define _PCH_DPD_AUX_CH_DATA1	0xe4314
+#define _PCH_DPD_AUX_CH_DATA2	0xe4318
+#define _PCH_DPD_AUX_CH_DATA3	0xe431c
+#define _PCH_DPD_AUX_CH_DATA4	0xe4320
+#define _PCH_DPD_AUX_CH_DATA5	0xe4324
+
+#define PCH_DP_AUX_CH_CTL(port)		_PORT((port)-1, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
+#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port)-1, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT	0
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fa4e8b1..27df240 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 	else
 		precharge = 5;
 
-	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
+	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
 		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 	else
 		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -1012,35 +1012,16 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				enum port port)
 {
-	switch (port) {
-	case PORT_B:
-		return DPB_AUX_CH_CTL;
-	case PORT_C:
-		return DPC_AUX_CH_CTL;
-	case PORT_D:
-		return DPD_AUX_CH_CTL;
-	default:
-		MISSING_CASE(port);
-		return DPB_AUX_CH_CTL;
-	}
+	return DP_AUX_CH_CTL(port);
 }
 
 static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				enum port port)
 {
-	switch (port) {
-	case PORT_A:
-		return DPA_AUX_CH_CTL;
-	case PORT_B:
-		return PCH_DPB_AUX_CH_CTL;
-	case PORT_C:
-		return PCH_DPC_AUX_CH_CTL;
-	case PORT_D:
-		return PCH_DPD_AUX_CH_CTL;
-	default:
-		MISSING_CASE(port);
-		return DPA_AUX_CH_CTL;
-	}
+	if (port == PORT_A)
+		return DP_AUX_CH_CTL(port);
+	else
+		return PCH_DP_AUX_CH_CTL(port);
 }
 
 /*
@@ -1073,19 +1054,7 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	if (port == PORT_E)
 		port = skl_porte_aux_port(dev_priv);
 
-	switch (port) {
-	case PORT_A:
-		return DPA_AUX_CH_CTL;
-	case PORT_B:
-		return DPB_AUX_CH_CTL;
-	case PORT_C:
-		return DPC_AUX_CH_CTL;
-	case PORT_D:
-		return DPD_AUX_CH_CTL;
-	default:
-		MISSING_CASE(port);
-		return DPA_AUX_CH_CTL;
-	}
+	return DP_AUX_CH_CTL(port);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 213581c..ff66718 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		[3] = 1 - 1,
 		[4] = DP_SET_POWER_D0,
 	};
+	enum port port = dig_port->port;
 	int i;
 
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_AUX_FRAME_SYNC_ENABLE);
 
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
+		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
+		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-- 
2.4.6

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Re: [PATCH 38/43] drm/i915: Parametrize AUX registes

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
>  drivers/gpu/drm/i915/intel_dp.c  |  45 +++--------------
>  drivers/gpu/drm/i915/intel_psr.c |   5 +-
>  3 files changed, 62 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4e97bf2..04b2063 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3062,11 +3062,7 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
>  #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
> -#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
> -#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
> -#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
> -#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
> +#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
>  
>  #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
> @@ -4182,33 +4178,36 @@ enum skl_disp_power_wells {
>   * is 20 bytes in each direction, hence the 5 fixed
>   * data registers
>   */
> -#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> -#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> -#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> -#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> -#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> -#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> -
> -#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> -#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> -#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> -#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> -#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> -#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> -
> -#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> -#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> -#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> -#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> -#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> -#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> -
> -#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> -#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> -#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> -#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> -#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> -#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> +#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> +#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> +#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> +#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> +#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> +#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> +
> +#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> +#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> +#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> +#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> +#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> +#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> +
> +#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> +#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> +#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> +#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> +#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> +#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> +
> +#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> +#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> +#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> +#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> +#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> +#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> +
> +#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> +#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
>  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
> @@ -6543,28 +6542,31 @@ enum skl_disp_power_wells {
>  #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
>  
>  #define PCH_DP_B		0xe4100
> -#define PCH_DPB_AUX_CH_CTL	0xe4110
> -#define PCH_DPB_AUX_CH_DATA1	0xe4114
> -#define PCH_DPB_AUX_CH_DATA2	0xe4118
> -#define PCH_DPB_AUX_CH_DATA3	0xe411c
> -#define PCH_DPB_AUX_CH_DATA4	0xe4120
> -#define PCH_DPB_AUX_CH_DATA5	0xe4124
> +#define _PCH_DPB_AUX_CH_CTL	0xe4110
> +#define _PCH_DPB_AUX_CH_DATA1	0xe4114
> +#define _PCH_DPB_AUX_CH_DATA2	0xe4118
> +#define _PCH_DPB_AUX_CH_DATA3	0xe411c
> +#define _PCH_DPB_AUX_CH_DATA4	0xe4120
> +#define _PCH_DPB_AUX_CH_DATA5	0xe4124
>  
>  #define PCH_DP_C		0xe4200
> -#define PCH_DPC_AUX_CH_CTL	0xe4210
> -#define PCH_DPC_AUX_CH_DATA1	0xe4214
> -#define PCH_DPC_AUX_CH_DATA2	0xe4218
> -#define PCH_DPC_AUX_CH_DATA3	0xe421c
> -#define PCH_DPC_AUX_CH_DATA4	0xe4220
> -#define PCH_DPC_AUX_CH_DATA5	0xe4224
> +#define _PCH_DPC_AUX_CH_CTL	0xe4210
> +#define _PCH_DPC_AUX_CH_DATA1	0xe4214
> +#define _PCH_DPC_AUX_CH_DATA2	0xe4218
> +#define _PCH_DPC_AUX_CH_DATA3	0xe421c
> +#define _PCH_DPC_AUX_CH_DATA4	0xe4220
> +#define _PCH_DPC_AUX_CH_DATA5	0xe4224
>  
>  #define PCH_DP_D		0xe4300
> -#define PCH_DPD_AUX_CH_CTL	0xe4310
> -#define PCH_DPD_AUX_CH_DATA1	0xe4314
> -#define PCH_DPD_AUX_CH_DATA2	0xe4318
> -#define PCH_DPD_AUX_CH_DATA3	0xe431c
> -#define PCH_DPD_AUX_CH_DATA4	0xe4320
> -#define PCH_DPD_AUX_CH_DATA5	0xe4324
> +#define _PCH_DPD_AUX_CH_CTL	0xe4310
> +#define _PCH_DPD_AUX_CH_DATA1	0xe4314
> +#define _PCH_DPD_AUX_CH_DATA2	0xe4318
> +#define _PCH_DPD_AUX_CH_DATA3	0xe431c
> +#define _PCH_DPD_AUX_CH_DATA4	0xe4320
> +#define _PCH_DPD_AUX_CH_DATA5	0xe4324
> +
> +#define PCH_DP_AUX_CH_CTL(port)		_PORT((port)-1, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> +#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port)-1, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  /* CPT */
>  #define  PORT_TRANS_A_SEL_CPT	0
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fa4e8b1..27df240 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
>  	else
>  		precharge = 5;
>  
> -	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
> +	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
>  	else
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -1012,35 +1012,16 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
>  static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				enum port port)
>  {
> -	switch (port) {
> -	case PORT_B:
> -		return DPB_AUX_CH_CTL;
> -	case PORT_C:
> -		return DPC_AUX_CH_CTL;
> -	case PORT_D:
> -		return DPD_AUX_CH_CTL;
> -	default:
> -		MISSING_CASE(port);
> -		return DPB_AUX_CH_CTL;
> -	}
> +	return DP_AUX_CH_CTL(port);

Together with the previous patch you now lose all MISSING_CASE/BUG/WARN
for having an out-of-bounds/unsupported port. I kinda liked them.

BR,
Jani.

>  }
>  
>  static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				enum port port)
>  {
> -	switch (port) {
> -	case PORT_A:
> -		return DPA_AUX_CH_CTL;
> -	case PORT_B:
> -		return PCH_DPB_AUX_CH_CTL;
> -	case PORT_C:
> -		return PCH_DPC_AUX_CH_CTL;
> -	case PORT_D:
> -		return PCH_DPD_AUX_CH_CTL;
> -	default:
> -		MISSING_CASE(port);
> -		return DPA_AUX_CH_CTL;
> -	}
> +	if (port == PORT_A)
> +		return DP_AUX_CH_CTL(port);
> +	else
> +		return PCH_DP_AUX_CH_CTL(port);
>  }
>  
>  /*
> @@ -1073,19 +1054,7 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  	if (port == PORT_E)
>  		port = skl_porte_aux_port(dev_priv);
>  
> -	switch (port) {
> -	case PORT_A:
> -		return DPA_AUX_CH_CTL;
> -	case PORT_B:
> -		return DPB_AUX_CH_CTL;
> -	case PORT_C:
> -		return DPC_AUX_CH_CTL;
> -	case PORT_D:
> -		return DPD_AUX_CH_CTL;
> -	default:
> -		MISSING_CASE(port);
> -		return DPA_AUX_CH_CTL;
> -	}
> +	return DP_AUX_CH_CTL(port);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 213581c..ff66718 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  		[3] = 1 - 1,
>  		[4] = DP_SET_POWER_D0,
>  	};
> +	enum port port = dig_port->port;
>  	int i;
>  
>  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
> @@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  				DP_AUX_FRAME_SYNC_ENABLE);
>  
>  	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
> +		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
>  	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
> +		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
>  
>  	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 38/43] drm/i915: Parametrize AUX registes

[Daniel Vetter]

On Mon, Sep 28, 2015 at 03:15:18PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > @@ -1012,35 +1012,16 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
> >  static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> >  				enum port port)
> >  {
> > -	switch (port) {
> > -	case PORT_B:
> > -		return DPB_AUX_CH_CTL;
> > -	case PORT_C:
> > -		return DPC_AUX_CH_CTL;
> > -	case PORT_D:
> > -		return DPD_AUX_CH_CTL;
> > -	default:
> > -		MISSING_CASE(port);
> > -		return DPB_AUX_CH_CTL;
> > -	}
> > +	return DP_AUX_CH_CTL(port);
> 
> Together with the previous patch you now lose all MISSING_CASE/BUG/WARN
> for having an out-of-bounds/unsupported port. I kinda liked them.

MISSING_REG() to satisfy the typechecks would be good I think. Or
MISSING_CASE_REG().
-Danie
-- 
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http://blog.ffwll.ch
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Re: [PATCH 38/43] drm/i915: Parametrize AUX registes

[Ville Syrjälä]

On Mon, Sep 28, 2015 at 03:28:39PM +0200, Daniel Vetter wrote:
> On Mon, Sep 28, 2015 at 03:15:18PM +0300, Jani Nikula wrote:
> > On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > > @@ -1012,35 +1012,16 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
> > >  static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > >  				enum port port)
> > >  {
> > > -	switch (port) {
> > > -	case PORT_B:
> > > -		return DPB_AUX_CH_CTL;
> > > -	case PORT_C:
> > > -		return DPC_AUX_CH_CTL;
> > > -	case PORT_D:
> > > -		return DPD_AUX_CH_CTL;
> > > -	default:
> > > -		MISSING_CASE(port);
> > > -		return DPB_AUX_CH_CTL;
> > > -	}
> > > +	return DP_AUX_CH_CTL(port);
> > 
> > Together with the previous patch you now lose all MISSING_CASE/BUG/WARN
> > for having an out-of-bounds/unsupported port. I kinda liked them.
> 
> MISSING_REG() to satisfy the typechecks would be good I think. Or
> MISSING_CASE_REG().

I've never caught anything with such checks, but if people want then I
could keep them around. I suppose the fact that we don't have AUX for
port E+ means they could actually be useful here, at least on SKL. For
the other platforms they're pointless IMO, but I can include them there
if people so wish. I didn't actually check if port E on SKL was the only
exception, or if we continue with similar limitations in the future.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 38/43] drm/i915: Parametrize AUX registes

[Daniel Vetter]

On Mon, Sep 28, 2015 at 04:34:10PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 28, 2015 at 03:28:39PM +0200, Daniel Vetter wrote:
> > On Mon, Sep 28, 2015 at 03:15:18PM +0300, Jani Nikula wrote:
> > > On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > > > @@ -1012,35 +1012,16 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
> > > >  static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > > >  				enum port port)
> > > >  {
> > > > -	switch (port) {
> > > > -	case PORT_B:
> > > > -		return DPB_AUX_CH_CTL;
> > > > -	case PORT_C:
> > > > -		return DPC_AUX_CH_CTL;
> > > > -	case PORT_D:
> > > > -		return DPD_AUX_CH_CTL;
> > > > -	default:
> > > > -		MISSING_CASE(port);
> > > > -		return DPB_AUX_CH_CTL;
> > > > -	}
> > > > +	return DP_AUX_CH_CTL(port);
> > > 
> > > Together with the previous patch you now lose all MISSING_CASE/BUG/WARN
> > > for having an out-of-bounds/unsupported port. I kinda liked them.
> > 
> > MISSING_REG() to satisfy the typechecks would be good I think. Or
> > MISSING_CASE_REG().
> 
> I've never caught anything with such checks, but if people want then I
> could keep them around. I suppose the fact that we don't have AUX for
> port E+ means they could actually be useful here, at least on SKL. For
> the other platforms they're pointless IMO, but I can include them there
> if people so wish. I didn't actually check if port E on SKL was the only
> exception, or if we continue with similar limitations in the future.

It's not so much that it catches bugs, but it does prevent people from
using BUG() instead. And I don't take patches with BUG() any more because
too much time wasted with machines dying under console_lock because of
that ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 38/43] drm/i915: Parametrize AUX registes

[Jani Nikula]

On Mon, 28 Sep 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Sep 28, 2015 at 04:34:10PM +0300, Ville Syrjälä wrote:
>> On Mon, Sep 28, 2015 at 03:28:39PM +0200, Daniel Vetter wrote:
>> > On Mon, Sep 28, 2015 at 03:15:18PM +0300, Jani Nikula wrote:
>> > > On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
>> > > > @@ -1012,35 +1012,16 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
>> > > >  static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
>> > > >  				enum port port)
>> > > >  {
>> > > > -	switch (port) {
>> > > > -	case PORT_B:
>> > > > -		return DPB_AUX_CH_CTL;
>> > > > -	case PORT_C:
>> > > > -		return DPC_AUX_CH_CTL;
>> > > > -	case PORT_D:
>> > > > -		return DPD_AUX_CH_CTL;
>> > > > -	default:
>> > > > -		MISSING_CASE(port);
>> > > > -		return DPB_AUX_CH_CTL;
>> > > > -	}
>> > > > +	return DP_AUX_CH_CTL(port);
>> > > 
>> > > Together with the previous patch you now lose all MISSING_CASE/BUG/WARN
>> > > for having an out-of-bounds/unsupported port. I kinda liked them.
>> > 
>> > MISSING_REG() to satisfy the typechecks would be good I think. Or
>> > MISSING_CASE_REG().
>> 
>> I've never caught anything with such checks, but if people want then I
>> could keep them around. I suppose the fact that we don't have AUX for
>> port E+ means they could actually be useful here, at least on SKL. For
>> the other platforms they're pointless IMO, but I can include them there
>> if people so wish. I didn't actually check if port E on SKL was the only
>> exception, or if we continue with similar limitations in the future.
>
> It's not so much that it catches bugs, but it does prevent people from
> using BUG() instead. And I don't take patches with BUG() any more because
> too much time wasted with machines dying under console_lock because of
> that ;-)

We don't catch such bugs in the wild precisely because they've been
caught during enabling. Without the checks, some might slip through, and
we end up debugging.

BR,
Jani.


> -Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH v2 38/43] drm/i915: Parametrize AUX registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Keep some MISSING_CASE() stuff (Jani)
    s/-1/-PIPE_B/ in the register macro
    Fix typo in patch subject

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_dp.c  |  23 +++------
 drivers/gpu/drm/i915/intel_psr.c |   5 +-
 3 files changed, 63 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2c518a0..7723ed3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3068,11 +3068,7 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
 #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
-#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
-#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
-#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
-#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
+#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
 
 #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
@@ -4188,33 +4184,36 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
-#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
-#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
-#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
-#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
-#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
-
-#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
-#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
-#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
-#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
-#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
-#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
-
-#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
-#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
-#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
-#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
-#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
-#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
-
-#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
-#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
-#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
-#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
-#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
-#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
+
+#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
+#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
@@ -6549,28 +6548,31 @@ enum skl_disp_power_wells {
 #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B		0xe4100
-#define PCH_DPB_AUX_CH_CTL	0xe4110
-#define PCH_DPB_AUX_CH_DATA1	0xe4114
-#define PCH_DPB_AUX_CH_DATA2	0xe4118
-#define PCH_DPB_AUX_CH_DATA3	0xe411c
-#define PCH_DPB_AUX_CH_DATA4	0xe4120
-#define PCH_DPB_AUX_CH_DATA5	0xe4124
+#define _PCH_DPB_AUX_CH_CTL	0xe4110
+#define _PCH_DPB_AUX_CH_DATA1	0xe4114
+#define _PCH_DPB_AUX_CH_DATA2	0xe4118
+#define _PCH_DPB_AUX_CH_DATA3	0xe411c
+#define _PCH_DPB_AUX_CH_DATA4	0xe4120
+#define _PCH_DPB_AUX_CH_DATA5	0xe4124
 
 #define PCH_DP_C		0xe4200
-#define PCH_DPC_AUX_CH_CTL	0xe4210
-#define PCH_DPC_AUX_CH_DATA1	0xe4214
-#define PCH_DPC_AUX_CH_DATA2	0xe4218
-#define PCH_DPC_AUX_CH_DATA3	0xe421c
-#define PCH_DPC_AUX_CH_DATA4	0xe4220
-#define PCH_DPC_AUX_CH_DATA5	0xe4224
+#define _PCH_DPC_AUX_CH_CTL	0xe4210
+#define _PCH_DPC_AUX_CH_DATA1	0xe4214
+#define _PCH_DPC_AUX_CH_DATA2	0xe4218
+#define _PCH_DPC_AUX_CH_DATA3	0xe421c
+#define _PCH_DPC_AUX_CH_DATA4	0xe4220
+#define _PCH_DPC_AUX_CH_DATA5	0xe4224
 
 #define PCH_DP_D		0xe4300
-#define PCH_DPD_AUX_CH_CTL	0xe4310
-#define PCH_DPD_AUX_CH_DATA1	0xe4314
-#define PCH_DPD_AUX_CH_DATA2	0xe4318
-#define PCH_DPD_AUX_CH_DATA3	0xe431c
-#define PCH_DPD_AUX_CH_DATA4	0xe4320
-#define PCH_DPD_AUX_CH_DATA5	0xe4324
+#define _PCH_DPD_AUX_CH_CTL	0xe4310
+#define _PCH_DPD_AUX_CH_DATA1	0xe4314
+#define _PCH_DPD_AUX_CH_DATA2	0xe4318
+#define _PCH_DPD_AUX_CH_DATA3	0xe431c
+#define _PCH_DPD_AUX_CH_DATA4	0xe4320
+#define _PCH_DPD_AUX_CH_DATA5	0xe4324
+
+#define PCH_DP_AUX_CH_CTL(port)		_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
+#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT	0
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1180289..d252feb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 	else
 		precharge = 5;
 
-	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
+	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
 		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 	else
 		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -1014,14 +1014,12 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
 {
 	switch (port) {
 	case PORT_B:
-		return DPB_AUX_CH_CTL;
 	case PORT_C:
-		return DPC_AUX_CH_CTL;
 	case PORT_D:
-		return DPD_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(port);
 	default:
 		MISSING_CASE(port);
-		return DPB_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(PORT_A);
 	}
 }
 
@@ -1030,16 +1028,14 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 {
 	switch (port) {
 	case PORT_A:
-		return DPA_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(port);
 	case PORT_B:
-		return PCH_DPB_AUX_CH_CTL;
 	case PORT_C:
-		return PCH_DPC_AUX_CH_CTL;
 	case PORT_D:
-		return PCH_DPD_AUX_CH_CTL;
+		return PCH_DP_AUX_CH_CTL(port);
 	default:
 		MISSING_CASE(port);
-		return DPA_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(PORT_A);
 	}
 }
 
@@ -1075,16 +1071,13 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_A:
-		return DPA_AUX_CH_CTL;
 	case PORT_B:
-		return DPB_AUX_CH_CTL;
 	case PORT_C:
-		return DPC_AUX_CH_CTL;
 	case PORT_D:
-		return DPD_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(port);
 	default:
 		MISSING_CASE(port);
-		return DPA_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(PORT_A);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 213581c..ff66718 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		[3] = 1 - 1,
 		[4] = DP_SET_POWER_D0,
 	};
+	enum port port = dig_port->port;
 	int i;
 
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_AUX_FRAME_SYNC_ENABLE);
 
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
+		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
+		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-- 
2.4.6

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Re: [PATCH v2 38/43] drm/i915: Parametrize AUX registers

[Jani Nikula]

On Mon, 28 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> v2: Keep some MISSING_CASE() stuff (Jani)
>     s/-1/-PIPE_B/ in the register macro
>     Fix typo in patch subject
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
>  drivers/gpu/drm/i915/intel_dp.c  |  23 +++------
>  drivers/gpu/drm/i915/intel_psr.c |   5 +-
>  3 files changed, 63 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2c518a0..7723ed3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3068,11 +3068,7 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
>  #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
> -#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
> -#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
> -#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
> -#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
> +#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
>  
>  #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
> @@ -4188,33 +4184,36 @@ enum skl_disp_power_wells {
>   * is 20 bytes in each direction, hence the 5 fixed
>   * data registers
>   */
> -#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> -#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> -#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> -#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> -#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> -#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> -
> -#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> -#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> -#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> -#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> -#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> -#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> -
> -#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> -#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> -#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> -#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> -#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> -#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> -
> -#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> -#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> -#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> -#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> -#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> -#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> +#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> +#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> +#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> +#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> +#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> +#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> +
> +#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> +#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> +#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> +#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> +#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> +#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> +
> +#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> +#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> +#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> +#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> +#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> +#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> +
> +#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> +#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> +#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> +#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> +#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> +#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> +
> +#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> +#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
>  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
> @@ -6549,28 +6548,31 @@ enum skl_disp_power_wells {
>  #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
>  
>  #define PCH_DP_B		0xe4100
> -#define PCH_DPB_AUX_CH_CTL	0xe4110
> -#define PCH_DPB_AUX_CH_DATA1	0xe4114
> -#define PCH_DPB_AUX_CH_DATA2	0xe4118
> -#define PCH_DPB_AUX_CH_DATA3	0xe411c
> -#define PCH_DPB_AUX_CH_DATA4	0xe4120
> -#define PCH_DPB_AUX_CH_DATA5	0xe4124
> +#define _PCH_DPB_AUX_CH_CTL	0xe4110
> +#define _PCH_DPB_AUX_CH_DATA1	0xe4114
> +#define _PCH_DPB_AUX_CH_DATA2	0xe4118
> +#define _PCH_DPB_AUX_CH_DATA3	0xe411c
> +#define _PCH_DPB_AUX_CH_DATA4	0xe4120
> +#define _PCH_DPB_AUX_CH_DATA5	0xe4124
>  
>  #define PCH_DP_C		0xe4200
> -#define PCH_DPC_AUX_CH_CTL	0xe4210
> -#define PCH_DPC_AUX_CH_DATA1	0xe4214
> -#define PCH_DPC_AUX_CH_DATA2	0xe4218
> -#define PCH_DPC_AUX_CH_DATA3	0xe421c
> -#define PCH_DPC_AUX_CH_DATA4	0xe4220
> -#define PCH_DPC_AUX_CH_DATA5	0xe4224
> +#define _PCH_DPC_AUX_CH_CTL	0xe4210
> +#define _PCH_DPC_AUX_CH_DATA1	0xe4214
> +#define _PCH_DPC_AUX_CH_DATA2	0xe4218
> +#define _PCH_DPC_AUX_CH_DATA3	0xe421c
> +#define _PCH_DPC_AUX_CH_DATA4	0xe4220
> +#define _PCH_DPC_AUX_CH_DATA5	0xe4224
>  
>  #define PCH_DP_D		0xe4300
> -#define PCH_DPD_AUX_CH_CTL	0xe4310
> -#define PCH_DPD_AUX_CH_DATA1	0xe4314
> -#define PCH_DPD_AUX_CH_DATA2	0xe4318
> -#define PCH_DPD_AUX_CH_DATA3	0xe431c
> -#define PCH_DPD_AUX_CH_DATA4	0xe4320
> -#define PCH_DPD_AUX_CH_DATA5	0xe4324
> +#define _PCH_DPD_AUX_CH_CTL	0xe4310
> +#define _PCH_DPD_AUX_CH_DATA1	0xe4314
> +#define _PCH_DPD_AUX_CH_DATA2	0xe4318
> +#define _PCH_DPD_AUX_CH_DATA3	0xe431c
> +#define _PCH_DPD_AUX_CH_DATA4	0xe4320
> +#define _PCH_DPD_AUX_CH_DATA5	0xe4324
> +
> +#define PCH_DP_AUX_CH_CTL(port)		_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> +#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  /* CPT */
>  #define  PORT_TRANS_A_SEL_CPT	0
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1180289..d252feb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
>  	else
>  		precharge = 5;
>  
> -	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
> +	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
>  	else
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -1014,14 +1014,12 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  {
>  	switch (port) {
>  	case PORT_B:
> -		return DPB_AUX_CH_CTL;
>  	case PORT_C:
> -		return DPC_AUX_CH_CTL;
>  	case PORT_D:
> -		return DPD_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(port);
>  	default:
>  		MISSING_CASE(port);
> -		return DPB_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(PORT_A);

Changes default from port B to A.

Otherwise,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  	}
>  }
>  
> @@ -1030,16 +1028,14 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  {
>  	switch (port) {
>  	case PORT_A:
> -		return DPA_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(port);
>  	case PORT_B:
> -		return PCH_DPB_AUX_CH_CTL;
>  	case PORT_C:
> -		return PCH_DPC_AUX_CH_CTL;
>  	case PORT_D:
> -		return PCH_DPD_AUX_CH_CTL;
> +		return PCH_DP_AUX_CH_CTL(port);
>  	default:
>  		MISSING_CASE(port);
> -		return DPA_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(PORT_A);
>  	}
>  }
>  
> @@ -1075,16 +1071,13 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  
>  	switch (port) {
>  	case PORT_A:
> -		return DPA_AUX_CH_CTL;
>  	case PORT_B:
> -		return DPB_AUX_CH_CTL;
>  	case PORT_C:
> -		return DPC_AUX_CH_CTL;
>  	case PORT_D:
> -		return DPD_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(port);
>  	default:
>  		MISSING_CASE(port);
> -		return DPA_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(PORT_A);
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 213581c..ff66718 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  		[3] = 1 - 1,
>  		[4] = DP_SET_POWER_D0,
>  	};
> +	enum port port = dig_port->port;
>  	int i;
>  
>  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
> @@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  				DP_AUX_FRAME_SYNC_ENABLE);
>  
>  	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
> +		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
>  	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
> +		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
>  
>  	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
> -- 
> 2.4.6
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 38/43] drm/i915: Parametrize AUX registers

[Ville Syrjälä]

On Tue, Oct 20, 2015 at 04:05:24PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > v2: Keep some MISSING_CASE() stuff (Jani)
> >     s/-1/-PIPE_B/ in the register macro
> >     Fix typo in patch subject
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
> >  drivers/gpu/drm/i915/intel_dp.c  |  23 +++------
> >  drivers/gpu/drm/i915/intel_psr.c |   5 +-
> >  3 files changed, 63 insertions(+), 67 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 2c518a0..7723ed3 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3068,11 +3068,7 @@ enum skl_disp_power_wells {
> >  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
> >  
> >  #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
> > -#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
> > -#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
> > -#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
> > -#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
> > -#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
> > +#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
> >  
> >  #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
> >  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
> > @@ -4188,33 +4184,36 @@ enum skl_disp_power_wells {
> >   * is 20 bytes in each direction, hence the 5 fixed
> >   * data registers
> >   */
> > -#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> > -#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> > -#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> > -#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> > -#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> > -#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> > -
> > -#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> > -#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> > -#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> > -#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> > -#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> > -#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> > -
> > -#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> > -#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> > -#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> > -#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> > -#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> > -#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> > -
> > -#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> > -#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> > -#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> > -#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> > -#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> > -#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> > +#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> > +#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> > +#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> > +#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> > +#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> > +#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> > +
> > +#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> > +#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> > +#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> > +#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> > +#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> > +#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> > +
> > +#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> > +#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> > +#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> > +#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> > +#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> > +#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> > +
> > +#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> > +#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> > +#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> > +#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> > +#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> > +#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> > +
> > +#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> > +#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >  
> >  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
> >  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
> > @@ -6549,28 +6548,31 @@ enum skl_disp_power_wells {
> >  #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
> >  
> >  #define PCH_DP_B		0xe4100
> > -#define PCH_DPB_AUX_CH_CTL	0xe4110
> > -#define PCH_DPB_AUX_CH_DATA1	0xe4114
> > -#define PCH_DPB_AUX_CH_DATA2	0xe4118
> > -#define PCH_DPB_AUX_CH_DATA3	0xe411c
> > -#define PCH_DPB_AUX_CH_DATA4	0xe4120
> > -#define PCH_DPB_AUX_CH_DATA5	0xe4124
> > +#define _PCH_DPB_AUX_CH_CTL	0xe4110
> > +#define _PCH_DPB_AUX_CH_DATA1	0xe4114
> > +#define _PCH_DPB_AUX_CH_DATA2	0xe4118
> > +#define _PCH_DPB_AUX_CH_DATA3	0xe411c
> > +#define _PCH_DPB_AUX_CH_DATA4	0xe4120
> > +#define _PCH_DPB_AUX_CH_DATA5	0xe4124
> >  
> >  #define PCH_DP_C		0xe4200
> > -#define PCH_DPC_AUX_CH_CTL	0xe4210
> > -#define PCH_DPC_AUX_CH_DATA1	0xe4214
> > -#define PCH_DPC_AUX_CH_DATA2	0xe4218
> > -#define PCH_DPC_AUX_CH_DATA3	0xe421c
> > -#define PCH_DPC_AUX_CH_DATA4	0xe4220
> > -#define PCH_DPC_AUX_CH_DATA5	0xe4224
> > +#define _PCH_DPC_AUX_CH_CTL	0xe4210
> > +#define _PCH_DPC_AUX_CH_DATA1	0xe4214
> > +#define _PCH_DPC_AUX_CH_DATA2	0xe4218
> > +#define _PCH_DPC_AUX_CH_DATA3	0xe421c
> > +#define _PCH_DPC_AUX_CH_DATA4	0xe4220
> > +#define _PCH_DPC_AUX_CH_DATA5	0xe4224
> >  
> >  #define PCH_DP_D		0xe4300
> > -#define PCH_DPD_AUX_CH_CTL	0xe4310
> > -#define PCH_DPD_AUX_CH_DATA1	0xe4314
> > -#define PCH_DPD_AUX_CH_DATA2	0xe4318
> > -#define PCH_DPD_AUX_CH_DATA3	0xe431c
> > -#define PCH_DPD_AUX_CH_DATA4	0xe4320
> > -#define PCH_DPD_AUX_CH_DATA5	0xe4324
> > +#define _PCH_DPD_AUX_CH_CTL	0xe4310
> > +#define _PCH_DPD_AUX_CH_DATA1	0xe4314
> > +#define _PCH_DPD_AUX_CH_DATA2	0xe4318
> > +#define _PCH_DPD_AUX_CH_DATA3	0xe431c
> > +#define _PCH_DPD_AUX_CH_DATA4	0xe4320
> > +#define _PCH_DPD_AUX_CH_DATA5	0xe4324
> > +
> > +#define PCH_DP_AUX_CH_CTL(port)		_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> > +#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >  
> >  /* CPT */
> >  #define  PORT_TRANS_A_SEL_CPT	0
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 1180289..d252feb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
> >  	else
> >  		precharge = 5;
> >  
> > -	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
> > +	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
> >  		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> >  	else
> >  		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> > @@ -1014,14 +1014,12 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> >  {
> >  	switch (port) {
> >  	case PORT_B:
> > -		return DPB_AUX_CH_CTL;
> >  	case PORT_C:
> > -		return DPC_AUX_CH_CTL;
> >  	case PORT_D:
> > -		return DPD_AUX_CH_CTL;
> > +		return DP_AUX_CH_CTL(port);
> >  	default:
> >  		MISSING_CASE(port);
> > -		return DPB_AUX_CH_CTL;
> > +		return DP_AUX_CH_CTL(PORT_A);
> 
> Changes default from port B to A.

Whoops. No port A on these platforms, so I'll go fix it up.

> 
> Otherwise,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> >  	}
> >  }
> >  
> > @@ -1030,16 +1028,14 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
> >  {
> >  	switch (port) {
> >  	case PORT_A:
> > -		return DPA_AUX_CH_CTL;
> > +		return DP_AUX_CH_CTL(port);
> >  	case PORT_B:
> > -		return PCH_DPB_AUX_CH_CTL;
> >  	case PORT_C:
> > -		return PCH_DPC_AUX_CH_CTL;
> >  	case PORT_D:
> > -		return PCH_DPD_AUX_CH_CTL;
> > +		return PCH_DP_AUX_CH_CTL(port);
> >  	default:
> >  		MISSING_CASE(port);
> > -		return DPA_AUX_CH_CTL;
> > +		return DP_AUX_CH_CTL(PORT_A);
> >  	}
> >  }
> >  
> > @@ -1075,16 +1071,13 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
> >  
> >  	switch (port) {
> >  	case PORT_A:
> > -		return DPA_AUX_CH_CTL;
> >  	case PORT_B:
> > -		return DPB_AUX_CH_CTL;
> >  	case PORT_C:
> > -		return DPC_AUX_CH_CTL;
> >  	case PORT_D:
> > -		return DPD_AUX_CH_CTL;
> > +		return DP_AUX_CH_CTL(port);
> >  	default:
> >  		MISSING_CASE(port);
> > -		return DPA_AUX_CH_CTL;
> > +		return DP_AUX_CH_CTL(PORT_A);
> >  	}
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 213581c..ff66718 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> >  		[3] = 1 - 1,
> >  		[4] = DP_SET_POWER_D0,
> >  	};
> > +	enum port port = dig_port->port;
> >  	int i;
> >  
> >  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
> > @@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> >  				DP_AUX_FRAME_SYNC_ENABLE);
> >  
> >  	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> > -				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
> > +		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
> >  	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> > -				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
> > +		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
> >  
> >  	/* Setup AUX registers */
> >  	for (i = 0; i < sizeof(aux_msg); i += 4)
> > -- 
> > 2.4.6
> >
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
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[PATCH v3 38/43] drm/i915: Parametrize AUX registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Keep some MISSING_CASE() stuff (Jani)
    s/-1/-PIPE_B/ in the register macro
    Fix typo in patch subject
v3: Use PORT_B registers for invalid ports in g4x_aux_ctl_reg() (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_dp.c  |  23 +++------
 drivers/gpu/drm/i915/intel_psr.c |   5 +-
 3 files changed, 63 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2c518a0..7723ed3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3068,11 +3068,7 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
 #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
-#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
-#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
-#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
-#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
+#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
 
 #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
@@ -4188,33 +4184,36 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
-#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
-#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
-#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
-#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
-#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
-
-#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
-#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
-#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
-#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
-#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
-#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
-
-#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
-#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
-#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
-#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
-#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
-#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
-
-#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
-#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
-#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
-#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
-#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
-#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
+
+#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
+#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
@@ -6549,28 +6548,31 @@ enum skl_disp_power_wells {
 #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B		0xe4100
-#define PCH_DPB_AUX_CH_CTL	0xe4110
-#define PCH_DPB_AUX_CH_DATA1	0xe4114
-#define PCH_DPB_AUX_CH_DATA2	0xe4118
-#define PCH_DPB_AUX_CH_DATA3	0xe411c
-#define PCH_DPB_AUX_CH_DATA4	0xe4120
-#define PCH_DPB_AUX_CH_DATA5	0xe4124
+#define _PCH_DPB_AUX_CH_CTL	0xe4110
+#define _PCH_DPB_AUX_CH_DATA1	0xe4114
+#define _PCH_DPB_AUX_CH_DATA2	0xe4118
+#define _PCH_DPB_AUX_CH_DATA3	0xe411c
+#define _PCH_DPB_AUX_CH_DATA4	0xe4120
+#define _PCH_DPB_AUX_CH_DATA5	0xe4124
 
 #define PCH_DP_C		0xe4200
-#define PCH_DPC_AUX_CH_CTL	0xe4210
-#define PCH_DPC_AUX_CH_DATA1	0xe4214
-#define PCH_DPC_AUX_CH_DATA2	0xe4218
-#define PCH_DPC_AUX_CH_DATA3	0xe421c
-#define PCH_DPC_AUX_CH_DATA4	0xe4220
-#define PCH_DPC_AUX_CH_DATA5	0xe4224
+#define _PCH_DPC_AUX_CH_CTL	0xe4210
+#define _PCH_DPC_AUX_CH_DATA1	0xe4214
+#define _PCH_DPC_AUX_CH_DATA2	0xe4218
+#define _PCH_DPC_AUX_CH_DATA3	0xe421c
+#define _PCH_DPC_AUX_CH_DATA4	0xe4220
+#define _PCH_DPC_AUX_CH_DATA5	0xe4224
 
 #define PCH_DP_D		0xe4300
-#define PCH_DPD_AUX_CH_CTL	0xe4310
-#define PCH_DPD_AUX_CH_DATA1	0xe4314
-#define PCH_DPD_AUX_CH_DATA2	0xe4318
-#define PCH_DPD_AUX_CH_DATA3	0xe431c
-#define PCH_DPD_AUX_CH_DATA4	0xe4320
-#define PCH_DPD_AUX_CH_DATA5	0xe4324
+#define _PCH_DPD_AUX_CH_CTL	0xe4310
+#define _PCH_DPD_AUX_CH_DATA1	0xe4314
+#define _PCH_DPD_AUX_CH_DATA2	0xe4318
+#define _PCH_DPD_AUX_CH_DATA3	0xe431c
+#define _PCH_DPD_AUX_CH_DATA4	0xe4320
+#define _PCH_DPD_AUX_CH_DATA5	0xe4324
+
+#define PCH_DP_AUX_CH_CTL(port)		_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
+#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT	0
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8419890..ca219be 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 	else
 		precharge = 5;
 
-	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
+	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
 		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 	else
 		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -1014,14 +1014,12 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
 {
 	switch (port) {
 	case PORT_B:
-		return DPB_AUX_CH_CTL;
 	case PORT_C:
-		return DPC_AUX_CH_CTL;
 	case PORT_D:
-		return DPD_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(port);
 	default:
 		MISSING_CASE(port);
-		return DPB_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(PORT_B);
 	}
 }
 
@@ -1030,16 +1028,14 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 {
 	switch (port) {
 	case PORT_A:
-		return DPA_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(port);
 	case PORT_B:
-		return PCH_DPB_AUX_CH_CTL;
 	case PORT_C:
-		return PCH_DPC_AUX_CH_CTL;
 	case PORT_D:
-		return PCH_DPD_AUX_CH_CTL;
+		return PCH_DP_AUX_CH_CTL(port);
 	default:
 		MISSING_CASE(port);
-		return DPA_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(PORT_A);
 	}
 }
 
@@ -1075,16 +1071,13 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_A:
-		return DPA_AUX_CH_CTL;
 	case PORT_B:
-		return DPB_AUX_CH_CTL;
 	case PORT_C:
-		return DPC_AUX_CH_CTL;
 	case PORT_D:
-		return DPD_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(port);
 	default:
 		MISSING_CASE(port);
-		return DPA_AUX_CH_CTL;
+		return DP_AUX_CH_CTL(PORT_A);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 213581c..ff66718 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		[3] = 1 - 1,
 		[4] = DP_SET_POWER_D0,
 	};
+	enum port port = dig_port->port;
 	int i;
 
 	BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_AUX_FRAME_SYNC_ENABLE);
 
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
+		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
+		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-- 
2.4.9

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Re: [PATCH v3 38/43] drm/i915: Parametrize AUX registers

[Jani Nikula]

On Tue, 20 Oct 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> v2: Keep some MISSING_CASE() stuff (Jani)
>     s/-1/-PIPE_B/ in the register macro
>     Fix typo in patch subject
> v3: Use PORT_B registers for invalid ports in g4x_aux_ctl_reg() (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yuppers.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 102 ++++++++++++++++++++-------------------
>  drivers/gpu/drm/i915/intel_dp.c  |  23 +++------
>  drivers/gpu/drm/i915/intel_psr.c |   5 +-
>  3 files changed, 63 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2c518a0..7723ed3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3068,11 +3068,7 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
>  #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
> -#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
> -#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
> -#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
> -#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
> +#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
>  
>  #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
> @@ -4188,33 +4184,36 @@ enum skl_disp_power_wells {
>   * is 20 bytes in each direction, hence the 5 fixed
>   * data registers
>   */
> -#define DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> -#define DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> -#define DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> -#define DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> -#define DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> -#define DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> -
> -#define DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> -#define DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> -#define DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> -#define DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> -#define DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> -#define DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> -
> -#define DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> -#define DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> -#define DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> -#define DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> -#define DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> -#define DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> -
> -#define DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> -#define DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> -#define DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> -#define DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> -#define DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> -#define DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> +#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
> +#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
> +#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
> +#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
> +#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
> +#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
> +
> +#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
> +#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
> +#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
> +#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
> +#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
> +#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
> +
> +#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
> +#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
> +#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
> +#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
> +#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
> +#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
> +
> +#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
> +#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
> +#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
> +#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
> +#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
> +#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
> +
> +#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> +#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
>  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
> @@ -6549,28 +6548,31 @@ enum skl_disp_power_wells {
>  #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
>  
>  #define PCH_DP_B		0xe4100
> -#define PCH_DPB_AUX_CH_CTL	0xe4110
> -#define PCH_DPB_AUX_CH_DATA1	0xe4114
> -#define PCH_DPB_AUX_CH_DATA2	0xe4118
> -#define PCH_DPB_AUX_CH_DATA3	0xe411c
> -#define PCH_DPB_AUX_CH_DATA4	0xe4120
> -#define PCH_DPB_AUX_CH_DATA5	0xe4124
> +#define _PCH_DPB_AUX_CH_CTL	0xe4110
> +#define _PCH_DPB_AUX_CH_DATA1	0xe4114
> +#define _PCH_DPB_AUX_CH_DATA2	0xe4118
> +#define _PCH_DPB_AUX_CH_DATA3	0xe411c
> +#define _PCH_DPB_AUX_CH_DATA4	0xe4120
> +#define _PCH_DPB_AUX_CH_DATA5	0xe4124
>  
>  #define PCH_DP_C		0xe4200
> -#define PCH_DPC_AUX_CH_CTL	0xe4210
> -#define PCH_DPC_AUX_CH_DATA1	0xe4214
> -#define PCH_DPC_AUX_CH_DATA2	0xe4218
> -#define PCH_DPC_AUX_CH_DATA3	0xe421c
> -#define PCH_DPC_AUX_CH_DATA4	0xe4220
> -#define PCH_DPC_AUX_CH_DATA5	0xe4224
> +#define _PCH_DPC_AUX_CH_CTL	0xe4210
> +#define _PCH_DPC_AUX_CH_DATA1	0xe4214
> +#define _PCH_DPC_AUX_CH_DATA2	0xe4218
> +#define _PCH_DPC_AUX_CH_DATA3	0xe421c
> +#define _PCH_DPC_AUX_CH_DATA4	0xe4220
> +#define _PCH_DPC_AUX_CH_DATA5	0xe4224
>  
>  #define PCH_DP_D		0xe4300
> -#define PCH_DPD_AUX_CH_CTL	0xe4310
> -#define PCH_DPD_AUX_CH_DATA1	0xe4314
> -#define PCH_DPD_AUX_CH_DATA2	0xe4318
> -#define PCH_DPD_AUX_CH_DATA3	0xe431c
> -#define PCH_DPD_AUX_CH_DATA4	0xe4320
> -#define PCH_DPD_AUX_CH_DATA5	0xe4324
> +#define _PCH_DPD_AUX_CH_CTL	0xe4310
> +#define _PCH_DPD_AUX_CH_DATA1	0xe4314
> +#define _PCH_DPD_AUX_CH_DATA2	0xe4318
> +#define _PCH_DPD_AUX_CH_DATA3	0xe431c
> +#define _PCH_DPD_AUX_CH_DATA4	0xe4320
> +#define _PCH_DPD_AUX_CH_DATA5	0xe4324
> +
> +#define PCH_DP_AUX_CH_CTL(port)		_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> +#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  /* CPT */
>  #define  PORT_TRANS_A_SEL_CPT	0
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8419890..ca219be 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
>  	else
>  		precharge = 5;
>  
> -	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
> +	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
>  	else
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -1014,14 +1014,12 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  {
>  	switch (port) {
>  	case PORT_B:
> -		return DPB_AUX_CH_CTL;
>  	case PORT_C:
> -		return DPC_AUX_CH_CTL;
>  	case PORT_D:
> -		return DPD_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(port);
>  	default:
>  		MISSING_CASE(port);
> -		return DPB_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(PORT_B);
>  	}
>  }
>  
> @@ -1030,16 +1028,14 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  {
>  	switch (port) {
>  	case PORT_A:
> -		return DPA_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(port);
>  	case PORT_B:
> -		return PCH_DPB_AUX_CH_CTL;
>  	case PORT_C:
> -		return PCH_DPC_AUX_CH_CTL;
>  	case PORT_D:
> -		return PCH_DPD_AUX_CH_CTL;
> +		return PCH_DP_AUX_CH_CTL(port);
>  	default:
>  		MISSING_CASE(port);
> -		return DPA_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(PORT_A);
>  	}
>  }
>  
> @@ -1075,16 +1071,13 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  
>  	switch (port) {
>  	case PORT_A:
> -		return DPA_AUX_CH_CTL;
>  	case PORT_B:
> -		return DPB_AUX_CH_CTL;
>  	case PORT_C:
> -		return DPC_AUX_CH_CTL;
>  	case PORT_D:
> -		return DPD_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(port);
>  	default:
>  		MISSING_CASE(port);
> -		return DPA_AUX_CH_CTL;
> +		return DP_AUX_CH_CTL(PORT_A);
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 213581c..ff66718 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  		[3] = 1 - 1,
>  		[4] = DP_SET_POWER_D0,
>  	};
> +	enum port port = dig_port->port;
>  	int i;
>  
>  	BUILD_BUG_ON(sizeof(aux_msg) > 20);
> @@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  				DP_AUX_FRAME_SYNC_ENABLE);
>  
>  	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
> +		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
>  	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -				DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
> +		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
>  
>  	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
> -- 
> 2.4.9
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 39/43] drm/i915: Add dev_priv->psr_mmio_base

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
under dev_priv, like we for DSI and GPIO for example.

TODO: could probably move a bunch of this kind of stuff into the device
info instead...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h     |  2 ++
 drivers/gpu/drm/i915/i915_reg.h     | 15 ++++++++-------
 drivers/gpu/drm/i915/intel_psr.c    | 28 ++++++++++++++++------------
 4 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2322dac..38b0e38 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2536,7 +2536,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
 	if (HAS_DDI(dev))
-		enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
 	else {
 		for_each_pipe(dev_priv, pipe) {
 			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
@@ -2558,7 +2558,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 	/* CHV PSR has no kind of performance counter */
 	if (HAS_DDI(dev)) {
-		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
+		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
 			EDP_PSR_PERF_CNT_MASK;
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ed3c2..4359af1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1744,6 +1744,8 @@ struct drm_i915_private {
 	/* MMIO base address for MIPI regs */
 	uint32_t mipi_mmio_base;
 
+	uint32_t psr_mmio_base;
+
 	wait_queue_head_t gmbus_wait_queue;
 
 	struct pci_dev *bridge_dev;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04b2063..3437934 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3037,8 +3037,9 @@ enum skl_disp_power_wells {
 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
 
 /* HSW+ eDP PSR registers */
-#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
-#define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
+#define HSW_EDP_PSR_BASE	0x64800
+#define BDW_EDP_PSR_BASE	0x6f800
+#define EDP_PSR_CTL				(dev_priv->psr_mmio_base + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   BDW_PSR_SINGLE_FRAME			(1<<30)
 #define   EDP_PSR_LINK_STANDBY			(1<<27)
@@ -3061,10 +3062,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_TP1_TIME_0us			(3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
-#define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_CTL				(dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_DATA(i)			(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
+#define EDP_PSR_STATUS_CTL			(dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
@@ -3088,10 +3089,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
 
-#define EDP_PSR_PERF_CNT(dev)		(EDP_PSR_BASE(dev) + 0x44)
+#define EDP_PSR_PERF_CNT		(dev_priv->psr_mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
-#define EDP_PSR_DEBUG_CTL(dev)		(EDP_PSR_BASE(dev) + 0x60)
+#define EDP_PSR_DEBUG_CTL		(dev_priv->psr_mmio_base + 0x60)
 #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ff66718..90153e7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_AUX_FRAME_SYNC_ENABLE);
 
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
+		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
+		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
@@ -277,7 +277,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 		idle_frames += 4;
 	}
 
-	I915_WRITE(EDP_PSR_CTL(dev), val |
+	I915_WRITE(EDP_PSR_CTL, val |
 		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
 		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
@@ -341,7 +341,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
@@ -405,7 +405,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 		}
 
 		/* Avoid continuous PSR exit by masking memup and hpd */
-		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 			   EDP_PSR_DEBUG_MASK_HPD);
 
 		/* Enable PSR on the panel */
@@ -467,17 +467,17 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (dev_priv->psr.active) {
-		I915_WRITE(EDP_PSR_CTL(dev),
-			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
+		I915_WRITE(EDP_PSR_CTL,
+			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 
 		/* Wait till PSR is idle */
-		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
+		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
 			DRM_ERROR("Timed out waiting for PSR Idle State\n");
 
 		dev_priv->psr.active = false;
 	} else {
-		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	}
 }
 
@@ -524,7 +524,7 @@ static void intel_psr_work(struct work_struct *work)
 	 * and be ready for re-enable.
 	 */
 	if (HAS_DDI(dev_priv->dev)) {
-		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 			return;
@@ -567,11 +567,11 @@ static void intel_psr_exit(struct drm_device *dev)
 		return;
 
 	if (HAS_DDI(dev)) {
-		val = I915_READ(EDP_PSR_CTL(dev));
+		val = I915_READ(EDP_PSR_CTL);
 
 		WARN_ON(!(val & EDP_PSR_ENABLE));
 
-		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
+		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 	} else {
 		val = I915_READ(VLV_PSRCTL(pipe));
 
@@ -752,6 +752,10 @@ void intel_psr_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
+		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
+
 	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 	mutex_init(&dev_priv->psr.lock);
+
 }
-- 
2.4.6

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Re: [PATCH 39/43] drm/i915: Add dev_priv->psr_mmio_base

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
> under dev_priv, like we for DSI and GPIO for example.
>
> TODO: could probably move a bunch of this kind of stuff into the device
> info instead...
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
>  drivers/gpu/drm/i915/i915_drv.h     |  2 ++
>  drivers/gpu/drm/i915/i915_reg.h     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_psr.c    | 28 ++++++++++++++++------------
>  4 files changed, 28 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2322dac..38b0e38 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2536,7 +2536,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  		   yesno(work_busy(&dev_priv->psr.work.work)));
>  
>  	if (HAS_DDI(dev))
> -		enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
> +		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>  	else {
>  		for_each_pipe(dev_priv, pipe) {
>  			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
> @@ -2558,7 +2558,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  
>  	/* CHV PSR has no kind of performance counter */
>  	if (HAS_DDI(dev)) {
> -		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> +		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
>  			EDP_PSR_PERF_CNT_MASK;
>  
>  		seq_printf(m, "Performance_Counter: %u\n", psrperf);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 91ed3c2..4359af1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1744,6 +1744,8 @@ struct drm_i915_private {
>  	/* MMIO base address for MIPI regs */
>  	uint32_t mipi_mmio_base;
>  
> +	uint32_t psr_mmio_base;
> +
>  	wait_queue_head_t gmbus_wait_queue;
>  
>  	struct pci_dev *bridge_dev;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 04b2063..3437934 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3037,8 +3037,9 @@ enum skl_disp_power_wells {
>  #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
>  
>  /* HSW+ eDP PSR registers */
> -#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
> -#define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
> +#define HSW_EDP_PSR_BASE	0x64800
> +#define BDW_EDP_PSR_BASE	0x6f800
> +#define EDP_PSR_CTL				(dev_priv->psr_mmio_base + 0)
>  #define   EDP_PSR_ENABLE			(1<<31)
>  #define   BDW_PSR_SINGLE_FRAME			(1<<30)
>  #define   EDP_PSR_LINK_STANDBY			(1<<27)
> @@ -3061,10 +3062,10 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_TP1_TIME_0us			(3<<4)
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
> -#define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
> +#define EDP_PSR_AUX_CTL				(dev_priv->psr_mmio_base + 0x10)
> +#define EDP_PSR_AUX_DATA(i)			(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>  
> -#define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
> +#define EDP_PSR_STATUS_CTL			(dev_priv->psr_mmio_base + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
>  #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
>  #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
> @@ -3088,10 +3089,10 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
>  #define   EDP_PSR_STATUS_IDLE_MASK		0xf
>  
> -#define EDP_PSR_PERF_CNT(dev)		(EDP_PSR_BASE(dev) + 0x44)
> +#define EDP_PSR_PERF_CNT		(dev_priv->psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
>  
> -#define EDP_PSR_DEBUG_CTL(dev)		(EDP_PSR_BASE(dev) + 0x60)
> +#define EDP_PSR_DEBUG_CTL		(dev_priv->psr_mmio_base + 0x60)
>  #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
>  #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index ff66718..90153e7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  				DP_AUX_FRAME_SYNC_ENABLE);
>  
>  	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
> +		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
>  	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
> +		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
>  
>  	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
> @@ -277,7 +277,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>  		idle_frames += 4;
>  	}
>  
> -	I915_WRITE(EDP_PSR_CTL(dev), val |
> +	I915_WRITE(EDP_PSR_CTL, val |
>  		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
>  		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
>  		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
> @@ -341,7 +341,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> +	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>  	WARN_ON(dev_priv->psr.active);
>  	lockdep_assert_held(&dev_priv->psr.lock);
>  
> @@ -405,7 +405,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  		}
>  
>  		/* Avoid continuous PSR exit by masking memup and hpd */
> -		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> +		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
>  			   EDP_PSR_DEBUG_MASK_HPD);
>  
>  		/* Enable PSR on the panel */
> @@ -467,17 +467,17 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	if (dev_priv->psr.active) {
> -		I915_WRITE(EDP_PSR_CTL(dev),
> -			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
> +		I915_WRITE(EDP_PSR_CTL,
> +			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>  
>  		/* Wait till PSR is idle */
> -		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
> +		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
>  			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
>  			DRM_ERROR("Timed out waiting for PSR Idle State\n");
>  
>  		dev_priv->psr.active = false;
>  	} else {
> -		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> +		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>  	}
>  }
>  
> @@ -524,7 +524,7 @@ static void intel_psr_work(struct work_struct *work)
>  	 * and be ready for re-enable.
>  	 */
>  	if (HAS_DDI(dev_priv->dev)) {
> -		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
> +		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
>  			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>  			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>  			return;
> @@ -567,11 +567,11 @@ static void intel_psr_exit(struct drm_device *dev)
>  		return;
>  
>  	if (HAS_DDI(dev)) {
> -		val = I915_READ(EDP_PSR_CTL(dev));
> +		val = I915_READ(EDP_PSR_CTL);
>  
>  		WARN_ON(!(val & EDP_PSR_ENABLE));
>  
> -		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
> +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
>  	} else {
>  		val = I915_READ(VLV_PSRCTL(pipe));
>  
> @@ -752,6 +752,10 @@ void intel_psr_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> +	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
> +		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
> +
>  	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
>  	mutex_init(&dev_priv->psr.lock);
> +

Nitpick, superfluous whitespace.

Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  }
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 39/43] drm/i915: Add dev_priv->psr_mmio_base

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
under dev_priv, like we for DSI and GPIO for example.

TODO: could probably move a bunch of this kind of stuff into the device
info instead...

v2: Drop the surious whitespace change (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h     |  2 ++
 drivers/gpu/drm/i915/i915_reg.h     | 15 ++++++++-------
 drivers/gpu/drm/i915/intel_psr.c    | 27 +++++++++++++++------------
 4 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c38f766..74b17b4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2536,7 +2536,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
 	if (HAS_DDI(dev))
-		enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
 	else {
 		for_each_pipe(dev_priv, pipe) {
 			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
@@ -2558,7 +2558,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 	/* CHV PSR has no kind of performance counter */
 	if (HAS_DDI(dev)) {
-		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
+		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
 			EDP_PSR_PERF_CNT_MASK;
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e79f239..71a496d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1744,6 +1744,8 @@ struct drm_i915_private {
 	/* MMIO base address for MIPI regs */
 	uint32_t mipi_mmio_base;
 
+	uint32_t psr_mmio_base;
+
 	wait_queue_head_t gmbus_wait_queue;
 
 	struct pci_dev *bridge_dev;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7723ed3..ed90915 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3043,8 +3043,9 @@ enum skl_disp_power_wells {
 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
 
 /* HSW+ eDP PSR registers */
-#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
-#define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
+#define HSW_EDP_PSR_BASE	0x64800
+#define BDW_EDP_PSR_BASE	0x6f800
+#define EDP_PSR_CTL				(dev_priv->psr_mmio_base + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   BDW_PSR_SINGLE_FRAME			(1<<30)
 #define   EDP_PSR_LINK_STANDBY			(1<<27)
@@ -3067,10 +3068,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_TP1_TIME_0us			(3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
-#define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_CTL				(dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_DATA(i)			(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
+#define EDP_PSR_STATUS_CTL			(dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
@@ -3094,10 +3095,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
 
-#define EDP_PSR_PERF_CNT(dev)		(EDP_PSR_BASE(dev) + 0x44)
+#define EDP_PSR_PERF_CNT		(dev_priv->psr_mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
-#define EDP_PSR_DEBUG_CTL(dev)		(EDP_PSR_BASE(dev) + 0x60)
+#define EDP_PSR_DEBUG_CTL		(dev_priv->psr_mmio_base + 0x60)
 #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ff66718..3c973c5 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_AUX_FRAME_SYNC_ENABLE);
 
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
+		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
+		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
@@ -277,7 +277,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 		idle_frames += 4;
 	}
 
-	I915_WRITE(EDP_PSR_CTL(dev), val |
+	I915_WRITE(EDP_PSR_CTL, val |
 		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
 		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
@@ -341,7 +341,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
@@ -405,7 +405,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 		}
 
 		/* Avoid continuous PSR exit by masking memup and hpd */
-		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 			   EDP_PSR_DEBUG_MASK_HPD);
 
 		/* Enable PSR on the panel */
@@ -467,17 +467,17 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (dev_priv->psr.active) {
-		I915_WRITE(EDP_PSR_CTL(dev),
-			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
+		I915_WRITE(EDP_PSR_CTL,
+			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 
 		/* Wait till PSR is idle */
-		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
+		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
 			DRM_ERROR("Timed out waiting for PSR Idle State\n");
 
 		dev_priv->psr.active = false;
 	} else {
-		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	}
 }
 
@@ -524,7 +524,7 @@ static void intel_psr_work(struct work_struct *work)
 	 * and be ready for re-enable.
 	 */
 	if (HAS_DDI(dev_priv->dev)) {
-		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 			return;
@@ -567,11 +567,11 @@ static void intel_psr_exit(struct drm_device *dev)
 		return;
 
 	if (HAS_DDI(dev)) {
-		val = I915_READ(EDP_PSR_CTL(dev));
+		val = I915_READ(EDP_PSR_CTL);
 
 		WARN_ON(!(val & EDP_PSR_ENABLE));
 
-		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
+		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 	} else {
 		val = I915_READ(VLV_PSRCTL(pipe));
 
@@ -752,6 +752,9 @@ void intel_psr_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
+		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
+
 	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 	mutex_init(&dev_priv->psr.lock);
 }
-- 
2.4.9

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Re: [PATCH v2 39/43] drm/i915: Add dev_priv->psr_mmio_base

[Jani Nikula]

On Tue, 20 Oct 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
> under dev_priv, like we for DSI and GPIO for example.
>
> TODO: could probably move a bunch of this kind of stuff into the device
> info instead...
>
> v2: Drop the surious whitespace change (Jani)

Are you surious about that?

> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yes.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
>  drivers/gpu/drm/i915/i915_drv.h     |  2 ++
>  drivers/gpu/drm/i915/i915_reg.h     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_psr.c    | 27 +++++++++++++++------------
>  4 files changed, 27 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c38f766..74b17b4 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2536,7 +2536,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  		   yesno(work_busy(&dev_priv->psr.work.work)));
>  
>  	if (HAS_DDI(dev))
> -		enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
> +		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>  	else {
>  		for_each_pipe(dev_priv, pipe) {
>  			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
> @@ -2558,7 +2558,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  
>  	/* CHV PSR has no kind of performance counter */
>  	if (HAS_DDI(dev)) {
> -		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> +		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
>  			EDP_PSR_PERF_CNT_MASK;
>  
>  		seq_printf(m, "Performance_Counter: %u\n", psrperf);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e79f239..71a496d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1744,6 +1744,8 @@ struct drm_i915_private {
>  	/* MMIO base address for MIPI regs */
>  	uint32_t mipi_mmio_base;
>  
> +	uint32_t psr_mmio_base;
> +
>  	wait_queue_head_t gmbus_wait_queue;
>  
>  	struct pci_dev *bridge_dev;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7723ed3..ed90915 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3043,8 +3043,9 @@ enum skl_disp_power_wells {
>  #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
>  
>  /* HSW+ eDP PSR registers */
> -#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
> -#define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
> +#define HSW_EDP_PSR_BASE	0x64800
> +#define BDW_EDP_PSR_BASE	0x6f800
> +#define EDP_PSR_CTL				(dev_priv->psr_mmio_base + 0)
>  #define   EDP_PSR_ENABLE			(1<<31)
>  #define   BDW_PSR_SINGLE_FRAME			(1<<30)
>  #define   EDP_PSR_LINK_STANDBY			(1<<27)
> @@ -3067,10 +3068,10 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_TP1_TIME_0us			(3<<4)
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
> -#define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA(dev, i)		(EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
> +#define EDP_PSR_AUX_CTL				(dev_priv->psr_mmio_base + 0x10)
> +#define EDP_PSR_AUX_DATA(i)			(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>  
> -#define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
> +#define EDP_PSR_STATUS_CTL			(dev_priv->psr_mmio_base + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
>  #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
>  #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
> @@ -3094,10 +3095,10 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
>  #define   EDP_PSR_STATUS_IDLE_MASK		0xf
>  
> -#define EDP_PSR_PERF_CNT(dev)		(EDP_PSR_BASE(dev) + 0x44)
> +#define EDP_PSR_PERF_CNT		(dev_priv->psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
>  
> -#define EDP_PSR_DEBUG_CTL(dev)		(EDP_PSR_BASE(dev) + 0x60)
> +#define EDP_PSR_DEBUG_CTL		(dev_priv->psr_mmio_base + 0x60)
>  #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
>  #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index ff66718..3c973c5 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  				DP_AUX_FRAME_SYNC_ENABLE);
>  
>  	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
> +		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
>  	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> -		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
> +		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
>  
>  	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
> @@ -277,7 +277,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>  		idle_frames += 4;
>  	}
>  
> -	I915_WRITE(EDP_PSR_CTL(dev), val |
> +	I915_WRITE(EDP_PSR_CTL, val |
>  		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
>  		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
>  		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
> @@ -341,7 +341,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> +	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>  	WARN_ON(dev_priv->psr.active);
>  	lockdep_assert_held(&dev_priv->psr.lock);
>  
> @@ -405,7 +405,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  		}
>  
>  		/* Avoid continuous PSR exit by masking memup and hpd */
> -		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> +		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
>  			   EDP_PSR_DEBUG_MASK_HPD);
>  
>  		/* Enable PSR on the panel */
> @@ -467,17 +467,17 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	if (dev_priv->psr.active) {
> -		I915_WRITE(EDP_PSR_CTL(dev),
> -			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
> +		I915_WRITE(EDP_PSR_CTL,
> +			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>  
>  		/* Wait till PSR is idle */
> -		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
> +		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
>  			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
>  			DRM_ERROR("Timed out waiting for PSR Idle State\n");
>  
>  		dev_priv->psr.active = false;
>  	} else {
> -		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> +		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>  	}
>  }
>  
> @@ -524,7 +524,7 @@ static void intel_psr_work(struct work_struct *work)
>  	 * and be ready for re-enable.
>  	 */
>  	if (HAS_DDI(dev_priv->dev)) {
> -		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
> +		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
>  			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>  			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>  			return;
> @@ -567,11 +567,11 @@ static void intel_psr_exit(struct drm_device *dev)
>  		return;
>  
>  	if (HAS_DDI(dev)) {
> -		val = I915_READ(EDP_PSR_CTL(dev));
> +		val = I915_READ(EDP_PSR_CTL);
>  
>  		WARN_ON(!(val & EDP_PSR_ENABLE));
>  
> -		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
> +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
>  	} else {
>  		val = I915_READ(VLV_PSRCTL(pipe));
>  
> @@ -752,6 +752,9 @@ void intel_psr_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> +	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
> +		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
> +
>  	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
>  	mutex_init(&dev_priv->psr.lock);
>  }
> -- 
> 2.4.9
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rather than computing on demand, store also the aux data reg
offsets under intel_dp.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 49 +++++++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 27df240..0e5f674 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,7 +791,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
-	uint32_t ch_data = ch_ctl + 4;
 	uint32_t aux_clock_divider;
 	int i, ret, recv_bytes;
 	uint32_t status;
@@ -857,7 +856,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		for (try = 0; try < 5; try++) {
 			/* Load the send data into the aux channel data registers */
 			for (i = 0; i < send_bytes; i += 4)
-				I915_WRITE(ch_data + i,
+				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 					   intel_dp_pack_aux(send + i,
 							     send_bytes - i));
 
@@ -921,7 +920,7 @@ done:
 		recv_bytes = recv_size;
 
 	for (i = 0; i < recv_bytes; i += 4)
-		intel_dp_unpack_aux(I915_READ(ch_data + i),
+		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 				    recv + i, recv_bytes - i);
 
 	ret = recv_bytes;
@@ -1009,19 +1008,22 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 	return ret;
 }
 
-static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
-				enum port port)
+static uint32_t g4x_aux_reg(struct drm_i915_private *dev_priv,
+			    enum port port, int index)
 {
-	return DP_AUX_CH_CTL(port);
+	return index < 0 ? DP_AUX_CH_CTL(port) :
+		DP_AUX_CH_DATA(port, index);
 }
 
-static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
-				enum port port)
+static uint32_t ilk_aux_reg(struct drm_i915_private *dev_priv,
+			    enum port port, int index)
 {
 	if (port == PORT_A)
-		return DP_AUX_CH_CTL(port);
+		return index < 0 ? DP_AUX_CH_CTL(port) :
+			DP_AUX_CH_DATA(port, index);
 	else
-		return PCH_DP_AUX_CH_CTL(port);
+		return index < 0 ? PCH_DP_AUX_CH_CTL(port) :
+			PCH_DP_AUX_CH_DATA(port, index);
 }
 
 /*
@@ -1048,13 +1050,28 @@ static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
 	}
 }
 
-static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
-				enum port port)
+static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
+			    enum port port, int index)
 {
 	if (port == PORT_E)
 		port = skl_porte_aux_port(dev_priv);
 
-	return DP_AUX_CH_CTL(port);
+	return index < 0 ? DP_AUX_CH_CTL(port) :
+		DP_AUX_CH_DATA(port, index);
+}
+
+static void aux_reg_init(struct intel_dp *intel_dp,
+			 uint32_t (*aux_reg)(struct drm_i915_private *dev_priv,
+					     enum port port, int index))
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+	enum port port = dp_to_dig_port(intel_dp)->port;
+	int i;
+
+	intel_dp->aux_ch_ctl_reg = aux_reg(dev_priv, port, -1);
+
+	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
+		intel_dp->aux_ch_data_reg[i] = aux_reg(dev_priv, port, i);
 }
 
 static void
@@ -1074,11 +1091,11 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 	};
 
 	if (INTEL_INFO(dev_priv)->gen >= 9)
-		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
+		aux_reg_init(intel_dp, skl_aux_reg);
 	else if (HAS_PCH_SPLIT(dev_priv))
-		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
+		aux_reg_init(intel_dp, ilk_aux_reg);
 	else
-		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
+		aux_reg_init(intel_dp, g4x_aux_reg);
 
 	intel_dp->aux.name = ddc_name[port];
 	intel_dp->aux.dev = dev->dev;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1df6ebf..3fea039 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -717,6 +717,7 @@ struct sink_crc {
 struct intel_dp {
 	uint32_t output_reg;
 	uint32_t aux_ch_ctl_reg;
+	uint32_t aux_ch_data_reg[5];
 	uint32_t DP;
 	int link_rate;
 	uint8_t lane_count;
-- 
2.4.6

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rather than computing on demand, store also the aux data reg
> offsets under intel_dp.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 49 +++++++++++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  2 files changed, 34 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 27df240..0e5f674 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -791,7 +791,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
> -	uint32_t ch_data = ch_ctl + 4;
>  	uint32_t aux_clock_divider;
>  	int i, ret, recv_bytes;
>  	uint32_t status;
> @@ -857,7 +856,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  		for (try = 0; try < 5; try++) {
>  			/* Load the send data into the aux channel data registers */
>  			for (i = 0; i < send_bytes; i += 4)
> -				I915_WRITE(ch_data + i,
> +				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
>  					   intel_dp_pack_aux(send + i,
>  							     send_bytes - i));
>  
> @@ -921,7 +920,7 @@ done:
>  		recv_bytes = recv_size;
>  
>  	for (i = 0; i < recv_bytes; i += 4)
> -		intel_dp_unpack_aux(I915_READ(ch_data + i),
> +		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
>  				    recv + i, recv_bytes - i);
>  
>  	ret = recv_bytes;
> @@ -1009,19 +1008,22 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
>  	return ret;
>  }
>  
> -static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> -				enum port port)
> +static uint32_t g4x_aux_reg(struct drm_i915_private *dev_priv,
> +			    enum port port, int index)
>  {
> -	return DP_AUX_CH_CTL(port);
> +	return index < 0 ? DP_AUX_CH_CTL(port) :
> +		DP_AUX_CH_DATA(port, index);
>  }
>  
> -static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
> -				enum port port)
> +static uint32_t ilk_aux_reg(struct drm_i915_private *dev_priv,
> +			    enum port port, int index)
>  {
>  	if (port == PORT_A)
> -		return DP_AUX_CH_CTL(port);
> +		return index < 0 ? DP_AUX_CH_CTL(port) :
> +			DP_AUX_CH_DATA(port, index);
>  	else
> -		return PCH_DP_AUX_CH_CTL(port);
> +		return index < 0 ? PCH_DP_AUX_CH_CTL(port) :
> +			PCH_DP_AUX_CH_DATA(port, index);
>  }
>  
>  /*
> @@ -1048,13 +1050,28 @@ static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> -static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
> -				enum port port)
> +static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
> +			    enum port port, int index)
>  {
>  	if (port == PORT_E)
>  		port = skl_porte_aux_port(dev_priv);
>  
> -	return DP_AUX_CH_CTL(port);
> +	return index < 0 ? DP_AUX_CH_CTL(port) :
> +		DP_AUX_CH_DATA(port, index);
> +}
> +
> +static void aux_reg_init(struct intel_dp *intel_dp,
> +			 uint32_t (*aux_reg)(struct drm_i915_private *dev_priv,
> +					     enum port port, int index))
> +{
> +	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> +	enum port port = dp_to_dig_port(intel_dp)->port;
> +	int i;
> +
> +	intel_dp->aux_ch_ctl_reg = aux_reg(dev_priv, port, -1);
> +
> +	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
> +		intel_dp->aux_ch_data_reg[i] = aux_reg(dev_priv, port, i);
>  }
>  
>  static void
> @@ -1074,11 +1091,11 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
>  	};
>  
>  	if (INTEL_INFO(dev_priv)->gen >= 9)
> -		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
> +		aux_reg_init(intel_dp, skl_aux_reg);
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
> +		aux_reg_init(intel_dp, ilk_aux_reg);
>  	else
> -		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
> +		aux_reg_init(intel_dp, g4x_aux_reg);


IMO there's too much trickery in this patch to get the registers set
up. -1 for ctl, i >> 2 to get the right index, function pointers for set
up only, etc. I don't think it would be too much duplication to add
separate initializers for each group of platforms, ditching the function
pointers and -1 for ctl.

BR,
Jani.




>  
>  	intel_dp->aux.name = ddc_name[port];
>  	intel_dp->aux.dev = dev->dev;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1df6ebf..3fea039 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -717,6 +717,7 @@ struct sink_crc {
>  struct intel_dp {
>  	uint32_t output_reg;
>  	uint32_t aux_ch_ctl_reg;
> +	uint32_t aux_ch_data_reg[5];
>  	uint32_t DP;
>  	int link_rate;
>  	uint8_t lane_count;
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

[Ville Syrjälä]

On Mon, Sep 28, 2015 at 03:28:18PM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rather than computing on demand, store also the aux data reg
> > offsets under intel_dp.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c  | 49 +++++++++++++++++++++++++++-------------
> >  drivers/gpu/drm/i915/intel_drv.h |  1 +
> >  2 files changed, 34 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 27df240..0e5f674 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -791,7 +791,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> >  	struct drm_device *dev = intel_dig_port->base.base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
> > -	uint32_t ch_data = ch_ctl + 4;
> >  	uint32_t aux_clock_divider;
> >  	int i, ret, recv_bytes;
> >  	uint32_t status;
> > @@ -857,7 +856,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> >  		for (try = 0; try < 5; try++) {
> >  			/* Load the send data into the aux channel data registers */
> >  			for (i = 0; i < send_bytes; i += 4)
> > -				I915_WRITE(ch_data + i,
> > +				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
> >  					   intel_dp_pack_aux(send + i,
> >  							     send_bytes - i));
> >  
> > @@ -921,7 +920,7 @@ done:
> >  		recv_bytes = recv_size;
> >  
> >  	for (i = 0; i < recv_bytes; i += 4)
> > -		intel_dp_unpack_aux(I915_READ(ch_data + i),
> > +		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
> >  				    recv + i, recv_bytes - i);
> >  
> >  	ret = recv_bytes;
> > @@ -1009,19 +1008,22 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
> >  	return ret;
> >  }
> >  
> > -static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > -				enum port port)
> > +static uint32_t g4x_aux_reg(struct drm_i915_private *dev_priv,
> > +			    enum port port, int index)
> >  {
> > -	return DP_AUX_CH_CTL(port);
> > +	return index < 0 ? DP_AUX_CH_CTL(port) :
> > +		DP_AUX_CH_DATA(port, index);
> >  }
> >  
> > -static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > -				enum port port)
> > +static uint32_t ilk_aux_reg(struct drm_i915_private *dev_priv,
> > +			    enum port port, int index)
> >  {
> >  	if (port == PORT_A)
> > -		return DP_AUX_CH_CTL(port);
> > +		return index < 0 ? DP_AUX_CH_CTL(port) :
> > +			DP_AUX_CH_DATA(port, index);
> >  	else
> > -		return PCH_DP_AUX_CH_CTL(port);
> > +		return index < 0 ? PCH_DP_AUX_CH_CTL(port) :
> > +			PCH_DP_AUX_CH_DATA(port, index);
> >  }
> >  
> >  /*
> > @@ -1048,13 +1050,28 @@ static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
> >  	}
> >  }
> >  
> > -static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > -				enum port port)
> > +static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
> > +			    enum port port, int index)
> >  {
> >  	if (port == PORT_E)
> >  		port = skl_porte_aux_port(dev_priv);
> >  
> > -	return DP_AUX_CH_CTL(port);
> > +	return index < 0 ? DP_AUX_CH_CTL(port) :
> > +		DP_AUX_CH_DATA(port, index);
> > +}
> > +
> > +static void aux_reg_init(struct intel_dp *intel_dp,
> > +			 uint32_t (*aux_reg)(struct drm_i915_private *dev_priv,
> > +					     enum port port, int index))
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> > +	enum port port = dp_to_dig_port(intel_dp)->port;
> > +	int i;
> > +
> > +	intel_dp->aux_ch_ctl_reg = aux_reg(dev_priv, port, -1);
> > +
> > +	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
> > +		intel_dp->aux_ch_data_reg[i] = aux_reg(dev_priv, port, i);
> >  }
> >  
> >  static void
> > @@ -1074,11 +1091,11 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
> >  	};
> >  
> >  	if (INTEL_INFO(dev_priv)->gen >= 9)
> > -		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
> > +		aux_reg_init(intel_dp, skl_aux_reg);
> >  	else if (HAS_PCH_SPLIT(dev_priv))
> > -		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
> > +		aux_reg_init(intel_dp, ilk_aux_reg);
> >  	else
> > -		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
> > +		aux_reg_init(intel_dp, g4x_aux_reg);
> 
> 
> IMO there's too much trickery in this patch to get the registers set
> up. -1 for ctl, i >> 2 to get the right index, function pointers for set
> up only, etc. I don't think it would be too much duplication to add
> separate initializers for each group of platforms, ditching the function
> pointers and -1 for ctl.

Less LOC, less bugs. But I can blow up the LOC count here if people
prefer that.

> 
> BR,
> Jani.
> 
> 
> 
> 
> >  
> >  	intel_dp->aux.name = ddc_name[port];
> >  	intel_dp->aux.dev = dev->dev;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 1df6ebf..3fea039 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -717,6 +717,7 @@ struct sink_crc {
> >  struct intel_dp {
> >  	uint32_t output_reg;
> >  	uint32_t aux_ch_ctl_reg;
> > +	uint32_t aux_ch_data_reg[5];
> >  	uint32_t DP;
> >  	int link_rate;
> >  	uint8_t lane_count;
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rather than computing on demand, store also the aux data reg
offsets under intel_dp.

v2: Duplicate some code to make things less magic (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 94 +++++++++++++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 85 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d252feb..cfb2efa 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,7 +791,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
-	uint32_t ch_data = ch_ctl + 4;
 	uint32_t aux_clock_divider;
 	int i, ret, recv_bytes;
 	uint32_t status;
@@ -857,7 +856,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		for (try = 0; try < 5; try++) {
 			/* Load the send data into the aux channel data registers */
 			for (i = 0; i < send_bytes; i += 4)
-				I915_WRITE(ch_data + i,
+				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 					   intel_dp_pack_aux(send + i,
 							     send_bytes - i));
 
@@ -921,7 +920,7 @@ done:
 		recv_bytes = recv_size;
 
 	for (i = 0; i < recv_bytes; i += 4)
-		intel_dp_unpack_aux(I915_READ(ch_data + i),
+		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 				    recv + i, recv_bytes - i);
 
 	ret = recv_bytes;
@@ -1023,6 +1022,20 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static uint32_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	switch (port) {
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		return DP_AUX_CH_DATA(port, index);
+	default:
+		MISSING_CASE(port);
+		return DP_AUX_CH_DATA(PORT_A, index);
+	}
+}
+
 static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				enum port port)
 {
@@ -1039,6 +1052,22 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static uint32_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	switch (port) {
+	case PORT_A:
+		return DP_AUX_CH_DATA(port, index);
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		return PCH_DP_AUX_CH_DATA(port, index);
+	default:
+		MISSING_CASE(port);
+		return DP_AUX_CH_DATA(PORT_A, index);
+	}
+}
+
 /*
  * On SKL we don't have Aux for port E so we rely
  * on VBT to set a proper alternate aux channel.
@@ -1081,11 +1110,61 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static uint32_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	if (port == PORT_E)
+		port = skl_porte_aux_port(dev_priv);
+
+	switch (port) {
+	case PORT_A:
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		return DP_AUX_CH_DATA(port, index);
+	default:
+		MISSING_CASE(port);
+		return DP_AUX_CH_DATA(PORT_A, index);
+	}
+}
+
+static uint32_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				  enum port port)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return skl_aux_ctl_reg(dev_priv, port);
+	else if (HAS_PCH_SPLIT(dev_priv))
+		return ilk_aux_ctl_reg(dev_priv, port);
+	else
+		return g4x_aux_ctl_reg(dev_priv, port);
+}
+
+static uint32_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
+				   enum port port, int index)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return skl_aux_data_reg(dev_priv, port, index);
+	else if (HAS_PCH_SPLIT(dev_priv))
+		return ilk_aux_data_reg(dev_priv, port, index);
+	else
+		return g4x_aux_data_reg(dev_priv, port, index);
+}
+
+static void intel_aux_reg_init(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+	enum port port = dp_to_dig_port(intel_dp)->port;
+	int i;
+
+	intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
+	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
+		intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
+}
+
 static void
 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	enum port port = intel_dig_port->port;
 	int ret;
@@ -1097,12 +1176,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 		[PORT_E] = "DPDDC-E",
 	};
 
-	if (INTEL_INFO(dev_priv)->gen >= 9)
-		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
-	else if (HAS_PCH_SPLIT(dev_priv))
-		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
-	else
-		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
+	intel_aux_reg_init(intel_dp);
 
 	intel_dp->aux.name = ddc_name[port];
 	intel_dp->aux.dev = dev->dev;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1df6ebf..3fea039 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -717,6 +717,7 @@ struct sink_crc {
 struct intel_dp {
 	uint32_t output_reg;
 	uint32_t aux_ch_ctl_reg;
+	uint32_t aux_ch_data_reg[5];
 	uint32_t DP;
 	int link_rate;
 	uint8_t lane_count;
-- 
2.4.6

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[PATCH v3 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rather than computing on demand, store also the aux data reg
offsets under intel_dp.

v2: Duplicate some code to make things less magic (Jani)
v3: Use PORT_B registers for invalid ports in g4x_aux_data_reg()

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 94 +++++++++++++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 85 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca219be..cb41802 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,7 +791,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
-	uint32_t ch_data = ch_ctl + 4;
 	uint32_t aux_clock_divider;
 	int i, ret, recv_bytes;
 	uint32_t status;
@@ -857,7 +856,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		for (try = 0; try < 5; try++) {
 			/* Load the send data into the aux channel data registers */
 			for (i = 0; i < send_bytes; i += 4)
-				I915_WRITE(ch_data + i,
+				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 					   intel_dp_pack_aux(send + i,
 							     send_bytes - i));
 
@@ -921,7 +920,7 @@ done:
 		recv_bytes = recv_size;
 
 	for (i = 0; i < recv_bytes; i += 4)
-		intel_dp_unpack_aux(I915_READ(ch_data + i),
+		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 				    recv + i, recv_bytes - i);
 
 	ret = recv_bytes;
@@ -1023,6 +1022,20 @@ static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static uint32_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	switch (port) {
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		return DP_AUX_CH_DATA(port, index);
+	default:
+		MISSING_CASE(port);
+		return DP_AUX_CH_DATA(PORT_B, index);
+	}
+}
+
 static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				enum port port)
 {
@@ -1039,6 +1052,22 @@ static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static uint32_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	switch (port) {
+	case PORT_A:
+		return DP_AUX_CH_DATA(port, index);
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		return PCH_DP_AUX_CH_DATA(port, index);
+	default:
+		MISSING_CASE(port);
+		return DP_AUX_CH_DATA(PORT_A, index);
+	}
+}
+
 /*
  * On SKL we don't have Aux for port E so we rely
  * on VBT to set a proper alternate aux channel.
@@ -1081,11 +1110,61 @@ static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
+static uint32_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	if (port == PORT_E)
+		port = skl_porte_aux_port(dev_priv);
+
+	switch (port) {
+	case PORT_A:
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		return DP_AUX_CH_DATA(port, index);
+	default:
+		MISSING_CASE(port);
+		return DP_AUX_CH_DATA(PORT_A, index);
+	}
+}
+
+static uint32_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				  enum port port)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return skl_aux_ctl_reg(dev_priv, port);
+	else if (HAS_PCH_SPLIT(dev_priv))
+		return ilk_aux_ctl_reg(dev_priv, port);
+	else
+		return g4x_aux_ctl_reg(dev_priv, port);
+}
+
+static uint32_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
+				   enum port port, int index)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return skl_aux_data_reg(dev_priv, port, index);
+	else if (HAS_PCH_SPLIT(dev_priv))
+		return ilk_aux_data_reg(dev_priv, port, index);
+	else
+		return g4x_aux_data_reg(dev_priv, port, index);
+}
+
+static void intel_aux_reg_init(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+	enum port port = dp_to_dig_port(intel_dp)->port;
+	int i;
+
+	intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
+	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
+		intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
+}
+
 static void
 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	enum port port = intel_dig_port->port;
 	int ret;
@@ -1097,12 +1176,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 		[PORT_E] = "DPDDC-E",
 	};
 
-	if (INTEL_INFO(dev_priv)->gen >= 9)
-		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
-	else if (HAS_PCH_SPLIT(dev_priv))
-		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
-	else
-		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
+	intel_aux_reg_init(intel_dp);
 
 	intel_dp->aux.name = ddc_name[port];
 	intel_dp->aux.dev = dev->dev;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1df6ebf..3fea039 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -717,6 +717,7 @@ struct sink_crc {
 struct intel_dp {
 	uint32_t output_reg;
 	uint32_t aux_ch_ctl_reg;
+	uint32_t aux_ch_data_reg[5];
 	uint32_t DP;
 	int link_rate;
 	uint8_t lane_count;
-- 
2.4.9

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[PATCH 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 90153e7..0f944e2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -151,13 +151,24 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 }
 
+static uint32_t psr_aux_reg(struct drm_i915_private *dev_priv,
+			    enum port port, int index)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return index < 0 ? DP_AUX_CH_CTL(port) :
+			DP_AUX_CH_DATA(port, index);
+	else
+		return index < 0 ? EDP_PSR_AUX_CTL :
+			EDP_PSR_AUX_DATA(index);
+}
+
 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t aux_clock_divider;
-	uint32_t aux_data_reg, aux_ctl_reg;
+	uint32_t aux_ctl_reg;
 	int precharge = 0x3;
 	static const uint8_t aux_msg[] = {
 		[0] = DP_AUX_NATIVE_WRITE << 4,
@@ -182,14 +193,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 				DP_AUX_FRAME_SYNC_ENABLE);
 
-	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
-	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
+	aux_ctl_reg = psr_aux_reg(dev_priv, port, -1);
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-		I915_WRITE(aux_data_reg + i,
+		I915_WRITE(psr_aux_reg(dev_priv, port, i >> 2),
 			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
 	if (INTEL_INFO(dev)->gen >= 9) {
-- 
2.4.6

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[PATCH v2 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Split up the ctl vs. data reg handling like in the normal AUX code

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 90153e7..31d89b7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -151,13 +151,31 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 }
 
+static uint32_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
+				enum port port)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return DP_AUX_CH_CTL(port);
+	else
+		return EDP_PSR_AUX_CTL;
+}
+
+static uint32_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
+				 enum port port, int index)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return DP_AUX_CH_DATA(port, index);
+	else
+		return EDP_PSR_AUX_DATA(index);
+}
+
 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t aux_clock_divider;
-	uint32_t aux_data_reg, aux_ctl_reg;
+	uint32_t aux_ctl_reg;
 	int precharge = 0x3;
 	static const uint8_t aux_msg[] = {
 		[0] = DP_AUX_NATIVE_WRITE << 4,
@@ -182,14 +200,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 				DP_AUX_FRAME_SYNC_ENABLE);
 
-	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
-	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-		DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
+	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
-		I915_WRITE(aux_data_reg + i,
+		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
 	if (INTEL_INFO(dev)->gen >= 9) {
-- 
2.4.6

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[PATCH 42/43] drm/i915: Prefix raw register defines with underscore

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Most of our register defines follow the convention that if there's a
need for the raw register offset, that one has an underscore sa a
prefix. The define (possibly parametrized) without the underscore is
the one people should normally use, since it will take into account
all the paramters and other potential offsets that are needed.

Fix up the few stragglers that don't follow this convention.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 262 ++++++++++++++++++++--------------------
 1 file changed, 131 insertions(+), 131 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3437934..140076d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4689,37 +4689,37 @@ enum skl_disp_power_wells {
 #define I965_CURSOR_DFT_WM	8
 
 /* Watermark register definitions for SKL */
-#define CUR_WM_A_0		0x70140
-#define CUR_WM_B_0		0x71140
-#define PLANE_WM_1_A_0		0x70240
-#define PLANE_WM_1_B_0		0x71240
-#define PLANE_WM_2_A_0		0x70340
-#define PLANE_WM_2_B_0		0x71340
-#define PLANE_WM_TRANS_1_A_0	0x70268
-#define PLANE_WM_TRANS_1_B_0	0x71268
-#define PLANE_WM_TRANS_2_A_0	0x70368
-#define PLANE_WM_TRANS_2_B_0	0x71368
-#define CUR_WM_TRANS_A_0	0x70168
-#define CUR_WM_TRANS_B_0	0x71168
+#define _CUR_WM_A_0		0x70140
+#define _CUR_WM_B_0		0x71140
+#define _PLANE_WM_1_A_0		0x70240
+#define _PLANE_WM_1_B_0		0x71240
+#define _PLANE_WM_2_A_0		0x70340
+#define _PLANE_WM_2_B_0		0x71340
+#define _PLANE_WM_TRANS_1_A_0	0x70268
+#define _PLANE_WM_TRANS_1_B_0	0x71268
+#define _PLANE_WM_TRANS_2_A_0	0x70368
+#define _PLANE_WM_TRANS_2_B_0	0x71368
+#define _CUR_WM_TRANS_A_0	0x70168
+#define _CUR_WM_TRANS_B_0	0x71168
 #define   PLANE_WM_EN		(1 << 31)
 #define   PLANE_WM_LINES_SHIFT	14
 #define   PLANE_WM_LINES_MASK	0x1f
 #define   PLANE_WM_BLOCKS_MASK	0x3ff
 
-#define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
-#define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
+#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
+#define CUR_WM(pipe, level) (_CUR_WM_0(pipe) + ((4) * (level)))
+#define CUR_WM_TRANS(pipe) _PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
 
-#define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
 #define _PLANE_WM_BASE(pipe, plane)	\
 			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
 #define PLANE_WM(pipe, plane, level)	\
 			(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
 #define _PLANE_WM_TRANS_1(pipe)	\
-			_PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
+			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
 #define _PLANE_WM_TRANS_2(pipe)	\
-			_PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
+			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
 #define PLANE_WM_TRANS(pipe, plane)	\
 		_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
 
@@ -6185,74 +6185,74 @@ enum skl_disp_power_wells {
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
 /* Per-transcoder DIP controls (VLV) */
-#define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
-#define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
+#define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
+#define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
+#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
 
-#define VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
-#define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
+#define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
+#define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
+#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
 
-#define CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
-#define CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
-#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
+#define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
+#define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
+#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
 
 #define VLV_TVIDEO_DIP_CTL(pipe) \
-	_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
-	       VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
+	_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
+	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
 #define VLV_TVIDEO_DIP_DATA(pipe) \
-	_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
-	       VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
+	_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
+	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
 #define VLV_TVIDEO_DIP_GCP(pipe) \
-	_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
-		VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
+	_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
+		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
 
 /* Haswell DIP controls */
-#define HSW_VIDEO_DIP_CTL_A		0x60200
-#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
-#define HSW_VIDEO_DIP_VS_DATA_A		0x60260
-#define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
-#define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
-#define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
-#define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
-#define HSW_VIDEO_DIP_VS_ECC_A		0x60280
-#define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
-#define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
-#define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
-#define HSW_VIDEO_DIP_GCP_A		0x60210
-
-#define HSW_VIDEO_DIP_CTL_B		0x61200
-#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
-#define HSW_VIDEO_DIP_VS_DATA_B		0x61260
-#define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
-#define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
-#define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
-#define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
-#define HSW_VIDEO_DIP_VS_ECC_B		0x61280
-#define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
-#define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
-#define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
-#define HSW_VIDEO_DIP_GCP_B		0x61210
+#define _HSW_VIDEO_DIP_CTL_A		0x60200
+#define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
+#define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
+#define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
+#define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
+#define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
+#define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
+#define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
+#define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
+#define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
+#define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
+#define _HSW_VIDEO_DIP_GCP_A		0x60210
+
+#define _HSW_VIDEO_DIP_CTL_B		0x61200
+#define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
+#define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
+#define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
+#define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
+#define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
+#define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
+#define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
+#define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
+#define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
+#define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
+#define _HSW_VIDEO_DIP_GCP_B		0x61210
 
 #define HSW_TVIDEO_DIP_CTL(trans) \
-	 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
+	 _TRANSCODER2(trans, _HSW_VIDEO_DIP_CTL_A)
 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
-	(_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
+	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
-	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
+	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
-	(_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
+	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
 #define HSW_TVIDEO_DIP_GCP(trans) \
-	_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
+	_TRANSCODER2(trans, _HSW_VIDEO_DIP_GCP_A)
 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
-	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
+	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
 
-#define HSW_STEREO_3D_CTL_A	0x70020
+#define _HSW_STEREO_3D_CTL_A	0x70020
 #define   S3D_ENABLE		(1<<31)
-#define HSW_STEREO_3D_CTL_B	0x71020
+#define _HSW_STEREO_3D_CTL_B	0x71020
 
 #define HSW_STEREO_3D_CTL(trans) \
-	_PIPE2(trans, HSW_STEREO_3D_CTL_A)
+	_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
 
 #define _PCH_TRANS_HTOTAL_B          0xe1000
 #define _PCH_TRANS_HBLANK_B          0xe1004
@@ -6475,27 +6475,27 @@ enum skl_disp_power_wells {
 #define  LVDS_DETECTED	(1 << 1)
 
 /* vlv has 2 sets of panel control regs. */
-#define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
-#define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
-#define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
+#define _PIPEA_PP_STATUS	(VLV_DISPLAY_BASE + 0x61200)
+#define _PIPEA_PP_CONTROL	(VLV_DISPLAY_BASE + 0x61204)
+#define _PIPEA_PP_ON_DELAYS	(VLV_DISPLAY_BASE + 0x61208)
 #define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
-#define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
-#define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
+#define _PIPEA_PP_OFF_DELAYS	(VLV_DISPLAY_BASE + 0x6120c)
+#define _PIPEA_PP_DIVISOR	(VLV_DISPLAY_BASE + 0x61210)
 
-#define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
-#define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
-#define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
-#define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
-#define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
+#define _PIPEB_PP_STATUS	(VLV_DISPLAY_BASE + 0x61300)
+#define _PIPEB_PP_CONTROL	(VLV_DISPLAY_BASE + 0x61304)
+#define _PIPEB_PP_ON_DELAYS	(VLV_DISPLAY_BASE + 0x61308)
+#define _PIPEB_PP_OFF_DELAYS	(VLV_DISPLAY_BASE + 0x6130c)
+#define _PIPEB_PP_DIVISOR	(VLV_DISPLAY_BASE + 0x61310)
 
-#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
-#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
-		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+		_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
-		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+		_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
 #define VLV_PIPE_PP_DIVISOR(pipe) \
-		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+		_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
 
 #define PCH_PP_STATUS		0xc7200
 #define PCH_PP_CONTROL		0xc7204
@@ -6580,10 +6580,10 @@ enum skl_disp_power_wells {
 #define  SDVO_PORT_TO_PIPE_CHV(val)	(((val) & (3<<24)) >> 24)
 #define  DP_PORT_TO_PIPE_CHV(val)	(((val) & (3<<16)) >> 16)
 
-#define TRANS_DP_CTL_A		0xe0300
-#define TRANS_DP_CTL_B		0xe1300
-#define TRANS_DP_CTL_C		0xe2300
-#define TRANS_DP_CTL(pipe)	_PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
+#define _TRANS_DP_CTL_A		0xe0300
+#define _TRANS_DP_CTL_B		0xe1300
+#define _TRANS_DP_CTL_C		0xe2300
+#define TRANS_DP_CTL(pipe)	_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
 #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
 #define  TRANS_DP_PORT_SEL_B	(0<<29)
 #define  TRANS_DP_PORT_SEL_C	(1<<29)
@@ -7123,11 +7123,11 @@ enum skl_disp_power_wells {
 #define  SKL_FUSE_PG2_DIST_STATUS              (1<<25)
 
 /* Per-pipe DDI Function Control */
-#define TRANS_DDI_FUNC_CTL_A		0x60400
-#define TRANS_DDI_FUNC_CTL_B		0x61400
-#define TRANS_DDI_FUNC_CTL_C		0x62400
-#define TRANS_DDI_FUNC_CTL_EDP		0x6F400
-#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
+#define _TRANS_DDI_FUNC_CTL_A		0x60400
+#define _TRANS_DDI_FUNC_CTL_B		0x61400
+#define _TRANS_DDI_FUNC_CTL_C		0x62400
+#define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
+#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, _TRANS_DDI_FUNC_CTL_A)
 
 #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
@@ -7157,9 +7157,9 @@ enum skl_disp_power_wells {
 #define  TRANS_DDI_BFI_ENABLE		(1<<4)
 
 /* DisplayPort Transport Control */
-#define DP_TP_CTL_A			0x64040
-#define DP_TP_CTL_B			0x64140
-#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
+#define _DP_TP_CTL_A			0x64040
+#define _DP_TP_CTL_B			0x64140
+#define DP_TP_CTL(port) _PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
 #define  DP_TP_CTL_ENABLE			(1<<31)
 #define  DP_TP_CTL_MODE_SST			(0<<27)
 #define  DP_TP_CTL_MODE_MST			(1<<27)
@@ -7175,9 +7175,9 @@ enum skl_disp_power_wells {
 #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
 
 /* DisplayPort Transport Status */
-#define DP_TP_STATUS_A			0x64044
-#define DP_TP_STATUS_B			0x64144
-#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
+#define _DP_TP_STATUS_A			0x64044
+#define _DP_TP_STATUS_B			0x64144
+#define DP_TP_STATUS(port) _PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
 #define  DP_TP_STATUS_IDLE_DONE			(1<<25)
 #define  DP_TP_STATUS_ACT_SENT			(1<<24)
 #define  DP_TP_STATUS_MODE_STATUS_MST		(1<<23)
@@ -7187,9 +7187,9 @@ enum skl_disp_power_wells {
 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
 
 /* DDI Buffer Control */
-#define DDI_BUF_CTL_A				0x64000
-#define DDI_BUF_CTL_B				0x64100
-#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
+#define _DDI_BUF_CTL_A				0x64000
+#define _DDI_BUF_CTL_B				0x64100
+#define DDI_BUF_CTL(port) _PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1<<31)
 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
 #define  DDI_BUF_EMP_MASK			(0xf<<24)
@@ -7202,10 +7202,10 @@ enum skl_disp_power_wells {
 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
 
 /* DDI Buffer Translations */
-#define DDI_BUF_TRANS_A				0x64E00
-#define DDI_BUF_TRANS_B				0x64E60
-#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8)
-#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4)
+#define _DDI_BUF_TRANS_A		0x64E00
+#define _DDI_BUF_TRANS_B		0x64E60
+#define DDI_BUF_TRANS_LO(port, i)	 (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
+#define DDI_BUF_TRANS_HI(port, i)	 (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
@@ -7260,9 +7260,9 @@ enum skl_disp_power_wells {
 #define  SPLL_PLL_FREQ_MASK		(3<<26)
 
 /* WRPLL */
-#define WRPLL_CTL1			0x46040
-#define WRPLL_CTL2			0x46060
-#define WRPLL_CTL(pll)			_PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)
+#define _WRPLL_CTL1			0x46040
+#define _WRPLL_CTL2			0x46060
+#define WRPLL_CTL(pll)			_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
 #define  WRPLL_PLL_ENABLE		(1<<31)
 #define  WRPLL_PLL_SSC			(1<<28)
 #define  WRPLL_PLL_NON_SSC		(2<<28)
@@ -7279,9 +7279,9 @@ enum skl_disp_power_wells {
 #define  WRPLL_DIVIDER_FB_MASK		(0xff<<16)
 
 /* Port clock selection */
-#define PORT_CLK_SEL_A			0x46100
-#define PORT_CLK_SEL_B			0x46104
-#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
+#define _PORT_CLK_SEL_A			0x46100
+#define _PORT_CLK_SEL_B			0x46104
+#define PORT_CLK_SEL(port) _PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
 #define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
 #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
 #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
@@ -7293,18 +7293,18 @@ enum skl_disp_power_wells {
 #define  PORT_CLK_SEL_MASK		(7<<29)
 
 /* Transcoder clock selection */
-#define TRANS_CLK_SEL_A			0x46140
-#define TRANS_CLK_SEL_B			0x46144
-#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
+#define _TRANS_CLK_SEL_A		0x46140
+#define _TRANS_CLK_SEL_B		0x46144
+#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
 /* For each transcoder, we need to select the corresponding port clock */
 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
 #define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
 
-#define TRANSA_MSA_MISC			0x60410
-#define TRANSB_MSA_MISC			0x61410
-#define TRANSC_MSA_MISC			0x62410
-#define TRANS_EDP_MSA_MISC		0x6f410
-#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
+#define _TRANSA_MSA_MISC		0x60410
+#define _TRANSB_MSA_MISC		0x61410
+#define _TRANSC_MSA_MISC		0x62410
+#define _TRANS_EDP_MSA_MISC		0x6f410
+#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, _TRANSA_MSA_MISC)
 
 #define  TRANS_MSA_SYNC_CLK		(1<<0)
 #define  TRANS_MSA_6_BPC		(0<<5)
@@ -7382,17 +7382,17 @@ enum skl_disp_power_wells {
 #define  DPLL_LOCK(id) (1<<((id)*8))
 
 /* DPLL cfg */
-#define DPLL1_CFGCR1	0x6C040
-#define DPLL2_CFGCR1	0x6C048
-#define DPLL3_CFGCR1	0x6C050
+#define _DPLL1_CFGCR1	0x6C040
+#define _DPLL2_CFGCR1	0x6C048
+#define _DPLL3_CFGCR1	0x6C050
 #define  DPLL_CFGCR1_FREQ_ENABLE	(1<<31)
 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff<<9)
 #define  DPLL_CFGCR1_DCO_FRACTION(x)	((x)<<9)
 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
 
-#define DPLL1_CFGCR2	0x6C044
-#define DPLL2_CFGCR2	0x6C04C
-#define DPLL3_CFGCR2	0x6C054
+#define _DPLL1_CFGCR2	0x6C044
+#define _DPLL2_CFGCR2	0x6C04C
+#define _DPLL3_CFGCR2	0x6C054
 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff<<8)
 #define  DPLL_CFGCR2_QDIV_RATIO(x)	((x)<<8)
 #define  DPLL_CFGCR2_QDIV_MODE(x)	((x)<<7)
@@ -7410,8 +7410,8 @@ enum skl_disp_power_wells {
 #define  DPLL_CFGCR2_PDIV_7 (4<<2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
 
-#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
-#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
+#define DPLL_CFGCR1(id)	_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
+#define DPLL_CFGCR2(id)	_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			0x6d000
@@ -7441,10 +7441,10 @@ enum skl_disp_power_wells {
 #define  D_COMP_COMP_DISABLE		(1<<0)
 
 /* Pipe WM_LINETIME - watermark line time */
-#define PIPE_WM_LINETIME_A		0x45270
-#define PIPE_WM_LINETIME_B		0x45274
-#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
-					   PIPE_WM_LINETIME_B)
+#define _PIPE_WM_LINETIME_A		0x45270
+#define _PIPE_WM_LINETIME_B		0x45274
+#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, _PIPE_WM_LINETIME_A, \
+					   _PIPE_WM_LINETIME_B)
 #define   PIPE_WM_LINETIME_MASK			(0x1ff)
 #define   PIPE_WM_LINETIME_TIME(x)		((x))
 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
-- 
2.4.6

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.

This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.

There are a few uglies left:
- switch statements don't like structs as case values, even if
  you case 'case DEADBEEF.reg:'. Fortunately we don't have too many
  of those so can maybe switch them to use some port enums or such,
  or if all else fails if ladders
- cmd parser is still iffed out. I was just tool lazy to do that
  for an RFC
- the vgpu stuff is ugly cause I didn't spend any time figuring out
  what it really wants to do
- maybe something else I'm overlooking?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/dvo.h                 |    2 +-
 drivers/gpu/drm/i915/i915_cmd_parser.c     |   17 +-
 drivers/gpu/drm/i915/i915_debugfs.c        |    5 +-
 drivers/gpu/drm/i915/i915_drv.h            |   42 +-
 drivers/gpu/drm/i915/i915_gem_context.c    |    4 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |    2 +-
 drivers/gpu/drm/i915/i915_gem_fence.c      |    5 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        |   27 +-
 drivers/gpu/drm/i915/i915_gpu_error.c      |    4 +-
 drivers/gpu/drm/i915/i915_guc_reg.h        |   50 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |    2 +-
 drivers/gpu/drm/i915/i915_irq.c            |   32 +-
 drivers/gpu/drm/i915/i915_reg.h            | 2391 ++++++++++++++--------------
 drivers/gpu/drm/i915/i915_sysfs.c          |    6 +-
 drivers/gpu/drm/i915/i915_trace.h          |    4 +-
 drivers/gpu/drm/i915/i915_vgpu.c           |    6 +-
 drivers/gpu/drm/i915/i915_vgpu.h           |    2 +-
 drivers/gpu/drm/i915/intel_audio.c         |   14 +-
 drivers/gpu/drm/i915/intel_crt.c           |   14 +-
 drivers/gpu/drm/i915/intel_csr.c           |   12 +-
 drivers/gpu/drm/i915/intel_ddi.c           |   28 +-
 drivers/gpu/drm/i915/intel_display.c       |  123 +-
 drivers/gpu/drm/i915/intel_dp.c            |   65 +-
 drivers/gpu/drm/i915/intel_drv.h           |   15 +-
 drivers/gpu/drm/i915/intel_dsi.c           |    9 +-
 drivers/gpu/drm/i915/intel_dvo.c           |   14 +-
 drivers/gpu/drm/i915/intel_fifo_underrun.c |    4 +-
 drivers/gpu/drm/i915/intel_hdmi.c          |   55 +-
 drivers/gpu/drm/i915/intel_i2c.c           |   10 +-
 drivers/gpu/drm/i915/intel_lrc.c           |   44 +-
 drivers/gpu/drm/i915/intel_lrc.h           |   12 -
 drivers/gpu/drm/i915/intel_lvds.c          |    8 +-
 drivers/gpu/drm/i915/intel_pm.c            |    5 +-
 drivers/gpu/drm/i915/intel_psr.c           |    8 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c    |   15 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c          |   15 +-
 drivers/gpu/drm/i915/intel_uncore.c        |   97 +-
 drivers/pci/quirks.c                       |    8 +-
 39 files changed, 1567 insertions(+), 1611 deletions(-)

diff --git a/drivers/gpu/drm/i915/dvo.h b/drivers/gpu/drm/i915/dvo.h
index 3121633..81626cd 100644
--- a/drivers/gpu/drm/i915/dvo.h
+++ b/drivers/gpu/drm/i915/dvo.h
@@ -32,7 +32,7 @@ struct intel_dvo_device {
 	const char *name;
 	int type;
 	/* DVOA/B/C output register */
-	u32 dvo_reg;
+	struct i915_reg dvo_reg;
 	/* GPIO register used for i2c bus to control this device */
 	u32 gpio;
 	int slave_addr;
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 09932ca..9c22f40 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -414,7 +414,7 @@ struct drm_i915_reg_descriptor {
 
 /* Convenience macro for adding 32-bit registers. */
 #define REG32(address, ...)                             \
-	{ .addr = address, __VA_ARGS__ }
+	{ .addr = (address).reg, __VA_ARGS__ }
 
 /*
  * Convenience macro for adding 64-bit registers.
@@ -423,10 +423,12 @@ struct drm_i915_reg_descriptor {
  * access commands only allow 32-bit accesses. Hence, we have to include
  * entries for both halves of the 64-bit registers.
  */
-#define REG64(addr)                                     \
-	REG32(addr), REG32(addr + sizeof(u32))
+#define REG64(address)                                     \
+	{ .addr = (address).reg },			   \
+	{ .addr = (address).reg + sizeof(u32) }
 
 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
+#if 0
 	REG64(GPGPU_THREADS_DISPATCHED),
 	REG64(HS_INVOCATION_COUNT),
 	REG64(DS_INVOCATION_COUNT),
@@ -470,23 +472,30 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 	      .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
                         HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
 	      .value = 0),
+#endif
 };
 
 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
+#if 0
 	REG32(BCS_SWCTRL),
+#endif
 };
 
 static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
+#if 0
 	REG32(FORCEWAKE_MT),
 	REG32(DERRMR),
 	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
 	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
 	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
+#endif
 };
 
 static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
+#if 0
 	REG32(FORCEWAKE_MT),
 	REG32(DERRMR),
+#endif
 };
 
 #undef REG64
@@ -1020,7 +1029,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
 			 * to the register. Hence, limit OACONTROL writes to
 			 * only MI_LOAD_REGISTER_IMM commands.
 			 */
-			if (reg_addr == OACONTROL) {
+			if (reg_addr == OACONTROL.reg) {
 				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
 					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
 					return false;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 38b0e38..94808d4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3096,7 +3096,8 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
 
 	seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
 	for (i = 0; i < dev_priv->workarounds.count; ++i) {
-		u32 addr, mask, value, read;
+		struct i915_reg addr;
+		u32 mask, value, read;
 		bool ok;
 
 		addr = dev_priv->workarounds.reg[i].addr;
@@ -3105,7 +3106,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
 		read = I915_READ(addr);
 		ok = (value & mask) == (read & mask);
 		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
-			   addr, value, mask, read, ok ? "OK" : "FAIL");
+			   addr.reg, value, mask, read, ok ? "OK" : "FAIL");
 	}
 
 	intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4359af1..40d9741 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -698,18 +698,18 @@ struct intel_uncore_funcs {
 	void (*force_wake_put)(struct drm_i915_private *dev_priv,
 							enum forcewake_domains domains);
 
-	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
-	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
-	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
-	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
+	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
+	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
+	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
+	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
 
-	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writeb)(struct drm_i915_private *dev_priv, struct i915_reg r,
 				uint8_t val, bool trace);
-	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writew)(struct drm_i915_private *dev_priv, struct i915_reg r,
 				uint16_t val, bool trace);
-	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writel)(struct drm_i915_private *dev_priv, struct i915_reg r,
 				uint32_t val, bool trace);
-	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
+	void (*mmio_writeq)(struct drm_i915_private *dev_priv, struct i915_reg r,
 				uint64_t val, bool trace);
 };
 
@@ -726,11 +726,11 @@ struct intel_uncore {
 		enum forcewake_domain_id id;
 		unsigned wake_count;
 		struct timer_list timer;
-		u32 reg_set;
+		struct i915_reg reg_set;
 		u32 val_set;
 		u32 val_clear;
-		u32 reg_ack;
-		u32 reg_post;
+		struct i915_reg reg_ack;
+		struct i915_reg reg_post;
 		u32 val_reset;
 	} fw_domain[FW_DOMAIN_ID_COUNT];
 };
@@ -756,7 +756,7 @@ struct intel_csr {
 	uint32_t *dmc_payload;
 	uint32_t dmc_fw_size;
 	uint32_t mmio_count;
-	uint32_t mmioaddr[8];
+	struct i915_reg mmioaddr[8];
 	uint32_t mmiodata[8];
 	enum csr_state state;
 };
@@ -1022,7 +1022,7 @@ struct intel_gmbus {
 	struct i2c_adapter adapter;
 	u32 force_bit;
 	u32 reg0;
-	u32 gpio_reg;
+	struct i915_reg gpio_reg;
 	struct i2c_algo_bit_data bit_algo;
 	struct drm_i915_private *dev_priv;
 };
@@ -1678,7 +1678,7 @@ struct i915_frontbuffer_tracking {
 };
 
 struct i915_wa_reg {
-	u32 addr;
+	struct i915_reg addr;
 	u32 value;
 	/* bitmask representing WA bits */
 	u32 mask;
@@ -3426,8 +3426,8 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
  * Note: Should only be used between intel_uncore_forcewake_irqlock() and
  * intel_uncore_forcewake_irqunlock().
  */
-#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
-#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
+#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__).reg)
+#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__).reg)
 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
 
 /* "Broadcast RGB" property */
@@ -3435,7 +3435,7 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 #define INTEL_BROADCAST_RGB_FULL 1
 #define INTEL_BROADCAST_RGB_LIMITED 2
 
-static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
+static inline struct i915_reg i915_vgacntrl_reg(struct drm_device *dev)
 {
 	if (IS_VALLEYVIEW(dev))
 		return VLV_VGACNTRL;
@@ -3506,16 +3506,16 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
 
 #define __raw_read(x, s) \
 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
-					     uint32_t reg) \
+					     struct i915_reg reg) \
 { \
-	return read##s(dev_priv->regs + reg); \
+	return read##s(dev_priv->regs + reg.reg); \
 }
 
 #define __raw_write(x, s) \
 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
-				       uint32_t reg, uint##x##_t val) \
+				       struct i915_reg reg, uint##x##_t val) \
 { \
-	write##s(val, dev_priv->regs + reg); \
+	write##s(val, dev_priv->regs + reg.reg); \
 }
 __raw_read(8, b)
 __raw_read(16, w)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 74aa0c9..5799c3a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -532,7 +532,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
 				if (signaller == ring)
 					continue;
 
-				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
+				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base).reg);
 				intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
 			}
 		}
@@ -557,7 +557,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
 				if (signaller == ring)
 					continue;
 
-				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
+				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base).reg);
 				intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
 			}
 		}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 67ef118..5c4908a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1305,7 +1305,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
 
 		intel_ring_emit(ring, MI_NOOP);
 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-		intel_ring_emit(ring, INSTPM);
+		intel_ring_emit(ring, INSTPM.reg);
 		intel_ring_emit(ring, instp_mask << 16 | instp_mode);
 		intel_ring_advance(ring);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index ff94560..bdb9bfe 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -59,7 +59,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int fence_reg_lo, fence_reg_hi;
+	struct i915_reg fence_reg_lo, fence_reg_hi;
 	int fence_pitch_shift;
 
 	if (INTEL_INFO(dev)->gen >= 6) {
@@ -118,7 +118,8 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 fence_reg, val;
+	struct i915_reg fence_reg;
+	u32 val;
 
 	if (obj) {
 		u32 size = i915_gem_obj_ggtt_size(obj);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2b6dd70..abe9250 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -661,10 +661,10 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
 		return ret;
 
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
+	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry).reg);
 	intel_ring_emit(ring, upper_32_bits(addr));
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
+	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry).reg);
 	intel_ring_emit(ring, lower_32_bits(addr));
 	intel_ring_advance(ring);
 
@@ -904,25 +904,26 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
 	enum vgt_g2v_type msg;
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned int offset = vgtif_reg(pdp0_lo);
 	int i;
 
 	if (USES_FULL_48BIT_PPGTT(dev)) {
 		u64 daddr = px_dma(&ppgtt->pml4);
+		struct i915_reg offset_lo = vgtif_reg(pdp0_lo);
+		struct i915_reg offset_hi = vgtif_reg(pdp0_lo + 4);
 
-		I915_WRITE(offset, lower_32_bits(daddr));
-		I915_WRITE(offset + 4, upper_32_bits(daddr));
+		I915_WRITE(offset_lo, lower_32_bits(daddr));
+		I915_WRITE(offset_hi, upper_32_bits(daddr));
 
 		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 	} else {
 		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 			u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
+			struct i915_reg offset_lo = vgtif_reg(pdp0_lo + i * 8);
+			struct i915_reg offset_hi = vgtif_reg(pdp0_lo + i * 8 + 4);
 
-			I915_WRITE(offset, lower_32_bits(daddr));
-			I915_WRITE(offset + 4, upper_32_bits(daddr));
-
-			offset += 8;
+			I915_WRITE(offset_lo, lower_32_bits(daddr));
+			I915_WRITE(offset_hi, upper_32_bits(daddr));
 		}
 
 		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
@@ -1662,9 +1663,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 		return ret;
 
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
-	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
+	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring).reg);
 	intel_ring_emit(ring, PP_DIR_DCLV_2G);
-	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
+	intel_ring_emit(ring, RING_PP_DIR_BASE(ring).reg);
 	intel_ring_emit(ring, get_pd_offset(ppgtt));
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
@@ -1699,9 +1700,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 		return ret;
 
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
-	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
+	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring).reg);
 	intel_ring_emit(ring, PP_DIR_DCLV_2G);
-	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
+	intel_ring_emit(ring, RING_PP_DIR_BASE(ring).reg);
 	intel_ring_emit(ring, get_pd_offset(ppgtt));
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index e873eb4..33bd507 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -858,7 +858,7 @@ static void i915_record_ring_state(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (INTEL_INFO(dev)->gen >= 6) {
-		ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
+		ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
 		ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
 		if (INTEL_INFO(dev)->gen >= 8)
 			gen8_record_semaphore_state(dev_priv, error, ring, ering);
@@ -895,7 +895,7 @@ static void i915_record_ring_state(struct drm_device *dev,
 	ering->ctl = I915_READ_CTL(ring);
 
 	if (I915_NEED_GFX_HWS(dev)) {
-		int mmio;
+		struct i915_reg mmio;
 
 		if (IS_GEN7(dev)) {
 			switch (ring->id) {
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 848a563..334f58c 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -26,7 +26,7 @@
 
 /* Definitions of GuC H/W registers, bits, etc */
 
-#define GUC_STATUS			0xc000
+#define GUC_STATUS			_REG(0xc000)
 #define   GS_BOOTROM_SHIFT		1
 #define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
 #define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
@@ -38,39 +38,39 @@
 #define   GS_MIA_SHIFT			16
 #define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
 
-#define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
+#define SOFT_SCRATCH(n)			_REG(0xc180 + (n) * 4)
 
-#define UOS_RSA_SCRATCH(i)		(0xc200 + (i) * 4)
-#define DMA_ADDR_0_LOW			0xc300
-#define DMA_ADDR_0_HIGH			0xc304
-#define DMA_ADDR_1_LOW			0xc308
-#define DMA_ADDR_1_HIGH			0xc30c
+#define UOS_RSA_SCRATCH(i)		_REG(0xc200 + (i) * 4)
+#define DMA_ADDR_0_LOW			_REG(0xc300)
+#define DMA_ADDR_0_HIGH			_REG(0xc304)
+#define DMA_ADDR_1_LOW			_REG(0xc308)
+#define DMA_ADDR_1_HIGH			_REG(0xc30c)
 #define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
 #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
-#define DMA_COPY_SIZE			0xc310
-#define DMA_CTRL			0xc314
+#define DMA_COPY_SIZE			_REG(0xc310)
+#define DMA_CTRL			_REG(0xc314)
 #define   UOS_MOVE			  (1<<4)
 #define   START_DMA			  (1<<0)
-#define DMA_GUC_WOPCM_OFFSET		0xc340
+#define DMA_GUC_WOPCM_OFFSET		_REG(0xc340)
 #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
 
-#define GUC_WOPCM_SIZE			0xc050
+#define GUC_WOPCM_SIZE			_REG(0xc050)
 #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
 
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
 #define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
 
-#define GEN8_GT_PM_CONFIG		0x138140
-#define GEN9LP_GT_PM_CONFIG		0x138140
-#define GEN9_GT_PM_CONFIG		0x13816c
+#define GEN8_GT_PM_CONFIG		_REG(0x138140)
+#define GEN9LP_GT_PM_CONFIG		_REG(0x138140)
+#define GEN9_GT_PM_CONFIG		_REG(0x13816c)
 #define   GT_DOORBELL_ENABLE		  (1<<0)
 
-#define GEN8_GTCR			0x4274
+#define GEN8_GTCR			_REG(0x4274)
 #define   GEN8_GTCR_INVALIDATE		  (1<<0)
 
-#define GUC_ARAT_C6DIS			0xA178
+#define GUC_ARAT_C6DIS			_REG(0xA178)
 
-#define GUC_SHIM_CONTROL		0xc064
+#define GUC_SHIM_CONTROL		_REG(0xc064)
 #define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
 #define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
 #define   GUC_ENABLE_MIA_CACHING		(1<<2)
@@ -87,21 +87,21 @@
 				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \
 				 GUC_ENABLE_MIA_CLOCK_GATING)
 
-#define HOST2GUC_INTERRUPT		0xc4c8
+#define HOST2GUC_INTERRUPT		_REG(0xc4c8)
 #define   HOST2GUC_TRIGGER		  (1<<0)
 
 #define DRBMISC1			0x1984
 #define   DOORBELL_ENABLE		  (1<<0)
 
-#define GEN8_DRBREGL(x)			(0x1000 + (x) * 8)
+#define GEN8_DRBREGL(x)			_REG(0x1000 + (x) * 8)
 #define   GEN8_DRB_VALID		  (1<<0)
-#define GEN8_DRBREGU(x)			(GEN8_DRBREGL(x) + 4)
+#define GEN8_DRBREGU(x)			_REG(0x1000 + (x) * 8 + 4)
 
-#define DE_GUCRMR			0x44054
+#define DE_GUCRMR			_REG(0x44054)
 
-#define GUC_BCS_RCS_IER			0xC550
-#define GUC_VCS2_VCS1_IER		0xC554
-#define GUC_WD_VECS_IER			0xC558
-#define GUC_PM_P24C_IER			0xC55C
+#define GUC_BCS_RCS_IER			_REG(0xC550)
+#define GUC_VCS2_VCS1_IER		_REG(0xC554)
+#define GUC_WD_VECS_IER			_REG(0xC558)
+#define GUC_PM_P24C_IER			_REG(0xC55C)
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 792d0b9..336a1e70 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -249,7 +249,7 @@ static void guc_disable_doorbell(struct intel_guc *guc,
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct guc_doorbell_info *doorbell;
 	void *base;
-	int drbreg = GEN8_DRBREGL(client->doorbell_id);
+	struct i915_reg drbreg = GEN8_DRBREGL(client->doorbell_id);
 	int value;
 
 	base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a6c23b2..61d2c73 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -139,7 +139,8 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
-static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
+static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
+				    struct i915_reg reg)
 {
 	u32 val = I915_READ(reg);
 
@@ -147,7 +148,7 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
 		return;
 
 	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
-	     reg, val);
+	     reg.reg, val);
 	I915_WRITE(reg, 0xffffffff);
 	POSTING_READ(reg);
 	I915_WRITE(reg, 0xffffffff);
@@ -245,17 +246,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 	ilk_update_gt_irq(dev_priv, mask, 0);
 }
 
-static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
+static struct i915_reg gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
 	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
 
-static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
+static struct i915_reg gen6_pm_imr(struct drm_i915_private *dev_priv)
 {
 	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 }
 
-static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
+static struct i915_reg gen6_pm_ier(struct drm_i915_private *dev_priv)
 {
 	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 }
@@ -312,7 +313,7 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 void gen6_reset_rps_interrupts(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t reg = gen6_pm_iir(dev_priv);
+	struct i915_reg reg = gen6_pm_iir(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
 	I915_WRITE(reg, dev_priv->pm_rps_events);
@@ -439,7 +440,7 @@ static void
 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 		       u32 enable_mask, u32 status_mask)
 {
-	u32 reg = PIPESTAT(pipe);
+	struct i915_reg reg = PIPESTAT(pipe);
 	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 
 	assert_spin_locked(&dev_priv->irq_lock);
@@ -466,7 +467,7 @@ static void
 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 		        u32 enable_mask, u32 status_mask)
 {
-	u32 reg = PIPESTAT(pipe);
+	struct i915_reg reg = PIPESTAT(pipe);
 	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 
 	assert_spin_locked(&dev_priv->irq_lock);
@@ -626,8 +627,7 @@ static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long high_frame;
-	unsigned long low_frame;
+	struct i915_reg high_frame, low_frame;
 	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
@@ -1118,7 +1118,7 @@ static void ivybridge_parity_work(struct work_struct *work)
 	POSTING_READ(GEN7_MISCCPCTL);
 
 	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
-		u32 reg;
+		struct i915_reg reg;
 
 		slice--;
 		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
@@ -1126,7 +1126,7 @@ static void ivybridge_parity_work(struct work_struct *work)
 
 		dev_priv->l3_parity.which_slice &= ~(1<<slice);
 
-		reg = GEN7_L3CDERRST1 + (slice * 0x200);
+		reg = GEN7_L3CDERRST1(slice);
 
 		error_status = I915_READ(reg);
 		row = GEN7_PARITY_ERROR_ROW(error_status);
@@ -1555,7 +1555,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
 
 	spin_lock(&dev_priv->irq_lock);
 	for_each_pipe(dev_priv, pipe) {
-		int reg;
+		struct i915_reg reg;
 		u32 mask, iir_bit = 0;
 
 		/*
@@ -3778,7 +3778,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 
 		for_each_pipe(dev_priv, pipe) {
-			int reg = PIPESTAT(pipe);
+			struct i915_reg reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 
 			/*
@@ -3959,7 +3959,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 
 		for_each_pipe(dev_priv, pipe) {
-			int reg = PIPESTAT(pipe);
+			struct i915_reg reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 
 			/* Clear the PIPE*STAT regs before the IIR */
@@ -4180,7 +4180,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 
 		for_each_pipe(dev_priv, pipe) {
-			int reg = PIPESTAT(pipe);
+			struct i915_reg reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 
 			/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 140076d..0589aba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,16 +25,28 @@
 #ifndef _I915_REG_H_
 #define _I915_REG_H_
 
+struct i915_reg {
+	uint32_t reg;
+};
+
+#define _REG(r) ((const struct i915_reg){ .reg = (r) })
+
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _REG_PIPE(pipe, a, b) _REG(_PIPE(pipe, a, b))
 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
-#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
+#define _REG_PLANE(plane, a, b) _REG_PIPE(plane, a, b)
+#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
+#define _REG_TRANS(tran, a, b) _REG(_TRANS(tran, a, b))
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
+#define _REG_PORT(port, a, b) _REG(_PORT(port, a, b))
 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
 			       (pipe) == PIPE_B ? (b) : (c))
+#define _REG_PIPE3(pipe, a, b, c) _REG(_PIPE3(pipe, a, b, c))
 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
 			       (port) == PORT_B ? (b) : (c))
+#define _REG_PORT3(pipe, a, b, c) _REG(_PORT3(pipe, a, b, c))
 
-#define _MASKED_FIELD(mask, value) ({					   \
+#define _MASKED_FIELD(mask, value) ({					\
 	if (__builtin_constant_p(mask))					   \
 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
 	if (__builtin_constant_p(value))				   \
@@ -105,14 +117,14 @@
 #define  GRDOM_RESET_STATUS (1<<1)
 #define  GRDOM_RESET_ENABLE (1<<0)
 
-#define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
+#define ILK_GDSR _REG(MCHBAR_MIRROR_BASE + 0x2ca4)
 #define  ILK_GRDOM_FULL		(0<<1)
 #define  ILK_GRDOM_RENDER	(1<<1)
 #define  ILK_GRDOM_MEDIA	(3<<1)
 #define  ILK_GRDOM_MASK		(3<<1)
 #define  ILK_GRDOM_RESET_ENABLE (1<<0)
 
-#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
+#define GEN6_MBCUNIT_SNPCR	_REG(0x900c) /* for LLC config */
 #define   GEN6_MBC_SNPCR_SHIFT	21
 #define   GEN6_MBC_SNPCR_MASK	(3<<21)
 #define   GEN6_MBC_SNPCR_MAX	(0<<21)
@@ -120,31 +132,31 @@
 #define   GEN6_MBC_SNPCR_LOW	(2<<21)
 #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
 
-#define VLV_G3DCTL		0x9024
-#define VLV_GSCKGCTL		0x9028
+#define VLV_G3DCTL		_REG(0x9024)
+#define VLV_GSCKGCTL		_REG(0x9028)
 
-#define GEN6_MBCTL		0x0907c
+#define GEN6_MBCTL		_REG(0x0907c)
 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
 
-#define GEN6_GDRST	0x941c
+#define GEN6_GDRST	_REG(0x941c)
 #define  GEN6_GRDOM_FULL		(1 << 0)
 #define  GEN6_GRDOM_RENDER		(1 << 1)
 #define  GEN6_GRDOM_MEDIA		(1 << 2)
 #define  GEN6_GRDOM_BLT			(1 << 3)
 
-#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
-#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
-#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
+#define RING_PP_DIR_BASE(ring)		_REG((ring)->mmio_base+0x228)
+#define RING_PP_DIR_BASE_READ(ring)	_REG((ring)->mmio_base+0x518)
+#define RING_PP_DIR_DCLV(ring)		_REG((ring)->mmio_base+0x220)
 #define   PP_DIR_DCLV_2G		0xffffffff
 
-#define GEN8_RING_PDP_UDW(ring, n)	((ring)->mmio_base+0x270 + ((n) * 8 + 4))
-#define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)
+#define GEN8_RING_PDP_UDW(ring, n)	_REG((ring)->mmio_base+0x270 + (n) * 8 + 4)
+#define GEN8_RING_PDP_LDW(ring, n)	_REG((ring)->mmio_base+0x270 + (n) * 8)
 
-#define GEN8_R_PWR_CLK_STATE		0x20C8
+#define GEN8_R_PWR_CLK_STATE		_REG(0x20C8)
 #define   GEN8_RPCS_ENABLE		(1 << 31)
 #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
 #define   GEN8_RPCS_S_CNT_SHIFT		15
@@ -157,7 +169,7 @@
 #define   GEN8_RPCS_EU_MIN_SHIFT	0
 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
 
-#define GAM_ECOCHK			0x4090
+#define GAM_ECOCHK			_REG(0x4090)
 #define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
 #define   ECOCHK_SNB_BIT		(1<<10)
 #define   ECOCHK_DIS_TLB		(1<<8)
@@ -170,15 +182,15 @@
 #define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
 #define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
 
-#define GAC_ECO_BITS			0x14090
+#define GAC_ECO_BITS			_REG(0x14090)
 #define   ECOBITS_SNB_BIT		(1<<13)
 #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
 #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
 
-#define GAB_CTL				0x24000
+#define GAB_CTL				_REG(0x24000)
 #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
 
-#define GEN6_STOLEN_RESERVED		0x1082C0
+#define GEN6_STOLEN_RESERVED		_REG(0x1082C0)
 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
 #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
@@ -200,6 +212,7 @@
 #define VGA_ST01_MDA 0x3ba
 #define VGA_ST01_CGA 0x3da
 
+#define _VGA_MSR_WRITE _REG(0x3c2)
 #define VGA_MSR_WRITE 0x3c2
 #define VGA_MSR_READ 0x3cc
 #define   VGA_MSR_MEM_EN (1<<1)
@@ -377,10 +390,10 @@
 #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
 #define   MI_BATCH_RESOURCE_STREAMER (1<<10)
 
-#define MI_PREDICATE_SRC0	(0x2400)
-#define MI_PREDICATE_SRC1	(0x2408)
+#define MI_PREDICATE_SRC0	_REG(0x2400)
+#define MI_PREDICATE_SRC1	_REG(0x2408)
 
-#define MI_PREDICATE_RESULT_2	(0x2214)
+#define MI_PREDICATE_RESULT_2	_REG(0x2214)
 #define  LOWER_SLICE_ENABLED	(1<<0)
 #define  LOWER_SLICE_DISABLED	(0<<0)
 
@@ -509,45 +522,43 @@
 /*
  * Registers used only by the command parser
  */
-#define BCS_SWCTRL 0x22200
-
-#define GPGPU_THREADS_DISPATCHED        0x2290
-#define HS_INVOCATION_COUNT             0x2300
-#define DS_INVOCATION_COUNT             0x2308
-#define IA_VERTICES_COUNT               0x2310
-#define IA_PRIMITIVES_COUNT             0x2318
-#define VS_INVOCATION_COUNT             0x2320
-#define GS_INVOCATION_COUNT             0x2328
-#define GS_PRIMITIVES_COUNT             0x2330
-#define CL_INVOCATION_COUNT             0x2338
-#define CL_PRIMITIVES_COUNT             0x2340
-#define PS_INVOCATION_COUNT             0x2348
-#define PS_DEPTH_COUNT                  0x2350
+#define BCS_SWCTRL _REG(0x22200)
+
+#define GPGPU_THREADS_DISPATCHED        _REG(0x2290)
+#define HS_INVOCATION_COUNT             _REG(0x2300)
+#define DS_INVOCATION_COUNT             _REG(0x2308)
+#define IA_VERTICES_COUNT               _REG(0x2310)
+#define IA_PRIMITIVES_COUNT             _REG(0x2318)
+#define VS_INVOCATION_COUNT             _REG(0x2320)
+#define GS_INVOCATION_COUNT             _REG(0x2328)
+#define GS_PRIMITIVES_COUNT             _REG(0x2330)
+#define CL_INVOCATION_COUNT             _REG(0x2338)
+#define CL_PRIMITIVES_COUNT             _REG(0x2340)
+#define PS_INVOCATION_COUNT             _REG(0x2348)
+#define PS_DEPTH_COUNT                  _REG(0x2350)
 
 /* There are the 4 64-bit counter registers, one for each stream output */
-#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
+#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _REG(0x5200 + (n) * 8)
 
-#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
+#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  _REG(0x5240 + (n) * 8)
 
-#define GEN7_3DPRIM_END_OFFSET          0x2420
-#define GEN7_3DPRIM_START_VERTEX        0x2430
-#define GEN7_3DPRIM_VERTEX_COUNT        0x2434
-#define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
-#define GEN7_3DPRIM_START_INSTANCE      0x243C
-#define GEN7_3DPRIM_BASE_VERTEX         0x2440
+#define GEN7_3DPRIM_END_OFFSET          _REG(0x2420)
+#define GEN7_3DPRIM_START_VERTEX        _REG(0x2430)
+#define GEN7_3DPRIM_VERTEX_COUNT        _REG(0x2434)
+#define GEN7_3DPRIM_INSTANCE_COUNT      _REG(0x2438)
+#define GEN7_3DPRIM_START_INSTANCE      _REG(0x243C)
+#define GEN7_3DPRIM_BASE_VERTEX         _REG(0x2440)
 
-#define OACONTROL 0x2360
+#define OACONTROL _REG(0x2360)
 
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
-#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
-					 _GEN7_PIPEA_DE_LOAD_SL, \
-					 _GEN7_PIPEB_DE_LOAD_SL)
+#define GEN7_PIPE_DE_LOAD_SL(pipe) _REG_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL))
 
 /*
  * Reset registers
  */
-#define DEBUG_RESET_I830		0x6070
+#define DEBUG_RESET_I830		_REG(0x6070)
 #define  DEBUG_RESET_FULL		(1<<7)
 #define  DEBUG_RESET_RENDER		(1<<8)
 #define  DEBUG_RESET_DISPLAY		(1<<9)
@@ -555,7 +566,7 @@
 /*
  * IOSF sideband
  */
-#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
+#define VLV_IOSF_DOORBELL_REQ			_REG(VLV_DISPLAY_BASE + 0x2100)
 #define   IOSF_DEVFN_SHIFT			24
 #define   IOSF_OPCODE_SHIFT			16
 #define   IOSF_PORT_SHIFT			8
@@ -572,8 +583,8 @@
 #define   IOSF_PORT_CCU				0xA9
 #define   IOSF_PORT_GPS_CORE			0x48
 #define   IOSF_PORT_FLISDSI			0x1B
-#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
-#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
+#define VLV_IOSF_DATA				_REG(VLV_DISPLAY_BASE + 0x2104)
+#define VLV_IOSF_ADDR				_REG(VLV_DISPLAY_BASE + 0x2108)
 
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC				0x11
@@ -827,7 +838,7 @@ enum skl_disp_power_wells {
  */
 #define DPIO_DEVFN			0
 
-#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
+#define DPIO_CTL			_REG(VLV_DISPLAY_BASE + 0x2110)
 #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
 #define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
 #define  DPIO_SFR_BYPASS		(1<<1)
@@ -1180,9 +1191,9 @@ enum skl_disp_power_wells {
 #define   DPIO_UPAR_SHIFT		30
 
 /* BXT PHY registers */
-#define _BXT_PHY(phy, a, b)		_PIPE((phy), (a), (b))
+#define _BXT_PHY(phy, a, b)		_REG_PIPE((phy), (a), (b))
 
-#define BXT_P_CR_GT_DISP_PWRON		0x138090
+#define BXT_P_CR_GT_DISP_PWRON		_REG(0x138090)
 #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
 
 #define _PHY_CTL_FAMILY_EDP		0x64C80
@@ -1198,7 +1209,7 @@ enum skl_disp_power_wells {
 #define   PORT_PLL_ENABLE		(1 << 31)
 #define   PORT_PLL_LOCK			(1 << 30)
 #define   PORT_PLL_REF_SEL		(1 << 27)
-#define BXT_PORT_PLL_ENABLE(port)	_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
+#define BXT_PORT_PLL_ENABLE(port)	_REG_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
 
 #define _PORT_PLL_EBB_0_A		0x162034
 #define _PORT_PLL_EBB_0_B		0x6C034
@@ -1209,7 +1220,7 @@ enum skl_disp_power_wells {
 #define   PORT_PLL_P2_SHIFT		8
 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
 #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
-#define BXT_PORT_PLL_EBB_0(port)	_PORT3(port, _PORT_PLL_EBB_0_A, \
+#define BXT_PORT_PLL_EBB_0(port)	_REG_PORT3(port, _PORT_PLL_EBB_0_A, \
 						_PORT_PLL_EBB_0_B,	\
 						_PORT_PLL_EBB_0_C)
 
@@ -1218,7 +1229,7 @@ enum skl_disp_power_wells {
 #define _PORT_PLL_EBB_4_C		0x6C344
 #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
 #define   PORT_PLL_RECALIBRATE		(1 << 14)
-#define BXT_PORT_PLL_EBB_4(port)	_PORT3(port, _PORT_PLL_EBB_4_A, \
+#define BXT_PORT_PLL_EBB_4(port)	_REG_PORT3(port, _PORT_PLL_EBB_4_A, \
 						_PORT_PLL_EBB_4_B,	\
 						_PORT_PLL_EBB_4_C)
 
@@ -1254,7 +1265,7 @@ enum skl_disp_power_wells {
 #define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
 						_PORT_PLL_0_B,		\
 						_PORT_PLL_0_C)
-#define BXT_PORT_PLL(port, idx)		(_PORT_PLL_BASE(port) + (idx) * 4)
+#define BXT_PORT_PLL(port, idx)		_REG(_PORT_PLL_BASE(port) + (idx) * 4)
 
 /* BXT PHY common lane registers */
 #define _PORT_CL1CM_DW0_A		0x162000
@@ -1292,7 +1303,7 @@ enum skl_disp_power_wells {
 							_PORT_CL1CM_DW30_A)
 
 /* Defined for PHY0 only */
-#define BXT_PORT_CL2CM_DW6_BC		0x6C358
+#define BXT_PORT_CL2CM_DW6_BC		_REG(0x6C358)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
 /* BXT PHY Ref registers */
@@ -1332,10 +1343,10 @@ enum skl_disp_power_wells {
 #define _PORT_PCS_DW10_GRP_A		0x162C28
 #define _PORT_PCS_DW10_GRP_B		0x6CC28
 #define _PORT_PCS_DW10_GRP_C		0x6CE28
-#define BXT_PORT_PCS_DW10_LN01(port)	_PORT3(port, _PORT_PCS_DW10_LN01_A, \
+#define BXT_PORT_PCS_DW10_LN01(port)	_REG_PORT3(port, _PORT_PCS_DW10_LN01_A, \
 						     _PORT_PCS_DW10_LN01_B, \
 						     _PORT_PCS_DW10_LN01_C)
-#define BXT_PORT_PCS_DW10_GRP(port)	_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
+#define BXT_PORT_PCS_DW10_GRP(port)	_REG_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
 						     _PORT_PCS_DW10_GRP_B,  \
 						     _PORT_PCS_DW10_GRP_C)
 #define   TX2_SWING_CALC_INIT		(1 << 31)
@@ -1352,13 +1363,13 @@ enum skl_disp_power_wells {
 #define _PORT_PCS_DW12_GRP_C		0x6CE30
 #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
 #define   LANE_STAGGER_MASK		0x1F
-#define BXT_PORT_PCS_DW12_LN01(port)	_PORT3(port, _PORT_PCS_DW12_LN01_A, \
+#define BXT_PORT_PCS_DW12_LN01(port)	_REG_PORT3(port, _PORT_PCS_DW12_LN01_A, \
 						     _PORT_PCS_DW12_LN01_B, \
 						     _PORT_PCS_DW12_LN01_C)
-#define BXT_PORT_PCS_DW12_LN23(port)	_PORT3(port, _PORT_PCS_DW12_LN23_A, \
+#define BXT_PORT_PCS_DW12_LN23(port)	_REG_PORT3(port, _PORT_PCS_DW12_LN23_A, \
 						     _PORT_PCS_DW12_LN23_B, \
 						     _PORT_PCS_DW12_LN23_C)
-#define BXT_PORT_PCS_DW12_GRP(port)	_PORT3(port, _PORT_PCS_DW12_GRP_A, \
+#define BXT_PORT_PCS_DW12_GRP(port)	_REG_PORT3(port, _PORT_PCS_DW12_GRP_A, \
 						     _PORT_PCS_DW12_GRP_B, \
 						     _PORT_PCS_DW12_GRP_C)
 
@@ -1372,10 +1383,10 @@ enum skl_disp_power_wells {
 #define _PORT_TX_DW2_GRP_A		0x162D08
 #define _PORT_TX_DW2_GRP_B		0x6CD08
 #define _PORT_TX_DW2_GRP_C		0x6CF08
-#define BXT_PORT_TX_DW2_GRP(port)	_PORT3(port, _PORT_TX_DW2_GRP_A,  \
+#define BXT_PORT_TX_DW2_GRP(port)	_REG_PORT3(port, _PORT_TX_DW2_GRP_A,  \
 						     _PORT_TX_DW2_GRP_B,  \
 						     _PORT_TX_DW2_GRP_C)
-#define BXT_PORT_TX_DW2_LN0(port)	_PORT3(port, _PORT_TX_DW2_LN0_A,  \
+#define BXT_PORT_TX_DW2_LN0(port)	_REG_PORT3(port, _PORT_TX_DW2_LN0_A,  \
 						     _PORT_TX_DW2_LN0_B,  \
 						     _PORT_TX_DW2_LN0_C)
 #define   MARGIN_000_SHIFT		16
@@ -1389,10 +1400,10 @@ enum skl_disp_power_wells {
 #define _PORT_TX_DW3_GRP_A		0x162D0C
 #define _PORT_TX_DW3_GRP_B		0x6CD0C
 #define _PORT_TX_DW3_GRP_C		0x6CF0C
-#define BXT_PORT_TX_DW3_GRP(port)	_PORT3(port, _PORT_TX_DW3_GRP_A,  \
+#define BXT_PORT_TX_DW3_GRP(port)	_REG_PORT3(port, _PORT_TX_DW3_GRP_A,  \
 						     _PORT_TX_DW3_GRP_B,  \
 						     _PORT_TX_DW3_GRP_C)
-#define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
+#define BXT_PORT_TX_DW3_LN0(port)	_REG_PORT3(port, _PORT_TX_DW3_LN0_A,  \
 						     _PORT_TX_DW3_LN0_B,  \
 						     _PORT_TX_DW3_LN0_C)
 #define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
@@ -1403,10 +1414,10 @@ enum skl_disp_power_wells {
 #define _PORT_TX_DW4_GRP_A		0x162D10
 #define _PORT_TX_DW4_GRP_B		0x6CD10
 #define _PORT_TX_DW4_GRP_C		0x6CF10
-#define BXT_PORT_TX_DW4_LN0(port)	_PORT3(port, _PORT_TX_DW4_LN0_A,  \
+#define BXT_PORT_TX_DW4_LN0(port)	_REG_PORT3(port, _PORT_TX_DW4_LN0_A,  \
 						     _PORT_TX_DW4_LN0_B,  \
 						     _PORT_TX_DW4_LN0_C)
-#define BXT_PORT_TX_DW4_GRP(port)	_PORT3(port, _PORT_TX_DW4_GRP_A,  \
+#define BXT_PORT_TX_DW4_GRP(port)	_REG_PORT3(port, _PORT_TX_DW4_GRP_A,  \
 						     _PORT_TX_DW4_GRP_B,  \
 						     _PORT_TX_DW4_GRP_C)
 #define   DEEMPH_SHIFT			24
@@ -1417,17 +1428,17 @@ enum skl_disp_power_wells {
 #define _PORT_TX_DW14_LN0_C		0x6C938
 #define   LATENCY_OPTIM_SHIFT		30
 #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
-#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
+#define BXT_PORT_TX_DW14_LN(port, lane)	_REG(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
 							_PORT_TX_DW14_LN0_B,   \
 							_PORT_TX_DW14_LN0_C) + \
 					 _BXT_LANE_OFFSET(lane))
 
 /* UAIMI scratch pad register 1 */
-#define UAIMI_SPR1			0x4F074
+#define UAIMI_SPR1			_REG(0x4F074)
 /* SKL VccIO mask */
 #define SKL_VCCIO_MASK			0x1
 /* SKL balance leg register */
-#define DISPIO_CR_TX_BMU_CR0		0x6C00C
+#define DISPIO_CR_TX_BMU_CR0		_REG(0x6C00C)
 /* I_boost values */
 #define BALANCE_LEG_SHIFT(port)		(8+3*(port))
 #define BALANCE_LEG_MASK(port)		(7<<(8+3*(port)))
@@ -1437,8 +1448,8 @@ enum skl_disp_power_wells {
 /*
  * Fence registers
  */
-#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
-#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
+#define FENCE_REG_830(i)		_REG(0x2000 + (i) * 4) /* 8 registers */
+#define FENCE_REG_945_8(i)		_REG(0x3000 + ((i) - 8) * 4) /* 8 registers */
 #define   I830_FENCE_START_MASK		0x07f80000
 #define   I830_FENCE_TILING_Y_SHIFT	12
 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
@@ -1451,21 +1462,21 @@ enum skl_disp_power_wells {
 #define   I915_FENCE_START_MASK		0x0ff00000
 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
 
-#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
-#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
+#define FENCE_REG_965_LO(i)		_REG(0x03000 + (i) * 8)
+#define FENCE_REG_965_HI(i)		_REG(0x03000 + (i) * 8 + 4)
 #define   I965_FENCE_PITCH_SHIFT	2
 #define   I965_FENCE_TILING_Y_SHIFT	1
 #define   I965_FENCE_REG_VALID		(1<<0)
 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
 
-#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
-#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
+#define FENCE_REG_GEN6_LO(i)		_REG(0x100000 + (i) * 8)
+#define FENCE_REG_GEN6_HI(i)		_REG(0x100000 + (i) * 8 + 4)
 #define   GEN6_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
 
 /* control register for cpu gtt access */
-#define TILECTL				0x101000
+#define TILECTL				_REG(0x101000)
 #define   TILECTL_SWZCTL			(1 << 0)
 #define   TILECTL_TLBPF			(1 << 1)
 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
@@ -1474,30 +1485,30 @@ enum skl_disp_power_wells {
 /*
  * Instruction and interrupt control regs
  */
-#define PGTBL_CTL	0x02020
+#define PGTBL_CTL	_REG(0x02020)
 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
-#define PGTBL_ER	0x02024
-#define PRB0_BASE (0x2030-0x30)
-#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
-#define PRB2_BASE (0x2050-0x30) /* gen3 */
-#define SRB0_BASE (0x2100-0x30) /* gen2 */
-#define SRB1_BASE (0x2110-0x30) /* gen2 */
-#define SRB2_BASE (0x2120-0x30) /* 830 */
-#define SRB3_BASE (0x2130-0x30) /* 830 */
+#define PGTBL_ER	_REG(0x02024)
+#define PRB0_BASE	(0x2030-0x30)
+#define PRB1_BASE	(0x2040-0x30) /* 830,gen3 */
+#define PRB2_BASE	(0x2050-0x30) /* gen3 */
+#define SRB0_BASE	(0x2100-0x30) /* gen2 */
+#define SRB1_BASE	(0x2110-0x30) /* gen2 */
+#define SRB2_BASE	(0x2120-0x30) /* 830 */
+#define SRB3_BASE	(0x2130-0x30) /* 830 */
 #define RENDER_RING_BASE	0x02000
 #define BSD_RING_BASE		0x04000
 #define GEN6_BSD_RING_BASE	0x12000
 #define GEN8_BSD2_RING_BASE	0x1c000
 #define VEBOX_RING_BASE		0x1a000
 #define BLT_RING_BASE		0x22000
-#define RING_TAIL(base)		((base)+0x30)
-#define RING_HEAD(base)		((base)+0x34)
-#define RING_START(base)	((base)+0x38)
-#define RING_CTL(base)		((base)+0x3c)
-#define RING_SYNC_0(base)	((base)+0x40)
-#define RING_SYNC_1(base)	((base)+0x44)
-#define RING_SYNC_2(base)	((base)+0x48)
+#define RING_TAIL(base)		_REG((base)+0x30)
+#define RING_HEAD(base)		_REG((base)+0x34)
+#define RING_START(base)	_REG((base)+0x38)
+#define RING_CTL(base)		_REG((base)+0x3c)
+#define RING_SYNC_0(base)	_REG((base)+0x40)
+#define RING_SYNC_1(base)	_REG((base)+0x44)
+#define RING_SYNC_2(base)	_REG((base)+0x48)
 #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
 #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
 #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
@@ -1510,51 +1521,51 @@ enum skl_disp_power_wells {
 #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
 #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
 #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
-#define GEN6_NOSYNC 0
-#define RING_PSMI_CTL(base)	((base)+0x50)
-#define RING_MAX_IDLE(base)	((base)+0x54)
-#define RING_HWS_PGA(base)	((base)+0x80)
-#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
-#define RING_RESET_CTL(base)	((base)+0xd0)
+#define GEN6_NOSYNC _REG(0)
+#define RING_PSMI_CTL(base)	_REG((base)+0x50)
+#define RING_MAX_IDLE(base)	_REG((base)+0x54)
+#define RING_HWS_PGA(base)	_REG((base)+0x80)
+#define RING_HWS_PGA_GEN6(base)	_REG((base)+0x2080)
+#define RING_RESET_CTL(base)	_REG((base)+0xd0)
 #define   RESET_CTL_REQUEST_RESET  (1 << 0)
 #define   RESET_CTL_READY_TO_RESET (1 << 1)
 
-#define HSW_GTT_CACHE_EN	0x4024
+#define HSW_GTT_CACHE_EN	_REG(0x4024)
 #define   GTT_CACHE_EN_ALL	0xF0007FFF
-#define GEN7_WR_WATERMARK	0x4028
-#define GEN7_GFX_PRIO_CTRL	0x402C
-#define ARB_MODE		0x4030
+#define GEN7_WR_WATERMARK	_REG(0x4028)
+#define GEN7_GFX_PRIO_CTRL	_REG(0x402C)
+#define ARB_MODE		_REG(0x4030)
 #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
 #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
-#define GEN7_GFX_PEND_TLB0	0x4034
-#define GEN7_GFX_PEND_TLB1	0x4038
+#define GEN7_GFX_PEND_TLB0	_REG(0x4034)
+#define GEN7_GFX_PEND_TLB1	_REG(0x4038)
 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
-#define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
+#define GEN7_LRA_LIMITS(i)	_REG(0x403C + (i) * 4)
 #define GEN7_LRA_LIMITS_REG_NUM	13
-#define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
-#define GEN7_GFX_MAX_REQ_COUNT		0x4074
+#define GEN7_MEDIA_MAX_REQ_COUNT	_REG(0x4070)
+#define GEN7_GFX_MAX_REQ_COUNT		_REG(0x4074)
 
-#define GAMTARBMODE		0x04a08
+#define GAMTARBMODE		_REG(0x04a08)
 #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
 #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
-#define RENDER_HWS_PGA_GEN7	(0x04080)
-#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
+#define RENDER_HWS_PGA_GEN7	_REG(0x04080)
+#define RING_FAULT_REG(ring)	_REG(0x4094 + 0x100*(ring)->id)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
 #define   RING_FAULT_VALID	(1<<0)
-#define DONE_REG		0x40b0
-#define GEN8_PRIVATE_PAT_LO	0x40e0
-#define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
-#define BSD_HWS_PGA_GEN7	(0x04180)
-#define BLT_HWS_PGA_GEN7	(0x04280)
-#define VEBOX_HWS_PGA_GEN7	(0x04380)
-#define RING_ACTHD(base)	((base)+0x74)
-#define RING_ACTHD_UDW(base)	((base)+0x5c)
-#define RING_NOPID(base)	((base)+0x94)
-#define RING_IMR(base)		((base)+0xa8)
-#define RING_HWSTAM(base)	((base)+0x98)
-#define RING_TIMESTAMP(base)	((base)+0x358)
+#define DONE_REG		_REG(0x40b0)
+#define GEN8_PRIVATE_PAT_LO	_REG(0x40e0)
+#define GEN8_PRIVATE_PAT_HI	_REG(0x40e0 + 4)
+#define BSD_HWS_PGA_GEN7	_REG(0x04180)
+#define BLT_HWS_PGA_GEN7	_REG(0x04280)
+#define VEBOX_HWS_PGA_GEN7	_REG(0x04380)
+#define RING_ACTHD(base)	_REG((base)+0x74)
+#define RING_ACTHD_UDW(base)	_REG((base)+0x5c)
+#define RING_NOPID(base)	_REG((base)+0x94)
+#define RING_IMR(base)		_REG((base)+0xa8)
+#define RING_HWSTAM(base)	_REG((base)+0x98)
+#define RING_TIMESTAMP(base)	_REG((base)+0x358)
 #define   TAIL_ADDR		0x001FFFF8
 #define   HEAD_WRAP_COUNT	0xFFE00000
 #define   HEAD_WRAP_ONE		0x00200000
@@ -1571,54 +1582,54 @@ enum skl_disp_power_wells {
 #define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
 #define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
 
-#define GEN7_TLB_RD_ADDR	0x4700
+#define GEN7_TLB_RD_ADDR	_REG(0x4700)
 
 #if 0
-#define PRB0_TAIL	0x02030
-#define PRB0_HEAD	0x02034
-#define PRB0_START	0x02038
-#define PRB0_CTL	0x0203c
-#define PRB1_TAIL	0x02040 /* 915+ only */
-#define PRB1_HEAD	0x02044 /* 915+ only */
-#define PRB1_START	0x02048 /* 915+ only */
-#define PRB1_CTL	0x0204c /* 915+ only */
+#define PRB0_TAIL	_REG(0x2030)
+#define PRB0_HEAD	_REG(0x2034)
+#define PRB0_START	_REG(0x2038)
+#define PRB0_CTL	_REG(0x203c)
+#define PRB1_TAIL	_REG(0x2040) /* 915+ only */
+#define PRB1_HEAD	_REG(0x2044) /* 915+ only */
+#define PRB1_START	_REG(0x2048) /* 915+ only */
+#define PRB1_CTL	_REG(0x204c) /* 915+ only */
 #endif
-#define IPEIR_I965	0x02064
-#define IPEHR_I965	0x02068
-#define INSTDONE_I965	0x0206c
-#define GEN7_INSTDONE_1		0x0206c
-#define GEN7_SC_INSTDONE	0x07100
-#define GEN7_SAMPLER_INSTDONE	0x0e160
-#define GEN7_ROW_INSTDONE	0x0e164
+#define IPEIR_I965	_REG(0x2064)
+#define IPEHR_I965	_REG(0x2068)
+#define INSTDONE_I965	_REG(0x206c)
+#define GEN7_INSTDONE_1		_REG(0x206c)
+#define GEN7_SC_INSTDONE	_REG(0x7100)
+#define GEN7_SAMPLER_INSTDONE	_REG(0xe160)
+#define GEN7_ROW_INSTDONE	_REG(0xe164)
 #define I915_NUM_INSTDONE_REG	4
-#define RING_IPEIR(base)	((base)+0x64)
-#define RING_IPEHR(base)	((base)+0x68)
-#define RING_INSTDONE(base)	((base)+0x6c)
-#define RING_INSTPS(base)	((base)+0x70)
-#define RING_DMA_FADD(base)	((base)+0x78)
-#define RING_DMA_FADD_UDW(base)	((base)+0x60) /* gen8+ */
-#define RING_INSTPM(base)	((base)+0xc0)
-#define RING_MI_MODE(base)	((base)+0x9c)
-#define INSTPS		0x02070 /* 965+ only */
-#define INSTDONE1	0x0207c /* 965+ only */
-#define ACTHD_I965	0x02074
-#define HWS_PGA		0x02080
+#define RING_IPEIR(base)	_REG((base)+0x64)
+#define RING_IPEHR(base)	_REG((base)+0x68)
+#define RING_INSTDONE(base)	_REG((base)+0x6c)
+#define RING_INSTPS(base)	_REG((base)+0x70)
+#define RING_DMA_FADD(base)	_REG((base)+0x78)
+#define RING_DMA_FADD_UDW(base) _REG((base)+0x60) /* gen8+ */
+#define RING_INSTPM(base)	_REG((base)+0xc0)
+#define RING_MI_MODE(base)	_REG((base)+0x9c)
+#define INSTPS		_REG(0x2070) /* 965+ only */
+#define INSTDONE1	_REG(0x207c) /* 965+ only */
+#define ACTHD_I965	_REG(0x2074)
+#define HWS_PGA		_REG(0x2080)
 #define HWS_ADDRESS_MASK	0xfffff000
 #define HWS_START_ADDRESS_SHIFT	4
-#define PWRCTXA		0x2088 /* 965GM+ only */
+#define PWRCTXA		_REG(0x2088) /* 965GM+ only */
 #define   PWRCTX_EN	(1<<0)
-#define IPEIR		0x02088
-#define IPEHR		0x0208c
-#define INSTDONE	0x02090
-#define NOPID		0x02094
-#define HWSTAM		0x02098
-#define DMA_FADD_I8XX	0x020d0
-#define RING_BBSTATE(base)	((base)+0x110)
-#define RING_BBADDR(base)	((base)+0x140)
-#define RING_BBADDR_UDW(base)	((base)+0x168) /* gen8+ */
-
-#define ERROR_GEN6	0x040a0
-#define GEN7_ERR_INT	0x44040
+#define IPEIR		_REG(0x2088)
+#define IPEHR		_REG(0x208c)
+#define INSTDONE	_REG(0x2090)
+#define NOPID		_REG(0x2094)
+#define HWSTAM		_REG(0x2098)
+#define DMA_FADD_I8XX	_REG(0x20d0)
+#define RING_BBSTATE(base)	_REG((base)+0x110)
+#define RING_BBADDR(base)	_REG((base)+0x140)
+#define RING_BBADDR_UDW(base)	_REG((base)+0x168) /* gen8+ */
+
+#define ERROR_GEN6	_REG(0x40a0)
+#define GEN7_ERR_INT	_REG(0x44040)
 #define   ERR_INT_POISON		(1<<31)
 #define   ERR_INT_MMIO_UNCLAIMED	(1<<13)
 #define   ERR_INT_PIPE_CRC_DONE_C	(1<<8)
@@ -1630,13 +1641,13 @@ enum skl_disp_power_wells {
 #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
 
-#define GEN8_FAULT_TLB_DATA0		0x04b10
-#define GEN8_FAULT_TLB_DATA1		0x04b14
+#define GEN8_FAULT_TLB_DATA0		_REG(0x4b10)
+#define GEN8_FAULT_TLB_DATA1		_REG(0x4b14)
 
-#define FPGA_DBG		0x42300
+#define FPGA_DBG		_REG(0x42300)
 #define   FPGA_DBG_RM_NOCLAIM	(1<<31)
 
-#define DERRMR		0x44050
+#define DERRMR		_REG(0x44050)
 /* Note that HBLANK events are reserved on bdw+ */
 #define   DERRMR_PIPEA_SCANLINE		(1<<0)
 #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)
@@ -1660,29 +1671,29 @@ enum skl_disp_power_wells {
  * for various sorts of correct behavior.  The top 16 bits of each are
  * the enables for writing to the corresponding low bit.
  */
-#define _3D_CHICKEN	0x02084
+#define _3D_CHICKEN	_REG(0x2084)
 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
-#define _3D_CHICKEN2	0x0208c
+#define _3D_CHICKEN2	_REG(0x208c)
 /* Disables pipelining of read flushes past the SF-WIZ interface.
  * Required on all Ironlake steppings according to the B-Spec, but the
  * particular danger of not doing so is not specified.
  */
 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
-#define _3D_CHICKEN3	0x02090
+#define _3D_CHICKEN3	_REG(0x2090)
 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
 
-#define MI_MODE		0x0209c
+#define MI_MODE		_REG(0x209c)
 # define VS_TIMER_DISPATCH				(1 << 6)
 # define MI_FLUSH_ENABLE				(1 << 12)
 # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
 # define MODE_IDLE					(1 << 9)
 # define STOP_RING					(1 << 8)
 
-#define GEN6_GT_MODE	0x20d0
-#define GEN7_GT_MODE	0x7008
+#define GEN6_GT_MODE	_REG(0x20d0)
+#define GEN7_GT_MODE	_REG(0x7008)
 #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
 #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
 #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
@@ -1692,9 +1703,9 @@ enum skl_disp_power_wells {
 #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
 #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
 
-#define GFX_MODE	0x02520
-#define GFX_MODE_GEN7	0x0229c
-#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
+#define GFX_MODE	_REG(0x2520)
+#define GFX_MODE_GEN7	_REG(0x229c)
+#define RING_MODE_GEN7(ring)	_REG((ring)->mmio_base+0x29c)
 #define   GFX_RUN_LIST_ENABLE		(1<<15)
 #define   GFX_INTERRUPT_STEERING	(1<<14)
 #define   GFX_TLB_INVALIDATE_EXPLICIT	(1<<13)
@@ -1712,36 +1723,36 @@ enum skl_disp_power_wells {
 #define VLV_DISPLAY_BASE 0x180000
 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
 
-#define VLV_GU_CTL0	(VLV_DISPLAY_BASE + 0x2030)
-#define VLV_GU_CTL1	(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0		0x0209c /* 915+ only */
-#define IER		0x020a0
-#define IIR		0x020a4
-#define IMR		0x020a8
-#define ISR		0x020ac
-#define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
+#define VLV_GU_CTL0	_REG(VLV_DISPLAY_BASE + 0x2030)
+#define VLV_GU_CTL1	_REG(VLV_DISPLAY_BASE + 0x2034)
+#define SCPD0		_REG(0x209c) /* 915+ only */
+#define IER		_REG(0x20a0)
+#define IIR		_REG(0x20a4)
+#define IMR		_REG(0x20a8)
+#define ISR		_REG(0x20ac)
+#define VLV_GUNIT_CLOCK_GATE	_REG(VLV_DISPLAY_BASE + 0x2060)
 #define   GINT_DIS		(1<<22)
 #define   GCFG_DIS		(1<<8)
-#define VLV_GUNIT_CLOCK_GATE2	(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_GUNIT_CLOCK_GATE2	_REG(VLV_DISPLAY_BASE + 0x2064)
+#define VLV_IIR_RW	_REG(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER		_REG(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR		_REG(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR		_REG(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR		_REG(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR	_REG(VLV_DISPLAY_BASE + 0x2120)
 #define VLV_PCBR_ADDR_SHIFT	12
 
 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
-#define EIR		0x020b0
-#define EMR		0x020b4
-#define ESR		0x020b8
+#define EIR		_REG(0x20b0)
+#define EMR		_REG(0x20b4)
+#define ESR		_REG(0x20b8)
 #define   GM45_ERROR_PAGE_TABLE				(1<<5)
 #define   GM45_ERROR_MEM_PRIV				(1<<4)
 #define   I915_ERROR_PAGE_TABLE				(1<<4)
 #define   GM45_ERROR_CP_PRIV				(1<<3)
 #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
 #define   I915_ERROR_INSTRUCTION			(1<<0)
-#define INSTPM	        0x020c0
+#define INSTPM	        _REG(0x20c0)
 #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
 #define   INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
 					will not assert AGPBUSY# and will only
@@ -1749,14 +1760,14 @@ enum skl_disp_power_wells {
 #define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
 #define   INSTPM_TLB_INVALIDATE	(1<<9)
 #define   INSTPM_SYNC_FLUSH	(1<<5)
-#define ACTHD	        0x020c8
-#define MEM_MODE	0x020cc
+#define ACTHD	        _REG(0x20c8)
+#define MEM_MODE	_REG(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
-#define FW_BLC		0x020d8
-#define FW_BLC2		0x020dc
-#define FW_BLC_SELF	0x020e0 /* 915+ only */
+#define FW_BLC		_REG(0x20d8)
+#define FW_BLC2		_REG(0x20dc)
+#define FW_BLC_SELF	_REG(0x20e0) /* 915+ only */
 #define   FW_BLC_SELF_EN_MASK      (1<<31)
 #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
 #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
@@ -1764,7 +1775,7 @@ enum skl_disp_power_wells {
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
 #define LM_FIFO_WATERMARK   0x0000001F
-#define MI_ARB_STATE	0x020e4 /* 915+ only */
+#define MI_ARB_STATE	_REG(0x20e4) /* 915+ only */
 
 /* Make render/texture TLB fetches lower priorty than associated data
  *   fetches. This is not turned on by default
@@ -1828,11 +1839,11 @@ enum skl_disp_power_wells {
 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
 
-#define MI_STATE	0x020e4 /* gen2 only */
+#define MI_STATE	_REG(0x20e4) /* gen2 only */
 #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
 
-#define CACHE_MODE_0	0x02120 /* 915+ only */
+#define CACHE_MODE_0	_REG(0x2120) /* 915+ only */
 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
 #define   CM0_ZR_OPT_DISABLE      (1<<5)
@@ -1841,32 +1852,32 @@ enum skl_disp_power_wells {
 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
-#define GFX_FLSH_CNTL	0x02170 /* 915+ only */
-#define GFX_FLSH_CNTL_GEN6	0x101008
+#define GFX_FLSH_CNTL	_REG(0x2170) /* 915+ only */
+#define GFX_FLSH_CNTL_GEN6	_REG(0x101008)
 #define   GFX_FLSH_CNTL_EN	(1<<0)
-#define ECOSKPD		0x021d0
+#define ECOSKPD		_REG(0x21d0)
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
-#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
+#define CACHE_MODE_0_GEN7	_REG(0x7000) /* IVB+ */
 #define RC_OP_FLUSH_ENABLE (1<<0)
 #define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
-#define CACHE_MODE_1		0x7004 /* IVB+ */
+#define CACHE_MODE_1		_REG(0x7004) /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
 
-#define GEN6_BLITTER_ECOSKPD	0x221d0
+#define GEN6_BLITTER_ECOSKPD	_REG(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT			16
 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
 
-#define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
+#define GEN6_RC_SLEEP_PSMI_CONTROL	_REG(0x2050)
 #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
 
 /* Fuse readout registers for GT */
-#define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
+#define CHV_FUSE_GT			_REG(VLV_DISPLAY_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0		(1 << 10)
 #define   CHV_FGT_DISABLE_SS1		(1 << 11)
 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
@@ -1878,16 +1889,16 @@ enum skl_disp_power_wells {
 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
 
-#define GEN8_FUSE2			0x9120
+#define GEN8_FUSE2			_REG(0x9120)
 #define   GEN8_F2_S_ENA_SHIFT		25
 #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
 
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
-#define GEN9_EU_DISABLE(slice)		(0x9134 + (slice)*0x4)
+#define GEN9_EU_DISABLE(slice)		_REG(0x9134 + (slice)*0x4)
 
-#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
+#define GEN6_BSD_SLEEP_PSMI_CONTROL	_REG(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
 #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
@@ -1965,9 +1976,9 @@ enum skl_disp_power_wells {
 #define I915_ASLE_INTERRUPT				(1<<0)
 #define I915_BSD_USER_INTERRUPT				(1<<25)
 
-#define GEN6_BSD_RNCID			0x12198
+#define GEN6_BSD_RNCID			_REG(0x12198)
 
-#define GEN7_FF_THREAD_MODE		0x20a0
+#define GEN7_FF_THREAD_MODE		_REG(0x20a0)
 #define   GEN7_FF_SCHED_MASK		0x0077070
 #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
 #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
@@ -1988,9 +1999,9 @@ enum skl_disp_power_wells {
  * Framebuffer compression (915+ only)
  */
 
-#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
-#define FBC_LL_BASE		0x03204 /* 4k page aligned */
-#define FBC_CONTROL		0x03208
+#define FBC_CFB_BASE		_REG(0x3200) /* 4k page aligned */
+#define FBC_LL_BASE		_REG(0x3204) /* 4k page aligned */
+#define FBC_CONTROL		_REG(0x3208)
 #define   FBC_CTL_EN		(1<<31)
 #define   FBC_CTL_PERIODIC	(1<<30)
 #define   FBC_CTL_INTERVAL_SHIFT (16)
@@ -1998,14 +2009,14 @@ enum skl_disp_power_wells {
 #define   FBC_CTL_C3_IDLE	(1<<13)
 #define   FBC_CTL_STRIDE_SHIFT	(5)
 #define   FBC_CTL_FENCENO_SHIFT	(0)
-#define FBC_COMMAND		0x0320c
+#define FBC_COMMAND		_REG(0x320c)
 #define   FBC_CMD_COMPRESS	(1<<0)
-#define FBC_STATUS		0x03210
+#define FBC_STATUS		_REG(0x3210)
 #define   FBC_STAT_COMPRESSING	(1<<31)
 #define   FBC_STAT_COMPRESSED	(1<<30)
 #define   FBC_STAT_MODIFIED	(1<<29)
 #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
-#define FBC_CONTROL2		0x03214
+#define FBC_CONTROL2		_REG(0x3214)
 #define   FBC_CTL_FENCE_DBL	(0<<4)
 #define   FBC_CTL_IDLE_IMM	(0<<2)
 #define   FBC_CTL_IDLE_FULL	(1<<2)
@@ -2013,17 +2024,17 @@ enum skl_disp_power_wells {
 #define   FBC_CTL_IDLE_DEBUG	(3<<2)
 #define   FBC_CTL_CPU_FENCE	(1<<1)
 #define   FBC_CTL_PLANE(plane)	((plane)<<0)
-#define FBC_FENCE_OFF		0x03218 /* BSpec typo has 321Bh */
-#define FBC_TAG(i)		(0x03300 + (i) * 4)
+#define FBC_FENCE_OFF		_REG(0x3218) /* BSpec typo has 321Bh */
+#define FBC_TAG(i)		_REG(0x3300 + (i) * 4)
 
-#define FBC_STATUS2		0x43214
+#define FBC_STATUS2		_REG(0x43214)
 #define  FBC_COMPRESSION_MASK	0x7ff
 
 #define FBC_LL_SIZE		(1536)
 
 /* Framebuffer compression for GM45+ */
-#define DPFC_CB_BASE		0x3200
-#define DPFC_CONTROL		0x3208
+#define DPFC_CB_BASE		_REG(0x3200)
+#define DPFC_CONTROL		_REG(0x3208)
 #define   DPFC_CTL_EN		(1<<31)
 #define   DPFC_CTL_PLANE(plane)	((plane)<<30)
 #define   IVB_DPFC_CTL_PLANE(plane)	((plane)<<29)
@@ -2034,37 +2045,37 @@ enum skl_disp_power_wells {
 #define   DPFC_CTL_LIMIT_1X	(0<<6)
 #define   DPFC_CTL_LIMIT_2X	(1<<6)
 #define   DPFC_CTL_LIMIT_4X	(2<<6)
-#define DPFC_RECOMP_CTL		0x320c
+#define DPFC_RECOMP_CTL		_REG(0x320c)
 #define   DPFC_RECOMP_STALL_EN	(1<<27)
 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
-#define DPFC_STATUS		0x3210
+#define DPFC_STATUS		_REG(0x3210)
 #define   DPFC_INVAL_SEG_SHIFT  (16)
 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
 #define   DPFC_COMP_SEG_SHIFT	(0)
 #define   DPFC_COMP_SEG_MASK	(0x000003ff)
-#define DPFC_STATUS2		0x3214
-#define DPFC_FENCE_YOFF		0x3218
-#define DPFC_CHICKEN		0x3224
+#define DPFC_STATUS2		_REG(0x3214)
+#define DPFC_FENCE_YOFF		_REG(0x3218)
+#define DPFC_CHICKEN		_REG(0x3224)
 #define   DPFC_HT_MODIFY	(1<<31)
 
 /* Framebuffer compression for Ironlake */
-#define ILK_DPFC_CB_BASE	0x43200
-#define ILK_DPFC_CONTROL	0x43208
+#define ILK_DPFC_CB_BASE	_REG(0x43200)
+#define ILK_DPFC_CONTROL	_REG(0x43208)
 #define   FBC_CTL_FALSE_COLOR	(1<<10)
 /* The bit 28-8 is reserved */
 #define   DPFC_RESERVED		(0x1FFFFF00)
-#define ILK_DPFC_RECOMP_CTL	0x4320c
-#define ILK_DPFC_STATUS		0x43210
-#define ILK_DPFC_FENCE_YOFF	0x43218
-#define ILK_DPFC_CHICKEN	0x43224
-#define ILK_FBC_RT_BASE		0x2128
+#define ILK_DPFC_RECOMP_CTL	_REG(0x4320c)
+#define ILK_DPFC_STATUS		_REG(0x43210)
+#define ILK_DPFC_FENCE_YOFF	_REG(0x43218)
+#define ILK_DPFC_CHICKEN	_REG(0x43224)
+#define ILK_FBC_RT_BASE		_REG(0x2128)
 #define   ILK_FBC_RT_VALID	(1<<0)
 #define   SNB_FBC_FRONT_BUFFER	(1<<1)
 
-#define ILK_DISPLAY_CHICKEN1	0x42000
+#define ILK_DISPLAY_CHICKEN1	_REG(0x42000)
 #define   ILK_FBCQ_DIS		(1<<22)
 #define	  ILK_PABSTRETCH_DIS	(1<<21)
 
@@ -2074,31 +2085,31 @@ enum skl_disp_power_wells {
  *
  * The following two registers are of type GTTMMADR
  */
-#define SNB_DPFC_CTL_SA		0x100100
+#define SNB_DPFC_CTL_SA		_REG(0x100100)
 #define   SNB_CPU_FENCE_ENABLE	(1<<29)
-#define DPFC_CPU_FENCE_OFFSET	0x100104
+#define DPFC_CPU_FENCE_OFFSET	_REG(0x100104)
 
 /* Framebuffer compression for Ivybridge */
-#define IVB_FBC_RT_BASE			0x7020
+#define IVB_FBC_RT_BASE			_REG(0x7020)
 
-#define IPS_CTL		0x43408
+#define IPS_CTL		_REG(0x43408)
 #define   IPS_ENABLE	(1 << 31)
 
-#define MSG_FBC_REND_STATE	0x50380
+#define MSG_FBC_REND_STATE	_REG(0x50380)
 #define   FBC_REND_NUKE		(1<<2)
 #define   FBC_REND_CACHE_CLEAN	(1<<1)
 
 /*
  * GPIO regs
  */
-#define GPIOA			0x5010
-#define GPIOB			0x5014
-#define GPIOC			0x5018
-#define GPIOD			0x501c
-#define GPIOE			0x5020
-#define GPIOF			0x5024
-#define GPIOG			0x5028
-#define GPIOH			0x502c
+#define GPIOA			_REG(0x5010)
+#define GPIOB			_REG(0x5014)
+#define GPIOC			_REG(0x5018)
+#define GPIOD			_REG(0x501c)
+#define GPIOE			_REG(0x5020)
+#define GPIOF			_REG(0x5024)
+#define GPIOG			_REG(0x5028)
+#define GPIOH			_REG(0x502c)
 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
 # define GPIO_CLOCK_DIR_IN		(0 << 1)
 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
@@ -2114,7 +2125,7 @@ enum skl_disp_power_wells {
 # define GPIO_DATA_VAL_IN		(1 << 12)
 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
 
-#define GMBUS0			(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
+#define GMBUS0			_REG(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
 #define   GMBUS_RATE_100KHZ	(0<<8)
 #define   GMBUS_RATE_50KHZ	(1<<8)
 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
@@ -2133,7 +2144,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_2_BXT	2
 #define   GMBUS_PIN_3_BXT	3
 #define   GMBUS_NUM_PINS	7 /* including 0 */
-#define GMBUS1			(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
+#define GMBUS1			_REG(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
 #define   GMBUS_SW_RDY		(1<<30)
 #define   GMBUS_ENT		(1<<29) /* enable timeout */
@@ -2147,7 +2158,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ	(1<<0)
 #define   GMBUS_SLAVE_WRITE	(0<<0)
-#define GMBUS2			(dev_priv->gpio_mmio_base + 0x5108) /* status */
+#define GMBUS2			_REG(dev_priv->gpio_mmio_base + 0x5108) /* status */
 #define   GMBUS_INUSE		(1<<15)
 #define   GMBUS_HW_WAIT_PHASE	(1<<14)
 #define   GMBUS_STALL_TIMEOUT	(1<<13)
@@ -2155,27 +2166,27 @@ enum skl_disp_power_wells {
 #define   GMBUS_HW_RDY		(1<<11)
 #define   GMBUS_SATOER		(1<<10)
 #define   GMBUS_ACTIVE		(1<<9)
-#define GMBUS3			(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-#define GMBUS4			(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
+#define GMBUS3			_REG(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
+#define GMBUS4			_REG(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
 #define   GMBUS_NAK_EN		(1<<3)
 #define   GMBUS_IDLE_EN		(1<<2)
 #define   GMBUS_HW_WAIT_EN	(1<<1)
 #define   GMBUS_HW_RDY_EN	(1<<0)
-#define GMBUS5			(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
+#define GMBUS5			_REG(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
 #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
 
 /*
  * Clock control & power management
  */
-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
-#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
+#define _DPLL_A _REG(dev_priv->info.display_mmio_offset + 0x6014)
+#define _DPLL_B _REG(dev_priv->info.display_mmio_offset + 0x6018)
+#define _CHV_DPLL_C _REG(dev_priv->info.display_mmio_offset + 0x6030)
 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
 
-#define VGA0	0x6000
-#define VGA1	0x6004
-#define VGA_PD	0x6010
+#define VGA0	_REG(0x6000)
+#define VGA1	_REG(0x6004)
+#define VGA_PD	_REG(0x6010)
 #define   VGA0_PD_P2_DIV_4	(1 << 7)
 #define   VGA0_PD_P1_DIV_2	(1 << 5)
 #define   VGA0_PD_P1_SHIFT	0
@@ -2211,9 +2222,9 @@ enum skl_disp_power_wells {
 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
 
 /* Additional CHV pll/phy registers */
-#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
+#define DPIO_PHY_STATUS			_REG(VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK		(0xf)
-#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
+#define DISPLAY_PHY_CONTROL _REG(VLV_DISPLAY_BASE + 0x60100)
 #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2*(phy)+(ch)+27))
 #define   PHY_LDO_DELAY_0NS			0x0
 #define   PHY_LDO_DELAY_200NS			0x1
@@ -2224,7 +2235,7 @@ enum skl_disp_power_wells {
 #define   PHY_CH_DEEP_PSR			0x7
 #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6*(phy)+3*(ch)+2))
 #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
-#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
+#define DISPLAY_PHY_STATUS _REG(VLV_DISPLAY_BASE + 0x60104)
 #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
 #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6-(6*(phy)+3*(ch))))
 #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8-(6*(phy)+3*(ch)+(spline))))
@@ -2267,9 +2278,9 @@ enum skl_disp_power_wells {
 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
 
-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
-#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
+#define _DPLL_A_MD _REG(dev_priv->info.display_mmio_offset + 0x601c)
+#define _DPLL_B_MD _REG(dev_priv->info.display_mmio_offset + 0x6020)
+#define _CHV_DPLL_C_MD _REG(dev_priv->info.display_mmio_offset + 0x603c)
 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
 
 /*
@@ -2309,12 +2320,12 @@ enum skl_disp_power_wells {
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
 
-#define _FPA0	0x06040
-#define _FPA1	0x06044
-#define _FPB0	0x06048
-#define _FPB1	0x0604c
-#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
-#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
+#define _FPA0	0x6040
+#define _FPA1	0x6044
+#define _FPB0	0x6048
+#define _FPB1	0x604c
+#define FP0(pipe) _REG_PIPE(pipe, _FPA0, _FPB0)
+#define FP1(pipe) _REG_PIPE(pipe, _FPA1, _FPB1)
 #define   FP_N_DIV_MASK		0x003f0000
 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
 #define   FP_N_DIV_SHIFT		16
@@ -2323,7 +2334,7 @@ enum skl_disp_power_wells {
 #define   FP_M2_DIV_MASK	0x0000003f
 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
 #define   FP_M2_DIV_SHIFT		 0
-#define DPLL_TEST	0x606c
+#define DPLL_TEST	_REG(0x606c)
 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
@@ -2334,12 +2345,12 @@ enum skl_disp_power_wells {
 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
-#define D_STATE		0x6104
+#define D_STATE		_REG(0x6104)
 #define  DSTATE_GFX_RESET_I830			(1<<6)
 #define  DSTATE_PLL_D3_OFF			(1<<3)
 #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
 #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
-#define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D	_REG(dev_priv->info.display_mmio_offset + 0x6200)
 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
@@ -2378,7 +2389,7 @@ enum skl_disp_power_wells {
 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
 
-#define RENCLK_GATE_D1		0x6204
+#define RENCLK_GATE_D1		_REG(0x6204)
 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
@@ -2442,35 +2453,35 @@ enum skl_disp_power_wells {
 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
 
-#define RENCLK_GATE_D2		0x6208
+#define RENCLK_GATE_D2		_REG(0x6208)
 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
 
-#define VDECCLK_GATE_D		0x620C		/* g4x only */
+#define VDECCLK_GATE_D		_REG(0x620C)		/* g4x only */
 #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
 
-#define RAMCLK_GATE_D		0x6210		/* CRL only */
-#define DEUC			0x6214          /* CRL only */
+#define RAMCLK_GATE_D		_REG(0x6210)		/* CRL only */
+#define DEUC			_REG(0x6214)          /* CRL only */
 
-#define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
+#define FW_BLC_SELF_VLV		_REG(VLV_DISPLAY_BASE + 0x6500)
 #define  FW_CSPWRDWNEN		(1<<15)
 
-#define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
+#define MI_ARB_VLV		_REG(VLV_DISPLAY_BASE + 0x6504)
 
-#define CZCLK_CDCLK_FREQ_RATIO	(VLV_DISPLAY_BASE + 0x6508)
+#define CZCLK_CDCLK_FREQ_RATIO	_REG(VLV_DISPLAY_BASE + 0x6508)
 #define   CDCLK_FREQ_SHIFT	4
 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
 #define   CZCLK_FREQ_MASK	0xf
 
-#define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
+#define GCI_CONTROL		_REG(VLV_DISPLAY_BASE + 0x650C)
 #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
 #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
 #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
 #define   PFI_CREDIT_RESEND	(1 << 27)
 #define   VGA_FAST_MODE_DISABLE	(1 << 14)
 
-#define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
+#define GMBUSFREQ_VLV		_REG(VLV_DISPLAY_BASE + 0x6510)
 
 /*
  * Palette regs
@@ -2478,8 +2489,8 @@ enum skl_disp_power_wells {
 #define PALETTE_A_OFFSET 0xa000
 #define PALETTE_B_OFFSET 0xa800
 #define CHV_PALETTE_C_OFFSET 0xc000
-#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
-			  dev_priv->info.display_mmio_offset + (i) * 4)
+#define PALETTE(pipe, i) _REG(dev_priv->info.palette_offsets[pipe] +	\
+			      dev_priv->info.display_mmio_offset + (i) * 4)
 
 /* MCH MMIO space */
 
@@ -2498,31 +2509,31 @@ enum skl_disp_power_wells {
 #define MCHBAR_MIRROR_BASE_SNB	0x140000
 
 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
-#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
+#define DCLK _REG(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
 
 /* 915-945 and GM965 MCH register controlling DRAM channel access */
-#define DCC			0x10200
+#define DCC			_REG(MCHBAR_MIRROR_BASE + 0x200)
 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
-#define DCC2			0x10204
+#define DCC2			_REG(MCHBAR_MIRROR_BASE + 0x204)
 #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
 
 /* Pineview MCH register contains DDR3 setting */
-#define CSHRDDR3CTL            0x101a8
+#define CSHRDDR3CTL            _REG(MCHBAR_MIRROR_BASE + 0x1a8)
 #define CSHRDDR3CTL_DDR3       (1 << 2)
 
 /* 965 MCH register controlling DRAM channel configuration */
-#define C0DRB3			0x10206
-#define C1DRB3			0x10606
+#define C0DRB3			_REG(MCHBAR_MIRROR_BASE + 0x206)
+#define C1DRB3			_REG(MCHBAR_MIRROR_BASE + 0x606)
 
 /* snb MCH registers for reading the DRAM channel configuration */
-#define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
-#define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
-#define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
+#define MAD_DIMM_C0			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5004)
+#define MAD_DIMM_C1			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5008)
+#define MAD_DIMM_C2			_REG(MCHBAR_MIRROR_BASE_SNB + 0x500C)
 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
@@ -2542,14 +2553,14 @@ enum skl_disp_power_wells {
 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
 
 /* snb MCH registers for priority tuning */
-#define MCH_SSKPD			(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
+#define MCH_SSKPD			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
 #define   MCH_SSKPD_WM0_MASK		0x3f
 #define   MCH_SSKPD_WM0_VAL		0xc
 
-#define MCH_SECP_NRG_STTS		(MCHBAR_MIRROR_BASE_SNB + 0x592c)
+#define MCH_SECP_NRG_STTS		_REG(MCHBAR_MIRROR_BASE_SNB + 0x592c)
 
 /* Clocking configuration register */
-#define CLKCFG			0x10c00
+#define CLKCFG			_REG(MCHBAR_MIRROR_BASE + 0xc00)
 #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
@@ -2565,26 +2576,26 @@ enum skl_disp_power_wells {
 #define CLKCFG_MEM_800					(3 << 4)
 #define CLKCFG_MEM_MASK					(7 << 4)
 
-#define HPLLVCO                 (MCHBAR_MIRROR_BASE + 0xc38)
-#define HPLLVCO_MOBILE          (MCHBAR_MIRROR_BASE + 0xc0f)
+#define HPLLVCO                 _REG(MCHBAR_MIRROR_BASE + 0xc38)
+#define HPLLVCO_MOBILE          _REG(MCHBAR_MIRROR_BASE + 0xc0f)
 
-#define TSC1			0x11001
+#define TSC1			_REG(0x11001)
 #define   TSE			(1<<0)
-#define TR1			0x11006
-#define TSFS			0x11020
+#define TR1			_REG(0x11006)
+#define TSFS			_REG(0x11020)
 #define   TSFS_SLOPE_MASK	0x0000ff00
 #define   TSFS_SLOPE_SHIFT	8
 #define   TSFS_INTR_MASK	0x000000ff
 
-#define CRSTANDVID		0x11100
-#define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
+#define CRSTANDVID		_REG(0x11100)
+#define PXVFREQ(fstart)		_REG(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
 #define   PXVFREQ_PX_MASK	0x7f000000
 #define   PXVFREQ_PX_SHIFT	24
-#define VIDFREQ_BASE		0x11110
-#define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
-#define VIDFREQ2		0x11114
-#define VIDFREQ3		0x11118
-#define VIDFREQ4		0x1111c
+#define VIDFREQ_BASE		_REG(0x11110)
+#define VIDFREQ1		_REG(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
+#define VIDFREQ2		_REG(0x11114)
+#define VIDFREQ3		_REG(0x11118)
+#define VIDFREQ4		_REG(0x1111c)
 #define   VIDFREQ_P0_MASK	0x1f000000
 #define   VIDFREQ_P0_SHIFT	24
 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
@@ -2596,8 +2607,8 @@ enum skl_disp_power_wells {
 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
 #define   VIDFREQ_P1_CSCLK_SHIFT 4
 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
-#define INTTOEXT_BASE_ILK	0x11300
-#define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
+#define INTTOEXT_BASE_ILK	_REG(0x11300)
+#define INTTOEXT_BASE		_REG(0x11120) /* INTTOEXT1-8 (0x1113c) */
 #define   INTTOEXT_MAP3_SHIFT	24
 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
 #define   INTTOEXT_MAP2_SHIFT	16
@@ -2606,7 +2617,7 @@ enum skl_disp_power_wells {
 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
 #define   INTTOEXT_MAP0_SHIFT	0
 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
-#define MEMSWCTL		0x11170 /* Ironlake only */
+#define MEMSWCTL		_REG(0x11170) /* Ironlake only */
 #define   MEMCTL_CMD_MASK	0xe000
 #define   MEMCTL_CMD_SHIFT	13
 #define   MEMCTL_CMD_RCLK_OFF	0
@@ -2621,8 +2632,8 @@ enum skl_disp_power_wells {
 #define   MEMCTL_FREQ_SHIFT	8
 #define   MEMCTL_SFCAVM		(1<<7)
 #define   MEMCTL_TGT_VID_MASK	0x007f
-#define MEMIHYST		0x1117c
-#define MEMINTREN		0x11180 /* 16 bits */
+#define MEMIHYST		_REG(0x1117c)
+#define MEMINTREN		_REG(0x11180) /* 16 bits */
 #define   MEMINT_RSEXIT_EN	(1<<8)
 #define   MEMINT_CX_SUPR_EN	(1<<7)
 #define   MEMINT_CONT_BUSY_EN	(1<<6)
@@ -2632,7 +2643,7 @@ enum skl_disp_power_wells {
 #define   MEMINT_UP_EVAL_EN	(1<<2)
 #define   MEMINT_DOWN_EVAL_EN	(1<<1)
 #define   MEMINT_SW_CMD_EN	(1<<0)
-#define MEMINTRSTR		0x11182 /* 16 bits */
+#define MEMINTRSTR		_REG(0x11182) /* 16 bits */
 #define   MEM_RSEXIT_MASK	0xc000
 #define   MEM_RSEXIT_SHIFT	14
 #define   MEM_CONT_BUSY_MASK	0x3000
@@ -2652,7 +2663,7 @@ enum skl_disp_power_wells {
 #define   MEM_INT_STEER_CMR	1
 #define   MEM_INT_STEER_SMI	2
 #define   MEM_INT_STEER_SCI	3
-#define MEMINTRSTS		0x11184
+#define MEMINTRSTS		_REG(0x11184)
 #define   MEMINT_RSEXIT		(1<<7)
 #define   MEMINT_CONT_BUSY	(1<<6)
 #define   MEMINT_AVG_BUSY	(1<<5)
@@ -2661,7 +2672,7 @@ enum skl_disp_power_wells {
 #define   MEMINT_UP_EVAL	(1<<2)
 #define   MEMINT_DOWN_EVAL	(1<<1)
 #define   MEMINT_SW_CMD		(1<<0)
-#define MEMMODECTL		0x11190
+#define MEMMODECTL		_REG(0x11190)
 #define   MEMMODE_BOOST_EN	(1<<31)
 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
 #define   MEMMODE_BOOST_FREQ_SHIFT 24
@@ -2678,8 +2689,8 @@ enum skl_disp_power_wells {
 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
 #define   MEMMODE_FMAX_SHIFT	4
 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
-#define RCBMAXAVG		0x1119c
-#define MEMSWCTL2		0x1119e /* Cantiga only */
+#define RCBMAXAVG		_REG(0x1119c)
+#define MEMSWCTL2		_REG(0x1119e) /* Cantiga only */
 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
 #define   SWMEMCMD_RENDER_ON	(1 << 13)
 #define   SWMEMCMD_SWFREQ	(2 << 13)
@@ -2691,11 +2702,11 @@ enum skl_disp_power_wells {
 #define   SWFREQ_MASK		0x0380 /* P0-7 */
 #define   SWFREQ_SHIFT		7
 #define   TARVID_MASK		0x001f
-#define MEMSTAT_CTG		0x111a0
-#define RCBMINAVG		0x111a0
-#define RCUPEI			0x111b0
-#define RCDNEI			0x111b4
-#define RSTDBYCTL		0x111b8
+#define MEMSTAT_CTG		_REG(0x111a0)
+#define RCBMINAVG		_REG(0x111a0)
+#define RCUPEI			_REG(0x111b0)
+#define RCDNEI			_REG(0x111b4)
+#define RSTDBYCTL		_REG(0x111b8)
 #define   RS1EN			(1<<31)
 #define   RS2EN			(1<<30)
 #define   RS3EN			(1<<29)
@@ -2739,10 +2750,10 @@ enum skl_disp_power_wells {
 #define   RS_CSTATE_C367_RS2	(3<<4)
 #define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
 #define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
-#define VIDCTL			0x111c0
-#define VIDSTS			0x111c8
-#define VIDSTART		0x111cc /* 8 bits */
-#define MEMSTAT_ILK			0x111f8
+#define VIDCTL			_REG(0x111c0)
+#define VIDSTS			_REG(0x111c8)
+#define VIDSTART		_REG(0x111cc) /* 8 bits */
+#define MEMSTAT_ILK		_REG(0x111f8)
 #define   MEMSTAT_VID_MASK	0x7f00
 #define   MEMSTAT_VID_SHIFT	8
 #define   MEMSTAT_PSTATE_MASK	0x00f8
@@ -2753,55 +2764,55 @@ enum skl_disp_power_wells {
 #define   MEMSTAT_SRC_CTL_TRB	1
 #define   MEMSTAT_SRC_CTL_THM	2
 #define   MEMSTAT_SRC_CTL_STDBY 3
-#define RCPREVBSYTUPAVG		0x113b8
-#define RCPREVBSYTDNAVG		0x113bc
-#define PMMISC			0x11214
+#define RCPREVBSYTUPAVG		_REG(0x113b8)
+#define RCPREVBSYTDNAVG		_REG(0x113bc)
+#define PMMISC			_REG(0x11214)
 #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
-#define SDEW			0x1124c
-#define CSIEW0			0x11250
-#define CSIEW1			0x11254
-#define CSIEW2			0x11258
-#define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */
-#define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */
-#define MCHAFE			0x112c0
-#define CSIEC			0x112e0
-#define DMIEC			0x112e4
-#define DDREC			0x112e8
-#define PEG0EC			0x112ec
-#define PEG1EC			0x112f0
-#define GFXEC			0x112f4
-#define RPPREVBSYTUPAVG		0x113b8
-#define RPPREVBSYTDNAVG		0x113bc
-#define ECR			0x11600
+#define SDEW			_REG(0x1124c)
+#define CSIEW0			_REG(0x11250)
+#define CSIEW1			_REG(0x11254)
+#define CSIEW2			_REG(0x11258)
+#define PEW(i)			_REG(0x1125c + (i) * 4) /* 5 registers */
+#define DEW(i)			_REG(0x11270 + (i) * 4) /* 3 registers */
+#define MCHAFE			_REG(0x112c0)
+#define CSIEC			_REG(0x112e0)
+#define DMIEC			_REG(0x112e4)
+#define DDREC			_REG(0x112e8)
+#define PEG0EC			_REG(0x112ec)
+#define PEG1EC			_REG(0x112f0)
+#define GFXEC			_REG(0x112f4)
+#define RPPREVBSYTUPAVG		_REG(0x113b8)
+#define RPPREVBSYTDNAVG		_REG(0x113bc)
+#define ECR			_REG(0x11600)
 #define   ECR_GPFE		(1<<31)
 #define   ECR_IMONE		(1<<30)
 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
-#define OGW0			0x11608
-#define OGW1			0x1160c
-#define EG0			0x11610
-#define EG1			0x11614
-#define EG2			0x11618
-#define EG3			0x1161c
-#define EG4			0x11620
-#define EG5			0x11624
-#define EG6			0x11628
-#define EG7			0x1162c
-#define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */
-#define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */
-#define LCFUSE02		0x116c0
+#define OGW0			_REG(0x11608)
+#define OGW1			_REG(0x1160c)
+#define EG0			_REG(0x11610)
+#define EG1			_REG(0x11614)
+#define EG2			_REG(0x11618)
+#define EG3			_REG(0x1161c)
+#define EG4			_REG(0x11620)
+#define EG5			_REG(0x11624)
+#define EG6			_REG(0x11628)
+#define EG7			_REG(0x1162c)
+#define PXW(i)			_REG(0x11664 + (i) * 4) /* 4 registers */
+#define PXWL(i)			_REG(0x11680 + (i) * 8) /* 8 registers */
+#define LCFUSE02		_REG(0x116c0)
 #define   LCFUSE_HIV_MASK	0x000000ff
-#define CSIPLL0			0x12c10
-#define DDRMPLL1		0X12c20
-#define PEG_BAND_GAP_DATA	0x14d68
+#define CSIPLL0			_REG(0x12c10)
+#define DDRMPLL1		_REG(0X12c20)
+#define PEG_BAND_GAP_DATA	_REG(0x14d68)
 
-#define GEN6_GT_THREAD_STATUS_REG 0x13805c
+#define GEN6_GT_THREAD_STATUS_REG _REG(0x13805c)
 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
 
-#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
-#define BXT_GT_PERF_STATUS      (MCHBAR_MIRROR_BASE_SNB + 0x7070)
-#define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
-#define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
-#define BXT_RP_STATE_CAP        0x138170
+#define GEN6_GT_PERF_STATUS	_REG(MCHBAR_MIRROR_BASE_SNB + 0x5948)
+#define BXT_GT_PERF_STATUS      _REG(MCHBAR_MIRROR_BASE_SNB + 0x7070)
+#define GEN6_RP_STATE_LIMITS	_REG(MCHBAR_MIRROR_BASE_SNB + 0x5994)
+#define GEN6_RP_STATE_CAP	_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
+#define BXT_RP_STATE_CAP        _REG(0x138170)
 
 #define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
@@ -2812,7 +2823,7 @@ enum skl_disp_power_wells {
 /*
  * Logical Context regs
  */
-#define CCID			0x2180
+#define CCID			_REG(0x2180)
 #define   CCID_EN		(1<<0)
 /*
  * Notes on SNB/IVB/VLV context size:
@@ -2827,7 +2838,7 @@ enum skl_disp_power_wells {
  * - GT1 size just indicates how much of render context
  *   doesn't need saving on GT1
  */
-#define CXT_SIZE		0x21a0
+#define CXT_SIZE		_REG(0x21a0)
 #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
 #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
@@ -2836,7 +2847,7 @@ enum skl_disp_power_wells {
 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
-#define GEN7_CXT_SIZE		0x21a8
+#define GEN7_CXT_SIZE		_REG(0x21a8)
 #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
 #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
@@ -2856,23 +2867,23 @@ enum skl_disp_power_wells {
 /* Same as Haswell, but 72064 bytes now. */
 #define GEN8_CXT_TOTAL_SIZE		(18 * PAGE_SIZE)
 
-#define CHV_CLK_CTL1			0x101100
-#define VLV_CLK_CTL2			0x101104
+#define CHV_CLK_CTL1			_REG(0x101100)
+#define VLV_CLK_CTL2			_REG(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
 
 /*
  * Overlay regs
  */
 
-#define OVADD			0x30000
-#define DOVSTA			0x30008
+#define OVADD			_REG(0x30000)
+#define DOVSTA			_REG(0x30008)
 #define OC_BUF			(0x3<<20)
-#define OGAMC5			0x30010
-#define OGAMC4			0x30014
-#define OGAMC3			0x30018
-#define OGAMC2			0x3001c
-#define OGAMC1			0x30020
-#define OGAMC0			0x30024
+#define OGAMC5			_REG(0x30010)
+#define OGAMC4			_REG(0x30014)
+#define OGAMC3			_REG(0x30018)
+#define OGAMC2			_REG(0x3001c)
+#define OGAMC1			_REG(0x30020)
+#define OGAMC0			_REG(0x30024)
 
 /*
  * Display engine regs
@@ -2932,28 +2943,18 @@ enum skl_disp_power_wells {
 #define _PIPE_CRC_RES_4_B_IVB		0x61070
 #define _PIPE_CRC_RES_5_B_IVB		0x61074
 
-#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
-#define PIPE_CRC_RES_1_IVB(pipe)	\
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
-#define PIPE_CRC_RES_2_IVB(pipe)	\
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
-#define PIPE_CRC_RES_3_IVB(pipe)	\
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
-#define PIPE_CRC_RES_4_IVB(pipe)	\
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
-#define PIPE_CRC_RES_5_IVB(pipe)	\
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
-
-#define PIPE_CRC_RES_RED(pipe) \
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
-#define PIPE_CRC_RES_GREEN(pipe) \
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
-#define PIPE_CRC_RES_BLUE(pipe) \
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
-#define PIPE_CRC_RES_RES1_I915(pipe) \
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
-#define PIPE_CRC_RES_RES2_G4X(pipe) \
-	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
+#define PIPE_CRC_CTL(pipe)		_REG_TRANS2(pipe, _PIPE_CRC_CTL_A)
+#define PIPE_CRC_RES_1_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
+#define PIPE_CRC_RES_2_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
+#define PIPE_CRC_RES_3_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
+#define PIPE_CRC_RES_4_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
+#define PIPE_CRC_RES_5_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
+
+#define PIPE_CRC_RES_RED(pipe)		_REG_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
+#define PIPE_CRC_RES_GREEN(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
+#define PIPE_CRC_RES_BLUE(pipe)		_REG_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
+#define PIPE_CRC_RES_RES1_I915(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
+#define PIPE_CRC_RES_RES2_G4X(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
 
 /* Pipe A timing regs */
 #define _HTOTAL_A	0x60000
@@ -2985,20 +2986,20 @@ enum skl_disp_power_wells {
 #define CHV_TRANSCODER_C_OFFSET 0x63000
 #define TRANSCODER_EDP_OFFSET 0x6f000
 
-#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
+#define _REG_TRANS2(pipe, reg) _REG(dev_priv->info.trans_offsets[(pipe)] - \
 	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
 	dev_priv->info.display_mmio_offset)
 
-#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
-#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
-#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
-#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
-#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
-#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
-#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
-#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
-#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
-#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
+#define HTOTAL(trans)		_REG_TRANS2(trans, _HTOTAL_A)
+#define HBLANK(trans)		_REG_TRANS2(trans, _HBLANK_A)
+#define HSYNC(trans)		_REG_TRANS2(trans, _HSYNC_A)
+#define VTOTAL(trans)		_REG_TRANS2(trans, _VTOTAL_A)
+#define VBLANK(trans)		_REG_TRANS2(trans, _VBLANK_A)
+#define VSYNC(trans)		_REG_TRANS2(trans, _VSYNC_A)
+#define BCLRPAT(trans)		_REG_TRANS2(trans, _BCLRPAT_A)
+#define VSYNCSHIFT(trans)	_REG_TRANS2(trans, _VSYNCSHIFT_A)
+#define PIPESRC(trans)		_REG_TRANS2(trans, _PIPEASRC)
+#define PIPE_MULT(trans)	_REG_TRANS2(trans, _PIPE_MULT_A)
 
 /* VLV eDP PSR registers */
 #define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
@@ -3014,14 +3015,14 @@ enum skl_disp_power_wells {
 #define  VLV_EDP_PSR_DBL_FRAME			(1<<10)
 #define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff<<16)
 #define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
-#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
+#define VLV_PSRCTL(pipe)	_REG_PIPE(pipe, _PSRCTLA, _PSRCTLB)
 
 #define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
 #define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
 #define  VLV_EDP_PSR_SDP_FREQ_MASK	(3<<30)
 #define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1<<31)
 #define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1<<30)
-#define VLV_VSCSDP(pipe)	_PIPE(pipe, _VSCSDPA, _VSCSDPB)
+#define VLV_VSCSDP(pipe)	_REG_PIPE(pipe, _VSCSDPA, _VSCSDPB)
 
 #define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
 #define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
@@ -3034,12 +3035,12 @@ enum skl_disp_power_wells {
 #define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4<<0)
 #define  VLV_EDP_PSR_EXIT		(5<<0)
 #define  VLV_EDP_PSR_IN_TRANS		(1<<7)
-#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
+#define VLV_PSRSTAT(pipe)	_REG_PIPE(pipe, _PSRSTATA, _PSRSTATB)
 
 /* HSW+ eDP PSR registers */
 #define HSW_EDP_PSR_BASE	0x64800
 #define BDW_EDP_PSR_BASE	0x6f800
-#define EDP_PSR_CTL				(dev_priv->psr_mmio_base + 0)
+#define EDP_PSR_CTL				_REG(dev_priv->psr_mmio_base + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   BDW_PSR_SINGLE_FRAME			(1<<30)
 #define   EDP_PSR_LINK_STANDBY			(1<<27)
@@ -3062,10 +3063,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_TP1_TIME_0us			(3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
-#define EDP_PSR_AUX_CTL				(dev_priv->psr_mmio_base + 0x10)
-#define EDP_PSR_AUX_DATA(i)			(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_CTL				_REG(dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_DATA(i)			_REG(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS_CTL			(dev_priv->psr_mmio_base + 0x40)
+#define EDP_PSR_STATUS_CTL			_REG(dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
@@ -3089,15 +3090,15 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
 
-#define EDP_PSR_PERF_CNT		(dev_priv->psr_mmio_base + 0x44)
+#define EDP_PSR_PERF_CNT		_REG(dev_priv->psr_mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
-#define EDP_PSR_DEBUG_CTL		(dev_priv->psr_mmio_base + 0x60)
+#define EDP_PSR_DEBUG_CTL		_REG(dev_priv->psr_mmio_base + 0x60)
 #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
 
-#define EDP_PSR2_CTL			0x6f900
+#define EDP_PSR2_CTL			_REG(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
 #define   EDP_SU_TRACK_ENABLE		(1<<30)
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
@@ -3112,9 +3113,9 @@ enum skl_disp_power_wells {
 #define   EDP_PSR2_IDLE_MASK		0xf
 
 /* VGA port control */
-#define ADPA			0x61100
-#define PCH_ADPA                0xe1100
-#define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
+#define ADPA			_REG(0x61100)
+#define PCH_ADPA                _REG(0xe1100)
+#define VLV_ADPA		_REG(VLV_DISPLAY_BASE + 0x61100)
 
 #define   ADPA_DAC_ENABLE	(1<<31)
 #define   ADPA_DAC_DISABLE	0
@@ -3160,7 +3161,7 @@ enum skl_disp_power_wells {
 
 
 /* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN		_REG(dev_priv->info.display_mmio_offset + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
@@ -3190,7 +3191,7 @@ enum skl_disp_power_wells {
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
 
-#define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT	_REG(dev_priv->info.display_mmio_offset + 0x61114)
 /*
  * HDMI/DP bits are gen4+
  *
@@ -3255,21 +3256,23 @@ enum skl_disp_power_wells {
 
 /* SDVO and HDMI port control.
  * The same register may be used for SDVO or HDMI */
-#define GEN3_SDVOB	0x61140
-#define GEN3_SDVOC	0x61160
+#define _GEN3_SDVOB	0x61140
+#define _GEN3_SDVOC	0x61160
+#define GEN3_SDVOB	_REG(_GEN3_SDVOB)
+#define GEN3_SDVOC	_REG(_GEN3_SDVOC)
 #define GEN4_HDMIB	GEN3_SDVOB
 #define GEN4_HDMIC	GEN3_SDVOC
-#define VLV_HDMIB	(VLV_DISPLAY_BASE + GEN4_HDMIB)
-#define VLV_HDMIC	(VLV_DISPLAY_BASE + GEN4_HDMIC)
-#define CHV_HDMID	(VLV_DISPLAY_BASE + 0x6116C)
-#define PCH_SDVOB	0xe1140
+#define VLV_HDMIB	_REG(VLV_DISPLAY_BASE + 0x61140)
+#define VLV_HDMIC	_REG(VLV_DISPLAY_BASE + 0x61160)
+#define CHV_HDMID	_REG(VLV_DISPLAY_BASE + 0x6116C)
+#define PCH_SDVOB	_REG(0xe1140)
 #define PCH_HDMIB	PCH_SDVOB
-#define PCH_HDMIC	0xe1150
-#define PCH_HDMID	0xe1160
+#define PCH_HDMIC	_REG(0xe1150)
+#define PCH_HDMID	_REG(0xe1160)
 
-#define PORT_DFT_I9XX				0x61150
+#define PORT_DFT_I9XX				_REG(0x61150)
 #define   DC_BALANCE_RESET			(1 << 25)
-#define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
+#define PORT_DFT2_G4X		_REG(dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
 #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
@@ -3329,9 +3332,12 @@ enum skl_disp_power_wells {
 
 
 /* DVO port control */
-#define DVOA			0x61120
-#define DVOB			0x61140
-#define DVOC			0x61160
+#define _DVOA			0x61120
+#define DVOA			_REG(_DVOA)
+#define _DVOB			0x61140
+#define DVOB			_REG(_DVOB)
+#define _DVOC			0x61160
+#define DVOC			_REG(_DVOC)
 #define   DVO_ENABLE			(1 << 31)
 #define   DVO_PIPE_B_SELECT		(1 << 30)
 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
@@ -3356,14 +3362,14 @@ enum skl_disp_power_wells {
 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
 #define   DVO_PRESERVE_MASK		(0x7<<24)
-#define DVOA_SRCDIM		0x61124
-#define DVOB_SRCDIM		0x61144
-#define DVOC_SRCDIM		0x61164
+#define DVOA_SRCDIM		_REG(0x61124)
+#define DVOB_SRCDIM		_REG(0x61144)
+#define DVOC_SRCDIM		_REG(0x61164)
 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
 
 /* LVDS port control */
-#define LVDS			0x61180
+#define LVDS			_REG(0x61180)
 /*
  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
  * the DPLL semantics change when the LVDS is assigned to that pipe.
@@ -3413,13 +3419,13 @@ enum skl_disp_power_wells {
 #define   LVDS_B0B3_POWER_UP		(3 << 2)
 
 /* Video Data Island Packet control */
-#define VIDEO_DIP_DATA		0x61178
+#define VIDEO_DIP_DATA		_REG(0x61178)
 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE	32
 #define   VIDEO_DIP_VSC_DATA_SIZE	36
-#define VIDEO_DIP_CTL		0x61170
+#define VIDEO_DIP_CTL		_REG(0x61170)
 /* Pre HSW: */
 #define   VIDEO_DIP_ENABLE		(1 << 31)
 #define   VIDEO_DIP_PORT(port)		((port) << 29)
@@ -3446,7 +3452,7 @@ enum skl_disp_power_wells {
 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
 
 /* Panel power sequencing */
-#define PP_STATUS	0x61200
+#define PP_STATUS	_REG(0x61200)
 #define   PP_ON		(1 << 31)
 /*
  * Indicates that all dependencies of the panel are on:
@@ -3472,14 +3478,14 @@ enum skl_disp_power_wells {
 #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
 #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
 #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
-#define PP_CONTROL	0x61204
+#define PP_CONTROL	_REG(0x61204)
 #define   POWER_TARGET_ON	(1 << 0)
-#define PP_ON_DELAYS	0x61208
-#define PP_OFF_DELAYS	0x6120c
-#define PP_DIVISOR	0x61210
+#define PP_ON_DELAYS	_REG(0x61208)
+#define PP_OFF_DELAYS	_REG(0x6120c)
+#define PP_DIVISOR	_REG(0x61210)
 
 /* Panel fitting */
-#define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
+#define PFIT_CONTROL	_REG(dev_priv->info.display_mmio_offset + 0x61230)
 #define   PFIT_ENABLE		(1 << 31)
 #define   PFIT_PIPE_MASK	(3 << 29)
 #define   PFIT_PIPE_SHIFT	29
@@ -3497,7 +3503,7 @@ enum skl_disp_power_wells {
 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
 #define   PFIT_SCALING_PILLAR	(2 << 26)
 #define   PFIT_SCALING_LETTER	(3 << 26)
-#define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS _REG(dev_priv->info.display_mmio_offset + 0x61234)
 /* Pre-965 */
 #define		PFIT_VERT_SCALE_SHIFT		20
 #define		PFIT_VERT_SCALE_MASK		0xfff00000
@@ -3509,25 +3515,25 @@ enum skl_disp_power_wells {
 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
 
-#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS _REG(dev_priv->info.display_mmio_offset + 0x61238)
 
 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
-#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
-				     _VLV_BLC_PWM_CTL2_B)
+#define VLV_BLC_PWM_CTL2(pipe) _REG_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
+					 _VLV_BLC_PWM_CTL2_B)
 
 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
-#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
-				    _VLV_BLC_PWM_CTL_B)
+#define VLV_BLC_PWM_CTL(pipe) _REG_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
+					_VLV_BLC_PWM_CTL_B)
 
 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
-#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
-				     _VLV_BLC_HIST_CTL_B)
+#define VLV_BLC_HIST_CTL(pipe) _REG_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
+					 _VLV_BLC_HIST_CTL_B)
 
 /* Backlight control */
-#define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2	_REG(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE		(1 << 31)
 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT		(1 << 29)
@@ -3550,7 +3556,7 @@ enum skl_disp_power_wells {
 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
-#define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL	_REG(dev_priv->info.display_mmio_offset + 0x61254)
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.
@@ -3572,44 +3578,44 @@ enum skl_disp_power_wells {
 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
 
-#define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL	_REG(dev_priv->info.display_mmio_offset + 0x61260)
 #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
-#define BLC_PWM_CPU_CTL2	0x48250
-#define BLC_PWM_CPU_CTL		0x48254
+#define BLC_PWM_CPU_CTL2	_REG(0x48250)
+#define BLC_PWM_CPU_CTL		_REG(0x48254)
 
-#define HSW_BLC_PWM2_CTL	0x48350
+#define HSW_BLC_PWM2_CTL	_REG(0x48350)
 
 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
-#define BLC_PWM_PCH_CTL1	0xc8250
+#define BLC_PWM_PCH_CTL1	_REG(0xc8250)
 #define   BLM_PCH_PWM_ENABLE			(1 << 31)
 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
 #define   BLM_PCH_POLARITY			(1 << 29)
-#define BLC_PWM_PCH_CTL2	0xc8254
+#define BLC_PWM_PCH_CTL2	_REG(0xc8254)
 
-#define UTIL_PIN_CTL		0x48400
+#define UTIL_PIN_CTL		_REG(0x48400)
 #define   UTIL_PIN_ENABLE	(1 << 31)
 
 /* BXT backlight register definition. */
-#define BXT_BLC_PWM_CTL1			0xC8250
+#define BXT_BLC_PWM_CTL1			_REG(0xC8250)
 #define   BXT_BLC_PWM_ENABLE			(1 << 31)
 #define   BXT_BLC_PWM_POLARITY			(1 << 29)
-#define BXT_BLC_PWM_FREQ1			0xC8254
-#define BXT_BLC_PWM_DUTY1			0xC8258
+#define BXT_BLC_PWM_FREQ1			_REG(0xC8254)
+#define BXT_BLC_PWM_DUTY1			_REG(0xC8258)
 
-#define BXT_BLC_PWM_CTL2			0xC8350
-#define BXT_BLC_PWM_FREQ2			0xC8354
-#define BXT_BLC_PWM_DUTY2			0xC8358
+#define BXT_BLC_PWM_CTL2			_REG(0xC8350)
+#define BXT_BLC_PWM_FREQ2			_REG(0xC8354)
+#define BXT_BLC_PWM_DUTY2			_REG(0xC8358)
 
 
-#define PCH_GTC_CTL		0xe7000
+#define PCH_GTC_CTL		_REG(0xe7000)
 #define   PCH_GTC_ENABLE	(1 << 31)
 
 /* TV port control */
-#define TV_CTL			0x68000
+#define TV_CTL			_REG(0x68000)
 /* Enables the TV encoder */
 # define TV_ENC_ENABLE			(1 << 31)
 /* Sources the TV encoder input from pipe B instead of A. */
@@ -3676,7 +3682,7 @@ enum skl_disp_power_wells {
 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
 # define TV_TEST_MODE_MASK		(7 << 0)
 
-#define TV_DAC			0x68004
+#define TV_DAC			_REG(0x68004)
 # define TV_DAC_SAVE		0x00ffff00
 /*
  * Reports that DAC state change logic has reported change (RO).
@@ -3727,13 +3733,13 @@ enum skl_disp_power_wells {
  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
  * -1 (0x3) being the only legal negative value.
  */
-#define TV_CSC_Y		0x68010
+#define TV_CSC_Y		_REG(0x68010)
 # define TV_RY_MASK			0x07ff0000
 # define TV_RY_SHIFT			16
 # define TV_GY_MASK			0x00000fff
 # define TV_GY_SHIFT			0
 
-#define TV_CSC_Y2		0x68014
+#define TV_CSC_Y2		_REG(0x68014)
 # define TV_BY_MASK			0x07ff0000
 # define TV_BY_SHIFT			16
 /*
@@ -3744,13 +3750,13 @@ enum skl_disp_power_wells {
 # define TV_AY_MASK			0x000003ff
 # define TV_AY_SHIFT			0
 
-#define TV_CSC_U		0x68018
+#define TV_CSC_U		_REG(0x68018)
 # define TV_RU_MASK			0x07ff0000
 # define TV_RU_SHIFT			16
 # define TV_GU_MASK			0x000007ff
 # define TV_GU_SHIFT			0
 
-#define TV_CSC_U2		0x6801c
+#define TV_CSC_U2		_REG(0x6801c)
 # define TV_BU_MASK			0x07ff0000
 # define TV_BU_SHIFT			16
 /*
@@ -3761,13 +3767,13 @@ enum skl_disp_power_wells {
 # define TV_AU_MASK			0x000003ff
 # define TV_AU_SHIFT			0
 
-#define TV_CSC_V		0x68020
+#define TV_CSC_V		_REG(0x68020)
 # define TV_RV_MASK			0x0fff0000
 # define TV_RV_SHIFT			16
 # define TV_GV_MASK			0x000007ff
 # define TV_GV_SHIFT			0
 
-#define TV_CSC_V2		0x68024
+#define TV_CSC_V2		_REG(0x68024)
 # define TV_BV_MASK			0x07ff0000
 # define TV_BV_SHIFT			16
 /*
@@ -3778,7 +3784,7 @@ enum skl_disp_power_wells {
 # define TV_AV_MASK			0x000007ff
 # define TV_AV_SHIFT			0
 
-#define TV_CLR_KNOBS		0x68028
+#define TV_CLR_KNOBS		_REG(0x68028)
 /* 2s-complement brightness adjustment */
 # define TV_BRIGHTNESS_MASK		0xff000000
 # define TV_BRIGHTNESS_SHIFT		24
@@ -3792,7 +3798,7 @@ enum skl_disp_power_wells {
 # define TV_HUE_MASK			0x000000ff
 # define TV_HUE_SHIFT			0
 
-#define TV_CLR_LEVEL		0x6802c
+#define TV_CLR_LEVEL		_REG(0x6802c)
 /* Controls the DAC level for black */
 # define TV_BLACK_LEVEL_MASK		0x01ff0000
 # define TV_BLACK_LEVEL_SHIFT		16
@@ -3800,7 +3806,7 @@ enum skl_disp_power_wells {
 # define TV_BLANK_LEVEL_MASK		0x000001ff
 # define TV_BLANK_LEVEL_SHIFT		0
 
-#define TV_H_CTL_1		0x68030
+#define TV_H_CTL_1		_REG(0x68030)
 /* Number of pixels in the hsync. */
 # define TV_HSYNC_END_MASK		0x1fff0000
 # define TV_HSYNC_END_SHIFT		16
@@ -3808,7 +3814,7 @@ enum skl_disp_power_wells {
 # define TV_HTOTAL_MASK			0x00001fff
 # define TV_HTOTAL_SHIFT		0
 
-#define TV_H_CTL_2		0x68034
+#define TV_H_CTL_2		_REG(0x68034)
 /* Enables the colorburst (needed for non-component color) */
 # define TV_BURST_ENA			(1 << 31)
 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
@@ -3818,7 +3824,7 @@ enum skl_disp_power_wells {
 # define TV_HBURST_LEN_SHIFT		0
 # define TV_HBURST_LEN_MASK		0x0001fff
 
-#define TV_H_CTL_3		0x68038
+#define TV_H_CTL_3		_REG(0x68038)
 /* End of hblank, measured in pixels minus one from start of hsync */
 # define TV_HBLANK_END_SHIFT		16
 # define TV_HBLANK_END_MASK		0x1fff0000
@@ -3826,7 +3832,7 @@ enum skl_disp_power_wells {
 # define TV_HBLANK_START_SHIFT		0
 # define TV_HBLANK_START_MASK		0x0001fff
 
-#define TV_V_CTL_1		0x6803c
+#define TV_V_CTL_1		_REG(0x6803c)
 /* XXX */
 # define TV_NBR_END_SHIFT		16
 # define TV_NBR_END_MASK		0x07ff0000
@@ -3837,7 +3843,7 @@ enum skl_disp_power_wells {
 # define TV_VI_END_F2_SHIFT		0
 # define TV_VI_END_F2_MASK		0x0000003f
 
-#define TV_V_CTL_2		0x68040
+#define TV_V_CTL_2		_REG(0x68040)
 /* Length of vsync, in half lines */
 # define TV_VSYNC_LEN_MASK		0x07ff0000
 # define TV_VSYNC_LEN_SHIFT		16
@@ -3853,7 +3859,7 @@ enum skl_disp_power_wells {
 # define TV_VSYNC_START_F2_MASK		0x0000007f
 # define TV_VSYNC_START_F2_SHIFT	0
 
-#define TV_V_CTL_3		0x68044
+#define TV_V_CTL_3		_REG(0x68044)
 /* Enables generation of the equalization signal */
 # define TV_EQUAL_ENA			(1 << 31)
 /* Length of vsync, in half lines */
@@ -3871,7 +3877,7 @@ enum skl_disp_power_wells {
 # define TV_VEQ_START_F2_MASK		0x000007f
 # define TV_VEQ_START_F2_SHIFT		0
 
-#define TV_V_CTL_4		0x68048
+#define TV_V_CTL_4		_REG(0x68048)
 /*
  * Offset to start of vertical colorburst, measured in one less than the
  * number of lines from vertical start.
@@ -3885,7 +3891,7 @@ enum skl_disp_power_wells {
 # define TV_VBURST_END_F1_MASK		0x000000ff
 # define TV_VBURST_END_F1_SHIFT		0
 
-#define TV_V_CTL_5		0x6804c
+#define TV_V_CTL_5		_REG(0x6804c)
 /*
  * Offset to start of vertical colorburst, measured in one less than the
  * number of lines from vertical start.
@@ -3899,7 +3905,7 @@ enum skl_disp_power_wells {
 # define TV_VBURST_END_F2_MASK		0x000000ff
 # define TV_VBURST_END_F2_SHIFT		0
 
-#define TV_V_CTL_6		0x68050
+#define TV_V_CTL_6		_REG(0x68050)
 /*
  * Offset to start of vertical colorburst, measured in one less than the
  * number of lines from vertical start.
@@ -3913,7 +3919,7 @@ enum skl_disp_power_wells {
 # define TV_VBURST_END_F3_MASK		0x000000ff
 # define TV_VBURST_END_F3_SHIFT		0
 
-#define TV_V_CTL_7		0x68054
+#define TV_V_CTL_7		_REG(0x68054)
 /*
  * Offset to start of vertical colorburst, measured in one less than the
  * number of lines from vertical start.
@@ -3927,7 +3933,7 @@ enum skl_disp_power_wells {
 # define TV_VBURST_END_F4_MASK		0x000000ff
 # define TV_VBURST_END_F4_SHIFT		0
 
-#define TV_SC_CTL_1		0x68060
+#define TV_SC_CTL_1		_REG(0x68060)
 /* Turns on the first subcarrier phase generation DDA */
 # define TV_SC_DDA1_EN			(1 << 31)
 /* Turns on the first subcarrier phase generation DDA */
@@ -3949,7 +3955,7 @@ enum skl_disp_power_wells {
 # define TV_SCDDA1_INC_MASK		0x00000fff
 # define TV_SCDDA1_INC_SHIFT		0
 
-#define TV_SC_CTL_2		0x68064
+#define TV_SC_CTL_2		_REG(0x68064)
 /* Sets the rollover for the second subcarrier phase generation DDA */
 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
 # define TV_SCDDA2_SIZE_SHIFT		16
@@ -3957,7 +3963,7 @@ enum skl_disp_power_wells {
 # define TV_SCDDA2_INC_MASK		0x00007fff
 # define TV_SCDDA2_INC_SHIFT		0
 
-#define TV_SC_CTL_3		0x68068
+#define TV_SC_CTL_3		_REG(0x68068)
 /* Sets the rollover for the third subcarrier phase generation DDA */
 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
 # define TV_SCDDA3_SIZE_SHIFT		16
@@ -3965,7 +3971,7 @@ enum skl_disp_power_wells {
 # define TV_SCDDA3_INC_MASK		0x00007fff
 # define TV_SCDDA3_INC_SHIFT		0
 
-#define TV_WIN_POS		0x68070
+#define TV_WIN_POS		_REG(0x68070)
 /* X coordinate of the display from the start of horizontal active */
 # define TV_XPOS_MASK			0x1fff0000
 # define TV_XPOS_SHIFT			16
@@ -3973,7 +3979,7 @@ enum skl_disp_power_wells {
 # define TV_YPOS_MASK			0x00000fff
 # define TV_YPOS_SHIFT			0
 
-#define TV_WIN_SIZE		0x68074
+#define TV_WIN_SIZE		_REG(0x68074)
 /* Horizontal size of the display window, measured in pixels*/
 # define TV_XSIZE_MASK			0x1fff0000
 # define TV_XSIZE_SHIFT			16
@@ -3985,7 +3991,7 @@ enum skl_disp_power_wells {
 # define TV_YSIZE_MASK			0x00000fff
 # define TV_YSIZE_SHIFT			0
 
-#define TV_FILTER_CTL_1		0x68080
+#define TV_FILTER_CTL_1		_REG(0x68080)
 /*
  * Enables automatic scaling calculation.
  *
@@ -4018,7 +4024,7 @@ enum skl_disp_power_wells {
 # define TV_HSCALE_FRAC_MASK		0x00003fff
 # define TV_HSCALE_FRAC_SHIFT		0
 
-#define TV_FILTER_CTL_2		0x68084
+#define TV_FILTER_CTL_2		_REG(0x68084)
 /*
  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  *
@@ -4034,7 +4040,7 @@ enum skl_disp_power_wells {
 # define TV_VSCALE_FRAC_MASK		0x00007fff
 # define TV_VSCALE_FRAC_SHIFT		0
 
-#define TV_FILTER_CTL_3		0x68088
+#define TV_FILTER_CTL_3		_REG(0x68088)
 /*
  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  *
@@ -4054,7 +4060,7 @@ enum skl_disp_power_wells {
 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
 # define TV_VSCALE_IP_FRAC_SHIFT		0
 
-#define TV_CC_CONTROL		0x68090
+#define TV_CC_CONTROL		_REG(0x68090)
 # define TV_CC_ENABLE			(1 << 31)
 /*
  * Specifies which field to send the CC data in.
@@ -4070,7 +4076,7 @@ enum skl_disp_power_wells {
 # define TV_CC_LINE_MASK		0x0000003f
 # define TV_CC_LINE_SHIFT		0
 
-#define TV_CC_DATA		0x68094
+#define TV_CC_DATA		_REG(0x68094)
 # define TV_CC_RDY			(1 << 31)
 /* Second word of CC data to be transmitted. */
 # define TV_CC_DATA_2_MASK		0x007f0000
@@ -4079,20 +4085,20 @@ enum skl_disp_power_wells {
 # define TV_CC_DATA_1_MASK		0x0000007f
 # define TV_CC_DATA_1_SHIFT		0
 
-#define TV_H_LUMA(i)		(0x68100 + (i) * 4) /* 60 registers */
-#define TV_H_CHROMA(i)		(0x68200 + (i) * 4) /* 60 registers */
-#define TV_V_LUMA(i)		(0x68300 + (i) * 4) /* 43 registers */
-#define TV_V_CHROMA(i)		(0x68400 + (i) * 4) /* 43 registers */
+#define TV_H_LUMA(i)		_REG(0x68100 + (i) * 4) /* 60 registers */
+#define TV_H_CHROMA(i)		_REG(0x68200 + (i) * 4) /* 60 registers */
+#define TV_V_LUMA(i)		_REG(0x68300 + (i) * 4) /* 43 registers */
+#define TV_V_CHROMA(i)		_REG(0x68400 + (i) * 4) /* 43 registers */
 
 /* Display Port */
-#define DP_A				0x64000 /* eDP */
-#define DP_B				0x64100
-#define DP_C				0x64200
-#define DP_D				0x64300
+#define DP_A			_REG(0x64000) /* eDP */
+#define DP_B			_REG(0x64100)
+#define DP_C			_REG(0x64200)
+#define DP_D			_REG(0x64300)
 
-#define VLV_DP_B			(VLV_DISPLAY_BASE + DP_B)
-#define VLV_DP_C			(VLV_DISPLAY_BASE + DP_C)
-#define CHV_DP_D			(VLV_DISPLAY_BASE + DP_D)
+#define VLV_DP_B		_REG(VLV_DISPLAY_BASE + 0x64100)
+#define VLV_DP_C		_REG(VLV_DISPLAY_BASE + 0x64200)
+#define CHV_DP_D		_REG(VLV_DISPLAY_BASE + 0x64300)
 
 #define   DP_PORT_EN			(1 << 31)
 #define   DP_PIPEB_SELECT		(1 << 30)
@@ -4207,8 +4213,8 @@ enum skl_disp_power_wells {
 #define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
 #define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
 
-#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
-#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define DP_AUX_CH_CTL(port)	_REG_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
+#define DP_AUX_CH_DATA(port, i)	_REG(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
@@ -4285,10 +4291,10 @@ enum skl_disp_power_wells {
 #define _PIPEB_LINK_N_G4X	0x71064
 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
 
-#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
-#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
-#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
-#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
+#define PIPE_DATA_M_G4X(pipe) _REG_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
+#define PIPE_DATA_N_G4X(pipe) _REG_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
+#define PIPE_LINK_M_G4X(pipe) _REG_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
+#define PIPE_LINK_N_G4X(pipe) _REG_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
 
 /* Display & cursor control */
 
@@ -4404,15 +4410,15 @@ enum skl_disp_power_wells {
  */
 #define PIPE_EDP_OFFSET	0x7f000
 
-#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
+#define _REG_PIPE2(pipe, reg) _REG(dev_priv->info.pipe_offsets[pipe] - \
 	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
 	dev_priv->info.display_mmio_offset)
 
-#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
-#define PIPEDSL(pipe)  _PIPE2(pipe, _PIPEADSL)
-#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
-#define PIPEFRAMEPIXEL(pipe)  _PIPE2(pipe, _PIPEAFRAMEPIXEL)
-#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
+#define PIPECONF(pipe)		_REG_PIPE2(pipe, _PIPEACONF)
+#define PIPEDSL(pipe)		_REG_PIPE2(pipe, _PIPEADSL)
+#define PIPEFRAME(pipe)		_REG_PIPE2(pipe, _PIPEAFRAMEHIGH)
+#define PIPEFRAMEPIXEL(pipe)	_REG_PIPE2(pipe, _PIPEAFRAMEPIXEL)
+#define PIPESTAT(pipe)		_REG_PIPE2(pipe, _PIPEASTAT)
 
 #define _PIPE_MISC_A			0x70030
 #define _PIPE_MISC_B			0x71030
@@ -4424,9 +4430,9 @@ enum skl_disp_power_wells {
 #define   PIPEMISC_DITHER_ENABLE	(1<<4)
 #define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)
 #define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
-#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
+#define PIPEMISC(pipe)			_REG_PIPE2(pipe, _PIPE_MISC_A)
 
-#define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
+#define VLV_DPFLIPSTAT				_REG(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
 #define   PIPEB_HLINE_INT_EN			(1<<28)
 #define   PIPEB_VBLANK_INT_EN			(1<<27)
@@ -4447,7 +4453,7 @@ enum skl_disp_power_wells {
 #define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
 #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
 
-#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
+#define DPINVGTT				_REG(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
 #define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
 #define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
 #define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
@@ -4477,7 +4483,7 @@ enum skl_disp_power_wells {
 #define   DPINVGTT_STATUS_MASK			0xff
 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
-#define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
+#define DSPARB			_REG(dev_priv->info.display_mmio_offset + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)
@@ -4492,7 +4498,7 @@ enum skl_disp_power_wells {
 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
 #define   DSPARB_SPRITED_SHIFT_VLV	24
 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
-#define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
+#define DSPARB2				_REG(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
 #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
@@ -4505,14 +4511,14 @@ enum skl_disp_power_wells {
 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
 #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
-#define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
+#define DSPARB3				_REG(VLV_DISPLAY_BASE + 0x7006c) /* chv */
 #define   DSPARB_SPRITEE_SHIFT_VLV	0
 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
 #define   DSPARB_SPRITEF_SHIFT_VLV	8
 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
 
 /* pnv/gen4/g4x/vlv/chv */
-#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
+#define DSPFW1		_REG(dev_priv->info.display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT		23
 #define   DSPFW_SR_MASK			(0x1ff<<23)
 #define   DSPFW_CURSORB_SHIFT		16
@@ -4523,7 +4529,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_PLANEA_SHIFT		0
 #define   DSPFW_PLANEA_MASK		(0x7f<<0)
 #define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
-#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
+#define DSPFW2		_REG(dev_priv->info.display_mmio_offset + 0x70038)
 #define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
 #define   DSPFW_FBC_SR_SHIFT		28
 #define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
@@ -4539,7 +4545,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_SPRITEA_SHIFT		0
 #define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
 #define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
-#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
+#define DSPFW3		_REG(dev_priv->info.display_mmio_offset + 0x7003c)
 #define   DSPFW_HPLL_SR_EN		(1<<31)
 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
 #define   DSPFW_CURSOR_SR_SHIFT		24
@@ -4550,14 +4556,14 @@ enum skl_disp_power_wells {
 #define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
 
 /* vlv/chv */
-#define DSPFW4			(VLV_DISPLAY_BASE + 0x70070)
+#define DSPFW4		_REG(VLV_DISPLAY_BASE + 0x70070)
 #define   DSPFW_SPRITEB_WM1_SHIFT	16
 #define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
 #define   DSPFW_CURSORA_WM1_SHIFT	8
 #define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
 #define   DSPFW_SPRITEA_WM1_SHIFT	0
 #define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
-#define DSPFW5			(VLV_DISPLAY_BASE + 0x70074)
+#define DSPFW5		_REG(VLV_DISPLAY_BASE + 0x70074)
 #define   DSPFW_PLANEB_WM1_SHIFT	24
 #define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
 #define   DSPFW_PLANEA_WM1_SHIFT	16
@@ -4566,11 +4572,11 @@ enum skl_disp_power_wells {
 #define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
-#define DSPFW6			(VLV_DISPLAY_BASE + 0x70078)
+#define DSPFW6		_REG(VLV_DISPLAY_BASE + 0x70078)
 #define   DSPFW_SR_WM1_SHIFT		0
 #define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
-#define DSPFW7			(VLV_DISPLAY_BASE + 0x7007c)
-#define DSPFW7_CHV		(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
+#define DSPFW7		_REG(VLV_DISPLAY_BASE + 0x7007c)
+#define DSPFW7_CHV	_REG(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
 #define   DSPFW_SPRITED_WM1_SHIFT	24
 #define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
 #define   DSPFW_SPRITED_SHIFT		16
@@ -4579,7 +4585,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
 #define   DSPFW_SPRITEC_SHIFT		0
 #define   DSPFW_SPRITEC_MASK_VLV	(0xff<<0)
-#define DSPFW8_CHV		(VLV_DISPLAY_BASE + 0x700b8)
+#define DSPFW8_CHV	_REG(VLV_DISPLAY_BASE + 0x700b8)
 #define   DSPFW_SPRITEF_WM1_SHIFT	24
 #define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
 #define   DSPFW_SPRITEF_SHIFT		16
@@ -4588,7 +4594,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
 #define   DSPFW_SPRITEE_SHIFT		0
 #define   DSPFW_SPRITEE_MASK_VLV	(0xff<<0)
-#define DSPFW9_CHV		(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
+#define DSPFW9_CHV	_REG(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
 #define   DSPFW_PLANEC_WM1_SHIFT	24
 #define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
 #define   DSPFW_PLANEC_SHIFT		16
@@ -4599,7 +4605,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_CURSORC_MASK		(0x3f<<0)
 
 /* vlv/chv high order bits */
-#define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
+#define DSPHOWM		_REG(VLV_DISPLAY_BASE + 0x70064)
 #define   DSPFW_SR_HI_SHIFT		24
 #define   DSPFW_SR_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
 #define   DSPFW_SPRITEF_HI_SHIFT	23
@@ -4620,7 +4626,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_SPRITEA_HI_MASK		(1<<4)
 #define   DSPFW_PLANEA_HI_SHIFT		0
 #define   DSPFW_PLANEA_HI_MASK		(1<<0)
-#define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70068)
+#define DSPHOWM1	_REG(VLV_DISPLAY_BASE + 0x70068)
 #define   DSPFW_SR_WM1_HI_SHIFT		24
 #define   DSPFW_SR_WM1_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
 #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
@@ -4643,7 +4649,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
 
 /* drain latency register values*/
-#define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
+#define VLV_DDL(pipe)			_REG(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
 #define DDL_CURSOR_SHIFT		24
 #define DDL_SPRITE_SHIFT(sprite)	(8+8*(sprite))
 #define DDL_PLANE_SHIFT			0
@@ -4651,7 +4657,7 @@ enum skl_disp_power_wells {
 #define DDL_PRECISION_LOW		(0<<7)
 #define DRAIN_LATENCY_MASK		0x7f
 
-#define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
+#define CBR1_VLV			_REG(VLV_DISPLAY_BASE + 0x70400)
 #define  CBR_PND_DEADLINE_DISABLE	(1<<31)
 #define  CBR_PWM_CLOCK_MUX_SELECT	(1<<30)
 
@@ -4707,33 +4713,33 @@ enum skl_disp_power_wells {
 #define   PLANE_WM_BLOCKS_MASK	0x3ff
 
 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
-#define CUR_WM(pipe, level) (_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_TRANS(pipe) _PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
+#define CUR_WM(pipe, level) _REG(_CUR_WM_0(pipe) + ((4) * (level)))
+#define CUR_WM_TRANS(pipe) _REG_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
 
 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
 #define _PLANE_WM_BASE(pipe, plane)	\
 			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
 #define PLANE_WM(pipe, plane, level)	\
-			(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+			_REG(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
 #define _PLANE_WM_TRANS_1(pipe)	\
 			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
 #define _PLANE_WM_TRANS_2(pipe)	\
 			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
 #define PLANE_WM_TRANS(pipe, plane)	\
-		_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
+	_REG(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
 
 /* define the Watermark register on Ironlake */
-#define WM0_PIPEA_ILK		0x45100
+#define WM0_PIPEA_ILK		_REG(0x45100)
 #define  WM0_PIPE_PLANE_MASK	(0xffff<<16)
 #define  WM0_PIPE_PLANE_SHIFT	16
 #define  WM0_PIPE_SPRITE_MASK	(0xff<<8)
 #define  WM0_PIPE_SPRITE_SHIFT	8
 #define  WM0_PIPE_CURSOR_MASK	(0xff)
 
-#define WM0_PIPEB_ILK		0x45104
-#define WM0_PIPEC_IVB		0x45200
-#define WM1_LP_ILK		0x45108
+#define WM0_PIPEB_ILK		_REG(0x45104)
+#define WM0_PIPEC_IVB		_REG(0x45200)
+#define WM1_LP_ILK		_REG(0x45108)
 #define  WM1_LP_SR_EN		(1<<31)
 #define  WM1_LP_LATENCY_SHIFT	24
 #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
@@ -4743,13 +4749,13 @@ enum skl_disp_power_wells {
 #define  WM1_LP_SR_MASK		(0x7ff<<8)
 #define  WM1_LP_SR_SHIFT	8
 #define  WM1_LP_CURSOR_MASK	(0xff)
-#define WM2_LP_ILK		0x4510c
+#define WM2_LP_ILK		_REG(0x4510c)
 #define  WM2_LP_EN		(1<<31)
-#define WM3_LP_ILK		0x45110
+#define WM3_LP_ILK		_REG(0x45110)
 #define  WM3_LP_EN		(1<<31)
-#define WM1S_LP_ILK		0x45120
-#define WM2S_LP_IVB		0x45124
-#define WM3S_LP_IVB		0x45128
+#define WM1S_LP_ILK		_REG(0x45120)
+#define WM2S_LP_IVB		_REG(0x45124)
+#define WM3S_LP_IVB		_REG(0x45128)
 #define  WM1S_LP_EN		(1<<31)
 
 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
@@ -4757,7 +4763,7 @@ enum skl_disp_power_wells {
 	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
 
 /* Memory latency timer register */
-#define MLTR_ILK		0x11222
+#define MLTR_ILK		_REG(0x11222)
 #define  MLTR_WM1_SHIFT		0
 #define  MLTR_WM2_SHIFT		8
 /* the unit of memory self-refresh latency time is 0.5us */
@@ -4765,7 +4771,7 @@ enum skl_disp_power_wells {
 
 
 /* the address where we get all kinds of latency value */
-#define SSKPD			0x5d10
+#define SSKPD			_REG(0x5d10)
 #define SSKPD_WM_MASK		0x3f
 #define SSKPD_WM0_SHIFT		0
 #define SSKPD_WM1_SHIFT		8
@@ -4798,8 +4804,8 @@ enum skl_disp_power_wells {
 /* GM45+ just has to be different */
 #define _PIPEA_FRMCOUNT_G4X	0x70040
 #define _PIPEA_FLIPCOUNT_G4X	0x70044
-#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
-#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
+#define PIPE_FRMCOUNT_G4X(pipe) _REG_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
+#define PIPE_FLIPCOUNT_G4X(pipe) _REG_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
 
 /* Cursor A & B regs */
 #define _CURACNTR		0x70080
@@ -4837,7 +4843,7 @@ enum skl_disp_power_wells {
 #define   CURSOR_POS_SIGN       0x8000
 #define   CURSOR_X_SHIFT        0
 #define   CURSOR_Y_SHIFT        16
-#define CURSIZE			0x700a0
+#define CURSIZE			_REG(0x700a0)
 #define _CURBCNTR		0x700c0
 #define _CURBBASE		0x700c4
 #define _CURBPOS		0x700c8
@@ -4846,7 +4852,7 @@ enum skl_disp_power_wells {
 #define _CURBBASE_IVB		0x71084
 #define _CURBPOS_IVB		0x71088
 
-#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
+#define _CURSOR2(pipe, reg) _REG(dev_priv->info.cursor_offsets[(pipe)] - \
 	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
 	dev_priv->info.display_mmio_offset)
 
@@ -4907,16 +4913,16 @@ enum skl_disp_power_wells {
 #define _DSPAOFFSET				0x701A4 /* HSW */
 #define _DSPASURFLIVE				0x701AC
 
-#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
-#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
-#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
-#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
-#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
-#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
-#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
-#define DSPLINOFF(plane) DSPADDR(plane)
-#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
-#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
+#define DSPCNTR(plane)		_REG_PIPE2(plane, _DSPACNTR)
+#define DSPADDR(plane)		_REG_PIPE2(plane, _DSPAADDR)
+#define DSPSTRIDE(plane)	_REG_PIPE2(plane, _DSPASTRIDE)
+#define DSPPOS(plane)		_REG_PIPE2(plane, _DSPAPOS)
+#define DSPSIZE(plane)		_REG_PIPE2(plane, _DSPASIZE)
+#define DSPSURF(plane)		_REG_PIPE2(plane, _DSPASURF)
+#define DSPTILEOFF(plane)	_REG_PIPE2(plane, _DSPATILEOFF)
+#define DSPLINOFF(plane)	DSPADDR(plane)
+#define DSPOFFSET(plane)	_REG_PIPE2(plane, _DSPAOFFSET)
+#define DSPSURFLIVE(plane)	_REG_PIPE2(plane, _DSPASURFLIVE)
 
 /* CHV pipe B blender and primary plane */
 #define _CHV_BLEND_A		0x60a00
@@ -4930,11 +4936,11 @@ enum skl_disp_power_wells {
 #define _PRIMCNSTALPHA_A	0x60a10
 #define   PRIM_CONST_ALPHA_ENABLE	(1<<31)
 
-#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
-#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
-#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
-#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
-#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
+#define CHV_BLEND(pipe)		_REG_TRANS2(pipe, _CHV_BLEND_A)
+#define CHV_CANVAS(pipe)	_REG_TRANS2(pipe, _CHV_CANVAS_A)
+#define PRIMPOS(plane)		_REG_TRANS2(plane, _PRIMPOS_A)
+#define PRIMSIZE(plane)		_REG_TRANS2(plane, _PRIMSIZE_A)
+#define PRIMCNSTALPHA(plane)	_REG_TRANS2(plane, _PRIMCNSTALPHA_A)
 
 /* Display/Sprite base address macros */
 #define DISP_BASEADDR_MASK	(0xfffff000)
@@ -4952,9 +4958,9 @@ enum skl_disp_power_wells {
  * [10:1f] all
  * [30:32] all
  */
-#define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
-#define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
-#define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
+#define SWF0(i)	_REG(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i)	_REG(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i)	_REG(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
 
 /* Pipe B */
 #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
@@ -5036,18 +5042,18 @@ enum skl_disp_power_wells {
 #define _DVSBSCALE		0x73204
 #define _DVSBGAMC		0x73300
 
-#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
-#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
-#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
-#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
-#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
-#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
-#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
-#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
-#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
-#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
-#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
-#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
+#define DVSCNTR(pipe) _REG_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
+#define DVSLINOFF(pipe) _REG_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
+#define DVSSTRIDE(pipe) _REG_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+#define DVSPOS(pipe) _REG_PIPE(pipe, _DVSAPOS, _DVSBPOS)
+#define DVSSURF(pipe) _REG_PIPE(pipe, _DVSASURF, _DVSBSURF)
+#define DVSKEYMAX(pipe) _REG_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
+#define DVSSIZE(pipe) _REG_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
+#define DVSSCALE(pipe) _REG_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
+#define DVSTILEOFF(pipe) _REG_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define DVSKEYVAL(pipe) _REG_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+#define DVSKEYMSK(pipe) _REG_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
+#define DVSSURFLIVE(pipe) _REG_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
 
 #define _SPRA_CTL		0x70280
 #define   SPRITE_ENABLE			(1<<31)
@@ -5110,20 +5116,20 @@ enum skl_disp_power_wells {
 #define _SPRB_SCALE		0x71304
 #define _SPRB_GAMC		0x71400
 
-#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
-#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
-#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
-#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
-#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
-#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
-#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
-#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
-#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
-#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
-#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
-#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
-#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
-#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+#define SPRCTL(pipe) _REG_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
+#define SPRLINOFF(pipe) _REG_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
+#define SPRSTRIDE(pipe) _REG_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
+#define SPRPOS(pipe) _REG_PIPE(pipe, _SPRA_POS, _SPRB_POS)
+#define SPRSIZE(pipe) _REG_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
+#define SPRKEYVAL(pipe) _REG_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
+#define SPRKEYMSK(pipe) _REG_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
+#define SPRSURF(pipe) _REG_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
+#define SPRKEYMAX(pipe) _REG_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
+#define SPRTILEOFF(pipe) _REG_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
+#define SPROFFSET(pipe) _REG_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
+#define SPRSCALE(pipe) _REG_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
+#define SPRGAMC(pipe) _REG_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
+#define SPRSURFLIVE(pipe) _REG_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
 
 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
 #define   SP_ENABLE			(1<<31)
@@ -5173,18 +5179,18 @@ enum skl_disp_power_wells {
 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
 
-#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
+#define SPCNTR(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
 
 /*
  * CHV pipe B sprite CSC
@@ -5193,29 +5199,29 @@ enum skl_disp_power_wells {
  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
  */
-#define SPCSCYGOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
-#define SPCSCCBOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
-#define SPCSCCROFF(sprite)	(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
+#define SPCSCYGOFF(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
+#define SPCSCCBOFF(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
+#define SPCSCCROFF(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
 
-#define SPCSCC01(sprite)	(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
-#define SPCSCC23(sprite)	(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
-#define SPCSCC45(sprite)	(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
-#define SPCSCC67(sprite)	(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
-#define SPCSCC8(sprite)		(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
+#define SPCSCC01(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
+#define SPCSCC23(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
+#define SPCSCC45(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
+#define SPCSCC67(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
+#define SPCSCC8(sprite)		_REG(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
 
-#define SPCSCYGICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
-#define SPCSCCBICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
-#define SPCSCCRICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
+#define SPCSCYGICLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
+#define SPCSCCBICLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
+#define SPCSCCRICLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
 
-#define SPCSCYGOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
-#define SPCSCCBOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
-#define SPCSCCROCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
+#define SPCSCYGOCLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
+#define SPCSCCBOCLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
+#define SPCSCCROCLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
 #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
 
@@ -5296,7 +5302,7 @@ enum skl_disp_power_wells {
 #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
 #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
 #define PLANE_CTL(pipe, plane)	\
-	_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
+	_REG_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
 
 #define _PLANE_STRIDE_1_B			0x71188
 #define _PLANE_STRIDE_2_B			0x71288
@@ -5308,7 +5314,7 @@ enum skl_disp_power_wells {
 #define _PLANE_STRIDE_3(pipe)	\
 	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
 #define PLANE_STRIDE(pipe, plane)	\
-	_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+	_REG_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
 
 #define _PLANE_POS_1_B				0x7118c
 #define _PLANE_POS_2_B				0x7128c
@@ -5317,7 +5323,7 @@ enum skl_disp_power_wells {
 #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
 #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
 #define PLANE_POS(pipe, plane)	\
-	_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
+	_REG_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
 
 #define _PLANE_SIZE_1_B				0x71190
 #define _PLANE_SIZE_2_B				0x71290
@@ -5326,7 +5332,7 @@ enum skl_disp_power_wells {
 #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
 #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
 #define PLANE_SIZE(pipe, plane)	\
-	_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+	_REG_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
 
 #define _PLANE_SURF_1_B				0x7119c
 #define _PLANE_SURF_2_B				0x7129c
@@ -5335,35 +5341,35 @@ enum skl_disp_power_wells {
 #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
 #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
 #define PLANE_SURF(pipe, plane)	\
-	_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+	_REG_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
 
 #define _PLANE_OFFSET_1_B			0x711a4
 #define _PLANE_OFFSET_2_B			0x712a4
 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
 #define PLANE_OFFSET(pipe, plane)	\
-	_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
+	_REG_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
 
 #define _PLANE_KEYVAL_1_B			0x71194
 #define _PLANE_KEYVAL_2_B			0x71294
 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
 #define PLANE_KEYVAL(pipe, plane)	\
-	_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+	_REG_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
 
 #define _PLANE_KEYMSK_1_B			0x71198
 #define _PLANE_KEYMSK_2_B			0x71298
 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
 #define PLANE_KEYMSK(pipe, plane)	\
-	_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
+	_REG_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
 
 #define _PLANE_KEYMAX_1_B			0x711a0
 #define _PLANE_KEYMAX_2_B			0x712a0
 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
 #define PLANE_KEYMAX(pipe, plane)	\
-	_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+	_REG_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
 
 #define _PLANE_BUF_CFG_1_B			0x7127c
 #define _PLANE_BUF_CFG_2_B			0x7137c
@@ -5372,7 +5378,7 @@ enum skl_disp_power_wells {
 #define _PLANE_BUF_CFG_2(pipe)	\
 	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
 #define PLANE_BUF_CFG(pipe, plane)	\
-	_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
+	_REG_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
 
 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
@@ -5381,26 +5387,26 @@ enum skl_disp_power_wells {
 #define _PLANE_NV12_BUF_CFG_2(pipe)	\
 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
 #define PLANE_NV12_BUF_CFG(pipe, plane)	\
-	_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+	_REG_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
 
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
 #define _CUR_BUF_CFG_B				0x7117c
-#define CUR_BUF_CFG(pipe)	_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+#define CUR_BUF_CFG(pipe)	_REG_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
 
 /* VBIOS regs */
-#define VGACNTRL		0x71400
+#define VGACNTRL		_REG(0x71400)
 # define VGA_DISP_DISABLE			(1 << 31)
 # define VGA_2X_MODE				(1 << 30)
 # define VGA_PIPE_B_SELECT			(1 << 29)
 
-#define VLV_VGACNTRL		(VLV_DISPLAY_BASE + 0x71400)
+#define VLV_VGACNTRL		_REG(VLV_DISPLAY_BASE + 0x71400)
 
 /* Ironlake */
 
-#define CPU_VGACNTRL	0x41000
+#define CPU_VGACNTRL	_REG(0x41000)
 
-#define DIGITAL_PORT_HOTPLUG_CNTRL	0x44030
+#define DIGITAL_PORT_HOTPLUG_CNTRL	_REG(0x44030)
 #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
 #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
@@ -5413,26 +5419,26 @@ enum skl_disp_power_wells {
 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
 
 /* refresh rate hardware control */
-#define RR_HW_CTL       0x45300
+#define RR_HW_CTL       _REG(0x45300)
 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
 
-#define FDI_PLL_BIOS_0  0x46000
+#define FDI_PLL_BIOS_0  _REG(0x46000)
 #define  FDI_PLL_FB_CLOCK_MASK  0xff
-#define FDI_PLL_BIOS_1  0x46004
-#define FDI_PLL_BIOS_2  0x46008
-#define DISPLAY_PORT_PLL_BIOS_0         0x4600c
-#define DISPLAY_PORT_PLL_BIOS_1         0x46010
-#define DISPLAY_PORT_PLL_BIOS_2         0x46014
+#define FDI_PLL_BIOS_1  _REG(0x46004)
+#define FDI_PLL_BIOS_2  _REG(0x46008)
+#define DISPLAY_PORT_PLL_BIOS_0         _REG(0x4600c)
+#define DISPLAY_PORT_PLL_BIOS_1         _REG(0x46010)
+#define DISPLAY_PORT_PLL_BIOS_2         _REG(0x46014)
 
-#define PCH_3DCGDIS0		0x46020
+#define PCH_3DCGDIS0		_REG(0x46020)
 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
 
-#define PCH_3DCGDIS1		0x46024
+#define PCH_3DCGDIS1		_REG(0x46024)
 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
-#define FDI_PLL_FREQ_CTL        0x46030
+#define FDI_PLL_FREQ_CTL        _REG(0x46030)
 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
@@ -5469,14 +5475,14 @@ enum skl_disp_power_wells {
 #define _PIPEB_LINK_M2		0x61048
 #define _PIPEB_LINK_N2		0x6104c
 
-#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
-#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
-#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
-#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
-#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
-#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
-#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
-#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
+#define PIPE_DATA_M1(tran) _REG_TRANS2(tran, _PIPEA_DATA_M1)
+#define PIPE_DATA_N1(tran) _REG_TRANS2(tran, _PIPEA_DATA_N1)
+#define PIPE_DATA_M2(tran) _REG_TRANS2(tran, _PIPEA_DATA_M2)
+#define PIPE_DATA_N2(tran) _REG_TRANS2(tran, _PIPEA_DATA_N2)
+#define PIPE_LINK_M1(tran) _REG_TRANS2(tran, _PIPEA_LINK_M1)
+#define PIPE_LINK_N1(tran) _REG_TRANS2(tran, _PIPEA_LINK_N1)
+#define PIPE_LINK_M2(tran) _REG_TRANS2(tran, _PIPEA_LINK_M2)
+#define PIPE_LINK_N2(tran) _REG_TRANS2(tran, _PIPEA_LINK_N2)
 
 /* CPU panel fitter */
 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
@@ -5499,11 +5505,11 @@ enum skl_disp_power_wells {
 #define _PFA_HSCALE		0x68090
 #define _PFB_HSCALE		0x68890
 
-#define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
-#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
-#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
-#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
-#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
+#define PF_CTL(pipe)		_REG_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
+#define PF_WIN_SZ(pipe)		_REG_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
+#define PF_WIN_POS(pipe)	_REG_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
+#define PF_VSCALE(pipe)		_REG_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
+#define PF_HSCALE(pipe)		_REG_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
 
 #define _PSA_CTL		0x68180
 #define _PSB_CTL		0x68980
@@ -5513,9 +5519,9 @@ enum skl_disp_power_wells {
 #define _PSA_WIN_POS		0x68170
 #define _PSB_WIN_POS		0x68970
 
-#define PS_CTL(pipe)		_PIPE(pipe, _PSA_CTL, _PSB_CTL)
-#define PS_WIN_SZ(pipe)		_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
-#define PS_WIN_POS(pipe)	_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
+#define PS_CTL(pipe)		_REG_PIPE(pipe, _PSA_CTL, _PSB_CTL)
+#define PS_WIN_SZ(pipe)		_REG_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
+#define PS_WIN_POS(pipe)	_REG_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
 
 /*
  * Skylake scalers
@@ -5604,42 +5610,42 @@ enum skl_disp_power_wells {
 #define _PS_ECC_STAT_1C     0x691D0
 
 #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
-#define SKL_PS_CTRL(pipe, id) _PIPE(pipe,        \
+#define SKL_PS_CTRL(pipe, id) _REG_PIPE(pipe,        \
 			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
 			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
-#define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe,    \
+#define SKL_PS_PWR_GATE(pipe, id) _REG_PIPE(pipe,    \
 			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
 			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
-#define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe,     \
+#define SKL_PS_WIN_POS(pipe, id) _REG_PIPE(pipe,     \
 			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
 			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
-#define SKL_PS_WIN_SZ(pipe, id)  _PIPE(pipe,     \
+#define SKL_PS_WIN_SZ(pipe, id)  _REG_PIPE(pipe,     \
 			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
 			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
-#define SKL_PS_VSCALE(pipe, id)  _PIPE(pipe,     \
+#define SKL_PS_VSCALE(pipe, id)  _REG_PIPE(pipe,     \
 			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
 			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
-#define SKL_PS_HSCALE(pipe, id)  _PIPE(pipe,     \
+#define SKL_PS_HSCALE(pipe, id)  _REG_PIPE(pipe,     \
 			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
 			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
-#define SKL_PS_VPHASE(pipe, id)  _PIPE(pipe,     \
+#define SKL_PS_VPHASE(pipe, id)  _REG_PIPE(pipe,     \
 			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
 			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
-#define SKL_PS_HPHASE(pipe, id)  _PIPE(pipe,     \
+#define SKL_PS_HPHASE(pipe, id)  _REG_PIPE(pipe,     \
 			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
 			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
-#define SKL_PS_ECC_STAT(pipe, id)  _PIPE(pipe,     \
+#define SKL_PS_ECC_STAT(pipe, id)  _REG_PIPE(pipe,     \
 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
 
 /* legacy palette */
 #define _LGC_PALETTE_A           0x4a000
 #define _LGC_PALETTE_B           0x4a800
-#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
+#define LGC_PALETTE(pipe, i) _REG(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
 
 #define _GAMMA_MODE_A		0x4a480
 #define _GAMMA_MODE_B		0x4ac80
-#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
+#define GAMMA_MODE(pipe) _REG_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
 #define GAMMA_MODE_MODE_MASK	(3 << 0)
 #define GAMMA_MODE_MODE_8BIT	(0 << 0)
 #define GAMMA_MODE_MODE_10BIT	(1 << 0)
@@ -5697,20 +5703,20 @@ enum skl_disp_power_wells {
 #define DE_PIPEA_VBLANK_IVB		(1<<0)
 #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
 
-#define VLV_MASTER_IER			0x4400c /* Gunit master IER */
+#define VLV_MASTER_IER			_REG(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1<<31)
 
-#define DEISR   0x44000
-#define DEIMR   0x44004
-#define DEIIR   0x44008
-#define DEIER   0x4400c
+#define DEISR   _REG(0x44000)
+#define DEIMR   _REG(0x44004)
+#define DEIIR   _REG(0x44008)
+#define DEIER   _REG(0x4400c)
 
-#define GTISR   0x44010
-#define GTIMR   0x44014
-#define GTIIR   0x44018
-#define GTIER   0x4401c
+#define GTISR   _REG(0x44010)
+#define GTIMR   _REG(0x44014)
+#define GTIIR   _REG(0x44018)
+#define GTIER   _REG(0x4401c)
 
-#define GEN8_MASTER_IRQ			0x44200
+#define GEN8_MASTER_IRQ			_REG(0x44200)
 #define  GEN8_MASTER_IRQ_CONTROL	(1<<31)
 #define  GEN8_PCU_IRQ			(1<<30)
 #define  GEN8_DE_PCH_IRQ		(1<<23)
@@ -5727,10 +5733,10 @@ enum skl_disp_power_wells {
 #define  GEN8_GT_BCS_IRQ		(1<<1)
 #define  GEN8_GT_RCS_IRQ		(1<<0)
 
-#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
-#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
-#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
-#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
+#define GEN8_GT_ISR(which) _REG(0x44300 + (0x10 * (which)))
+#define GEN8_GT_IMR(which) _REG(0x44304 + (0x10 * (which)))
+#define GEN8_GT_IIR(which) _REG(0x44308 + (0x10 * (which)))
+#define GEN8_GT_IER(which) _REG(0x4430c + (0x10 * (which)))
 
 #define GEN8_RCS_IRQ_SHIFT 0
 #define GEN8_BCS_IRQ_SHIFT 16
@@ -5739,10 +5745,10 @@ enum skl_disp_power_wells {
 #define GEN8_VECS_IRQ_SHIFT 0
 #define GEN8_WD_IRQ_SHIFT 16
 
-#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
-#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
-#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
-#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_ISR(pipe) _REG(0x44400 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IMR(pipe) _REG(0x44404 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IIR(pipe) _REG(0x44408 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IER(pipe) _REG(0x4440c + (0x10 * (pipe)))
 #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
@@ -5775,10 +5781,10 @@ enum skl_disp_power_wells {
 	 GEN9_PIPE_PLANE2_FAULT | \
 	 GEN9_PIPE_PLANE1_FAULT)
 
-#define GEN8_DE_PORT_ISR 0x44440
-#define GEN8_DE_PORT_IMR 0x44444
-#define GEN8_DE_PORT_IIR 0x44448
-#define GEN8_DE_PORT_IER 0x4444c
+#define GEN8_DE_PORT_ISR _REG(0x44440)
+#define GEN8_DE_PORT_IMR _REG(0x44444)
+#define GEN8_DE_PORT_IIR _REG(0x44448)
+#define GEN8_DE_PORT_IER _REG(0x4444c)
 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
@@ -5792,23 +5798,23 @@ enum skl_disp_power_wells {
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 
-#define GEN8_DE_MISC_ISR 0x44460
-#define GEN8_DE_MISC_IMR 0x44464
-#define GEN8_DE_MISC_IIR 0x44468
-#define GEN8_DE_MISC_IER 0x4446c
+#define GEN8_DE_MISC_ISR _REG(0x44460)
+#define GEN8_DE_MISC_IMR _REG(0x44464)
+#define GEN8_DE_MISC_IIR _REG(0x44468)
+#define GEN8_DE_MISC_IER _REG(0x4446c)
 #define  GEN8_DE_MISC_GSE		(1 << 27)
 
-#define GEN8_PCU_ISR 0x444e0
-#define GEN8_PCU_IMR 0x444e4
-#define GEN8_PCU_IIR 0x444e8
-#define GEN8_PCU_IER 0x444ec
+#define GEN8_PCU_ISR _REG(0x444e0)
+#define GEN8_PCU_IMR _REG(0x444e4)
+#define GEN8_PCU_IIR _REG(0x444e8)
+#define GEN8_PCU_IER _REG(0x444ec)
 
-#define ILK_DISPLAY_CHICKEN2	0x42004
+#define ILK_DISPLAY_CHICKEN2	_REG(0x42004)
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
 #define  ILK_DPARB_GATE	(1<<22)
 #define  ILK_VSDPFD_FULL	(1<<21)
-#define FUSE_STRAP			0x42014
+#define FUSE_STRAP			_REG(0x42014)
 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
 #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
@@ -5817,18 +5823,18 @@ enum skl_disp_power_wells {
 #define  HSW_CDCLK_LIMIT		(1 << 24)
 #define  ILK_DESKTOP			(1 << 23)
 
-#define ILK_DSPCLK_GATE_D			0x42020
+#define ILK_DSPCLK_GATE_D			_REG(0x42020)
 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
 
-#define IVB_CHICKEN3	0x4200c
+#define IVB_CHICKEN3	_REG(0x4200c)
 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
 
-#define CHICKEN_PAR1_1		0x42080
+#define CHICKEN_PAR1_1		_REG(0x42080)
 #define  DPA_MASK_VBLANK_SRD	(1 << 15)
 #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
 
@@ -5836,70 +5842,70 @@ enum skl_disp_power_wells {
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
-#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_PIPESL_1(pipe) _REG_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
 
-#define DISP_ARB_CTL	0x45000
+#define DISP_ARB_CTL	_REG(0x45000)
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
-#define DISP_ARB_CTL2	0x45004
+#define DISP_ARB_CTL2	_REG(0x45004)
 #define  DISP_DATA_PARTITION_5_6	(1<<6)
-#define DBUF_CTL	0x45008
+#define DBUF_CTL	_REG(0x45008)
 #define  DBUF_POWER_REQUEST		(1<<31)
 #define  DBUF_POWER_STATE		(1<<30)
-#define GEN7_MSG_CTL	0x45010
+#define GEN7_MSG_CTL	_REG(0x45010)
 #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
 #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
-#define HSW_NDE_RSTWRN_OPT	0x46408
+#define HSW_NDE_RSTWRN_OPT	_REG(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
 
-#define SKL_DFSM			0x51000
+#define SKL_DFSM			_REG(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
 
-#define FF_SLICE_CS_CHICKEN2			0x20e4
+#define FF_SLICE_CS_CHICKEN2			_REG(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
 
 /* GEN7 chicken */
-#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
+#define GEN7_COMMON_SLICE_CHICKEN1		_REG(0x7010)
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
 # define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
-#define COMMON_SLICE_CHICKEN2			0x7014
+#define COMMON_SLICE_CHICKEN2			_REG(0x7014)
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
-#define HIZ_CHICKEN					0x7018
+#define HIZ_CHICKEN					_REG(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
 
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
+#define GEN9_SLICE_COMMON_ECO_CHICKEN0		_REG(0x7308)
 #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
 
-#define GEN7_L3SQCREG1				0xB010
+#define GEN7_L3SQCREG1				_REG(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
 
-#define GEN8_L3SQCREG1				0xB100
+#define GEN8_L3SQCREG1				_REG(0xB100)
 #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
 
-#define GEN7_L3CNTLREG1				0xB01C
+#define GEN7_L3CNTLREG1				_REG(0xB01C)
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
 #define  GEN7_L3AGDIS				(1<<19)
-#define GEN7_L3CNTLREG2				0xB020
-#define GEN7_L3CNTLREG3				0xB024
+#define GEN7_L3CNTLREG2				_REG(0xB020)
+#define GEN7_L3CNTLREG3				_REG(0xB024)
 
-#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
+#define GEN7_L3_CHICKEN_MODE_REGISTER		_REG(0xB030)
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
 
-#define GEN7_L3SQCREG4				0xb034
+#define GEN7_L3SQCREG4				_REG(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
-#define GEN8_L3SQCREG4				0xb118
+#define GEN8_L3SQCREG4				_REG(0xb118)
 #define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
 
 /* GEN8 chicken */
-#define HDC_CHICKEN0				0x7300
+#define HDC_CHICKEN0				_REG(0x7300)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
@@ -5908,17 +5914,17 @@ enum skl_disp_power_wells {
 #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
 
 /* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0			0x7308
+#define SLICE_ECO_CHICKEN0			_REG(0x7308)
 #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
 
 /* WaCatErrorRejectionIssue */
-#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_REG(0x9030)
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
 
-#define HSW_SCRATCH1				0xb038
+#define HSW_SCRATCH1				_REG(0xb038)
 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
 
-#define BDW_SCRATCH1					0xb11c
+#define BDW_SCRATCH1					_REG(0xb11c)
 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1<<2)
 
 /* PCH */
@@ -6012,12 +6018,12 @@ enum skl_disp_power_wells {
 				 SDE_FDI_RXB_CPT | \
 				 SDE_FDI_RXA_CPT)
 
-#define SDEISR  0xc4000
-#define SDEIMR  0xc4004
-#define SDEIIR  0xc4008
-#define SDEIER  0xc400c
+#define SDEISR  _REG(0xc4000)
+#define SDEIMR  _REG(0xc4004)
+#define SDEIIR  _REG(0xc4008)
+#define SDEIER  _REG(0xc400c)
 
-#define SERR_INT			0xc4040
+#define SERR_INT			_REG(0xc4040)
 #define  SERR_INT_POISON		(1<<31)
 #define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
 #define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
@@ -6025,7 +6031,7 @@ enum skl_disp_power_wells {
 #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
 
 /* digital port hotplug */
-#define PCH_PORT_HOTPLUG		0xc4030	/* SHOTPLUG_CTL */
+#define PCH_PORT_HOTPLUG		_REG(0xc4030)	/* SHOTPLUG_CTL */
 #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
 #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
@@ -6062,42 +6068,42 @@ enum skl_disp_power_wells {
 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
 
-#define PCH_PORT_HOTPLUG2		0xc403C	/* SHOTPLUG_CTL2 SPT+ */
+#define PCH_PORT_HOTPLUG2		_REG(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
 #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
 
-#define PCH_GPIOA               0xc5010
-#define PCH_GPIOB               0xc5014
-#define PCH_GPIOC               0xc5018
-#define PCH_GPIOD               0xc501c
-#define PCH_GPIOE               0xc5020
-#define PCH_GPIOF               0xc5024
+#define PCH_GPIOA               _REG(0xc5010)
+#define PCH_GPIOB               _REG(0xc5014)
+#define PCH_GPIOC               _REG(0xc5018)
+#define PCH_GPIOD               _REG(0xc501c)
+#define PCH_GPIOE               _REG(0xc5020)
+#define PCH_GPIOF               _REG(0xc5024)
 
-#define PCH_GMBUS0		0xc5100
-#define PCH_GMBUS1		0xc5104
-#define PCH_GMBUS2		0xc5108
-#define PCH_GMBUS3		0xc510c
-#define PCH_GMBUS4		0xc5110
-#define PCH_GMBUS5		0xc5120
+#define PCH_GMBUS0		_REG(0xc5100)
+#define PCH_GMBUS1		_REG(0xc5104)
+#define PCH_GMBUS2		_REG(0xc5108)
+#define PCH_GMBUS3		_REG(0xc510c)
+#define PCH_GMBUS4		_REG(0xc5110)
+#define PCH_GMBUS5		_REG(0xc5120)
 
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
-#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+#define PCH_DPLL(pll) _REG(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
 
 #define _PCH_FPA0                0xc6040
 #define  FP_CB_TUNE		(0x3<<22)
 #define _PCH_FPA1                0xc6044
 #define _PCH_FPB0                0xc6048
 #define _PCH_FPB1                0xc604c
-#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
-#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
+#define PCH_FP0(pll) _REG(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define PCH_FP1(pll) _REG(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
 
-#define PCH_DPLL_TEST           0xc606c
+#define PCH_DPLL_TEST           _REG(0xc606c)
 
-#define PCH_DREF_CONTROL        0xC6200
+#define PCH_DREF_CONTROL        _REG(0xC6200)
 #define  DREF_CONTROL_MASK      0x7fc3
 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
@@ -6120,19 +6126,19 @@ enum skl_disp_power_wells {
 #define  DREF_SSC4_DISABLE                      (0)
 #define  DREF_SSC4_ENABLE                       (1)
 
-#define PCH_RAWCLK_FREQ         0xc6204
+#define PCH_RAWCLK_FREQ         _REG(0xc6204)
 #define  FDL_TP1_TIMER_SHIFT    12
 #define  FDL_TP1_TIMER_MASK     (3<<12)
 #define  FDL_TP2_TIMER_SHIFT    10
 #define  FDL_TP2_TIMER_MASK     (3<<10)
 #define  RAWCLK_FREQ_MASK       0x3ff
 
-#define PCH_DPLL_TMR_CFG        0xc6208
+#define PCH_DPLL_TMR_CFG        _REG(0xc6208)
 
-#define PCH_SSC4_PARMS          0xc6210
-#define PCH_SSC4_AUX_PARMS      0xc6214
+#define PCH_SSC4_PARMS          _REG(0xc6210)
+#define PCH_SSC4_AUX_PARMS      _REG(0xc6214)
 
-#define PCH_DPLL_SEL		0xc7000
+#define PCH_DPLL_SEL		_REG(0xc7000)
 #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
 #define	 TRANS_DPLLA_SEL(pipe)		0
 #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
@@ -6180,9 +6186,9 @@ enum skl_disp_power_wells {
 #define _VIDEO_DIP_DATA_B        0xe1208
 #define _VIDEO_DIP_GCP_B         0xe1210
 
-#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
-#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
-#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+#define TVIDEO_DIP_CTL(pipe) _REG_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _REG_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _REG_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
 /* Per-transcoder DIP controls (VLV) */
 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
@@ -6198,16 +6204,17 @@ enum skl_disp_power_wells {
 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
 
 #define VLV_TVIDEO_DIP_CTL(pipe) \
-	_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
+	_REG_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
 	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
 #define VLV_TVIDEO_DIP_DATA(pipe) \
-	_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
+	_REG_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
 	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
 #define VLV_TVIDEO_DIP_GCP(pipe) \
-	_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
+	_REG_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
 		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
 
 /* Haswell DIP controls */
+
 #define _HSW_VIDEO_DIP_CTL_A		0x60200
 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
@@ -6234,25 +6241,18 @@ enum skl_disp_power_wells {
 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
 #define _HSW_VIDEO_DIP_GCP_B		0x61210
 
-#define HSW_TVIDEO_DIP_CTL(trans) \
-	 _TRANSCODER2(trans, _HSW_VIDEO_DIP_CTL_A)
-#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
-	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
-#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
-	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
-#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
-	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
-#define HSW_TVIDEO_DIP_GCP(trans) \
-	_TRANSCODER2(trans, _HSW_VIDEO_DIP_GCP_A)
-#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
-	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
-
-#define _HSW_STEREO_3D_CTL_A	0x70020
-#define   S3D_ENABLE		(1<<31)
-#define _HSW_STEREO_3D_CTL_B	0x71020
-
-#define HSW_STEREO_3D_CTL(trans) \
-	_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
+#define HSW_TVIDEO_DIP_CTL(trans)		_REG_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
+#define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
+#define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
+#define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
+#define HSW_TVIDEO_DIP_GCP(trans) 		_REG_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
+#define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+
+#define _HSW_STEREO_3D_CTL_A		0x70020
+#define   S3D_ENABLE			(1<<31)
+#define _HSW_STEREO_3D_CTL_B		0x71020
+
+#define HSW_STEREO_3D_CTL(trans)	_REG_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
 
 #define _PCH_TRANS_HTOTAL_B          0xe1000
 #define _PCH_TRANS_HBLANK_B          0xe1004
@@ -6260,16 +6260,15 @@ enum skl_disp_power_wells {
 #define _PCH_TRANS_VTOTAL_B          0xe100c
 #define _PCH_TRANS_VBLANK_B          0xe1010
 #define _PCH_TRANS_VSYNC_B           0xe1014
-#define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028
+#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
 
-#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
-#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
-#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
-#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
-#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
-#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
-#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
-					 _PCH_TRANS_VSYNCSHIFT_B)
+#define PCH_TRANS_HTOTAL(pipe)		_REG_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
+#define PCH_TRANS_HBLANK(pipe)		_REG_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
+#define PCH_TRANS_HSYNC(pipe)		_REG_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
+#define PCH_TRANS_VTOTAL(pipe)		_REG_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
+#define PCH_TRANS_VBLANK(pipe)		_REG_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
+#define PCH_TRANS_VSYNC(pipe)		_REG_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
+#define PCH_TRANS_VSYNCSHIFT(pipe)	_REG_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
 
 #define _PCH_TRANSB_DATA_M1	0xe1030
 #define _PCH_TRANSB_DATA_N1	0xe1034
@@ -6280,19 +6279,19 @@ enum skl_disp_power_wells {
 #define _PCH_TRANSB_LINK_M2	0xe1048
 #define _PCH_TRANSB_LINK_N2	0xe104c
 
-#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
-#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
-#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
-#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
-#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
-#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
-#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
-#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
+#define PCH_TRANS_DATA_M1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
+#define PCH_TRANS_DATA_N1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
+#define PCH_TRANS_DATA_M2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
+#define PCH_TRANS_DATA_N2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
+#define PCH_TRANS_LINK_M1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
+#define PCH_TRANS_LINK_N1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
+#define PCH_TRANS_LINK_M2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
+#define PCH_TRANS_LINK_N2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
 
 #define _PCH_TRANSACONF              0xf0008
 #define _PCH_TRANSBCONF              0xf1008
-#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
-#define LPT_TRANSCONF		_PCH_TRANSACONF /* lpt has only one transcoder */
+#define PCH_TRANSCONF(pipe)	_REG_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
+#define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
 #define  TRANS_DISABLE          (0<<31)
 #define  TRANS_ENABLE           (1<<31)
 #define  TRANS_STATE_MASK       (1<<30)
@@ -6313,47 +6312,47 @@ enum skl_disp_power_wells {
 
 #define _TRANSA_CHICKEN1	 0xf0060
 #define _TRANSB_CHICKEN1	 0xf1060
-#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define TRANS_CHICKEN1(pipe)	_REG_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
 #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1<<10)
 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
 #define _TRANSA_CHICKEN2	 0xf0064
 #define _TRANSB_CHICKEN2	 0xf1064
-#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_CHICKEN2(pipe)	_REG_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
 #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1<<31)
 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
 
-#define SOUTH_CHICKEN1		0xc2000
+#define SOUTH_CHICKEN1		_REG(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
 #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
 #define  SPT_PWM_GRANULARITY		(1<<0)
-#define SOUTH_CHICKEN2		0xc2004
+#define SOUTH_CHICKEN2		_REG(0xc2004)
 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
 #define  LPT_PWM_GRANULARITY		(1<<5)
 #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
 
-#define _FDI_RXA_CHICKEN         0xc200c
-#define _FDI_RXB_CHICKEN         0xc2010
+#define _FDI_RXA_CHICKEN        0xc200c
+#define _FDI_RXB_CHICKEN        0xc2010
 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
-#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
+#define FDI_RX_CHICKEN(pipe)	_REG_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
 
-#define SOUTH_DSPCLK_GATE_D	0xc2020
+#define SOUTH_DSPCLK_GATE_D	_REG(0xc2020)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
 
 /* CPU: FDI_TX */
-#define _FDI_TXA_CTL             0x60100
-#define _FDI_TXB_CTL             0x61100
-#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
+#define _FDI_TXA_CTL            0x60100
+#define _FDI_TXB_CTL            0x61100
+#define FDI_TX_CTL(pipe)	_REG_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
 #define  FDI_TX_DISABLE         (0<<31)
 #define  FDI_TX_ENABLE          (1<<31)
 #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
@@ -6403,7 +6402,7 @@ enum skl_disp_power_wells {
 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
 #define _FDI_RXA_CTL             0xf000c
 #define _FDI_RXB_CTL             0xf100c
-#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
+#define FDI_RX_CTL(pipe)	_REG_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
 #define  FDI_RX_ENABLE          (1<<31)
 /* train, dp width same as FDI_TX */
 #define  FDI_FS_ERRC_ENABLE		(1<<27)
@@ -6439,14 +6438,14 @@ enum skl_disp_power_wells {
 #define  FDI_RX_TP1_TO_TP2_48		(2<<20)
 #define  FDI_RX_TP1_TO_TP2_64		(3<<20)
 #define  FDI_RX_FDI_DELAY_90		(0x90<<0)
-#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
+#define FDI_RX_MISC(pipe)	_REG_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
 
-#define _FDI_RXA_TUSIZE1         0xf0030
-#define _FDI_RXA_TUSIZE2         0xf0038
-#define _FDI_RXB_TUSIZE1         0xf1030
-#define _FDI_RXB_TUSIZE2         0xf1038
-#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
-#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
+#define _FDI_RXA_TUSIZE1        0xf0030
+#define _FDI_RXA_TUSIZE2        0xf0038
+#define _FDI_RXB_TUSIZE1        0xf1030
+#define _FDI_RXB_TUSIZE2        0xf1038
+#define FDI_RX_TUSIZE1(pipe)	_REG_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
+#define FDI_RX_TUSIZE2(pipe)	_REG_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
 
 /* FDI_RX interrupt register format */
 #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
@@ -6461,44 +6460,41 @@ enum skl_disp_power_wells {
 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
 
-#define _FDI_RXA_IIR             0xf0014
-#define _FDI_RXA_IMR             0xf0018
-#define _FDI_RXB_IIR             0xf1014
-#define _FDI_RXB_IMR             0xf1018
-#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
-#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
+#define _FDI_RXA_IIR            0xf0014
+#define _FDI_RXA_IMR            0xf0018
+#define _FDI_RXB_IIR            0xf1014
+#define _FDI_RXB_IMR            0xf1018
+#define FDI_RX_IIR(pipe)	_REG_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
+#define FDI_RX_IMR(pipe)	_REG_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
 
-#define FDI_PLL_CTL_1           0xfe000
-#define FDI_PLL_CTL_2           0xfe004
+#define FDI_PLL_CTL_1           _REG(0xfe000)
+#define FDI_PLL_CTL_2           _REG(0xfe004)
 
-#define PCH_LVDS	0xe1180
+#define PCH_LVDS	_REG(0xe1180)
 #define  LVDS_DETECTED	(1 << 1)
 
 /* vlv has 2 sets of panel control regs. */
-#define _PIPEA_PP_STATUS	(VLV_DISPLAY_BASE + 0x61200)
-#define _PIPEA_PP_CONTROL	(VLV_DISPLAY_BASE + 0x61204)
-#define _PIPEA_PP_ON_DELAYS	(VLV_DISPLAY_BASE + 0x61208)
+#define _PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
+#define _PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
+#define _PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
 #define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
-#define _PIPEA_PP_OFF_DELAYS	(VLV_DISPLAY_BASE + 0x6120c)
-#define _PIPEA_PP_DIVISOR	(VLV_DISPLAY_BASE + 0x61210)
-
-#define _PIPEB_PP_STATUS	(VLV_DISPLAY_BASE + 0x61300)
-#define _PIPEB_PP_CONTROL	(VLV_DISPLAY_BASE + 0x61304)
-#define _PIPEB_PP_ON_DELAYS	(VLV_DISPLAY_BASE + 0x61308)
-#define _PIPEB_PP_OFF_DELAYS	(VLV_DISPLAY_BASE + 0x6130c)
-#define _PIPEB_PP_DIVISOR	(VLV_DISPLAY_BASE + 0x61310)
-
-#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
-#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
-#define VLV_PIPE_PP_ON_DELAYS(pipe) \
-		_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
-#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
-		_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
-#define VLV_PIPE_PP_DIVISOR(pipe) \
-		_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
-
-#define PCH_PP_STATUS		0xc7200
-#define PCH_PP_CONTROL		0xc7204
+#define _PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
+#define _PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
+
+#define _PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
+#define _PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
+#define _PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
+#define _PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
+#define _PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
+
+#define VLV_PIPE_PP_STATUS(pipe)	_REG_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe)	_REG_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe)	_REG_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe)	_REG_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe)	_REG_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
+
+#define _PCH_PP_STATUS		0xc7200
+#define _PCH_PP_CONTROL		0xc7204
 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
 #define  PANEL_UNLOCK_MASK	(0xffff << 16)
 #define  BXT_POWER_CYCLE_DELAY_MASK	(0x1f0)
@@ -6508,7 +6504,7 @@ enum skl_disp_power_wells {
 #define  PANEL_POWER_RESET	(1 << 1)
 #define  PANEL_POWER_OFF	(0 << 0)
 #define  PANEL_POWER_ON		(1 << 0)
-#define PCH_PP_ON_DELAYS	0xc7208
+#define _PCH_PP_ON_DELAYS	0xc7208
 #define  PANEL_PORT_SELECT_MASK	(3 << 30)
 #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
 #define  PANEL_PORT_SELECT_DPA	(1 << 30)
@@ -6519,30 +6515,37 @@ enum skl_disp_power_wells {
 #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
 #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
 
-#define PCH_PP_OFF_DELAYS	0xc720c
+#define _PCH_PP_OFF_DELAYS		0xc720c
 #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
 #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
 #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
 #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
 
-#define PCH_PP_DIVISOR		0xc7210
+#define _PCH_PP_DIVISOR			0xc7210
 #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
 #define  PP_REFERENCE_DIVIDER_SHIFT	8
 #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
 
+#define PCH_PP_STATUS			_REG(_PCH_PP_STATUS)
+#define PCH_PP_CONTROL			_REG(_PCH_PP_CONTROL)
+#define PCH_PP_ON_DELAYS		_REG(_PCH_PP_ON_DELAYS)
+#define PCH_PP_OFF_DELAYS		_REG(_PCH_PP_OFF_DELAYS)
+#define PCH_PP_DIVISOR			_REG(_PCH_PP_DIVISOR)
+
 /* BXT PPS changes - 2nd set of PPS registers */
 #define _BXT_PP_STATUS2 	0xc7300
 #define _BXT_PP_CONTROL2 	0xc7304
 #define _BXT_PP_ON_DELAYS2	0xc7308
 #define _BXT_PP_OFF_DELAYS2	0xc730c
 
-#define BXT_PP_STATUS(n)	_PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
-#define BXT_PP_CONTROL(n)	_PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
-#define BXT_PP_ON_DELAYS(n)	_PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
-#define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
+#define BXT_PP_STATUS(n)	_REG_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2)
+#define BXT_PP_CONTROL(n)	_REG_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2)
+#define BXT_PP_ON_DELAYS(n)	_REG_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
+#define BXT_PP_OFF_DELAYS(n)	_REG_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
-#define PCH_DP_B		0xe4100
+#define _PCH_DP_B		0xe4100
+#define PCH_DP_B		_REG(_PCH_DP_B)
 #define _PCH_DPB_AUX_CH_CTL	0xe4110
 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
@@ -6550,7 +6553,8 @@ enum skl_disp_power_wells {
 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
 
-#define PCH_DP_C		0xe4200
+#define _PCH_DP_C		0xe4200
+#define PCH_DP_C		_REG(_PCH_DP_C)
 #define _PCH_DPC_AUX_CH_CTL	0xe4210
 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
@@ -6558,7 +6562,8 @@ enum skl_disp_power_wells {
 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
 
-#define PCH_DP_D		0xe4300
+#define _PCH_DP_D		0xe4300
+#define PCH_DP_D		_REG(_PCH_DP_D)
 #define _PCH_DPD_AUX_CH_CTL	0xe4310
 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
@@ -6566,8 +6571,8 @@ enum skl_disp_power_wells {
 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
 
-#define PCH_DP_AUX_CH_CTL(port)		_PORT((port)-1, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
-#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port)-1, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define PCH_DP_AUX_CH_CTL(port)		_REG_PORT((port)-1, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
+#define PCH_DP_AUX_CH_DATA(port, i)	_REG(_PORT((port)-1, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT	0
@@ -6583,7 +6588,7 @@ enum skl_disp_power_wells {
 #define _TRANS_DP_CTL_A		0xe0300
 #define _TRANS_DP_CTL_B		0xe1300
 #define _TRANS_DP_CTL_C		0xe2300
-#define TRANS_DP_CTL(pipe)	_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
+#define TRANS_DP_CTL(pipe)	_REG_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
 #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
 #define  TRANS_DP_PORT_SEL_B	(0<<29)
 #define  TRANS_DP_PORT_SEL_C	(1<<29)
@@ -6636,40 +6641,40 @@ enum skl_disp_power_wells {
 
 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
 
-#define  VLV_PMWGICZ				0x1300a4
+#define  VLV_PMWGICZ				_REG(0x1300a4)
 
-#define  FORCEWAKE				0xA18C
-#define  FORCEWAKE_VLV				0x1300b0
-#define  FORCEWAKE_ACK_VLV			0x1300b4
-#define  FORCEWAKE_MEDIA_VLV			0x1300b8
-#define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
-#define  FORCEWAKE_ACK_HSW			0x130044
-#define  FORCEWAKE_ACK				0x130090
-#define  VLV_GTLC_WAKE_CTRL			0x130090
+#define  FORCEWAKE				_REG(0xA18C)
+#define  FORCEWAKE_VLV				_REG(0x1300b0)
+#define  FORCEWAKE_ACK_VLV			_REG(0x1300b4)
+#define  FORCEWAKE_MEDIA_VLV			_REG(0x1300b8)
+#define  FORCEWAKE_ACK_MEDIA_VLV		_REG(0x1300bc)
+#define  FORCEWAKE_ACK_HSW			_REG(0x130044)
+#define  FORCEWAKE_ACK				_REG(0x130090)
+#define  VLV_GTLC_WAKE_CTRL			_REG(0x130090)
 #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
 #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
 #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
 
-#define  VLV_GTLC_PW_STATUS			0x130094
+#define  VLV_GTLC_PW_STATUS			_REG(0x130094)
 #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
 #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
 #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
 #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
-#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
-#define  FORCEWAKE_MEDIA_GEN9			0xa270
-#define  FORCEWAKE_RENDER_GEN9			0xa278
-#define  FORCEWAKE_BLITTER_GEN9			0xa188
-#define  FORCEWAKE_ACK_MEDIA_GEN9		0x0D88
-#define  FORCEWAKE_ACK_RENDER_GEN9		0x0D84
-#define  FORCEWAKE_ACK_BLITTER_GEN9		0x130044
+#define  FORCEWAKE_MT				_REG(0xa188) /* multi-threaded */
+#define  FORCEWAKE_MEDIA_GEN9			_REG(0xa270)
+#define  FORCEWAKE_RENDER_GEN9			_REG(0xa278)
+#define  FORCEWAKE_BLITTER_GEN9			_REG(0xa188)
+#define  FORCEWAKE_ACK_MEDIA_GEN9		_REG(0x0D88)
+#define  FORCEWAKE_ACK_RENDER_GEN9		_REG(0x0D84)
+#define  FORCEWAKE_ACK_BLITTER_GEN9		_REG(0x130044)
 #define   FORCEWAKE_KERNEL			0x1
 #define   FORCEWAKE_USER			0x2
-#define  FORCEWAKE_MT_ACK			0x130040
-#define  ECOBUS					0xa180
+#define  FORCEWAKE_MT_ACK			_REG(0x130040)
+#define  ECOBUS					_REG(0xa180)
 #define    FORCEWAKE_MT_ENABLE			(1<<5)
-#define  VLV_SPAREG2H				0xA194
+#define  VLV_SPAREG2H				_REG(0xA194)
 
-#define  GTFIFODBG				0x120000
+#define  GTFIFODBG				_REG(0x120000)
 #define    GT_FIFO_SBDROPERR			(1<<6)
 #define    GT_FIFO_BLOBDROPERR			(1<<5)
 #define    GT_FIFO_SB_READ_ABORTERR		(1<<4)
@@ -6678,23 +6683,23 @@ enum skl_disp_power_wells {
 #define    GT_FIFO_IAWRERR			(1<<1)
 #define    GT_FIFO_IARDERR			(1<<0)
 
-#define  GTFIFOCTL				0x120008
+#define  GTFIFOCTL				_REG(0x120008)
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
 #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
 #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
 
-#define  HSW_IDICR				0x9008
+#define  HSW_IDICR				_REG(0x9008)
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
-#define  HSW_EDRAM_PRESENT			0x120010
+#define  HSW_EDRAM_PRESENT			_REG(0x120010)
 #define    EDRAM_ENABLED			0x1
 
-#define GEN6_UCGCTL1				0x9400
+#define GEN6_UCGCTL1				_REG(0x9400)
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
 
-#define GEN6_UCGCTL2				0x9404
+#define GEN6_UCGCTL2				_REG(0x9404)
 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
@@ -6702,30 +6707,30 @@ enum skl_disp_power_wells {
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
-#define GEN6_UCGCTL3				0x9408
+#define GEN6_UCGCTL3				_REG(0x9408)
 
-#define GEN7_UCGCTL4				0x940c
+#define GEN7_UCGCTL4				_REG(0x940c)
 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
 
-#define GEN6_RCGCTL1				0x9410
-#define GEN6_RCGCTL2				0x9414
-#define GEN6_RSTCTL				0x9420
+#define GEN6_RCGCTL1				_REG(0x9410)
+#define GEN6_RCGCTL2				_REG(0x9414)
+#define GEN6_RSTCTL				_REG(0x9420)
 
-#define GEN8_UCGCTL6				0x9430
+#define GEN8_UCGCTL6				_REG(0x9430)
 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
 
-#define GEN6_GFXPAUSE				0xA000
-#define GEN6_RPNSWREQ				0xA008
+#define GEN6_GFXPAUSE				_REG(0xA000)
+#define GEN6_RPNSWREQ				_REG(0xA008)
 #define   GEN6_TURBO_DISABLE			(1<<31)
 #define   GEN6_FREQUENCY(x)			((x)<<25)
 #define   HSW_FREQUENCY(x)			((x)<<24)
 #define   GEN9_FREQUENCY(x)			((x)<<23)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
-#define GEN6_RC_VIDEO_FREQ			0xA00C
-#define GEN6_RC_CONTROL				0xA090
+#define GEN6_RC_VIDEO_FREQ			_REG(0xA00C)
+#define GEN6_RC_CONTROL				_REG(0xA090)
 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
 #define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
 #define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
@@ -6735,16 +6740,16 @@ enum skl_disp_power_wells {
 #define   GEN7_RC_CTL_TO_MODE			(1<<28)
 #define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
 #define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
-#define GEN6_RP_DOWN_TIMEOUT			0xA010
-#define GEN6_RP_INTERRUPT_LIMITS		0xA014
-#define GEN6_RPSTAT1				0xA01C
+#define GEN6_RP_DOWN_TIMEOUT			_REG(0xA010)
+#define GEN6_RP_INTERRUPT_LIMITS		_REG(0xA014)
+#define GEN6_RPSTAT1				_REG(0xA01C)
 #define   GEN6_CAGF_SHIFT			8
 #define   HSW_CAGF_SHIFT			7
 #define   GEN9_CAGF_SHIFT			23
 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
 #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
-#define GEN6_RP_CONTROL				0xA024
+#define GEN6_RP_CONTROL				_REG(0xA024)
 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
@@ -6758,53 +6763,53 @@ enum skl_disp_power_wells {
 #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
 #define   GEN6_RP_DOWN_IDLE_AVG			(0x2<<0)
 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
-#define GEN6_RP_UP_THRESHOLD			0xA02C
-#define GEN6_RP_DOWN_THRESHOLD			0xA030
-#define GEN6_RP_CUR_UP_EI			0xA050
+#define GEN6_RP_UP_THRESHOLD			_REG(0xA02C)
+#define GEN6_RP_DOWN_THRESHOLD			_REG(0xA030)
+#define GEN6_RP_CUR_UP_EI			_REG(0xA050)
 #define   GEN6_CURICONT_MASK			0xffffff
-#define GEN6_RP_CUR_UP				0xA054
+#define GEN6_RP_CUR_UP				_REG(0xA054)
 #define   GEN6_CURBSYTAVG_MASK			0xffffff
-#define GEN6_RP_PREV_UP				0xA058
-#define GEN6_RP_CUR_DOWN_EI			0xA05C
+#define GEN6_RP_PREV_UP				_REG(0xA058)
+#define GEN6_RP_CUR_DOWN_EI			_REG(0xA05C)
 #define   GEN6_CURIAVG_MASK			0xffffff
-#define GEN6_RP_CUR_DOWN			0xA060
-#define GEN6_RP_PREV_DOWN			0xA064
-#define GEN6_RP_UP_EI				0xA068
-#define GEN6_RP_DOWN_EI				0xA06C
-#define GEN6_RP_IDLE_HYSTERSIS			0xA070
-#define GEN6_RPDEUHWTC				0xA080
-#define GEN6_RPDEUC				0xA084
-#define GEN6_RPDEUCSW				0xA088
-#define GEN6_RC_STATE				0xA094
-#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
-#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
-#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
-#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
-#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
-#define GEN6_RC_SLEEP				0xA0B0
-#define GEN6_RCUBMABDTMR			0xA0B0
-#define GEN6_RC1e_THRESHOLD			0xA0B4
-#define GEN6_RC6_THRESHOLD			0xA0B8
-#define GEN6_RC6p_THRESHOLD			0xA0BC
-#define VLV_RCEDATA				0xA0BC
-#define GEN6_RC6pp_THRESHOLD			0xA0C0
-#define GEN6_PMINTRMSK				0xA168
+#define GEN6_RP_CUR_DOWN			_REG(0xA060)
+#define GEN6_RP_PREV_DOWN			_REG(0xA064)
+#define GEN6_RP_UP_EI				_REG(0xA068)
+#define GEN6_RP_DOWN_EI				_REG(0xA06C)
+#define GEN6_RP_IDLE_HYSTERSIS			_REG(0xA070)
+#define GEN6_RPDEUHWTC				_REG(0xA080)
+#define GEN6_RPDEUC				_REG(0xA084)
+#define GEN6_RPDEUCSW				_REG(0xA088)
+#define GEN6_RC_STATE				_REG(0xA094)
+#define GEN6_RC1_WAKE_RATE_LIMIT		_REG(0xA098)
+#define GEN6_RC6_WAKE_RATE_LIMIT		_REG(0xA09C)
+#define GEN6_RC6pp_WAKE_RATE_LIMIT		_REG(0xA0A0)
+#define GEN6_RC_EVALUATION_INTERVAL		_REG(0xA0A8)
+#define GEN6_RC_IDLE_HYSTERSIS			_REG(0xA0AC)
+#define GEN6_RC_SLEEP				_REG(0xA0B0)
+#define GEN6_RCUBMABDTMR			_REG(0xA0B0)
+#define GEN6_RC1e_THRESHOLD			_REG(0xA0B4)
+#define GEN6_RC6_THRESHOLD			_REG(0xA0B8)
+#define GEN6_RC6p_THRESHOLD			_REG(0xA0BC)
+#define VLV_RCEDATA				_REG(0xA0BC)
+#define GEN6_RC6pp_THRESHOLD			_REG(0xA0C0)
+#define GEN6_PMINTRMSK				_REG(0xA168)
 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
-#define VLV_PWRDWNUPCTL				0xA294
-#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		0xA0C4
-#define GEN9_RENDER_PG_IDLE_HYSTERESIS		0xA0C8
-#define GEN9_PG_ENABLE				0xA210
+#define VLV_PWRDWNUPCTL				_REG(0xA294)
+#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_REG(0xA0C4)
+#define GEN9_RENDER_PG_IDLE_HYSTERESIS		_REG(0xA0C8)
+#define GEN9_PG_ENABLE				_REG(0xA210)
 #define GEN9_RENDER_PG_ENABLE			(1<<0)
 #define GEN9_MEDIA_PG_ENABLE			(1<<1)
 
-#define VLV_CHICKEN_3				(VLV_DISPLAY_BASE + 0x7040C)
+#define VLV_CHICKEN_3				_REG(VLV_DISPLAY_BASE + 0x7040C)
 #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
 #define  PIXEL_OVERLAP_CNT_SHIFT		30
 
-#define GEN6_PMISR				0x44020
-#define GEN6_PMIMR				0x44024 /* rps_lock */
-#define GEN6_PMIIR				0x44028
-#define GEN6_PMIER				0x4402C
+#define GEN6_PMISR				_REG(0x44020)
+#define GEN6_PMIMR				_REG(0x44024) /* rps_lock */
+#define GEN6_PMIIR				_REG(0x44028)
+#define GEN6_PMIER				_REG(0x4402C)
 #define  GEN6_PM_MBOX_EVENT			(1<<25)
 #define  GEN6_PM_THERMAL_EVENT			(1<<24)
 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
@@ -6816,30 +6821,30 @@ enum skl_disp_power_wells {
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
-#define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
+#define GEN7_GT_SCRATCH(i)			_REG(0x4F100 + (i) * 4)
 #define GEN7_GT_SCRATCH_REG_NUM			8
 
-#define VLV_GTLC_SURVIVABILITY_REG              0x130098
+#define VLV_GTLC_SURVIVABILITY_REG              _REG(0x130098)
 #define VLV_GFX_CLK_STATUS_BIT			(1<<3)
 #define VLV_GFX_CLK_FORCE_ON_BIT		(1<<2)
 
-#define GEN6_GT_GFX_RC6_LOCKED			0x138104
-#define VLV_COUNTER_CONTROL			0x138104
+#define GEN6_GT_GFX_RC6_LOCKED			_REG(0x138104)
+#define VLV_COUNTER_CONTROL			_REG(0x138104)
 #define   VLV_COUNT_RANGE_HIGH			(1<<15)
 #define   VLV_MEDIA_RC0_COUNT_EN		(1<<5)
 #define   VLV_RENDER_RC0_COUNT_EN		(1<<4)
 #define   VLV_MEDIA_RC6_COUNT_EN		(1<<1)
 #define   VLV_RENDER_RC6_COUNT_EN		(1<<0)
-#define GEN6_GT_GFX_RC6				0x138108
-#define VLV_GT_RENDER_RC6			0x138108
-#define VLV_GT_MEDIA_RC6			0x13810C
+#define GEN6_GT_GFX_RC6				_REG(0x138108)
+#define VLV_GT_RENDER_RC6			_REG(0x138108)
+#define VLV_GT_MEDIA_RC6			_REG(0x13810C)
 
-#define GEN6_GT_GFX_RC6p			0x13810C
-#define GEN6_GT_GFX_RC6pp			0x138110
-#define VLV_RENDER_C0_COUNT			0x138118
-#define VLV_MEDIA_C0_COUNT			0x13811C
+#define GEN6_GT_GFX_RC6p			_REG(0x13810C)
+#define GEN6_GT_GFX_RC6pp			_REG(0x138110)
+#define VLV_RENDER_C0_COUNT			_REG(0x138118)
+#define VLV_MEDIA_C0_COUNT			_REG(0x13811C)
 
-#define GEN6_PCODE_MAILBOX			0x138124
+#define GEN6_PCODE_MAILBOX			_REG(0x138124)
 #define   GEN6_PCODE_READY			(1<<31)
 #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define	  GEN6_PCODE_READ_RC6VIDS		0x5
@@ -6862,12 +6867,12 @@ enum skl_disp_power_wells {
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
 #define   DISPLAY_IPS_CONTROL			0x19
 #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
-#define GEN6_PCODE_DATA				0x138128
+#define GEN6_PCODE_DATA				_REG(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
-#define GEN6_PCODE_DATA1			0x13812C
+#define GEN6_PCODE_DATA1			_REG(0x13812C)
 
-#define GEN6_GT_CORE_STATUS		0x138060
+#define GEN6_GT_CORE_STATUS		_REG(0x138060)
 #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
 #define   GEN6_RCn_MASK			7
 #define   GEN6_RC0			0
@@ -6875,23 +6880,23 @@ enum skl_disp_power_wells {
 #define   GEN6_RC6			3
 #define   GEN6_RC7			4
 
-#define CHV_POWER_SS0_SIG1		0xa720
-#define CHV_POWER_SS1_SIG1		0xa728
+#define CHV_POWER_SS0_SIG1		_REG(0xa720)
+#define CHV_POWER_SS1_SIG1		_REG(0xa728)
 #define   CHV_SS_PG_ENABLE		(1<<1)
 #define   CHV_EU08_PG_ENABLE		(1<<9)
 #define   CHV_EU19_PG_ENABLE		(1<<17)
 #define   CHV_EU210_PG_ENABLE		(1<<25)
 
-#define CHV_POWER_SS0_SIG2		0xa724
-#define CHV_POWER_SS1_SIG2		0xa72c
+#define CHV_POWER_SS0_SIG2		_REG(0xa724)
+#define CHV_POWER_SS1_SIG2		_REG(0xa72c)
 #define   CHV_EU311_PG_ENABLE		(1<<1)
 
-#define GEN9_SLICE_PGCTL_ACK(slice)	(0x804c + (slice)*0x4)
+#define GEN9_SLICE_PGCTL_ACK(slice)	_REG(0x804c + (slice)*0x4)
 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
 
-#define GEN9_SS01_EU_PGCTL_ACK(slice)	(0x805c + (slice)*0x8)
-#define GEN9_SS23_EU_PGCTL_ACK(slice)	(0x8060 + (slice)*0x8)
+#define GEN9_SS01_EU_PGCTL_ACK(slice)	_REG(0x805c + (slice)*0x8)
+#define GEN9_SS23_EU_PGCTL_ACK(slice)	_REG(0x8060 + (slice)*0x8)
 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
 #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
 #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
@@ -6901,18 +6906,18 @@ enum skl_disp_power_wells {
 #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
 #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
 
-#define GEN7_MISCCPCTL			(0x9424)
+#define GEN7_MISCCPCTL				_REG(0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
-#define GEN8_GARBCNTL                   0xB004
+#define GEN8_GARBCNTL                   _REG(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
 /* IVYBRIDGE DPF */
-#define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
-#define HSW_L3CDERRST11			0xB208 /* L3CD Error Status register 1 slice 1 */
+#define GEN7_L3CDERRST1(slice)		_REG(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
+#define HSW_L3CDERRST11			_REG(0xB208) /* L3CD Error Status register 1 slice 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
 #define   GEN7_PARITY_ERROR_VALID	(1<<13)
 #define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
@@ -6929,93 +6934,83 @@ enum skl_disp_power_wells {
 #define HSW_L3LOG_BASE_SLICE1		0xB270
 #define GEN7_L3LOG_SIZE			0x80
 
-#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
-#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
+#define GEN7_HALF_SLICE_CHICKEN1	_REG(0xe100) /* IVB GT1 + VLV */
+#define GEN7_HALF_SLICE_CHICKEN1_GT2	_REG(0xf100)
 #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
 #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)
 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
 
-#define GEN9_HALF_SLICE_CHICKEN5	0xe188
+#define GEN9_HALF_SLICE_CHICKEN5	_REG(0xe188)
 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
 #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
 
-#define GEN8_ROW_CHICKEN		0xe4f0
+#define GEN8_ROW_CHICKEN		_REG(0xe4f0)
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
 #define   STALL_DOP_GATING_DISABLE		(1<<5)
 
-#define GEN7_ROW_CHICKEN2		0xe4f4
-#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
+#define GEN7_ROW_CHICKEN2		_REG(0xe4f4)
+#define GEN7_ROW_CHICKEN2_GT2		_REG(0xf4f4)
 #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
 
-#define HSW_ROW_CHICKEN3		0xe49c
+#define HSW_ROW_CHICKEN3		_REG(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
 
-#define HALF_SLICE_CHICKEN2		0xe180
+#define HALF_SLICE_CHICKEN2		_REG(0xe180)
 #define   GEN8_ST_PO_DISABLE		(1<<13)
 
-#define HALF_SLICE_CHICKEN3		0xe184
+#define HALF_SLICE_CHICKEN3		_REG(0xe184)
 #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1<<5)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
 
-#define GEN9_HALF_SLICE_CHICKEN7	0xe194
+#define GEN9_HALF_SLICE_CHICKEN7	_REG(0xe194)
 #define   GEN9_ENABLE_YV12_BUGFIX	(1<<4)
 
 /* Audio */
-#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID			_REG(dev_priv->info.display_mmio_offset + 0x62020)
 #define   INTEL_AUDIO_DEVCL		0x808629FB
 #define   INTEL_AUDIO_DEVBLC		0x80862801
 #define   INTEL_AUDIO_DEVCTG		0x80862802
 
-#define G4X_AUD_CNTL_ST			0x620B4
+#define G4X_AUD_CNTL_ST			_REG(0x620B4)
 #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
 #define   G4X_ELDV_DEVCTG		(1 << 14)
 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
 #define   G4X_ELD_ACK			(1 << 4)
-#define G4X_HDMIW_HDMIEDID		0x6210C
+#define G4X_HDMIW_HDMIEDID		_REG(0x6210C)
 
 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
-#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
-					_IBX_HDMIW_HDMIEDID_A, \
-					_IBX_HDMIW_HDMIEDID_B)
+#define IBX_HDMIW_HDMIEDID(pipe)	_REG_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
+						  _IBX_HDMIW_HDMIEDID_B)
 #define _IBX_AUD_CNTL_ST_A		0xE20B4
 #define _IBX_AUD_CNTL_ST_B		0xE21B4
-#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
-					_IBX_AUD_CNTL_ST_A, \
-					_IBX_AUD_CNTL_ST_B)
+#define IBX_AUD_CNTL_ST(pipe)		_REG_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
+						  _IBX_AUD_CNTL_ST_B)
 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
 #define   IBX_ELD_ACK			(1 << 4)
-#define IBX_AUD_CNTL_ST2		0xE20C0
+#define IBX_AUD_CNTL_ST2		_REG(0xE20C0)
 #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
 
 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
-#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
-					_CPT_HDMIW_HDMIEDID_A, \
-					_CPT_HDMIW_HDMIEDID_B)
+#define CPT_HDMIW_HDMIEDID(pipe)	_REG_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
 #define _CPT_AUD_CNTL_ST_A		0xE50B4
 #define _CPT_AUD_CNTL_ST_B		0xE51B4
-#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
-					_CPT_AUD_CNTL_ST_A, \
-					_CPT_AUD_CNTL_ST_B)
-#define CPT_AUD_CNTRL_ST2		0xE50C0
+#define CPT_AUD_CNTL_ST(pipe)		_REG_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
+#define CPT_AUD_CNTRL_ST2		_REG(0xE50C0)
 
 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
-#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
-					_VLV_HDMIW_HDMIEDID_A, \
-					_VLV_HDMIW_HDMIEDID_B)
+#define VLV_HDMIW_HDMIEDID(pipe)	_REG_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
-#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
-					_VLV_AUD_CNTL_ST_A, \
-					_VLV_AUD_CNTL_ST_B)
-#define VLV_AUD_CNTL_ST2		(VLV_DISPLAY_BASE + 0x620C0)
+#define VLV_AUD_CNTL_ST(pipe)		_REG_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
+#define VLV_AUD_CNTL_ST2		_REG(VLV_DISPLAY_BASE + 0x620C0)
 
 /* These are the 4 32-bit write offset registers for each stream
  * output buffer.  It determines the offset from the
@@ -7025,19 +7020,13 @@ enum skl_disp_power_wells {
 
 #define _IBX_AUD_CONFIG_A		0xe2000
 #define _IBX_AUD_CONFIG_B		0xe2100
-#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
-					_IBX_AUD_CONFIG_A, \
-					_IBX_AUD_CONFIG_B)
+#define IBX_AUD_CFG(pipe)		_REG_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
 #define _CPT_AUD_CONFIG_A		0xe5000
 #define _CPT_AUD_CONFIG_B		0xe5100
-#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
-					_CPT_AUD_CONFIG_A, \
-					_CPT_AUD_CONFIG_B)
+#define CPT_AUD_CFG(pipe)		_REG_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
-#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
-					_VLV_AUD_CONFIG_A, \
-					_VLV_AUD_CONFIG_B)
+#define VLV_AUD_CFG(pipe)		_REG_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
 
 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
@@ -7062,61 +7051,51 @@ enum skl_disp_power_wells {
 /* HSW Audio */
 #define _HSW_AUD_CONFIG_A		0x65000
 #define _HSW_AUD_CONFIG_B		0x65100
-#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
-					_HSW_AUD_CONFIG_A, \
-					_HSW_AUD_CONFIG_B)
+#define HSW_AUD_CFG(pipe)		_REG_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
 
 #define _HSW_AUD_MISC_CTRL_A		0x65010
 #define _HSW_AUD_MISC_CTRL_B		0x65110
-#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
-					_HSW_AUD_MISC_CTRL_A, \
-					_HSW_AUD_MISC_CTRL_B)
+#define HSW_AUD_MISC_CTRL(pipe)		_REG_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
 
 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
-#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
-					_HSW_AUD_DIP_ELD_CTRL_ST_A, \
-					_HSW_AUD_DIP_ELD_CTRL_ST_B)
+#define HSW_AUD_DIP_ELD_CTRL(pipe)	_REG_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
 
 /* Audio Digital Converter */
 #define _HSW_AUD_DIG_CNVT_1		0x65080
 #define _HSW_AUD_DIG_CNVT_2		0x65180
-#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
-					_HSW_AUD_DIG_CNVT_1, \
-					_HSW_AUD_DIG_CNVT_2)
+#define AUD_DIG_CNVT(pipe)		_REG_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
 #define DIP_PORT_SEL_MASK		0x3
 
 #define _HSW_AUD_EDID_DATA_A		0x65050
 #define _HSW_AUD_EDID_DATA_B		0x65150
-#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
-					_HSW_AUD_EDID_DATA_A, \
-					_HSW_AUD_EDID_DATA_B)
+#define HSW_AUD_EDID_DATA(pipe)		_REG_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
 
-#define HSW_AUD_PIPE_CONV_CFG		0x6507c
-#define HSW_AUD_PIN_ELD_CP_VLD		0x650c0
+#define HSW_AUD_PIPE_CONV_CFG		_REG(0x6507c)
+#define HSW_AUD_PIN_ELD_CP_VLD		_REG(0x650c0)
 #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
 #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
 
-#define HSW_AUD_CHICKENBIT			0x65f10
+#define HSW_AUD_CHICKENBIT			_REG(0x65f10)
 #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
 
 /* HSW Power Wells */
-#define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
-#define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
-#define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */
-#define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */
+#define HSW_PWR_WELL_BIOS			_REG(0x45400) /* CTL1 */
+#define HSW_PWR_WELL_DRIVER			_REG(0x45404) /* CTL2 */
+#define HSW_PWR_WELL_KVMR			_REG(0x45408) /* CTL3 */
+#define HSW_PWR_WELL_DEBUG			_REG(0x4540C) /* CTL4 */
 #define   HSW_PWR_WELL_ENABLE_REQUEST		(1<<31)
 #define   HSW_PWR_WELL_STATE_ENABLED		(1<<30)
-#define HSW_PWR_WELL_CTL5			0x45410
+#define HSW_PWR_WELL_CTL5			_REG(0x45410)
 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
 #define   HSW_PWR_WELL_FORCE_ON			(1<<19)
-#define HSW_PWR_WELL_CTL6			0x45414
+#define HSW_PWR_WELL_CTL6			_REG(0x45414)
 
 /* SKL Fuse Status */
-#define SKL_FUSE_STATUS				0x42000
+#define SKL_FUSE_STATUS				_REG(0x42000)
 #define  SKL_FUSE_DOWNLOAD_STATUS              (1<<31)
 #define  SKL_FUSE_PG0_DIST_STATUS              (1<<27)
 #define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)
@@ -7127,7 +7106,7 @@ enum skl_disp_power_wells {
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
 #define _TRANS_DDI_FUNC_CTL_C		0x62400
 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
-#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, _TRANS_DDI_FUNC_CTL_A)
+#define TRANS_DDI_FUNC_CTL(tran) _REG_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
 
 #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
@@ -7159,7 +7138,7 @@ enum skl_disp_power_wells {
 /* DisplayPort Transport Control */
 #define _DP_TP_CTL_A			0x64040
 #define _DP_TP_CTL_B			0x64140
-#define DP_TP_CTL(port) _PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define DP_TP_CTL(port) _REG_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
 #define  DP_TP_CTL_ENABLE			(1<<31)
 #define  DP_TP_CTL_MODE_SST			(0<<27)
 #define  DP_TP_CTL_MODE_MST			(1<<27)
@@ -7177,7 +7156,7 @@ enum skl_disp_power_wells {
 /* DisplayPort Transport Status */
 #define _DP_TP_STATUS_A			0x64044
 #define _DP_TP_STATUS_B			0x64144
-#define DP_TP_STATUS(port) _PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS(port) _REG_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
 #define  DP_TP_STATUS_IDLE_DONE			(1<<25)
 #define  DP_TP_STATUS_ACT_SENT			(1<<24)
 #define  DP_TP_STATUS_MODE_STATUS_MST		(1<<23)
@@ -7189,7 +7168,7 @@ enum skl_disp_power_wells {
 /* DDI Buffer Control */
 #define _DDI_BUF_CTL_A				0x64000
 #define _DDI_BUF_CTL_B				0x64100
-#define DDI_BUF_CTL(port) _PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
+#define DDI_BUF_CTL(port) _REG_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1<<31)
 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
 #define  DDI_BUF_EMP_MASK			(0xf<<24)
@@ -7204,15 +7183,15 @@ enum skl_disp_power_wells {
 /* DDI Buffer Translations */
 #define _DDI_BUF_TRANS_A		0x64E00
 #define _DDI_BUF_TRANS_B		0x64E60
-#define DDI_BUF_TRANS_LO(port, i)	 (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
-#define DDI_BUF_TRANS_HI(port, i)	 (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+#define DDI_BUF_TRANS_LO(port, i)	_REG(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
+#define DDI_BUF_TRANS_HI(port, i)	_REG(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-#define SBI_ADDR			0xC6000
-#define SBI_DATA			0xC6004
-#define SBI_CTL_STAT			0xC6008
+#define SBI_ADDR			_REG(0xC6000)
+#define SBI_DATA			_REG(0xC6004)
+#define SBI_CTL_STAT			_REG(0xC6008)
 #define  SBI_CTL_DEST_ICLK		(0x0<<16)
 #define  SBI_CTL_DEST_MPHY		(0x1<<16)
 #define  SBI_CTL_OP_IORD		(0x2<<8)
@@ -7243,12 +7222,12 @@ enum skl_disp_power_wells {
 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1<<0)
 
 /* LPT PIXCLK_GATE */
-#define PIXCLK_GATE			0xC6020
+#define PIXCLK_GATE			_REG(0xC6020)
 #define  PIXCLK_GATE_UNGATE		(1<<0)
 #define  PIXCLK_GATE_GATE		(0<<0)
 
 /* SPLL */
-#define SPLL_CTL			0x46020
+#define SPLL_CTL			_REG(0x46020)
 #define  SPLL_PLL_ENABLE		(1<<31)
 #define  SPLL_PLL_SSC			(1<<28)
 #define  SPLL_PLL_NON_SSC		(2<<28)
@@ -7262,7 +7241,7 @@ enum skl_disp_power_wells {
 /* WRPLL */
 #define _WRPLL_CTL1			0x46040
 #define _WRPLL_CTL2			0x46060
-#define WRPLL_CTL(pll)			_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
+#define WRPLL_CTL(pll)			_REG_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
 #define  WRPLL_PLL_ENABLE		(1<<31)
 #define  WRPLL_PLL_SSC			(1<<28)
 #define  WRPLL_PLL_NON_SSC		(2<<28)
@@ -7281,7 +7260,7 @@ enum skl_disp_power_wells {
 /* Port clock selection */
 #define _PORT_CLK_SEL_A			0x46100
 #define _PORT_CLK_SEL_B			0x46104
-#define PORT_CLK_SEL(port) _PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
+#define PORT_CLK_SEL(port) _REG_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
 #define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
 #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
 #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
@@ -7295,7 +7274,7 @@ enum skl_disp_power_wells {
 /* Transcoder clock selection */
 #define _TRANS_CLK_SEL_A		0x46140
 #define _TRANS_CLK_SEL_B		0x46144
-#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
+#define TRANS_CLK_SEL(tran) _REG_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
 /* For each transcoder, we need to select the corresponding port clock */
 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
 #define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
@@ -7304,7 +7283,7 @@ enum skl_disp_power_wells {
 #define _TRANSB_MSA_MISC		0x61410
 #define _TRANSC_MSA_MISC		0x62410
 #define _TRANS_EDP_MSA_MISC		0x6f410
-#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, _TRANSA_MSA_MISC)
+#define TRANS_MSA_MISC(tran) _REG_TRANS2(tran, _TRANSA_MSA_MISC)
 
 #define  TRANS_MSA_SYNC_CLK		(1<<0)
 #define  TRANS_MSA_6_BPC		(0<<5)
@@ -7314,7 +7293,7 @@ enum skl_disp_power_wells {
 #define  TRANS_MSA_16_BPC		(4<<5)
 
 /* LCPLL Control */
-#define LCPLL_CTL			0x130040
+#define LCPLL_CTL			_REG(0x130040)
 #define  LCPLL_PLL_DISABLE		(1<<31)
 #define  LCPLL_PLL_LOCK			(1<<30)
 #define  LCPLL_CLK_FREQ_MASK		(3<<26)
@@ -7334,7 +7313,7 @@ enum skl_disp_power_wells {
  */
 
 /* CDCLK_CTL */
-#define CDCLK_CTL			0x46000
+#define CDCLK_CTL			_REG(0x46000)
 #define  CDCLK_FREQ_SEL_MASK		(3<<26)
 #define  CDCLK_FREQ_450_432		(0<<26)
 #define  CDCLK_FREQ_540			(1<<26)
@@ -7350,12 +7329,12 @@ enum skl_disp_power_wells {
 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
 
 /* LCPLL_CTL */
-#define LCPLL1_CTL		0x46010
-#define LCPLL2_CTL		0x46014
+#define LCPLL1_CTL		_REG(0x46010)
+#define LCPLL2_CTL		_REG(0x46014)
 #define  LCPLL_PLL_ENABLE	(1<<31)
 
 /* DPLL control1 */
-#define DPLL_CTRL1		0x6C058
+#define DPLL_CTRL1		_REG(0x6C058)
 #define  DPLL_CTRL1_HDMI_MODE(id)		(1<<((id)*6+5))
 #define  DPLL_CTRL1_SSC(id)			(1<<((id)*6+4))
 #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7<<((id)*6+1))
@@ -7370,7 +7349,7 @@ enum skl_disp_power_wells {
 #define  DPLL_CTRL1_LINK_RATE_2160		5
 
 /* DPLL control2 */
-#define DPLL_CTRL2				0x6C05C
+#define DPLL_CTRL2				_REG(0x6C05C)
 #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<((port)+15))
 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
@@ -7378,7 +7357,7 @@ enum skl_disp_power_wells {
 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
 
 /* DPLL Status */
-#define DPLL_STATUS	0x6C060
+#define DPLL_STATUS	_REG(0x6C060)
 #define  DPLL_LOCK(id) (1<<((id)*8))
 
 /* DPLL cfg */
@@ -7410,32 +7389,32 @@ enum skl_disp_power_wells {
 #define  DPLL_CFGCR2_PDIV_7 (4<<2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
 
-#define DPLL_CFGCR1(id)	_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
-#define DPLL_CFGCR2(id)	_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
+#define DPLL_CFGCR1(id)	_REG_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
+#define DPLL_CFGCR2(id)	_REG_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
 
 /* BXT display engine PLL */
-#define BXT_DE_PLL_CTL			0x6d000
+#define BXT_DE_PLL_CTL			_REG(0x6d000)
 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
 #define   BXT_DE_PLL_RATIO_MASK		0xff
 
-#define BXT_DE_PLL_ENABLE		0x46070
+#define BXT_DE_PLL_ENABLE		_REG(0x46070)
 #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
 #define   BXT_DE_PLL_LOCK		(1 << 30)
 
 /* GEN9 DC */
-#define DC_STATE_EN			0x45504
+#define DC_STATE_EN			_REG(0x45504)
 #define  DC_STATE_EN_UPTO_DC5		(1<<0)
 #define  DC_STATE_EN_DC9		(1<<3)
 #define  DC_STATE_EN_UPTO_DC6		(2<<0)
 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
 
-#define  DC_STATE_DEBUG                  0x45520
+#define  DC_STATE_DEBUG                  _REG(0x45520)
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1<<1)
 
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
-#define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
-#define D_COMP_BDW			0x138144
+#define D_COMP_HSW			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
+#define D_COMP_BDW			_REG(0x138144)
 #define  D_COMP_RCOMP_IN_PROGRESS	(1<<9)
 #define  D_COMP_COMP_FORCE		(1<<8)
 #define  D_COMP_COMP_DISABLE		(1<<0)
@@ -7443,25 +7422,24 @@ enum skl_disp_power_wells {
 /* Pipe WM_LINETIME - watermark line time */
 #define _PIPE_WM_LINETIME_A		0x45270
 #define _PIPE_WM_LINETIME_B		0x45274
-#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, _PIPE_WM_LINETIME_A, \
-					   _PIPE_WM_LINETIME_B)
+#define PIPE_WM_LINETIME(pipe) _REG_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
 #define   PIPE_WM_LINETIME_MASK			(0x1ff)
 #define   PIPE_WM_LINETIME_TIME(x)		((x))
 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x)<<16)
 
 /* SFUSE_STRAP */
-#define SFUSE_STRAP			0xc2014
+#define SFUSE_STRAP			_REG(0xc2014)
 #define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
 #define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
 #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
 #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
 
-#define WM_MISC				0x45260
+#define WM_MISC				_REG(0x45260)
 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
 
-#define WM_DBG				0x45280
+#define WM_DBG				_REG(0x45280)
 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
 #define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
 #define  WM_DBG_DISALLOW_SPRITE		(1<<2)
@@ -7498,27 +7476,28 @@ enum skl_disp_power_wells {
 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
 
-#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
-#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
-#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
-#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
-#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
-#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
-#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
-#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
-#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
-#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
-#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
-#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
-#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
+#define PIPE_CSC_COEFF_RY_GY(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
+#define PIPE_CSC_COEFF_BY(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
+#define PIPE_CSC_COEFF_RU_GU(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
+#define PIPE_CSC_COEFF_BU(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
+#define PIPE_CSC_COEFF_RV_GV(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
+#define PIPE_CSC_COEFF_BV(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
+#define PIPE_CSC_MODE(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
+#define PIPE_CSC_PREOFF_HI(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
+#define PIPE_CSC_PREOFF_ME(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
+#define PIPE_CSC_PREOFF_LO(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
+#define PIPE_CSC_POSTOFF_HI(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
+#define PIPE_CSC_POSTOFF_ME(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
+#define PIPE_CSC_POSTOFF_LO(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
 
 /* MIPI DSI registers */
 
-#define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
+#define _MIPI(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
+#define _REG_MIPI(port, a, c)	_REG(_MIPI(port, a, c))
 
 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
-#define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
+#define MIPI_PORT_CTRL(port)	_REG_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
 #define  DPI_ENABLE					(1 << 31) /* A + C */
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
@@ -7561,8 +7540,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
-#define MIPI_TEARING_CTRL(port)			_MIPI_PORT(port, \
-				_MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
+#define MIPI_TEARING_CTRL(port)			_REG_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
 #define  TEARING_EFFECT_DELAY_SHIFT			0
 #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
 
@@ -7573,8 +7551,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
 #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
-#define MIPI_DEVICE_READY(port)		_MIPI_PORT(port, _MIPIA_DEVICE_READY, \
-						_MIPIC_DEVICE_READY)
+#define MIPI_DEVICE_READY(port)		_REG_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
 #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
 #define  ULPS_STATE_MASK				(3 << 1)
 #define  ULPS_STATE_ENTER				(2 << 1)
@@ -7584,12 +7561,10 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
 #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
-#define MIPI_INTR_STAT(port)		_MIPI_PORT(port, _MIPIA_INTR_STAT, \
-					_MIPIC_INTR_STAT)
+#define MIPI_INTR_STAT(port)		_REG_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
 #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
 #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
-#define MIPI_INTR_EN(port)		_MIPI_PORT(port, _MIPIA_INTR_EN, \
-					_MIPIC_INTR_EN)
+#define MIPI_INTR_EN(port)		_REG_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
 #define  TEARING_EFFECT					(1 << 31)
 #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
 #define  GEN_READ_DATA_AVAIL				(1 << 29)
@@ -7625,8 +7600,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
 #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
-#define MIPI_DSI_FUNC_PRG(port)		_MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
-						_MIPIC_DSI_FUNC_PRG)
+#define MIPI_DSI_FUNC_PRG(port)		_REG_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
 #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
 #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
 #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
@@ -7649,32 +7623,27 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
 #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
-#define MIPI_HS_TX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
-					_MIPIC_HS_TX_TIMEOUT)
+#define MIPI_HS_TX_TIMEOUT(port)	_REG_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
 
 #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
 #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
-#define MIPI_LP_RX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
-					_MIPIC_LP_RX_TIMEOUT)
+#define MIPI_LP_RX_TIMEOUT(port)	_REG_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
 
 #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
 #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
-#define MIPI_TURN_AROUND_TIMEOUT(port)	_MIPI_PORT(port, \
-			_MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
+#define MIPI_TURN_AROUND_TIMEOUT(port)	_REG_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
 #define  TURN_AROUND_TIMEOUT_MASK			0x3f
 
 #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
 #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
-#define MIPI_DEVICE_RESET_TIMER(port)	_MIPI_PORT(port, \
-			_MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
+#define MIPI_DEVICE_RESET_TIMER(port)	_REG_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
 #define  DEVICE_RESET_TIMER_MASK			0xffff
 
 #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
 #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
-#define MIPI_DPI_RESOLUTION(port)	_MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
-					_MIPIC_DPI_RESOLUTION)
+#define MIPI_DPI_RESOLUTION(port)	_REG_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
 #define  VERTICAL_ADDRESS_SHIFT				16
 #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
 #define  HORIZONTAL_ADDRESS_SHIFT			0
@@ -7682,8 +7651,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
 #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
-#define MIPI_DBI_FIFO_THROTTLE(port)	_MIPI_PORT(port, \
-			_MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
+#define MIPI_DBI_FIFO_THROTTLE(port)	_REG_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
 #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
 #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
 #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
@@ -7691,50 +7659,41 @@ enum skl_disp_power_wells {
 /* regs below are bits 15:0 */
 #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
 #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
-#define MIPI_HSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \
-			_MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
+#define MIPI_HSYNC_PADDING_COUNT(port)	_REG_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
 
 #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
 #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
-#define MIPI_HBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HBP_COUNT, \
-					_MIPIC_HBP_COUNT)
+#define MIPI_HBP_COUNT(port)		_REG_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
 
 #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
 #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
-#define MIPI_HFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HFP_COUNT, \
-					_MIPIC_HFP_COUNT)
+#define MIPI_HFP_COUNT(port)		_REG_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
 
 #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
 #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
-#define MIPI_HACTIVE_AREA_COUNT(port)	_MIPI_PORT(port, \
-			_MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
+#define MIPI_HACTIVE_AREA_COUNT(port)	_REG_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
 
 #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
 #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
-#define MIPI_VSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \
-			_MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
+#define MIPI_VSYNC_PADDING_COUNT(port)	_REG_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
 
 #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
 #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
-#define MIPI_VBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VBP_COUNT, \
-					_MIPIC_VBP_COUNT)
+#define MIPI_VBP_COUNT(port)		_REG_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
 
 #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
 #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
-#define MIPI_VFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VFP_COUNT, \
-					_MIPIC_VFP_COUNT)
+#define MIPI_VFP_COUNT(port)		_REG_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
 
 #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
 #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
-#define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MIPI_PORT(port,	\
-		_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
+#define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_REG_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
 
 /* regs above are bits 15:0 */
 
 #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
 #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
-#define MIPI_DPI_CONTROL(port)		_MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
-					_MIPIC_DPI_CONTROL)
+#define MIPI_DPI_CONTROL(port)		_REG_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
 #define  DPI_LP_MODE					(1 << 6)
 #define  BACKLIGHT_OFF					(1 << 5)
 #define  BACKLIGHT_ON					(1 << 4)
@@ -7745,29 +7704,26 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
 #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
-#define MIPI_DPI_DATA(port)		_MIPI_PORT(port, _MIPIA_DPI_DATA, \
-					_MIPIC_DPI_DATA)
+#define MIPI_DPI_DATA(port)		_REG_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
 #define  COMMAND_BYTE_SHIFT				0
 #define  COMMAND_BYTE_MASK				(0x3f << 0)
 
 #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
 #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
-#define MIPI_INIT_COUNT(port)		_MIPI_PORT(port, _MIPIA_INIT_COUNT, \
-					_MIPIC_INIT_COUNT)
+#define MIPI_INIT_COUNT(port)		_REG_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
 #define  MASTER_INIT_TIMER_SHIFT			0
 #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
 
 #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
 #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
-#define MIPI_MAX_RETURN_PKT_SIZE(port)	_MIPI_PORT(port, \
+#define MIPI_MAX_RETURN_PKT_SIZE(port)	_REG_MIPI(port, \
 			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
 #define  MAX_RETURN_PKT_SIZE_SHIFT			0
 #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
 
 #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
 #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
-#define MIPI_VIDEO_MODE_FORMAT(port)	_MIPI_PORT(port, \
-			_MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
+#define MIPI_VIDEO_MODE_FORMAT(port)	_REG_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
 #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
 #define  DISABLE_VIDEO_BTA				(1 << 3)
 #define  IP_TG_CONFIG					(1 << 2)
@@ -7777,8 +7733,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
-#define MIPI_EOT_DISABLE(port)		_MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
-					_MIPIC_EOT_DISABLE)
+#define MIPI_EOT_DISABLE(port)		_REG_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
 #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
@@ -7790,31 +7745,26 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
 #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
-#define MIPI_LP_BYTECLK(port)		_MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
-					_MIPIC_LP_BYTECLK)
+#define MIPI_LP_BYTECLK(port)		_REG_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
 #define  LP_BYTECLK_SHIFT				0
 #define  LP_BYTECLK_MASK				(0xffff << 0)
 
 /* bits 31:0 */
 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
-#define MIPI_LP_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
-					_MIPIC_LP_GEN_DATA)
+#define MIPI_LP_GEN_DATA(port)		_REG_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
 
 /* bits 31:0 */
 #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
 #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
-#define MIPI_HS_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
-					_MIPIC_HS_GEN_DATA)
+#define MIPI_HS_GEN_DATA(port)		_REG_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
 
 #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
 #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
-#define MIPI_LP_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
-					_MIPIC_LP_GEN_CTRL)
+#define MIPI_LP_GEN_CTRL(port)		_REG_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
 #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
 #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
-#define MIPI_HS_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
-					_MIPIC_HS_GEN_CTRL)
+#define MIPI_HS_GEN_CTRL(port)		_REG_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
 #define  LONG_PACKET_WORD_COUNT_SHIFT			8
 #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
 #define  SHORT_PACKET_PARAM_SHIFT			8
@@ -7827,8 +7777,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
 #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
-#define MIPI_GEN_FIFO_STAT(port)	_MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
-					_MIPIC_GEN_FIFO_STAT)
+#define MIPI_GEN_FIFO_STAT(port)	_REG_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
 #define  DPI_FIFO_EMPTY					(1 << 28)
 #define  DBI_FIFO_EMPTY					(1 << 27)
 #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
@@ -7846,16 +7795,14 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
 #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
-#define MIPI_HS_LP_DBI_ENABLE(port)	_MIPI_PORT(port, \
-			_MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
+#define MIPI_HS_LP_DBI_ENABLE(port)	_REG_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
 #define  DBI_HS_LP_MODE_MASK				(1 << 0)
 #define  DBI_LP_MODE					(1 << 0)
 #define  DBI_HS_MODE					(0 << 0)
 
 #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
 #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
-#define MIPI_DPHY_PARAM(port)		_MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
-					_MIPIC_DPHY_PARAM)
+#define MIPI_DPHY_PARAM(port)		_REG_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
 #define  EXIT_ZERO_COUNT_SHIFT				24
 #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
 #define  TRAIL_COUNT_SHIFT				16
@@ -7868,15 +7815,11 @@ enum skl_disp_power_wells {
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-#define MIPI_DBI_BW_CTRL(port)		_MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
-					_MIPIC_DBI_BW_CTRL)
-
-#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \
-							+ 0xb088)
-#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \
-							+ 0xb888)
-#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MIPI_PORT(port, \
-	_MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
+#define MIPI_DBI_BW_CTRL(port)		_REG_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
+
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
+#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
+#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_REG_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
 #define  LP_HS_SSW_CNT_SHIFT				16
 #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
 #define  HS_LP_PWR_SW_CNT_SHIFT				0
@@ -7884,19 +7827,16 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
 #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
-#define MIPI_STOP_STATE_STALL(port)	_MIPI_PORT(port, \
-			_MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
+#define MIPI_STOP_STATE_STALL(port)	_REG_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
 #define  STOP_STATE_STALL_COUNTER_SHIFT			0
 #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
 
 #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
 #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
-#define MIPI_INTR_STAT_REG_1(port)	_MIPI_PORT(port, \
-				_MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
+#define MIPI_INTR_STAT_REG_1(port)	_REG_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
 #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
 #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
-#define MIPI_INTR_EN_REG_1(port)	_MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
-					_MIPIC_INTR_EN_REG_1)
+#define MIPI_INTR_EN_REG_1(port)	_REG_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
 #define  RX_CONTENTION_DETECTED				(1 << 0)
 
 /* XXX: only pipe A ?!? */
@@ -7916,8 +7856,7 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
-#define MIPI_CTRL(port)			_MIPI_PORT(port, _MIPIA_CTRL, \
-					_MIPIC_CTRL)
+#define MIPI_CTRL(port)			_REG_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
 #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
 #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
@@ -7931,23 +7870,20 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
-#define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
-					_MIPIC_DATA_ADDRESS)
+#define MIPI_DATA_ADDRESS(port)		_REG_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
 #define  DATA_MEM_ADDRESS_SHIFT				5
 #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
 #define  DATA_VALID					(1 << 0)
 
 #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
 #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
-#define MIPI_DATA_LENGTH(port)		_MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
-					_MIPIC_DATA_LENGTH)
+#define MIPI_DATA_LENGTH(port)		_REG_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
 #define  DATA_LENGTH_SHIFT				0
 #define  DATA_LENGTH_MASK				(0xfffff << 0)
 
 #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
 #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
-#define MIPI_COMMAND_ADDRESS(port)	_MIPI_PORT(port, \
-				_MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
+#define MIPI_COMMAND_ADDRESS(port)	_REG_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
 #define  COMMAND_MEM_ADDRESS_SHIFT			5
 #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
 #define  AUTO_PWG_ENABLE				(1 << 2)
@@ -7956,21 +7892,17 @@ enum skl_disp_power_wells {
 
 #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
 #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
-#define MIPI_COMMAND_LENGTH(port)	_MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
-					_MIPIC_COMMAND_LENGTH)
+#define MIPI_COMMAND_LENGTH(port)	_REG_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
 #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
 #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
 
 #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
 #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
-#define MIPI_READ_DATA_RETURN(port, n) \
-	(_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
-					+ 4 * (n)) /* n: 0...7 */
+#define MIPI_READ_DATA_RETURN(port, n) _REG(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
 
 #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
 #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
-#define MIPI_READ_DATA_VALID(port)	_MIPI_PORT(port, \
-				_MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
+#define MIPI_READ_DATA_VALID(port)	_REG_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
 #define  READ_DATA_VALID(n)				(1 << (n))
 
 /* For UMS only (deprecated): */
@@ -7986,4 +7918,27 @@ enum skl_disp_power_wells {
 #define GEN9_VEBOX_MOCS_0	0xcb00	/* Video MOCS base register*/
 #define GEN9_BLT_MOCS_0		0xcc00	/* Blitter MOCS base register*/
 
+/*
+* SKL CSR registers for DC5 and DC6
+*/
+#define CSR_PROGRAM(i)			_REG(0x80000 + (i) * 4)
+#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
+#define CSR_HTP_ADDR_SKL		0x00500034
+#define CSR_SSP_BASE			_REG(0x8F074)
+#define CSR_HTP_SKL			_REG(0x8F004)
+#define CSR_LAST_WRITE			_REG(0x8F034)
+#define CSR_LAST_WRITE_VALUE		0xc003b400
+
+/* Execlists regs */
+#define RING_ELSP(ring)				_REG((ring)->mmio_base + 0x230)
+#define RING_EXECLIST_STATUS_LO(ring)		_REG((ring)->mmio_base + 0x234)
+#define RING_EXECLIST_STATUS_HI(ring)		_REG((ring)->mmio_base + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(ring)		_REG((ring)->mmio_base + 0x244)
+#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
+#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
+#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
+#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_REG((ring)->mmio_base + 0x370 + (i) * 8)
+#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_REG((ring)->mmio_base + 0x370 + (i) * 8 + 4)
+#define RING_CONTEXT_STATUS_PTR(ring)		_REG((ring)->mmio_base + 0x3a0)
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 55bd04c..602d8a4 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -35,7 +35,8 @@
 #define dev_to_drm_minor(d) dev_get_drvdata((d))
 
 #ifdef CONFIG_PM
-static u32 calc_residency(struct drm_device *dev, const u32 reg)
+static u32 calc_residency(struct drm_device *dev,
+			  struct i915_reg reg)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u64 raw_time; /* 32b value may overflow during fixed point math */
@@ -49,7 +50,8 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
 
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 	if (IS_VALLEYVIEW(dev)) {
-		u32 clk_reg, czcount_30ns;
+		struct i915_reg clk_reg;
+		u32 czcount_30ns;
 
 		if (IS_CHERRYVIEW(dev))
 			clk_reg = CHV_CLK_CTL1;
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index d0993bc..9a5fa88 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -644,7 +644,7 @@ TRACE_EVENT(i915_flip_complete,
 );
 
 TRACE_EVENT_CONDITION(i915_reg_rw,
-	TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),
+	TP_PROTO(bool write, struct i915_reg reg, u64 val, int len, bool trace),
 
 	TP_ARGS(write, reg, val, len, trace),
 
@@ -659,7 +659,7 @@ TRACE_EVENT_CONDITION(i915_reg_rw,
 
 	TP_fast_assign(
 		__entry->val = (u64)val;
-		__entry->reg = reg;
+		__entry->reg = reg.reg;
 		__entry->write = write;
 		__entry->len = len;
 		),
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5eee75b..31edb68 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -69,13 +69,13 @@ void i915_check_vgpu(struct drm_device *dev)
 	if (!IS_HASWELL(dev))
 		return;
 
-	magic = readq(dev_priv->regs + vgtif_reg(magic));
+	magic = readq(dev_priv->regs + vgtif_reg(magic).reg);
 	if (magic != VGT_MAGIC)
 		return;
 
 	version = INTEL_VGT_IF_VERSION_ENCODE(
-		readw(dev_priv->regs + vgtif_reg(version_major)),
-		readw(dev_priv->regs + vgtif_reg(version_minor)));
+		readw(dev_priv->regs + vgtif_reg(version_major).reg),
+		readw(dev_priv->regs + vgtif_reg(version_minor).reg));
 	if (version != INTEL_VGT_IF_VERSION) {
 		DRM_INFO("VGT interface version mismatch!\n");
 		return;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 21c97f4..25d4829 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -108,7 +108,7 @@ struct vgt_if {
 } __packed;
 
 #define vgtif_reg(x) \
-	(VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)
+	_REG((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
 
 /* vGPU display status to be used by the host side */
 #define VGT_DRV_DISPLAY_NOT_READY 0
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index e35997e..19711f7 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -91,9 +91,9 @@ static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
 }
 
 static bool intel_eld_uptodate(struct drm_connector *connector,
-			       int reg_eldv, uint32_t bits_eldv,
-			       int reg_elda, uint32_t bits_elda,
-			       int reg_edid)
+			       struct i915_reg reg_eldv, uint32_t bits_eldv,
+			       struct i915_reg reg_elda, uint32_t bits_elda,
+			       struct i915_reg reg_edid)
 {
 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 	uint8_t *eld = connector->eld;
@@ -264,8 +264,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 	enum port port = intel_dig_port->port;
 	enum pipe pipe = intel_crtc->pipe;
 	uint32_t tmp, eldv;
-	int aud_config;
-	int aud_cntrl_st2;
+	struct i915_reg aud_config, aud_cntrl_st2;
 
 	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
 		      port_name(port), pipe_name(pipe));
@@ -316,10 +315,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
 	uint32_t eldv;
 	uint32_t tmp;
 	int len, i;
-	int hdmiw_hdmiedid;
-	int aud_config;
-	int aud_cntl_st;
-	int aud_cntrl_st2;
+	struct i915_reg hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 
 	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
 		      port_name(port), pipe_name(pipe), drm_eld_size(eld));
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 086b5c5..588714c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -50,7 +50,7 @@ struct intel_crt {
 	 * encoder's enable/disable callbacks */
 	struct intel_connector *connector;
 	bool force_hotplug_required;
-	u32 adpa_reg;
+	struct i915_reg adpa_reg;
 };
 
 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
@@ -502,12 +502,8 @@ intel_crt_load_detect(struct intel_crt *crt)
 	uint32_t vsample;
 	uint32_t vblank, vblank_start, vblank_end;
 	uint32_t dsl;
-	uint32_t bclrpat_reg;
-	uint32_t vtotal_reg;
-	uint32_t vblank_reg;
-	uint32_t vsync_reg;
-	uint32_t pipeconf_reg;
-	uint32_t pipe_dsl_reg;
+	struct i915_reg bclrpat_reg, vtotal_reg,
+		vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 	uint8_t	st00;
 	enum drm_connector_status status;
 
@@ -540,7 +536,7 @@ intel_crt_load_detect(struct intel_crt *crt)
 		/* Wait for next Vblank to substitue
 		 * border color for Color info */
 		intel_wait_for_vblank(dev, pipe);
-		st00 = I915_READ8(VGA_MSR_WRITE);
+		st00 = I915_READ8(_VGA_MSR_WRITE);
 		status = ((st00 & (1 << 4)) != 0) ?
 			connector_status_connected :
 			connector_status_disconnected;
@@ -585,7 +581,7 @@ intel_crt_load_detect(struct intel_crt *crt)
 		do {
 			count++;
 			/* Read the ST00 VGA status register */
-			st00 = I915_READ8(VGA_MSR_WRITE);
+			st00 = I915_READ8(_VGA_MSR_WRITE);
 			if (st00 & (1 << 4))
 				detect++;
 		} while ((I915_READ(pipe_dsl_reg) == dsl));
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 8174335..4fa026ef 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -45,16 +45,6 @@
 
 MODULE_FIRMWARE(I915_CSR_SKL);
 
-/*
-* SKL CSR registers for DC5 and DC6
-*/
-#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
-#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
-#define CSR_HTP_ADDR_SKL		0x00500034
-#define CSR_SSP_BASE			0x8F074
-#define CSR_HTP_SKL			0x8F004
-#define CSR_LAST_WRITE			0x8F034
-#define CSR_LAST_WRITE_VALUE		0xc003b400
 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
 #define CSR_MAX_FW_SIZE			0x2FFF
 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
@@ -355,7 +345,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 						dmc_header->mmioaddr[i]);
 			goto out;
 		}
-		csr->mmioaddr[i] = dmc_header->mmioaddr[i];
+		csr->mmioaddr[i].reg = dmc_header->mmioaddr[i];
 		csr->mmiodata[i] = dmc_header->mmiodata[i];
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fb456a4..ab7c156 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -329,7 +329,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 static bool
 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
 {
-	return intel_dig_port->hdmi.hdmi_reg;
+	return intel_dig_port->hdmi.hdmi_reg.reg;
 }
 
 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
@@ -558,12 +558,11 @@ void intel_prepare_ddi(struct drm_device *dev)
 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 				    enum port port)
 {
-	uint32_t reg = DDI_BUF_CTL(port);
 	int i;
 
 	for (i = 0; i < 16; i++) {
 		udelay(1);
-		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
+		if (I915_READ(DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE)
 			return;
 	}
 	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
@@ -913,7 +912,8 @@ static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 	/* Otherwise a < c && b >= d, do nothing */
 }
 
-static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
+static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
+				   struct i915_reg reg)
 {
 	int refclk = LC_FREQ;
 	int n, p, r;
@@ -949,7 +949,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 			       uint32_t dpll)
 {
-	uint32_t cfgcr1_reg, cfgcr2_reg;
+	struct i915_reg cfgcr1_reg, cfgcr2_reg;
 	uint32_t cfgcr1_val, cfgcr2_val;
 	uint32_t p0, p1, p2, dco_freq;
 
@@ -1912,7 +1912,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 				       enum transcoder cpu_transcoder)
 {
-	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
+	struct i915_reg reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 	uint32_t val = I915_READ(reg);
 
 	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
@@ -2055,7 +2055,7 @@ static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
 	uint8_t iboost;
 	uint8_t dp_iboost, hdmi_iboost;
 	int n_entries;
-	u32 reg;
+	u32 val;
 
 	/* VBT may override standard boost values */
 	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
@@ -2092,16 +2092,16 @@ static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
 		return;
 	}
 
-	reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
-	reg &= ~BALANCE_LEG_MASK(port);
-	reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
+	val = I915_READ(DISPIO_CR_TX_BMU_CR0);
+	val &= ~BALANCE_LEG_MASK(port);
+	val &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
 
 	if (iboost)
-		reg |= iboost << BALANCE_LEG_SHIFT(port);
+		val |= iboost << BALANCE_LEG_SHIFT(port);
 	else
-		reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
+		val |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
 
-	I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
+	I915_WRITE(DISPIO_CR_TX_BMU_CR0, val);
 }
 
 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
@@ -2472,7 +2472,7 @@ static const char * const skl_ddi_pll_names[] = {
 };
 
 struct skl_dpll_regs {
-	u32 ctl, cfgcr1, cfgcr2;
+	struct i915_reg ctl, cfgcr1, cfgcr2;
 };
 
 /* this array is indexed by the *shared* pll id */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 16e204d..7bc6c92 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1048,7 +1048,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg = PIPEDSL(pipe);
+	struct i915_reg reg = PIPEDSL(pipe);
 	u32 line1, line2;
 	u32 line_mask;
 
@@ -1088,7 +1088,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 	enum pipe pipe = crtc->pipe;
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		int reg = PIPECONF(cpu_transcoder);
+		struct i915_reg reg = PIPECONF(cpu_transcoder);
 
 		/* Wait for the Pipe State to go off */
 		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
@@ -1238,7 +1238,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 			   enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int pp_reg;
+	struct i915_reg pp_reg;
 	u32 val;
 	enum pipe panel_pipe = PIPE_A;
 	bool locked = true;
@@ -1433,8 +1433,7 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 		return false;
 
 	if (HAS_PCH_CPT(dev_priv->dev)) {
-		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
-		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
+		u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
 		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 			return false;
 	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
@@ -1498,12 +1497,13 @@ static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
 }
 
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
-				   enum pipe pipe, int reg, u32 port_sel)
+				   enum pipe pipe, struct i915_reg reg,
+				   u32 port_sel)
 {
 	u32 val = I915_READ(reg);
 	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
 	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
-	     reg, pipe_name(pipe));
+	     reg.reg, pipe_name(pipe));
 
 	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
 	     && (val & DP_PIPEB_SELECT),
@@ -1511,12 +1511,12 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 }
 
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
-				     enum pipe pipe, int reg)
+				     enum pipe pipe, struct i915_reg reg)
 {
 	u32 val = I915_READ(reg);
 	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
 	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
-	     reg, pipe_name(pipe));
+	     reg.reg, pipe_name(pipe));
 
 	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
 	     && (val & SDVO_PIPE_B_SELECT),
@@ -1552,7 +1552,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int reg = DPLL(crtc->pipe);
+	struct i915_reg reg = DPLL(crtc->pipe);
 	u32 dpll = pipe_config->dpll_hw_state.dpll;
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1641,7 +1641,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int reg = DPLL(crtc->pipe);
+	struct i915_reg reg = DPLL(crtc->pipe);
 	u32 dpll = crtc->config->dpll_hw_state.dpll;
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1781,7 +1781,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 			 unsigned int expected_mask)
 {
 	u32 port_mask;
-	int dpll_reg;
+	struct i915_reg dpll_reg;
 
 	switch (dport->port) {
 	case PORT_B:
@@ -1906,7 +1906,8 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	struct drm_device *dev = dev_priv->dev;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	uint32_t reg, val, pipeconf_val;
+	struct i915_reg reg;
+	uint32_t val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
 	BUG_ON(!HAS_PCH_SPLIT(dev));
@@ -1995,7 +1996,8 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 					    enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	uint32_t reg, val;
+	struct i915_reg reg;
+	uint32_t val;
 
 	/* FDI relies on the transcoder */
 	assert_fdi_tx_disabled(dev_priv, pipe);
@@ -2053,7 +2055,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 	enum pipe pch_transcoder;
-	int reg;
+	struct i915_reg reg;
 	u32 val;
 
 	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
@@ -2114,7 +2116,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
-	int reg;
 	u32 val;
 
 	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
@@ -2127,8 +2128,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	assert_cursor_disabled(dev_priv, pipe);
 	assert_sprites_disabled(dev_priv, pipe);
 
-	reg = PIPECONF(cpu_transcoder);
-	val = I915_READ(reg);
+	val = I915_READ(PIPECONF(cpu_transcoder));
 	if ((val & PIPECONF_ENABLE) == 0)
 		return;
 
@@ -2144,7 +2144,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	    !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
 		val &= ~PIPECONF_ENABLE;
 
-	I915_WRITE(reg, val);
+	I915_WRITE(PIPECONF(cpu_transcoder), val);
 	if ((val & PIPECONF_ENABLE) == 0)
 		intel_wait_for_pipe_off(crtc);
 }
@@ -2599,16 +2599,15 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	unsigned long linear_offset;
 	u32 dspcntr;
-	u32 reg = DSPCNTR(plane);
 	int pixel_size;
 
 	if (!visible || !fb) {
-		I915_WRITE(reg, 0);
+		I915_WRITE(DSPCNTR(plane), 0);
 		if (INTEL_INFO(dev)->gen >= 4)
 			I915_WRITE(DSPSURF(plane), 0);
 		else
 			I915_WRITE(DSPADDR(plane), 0);
-		POSTING_READ(reg);
+		POSTING_READ(DSPCNTR(plane));
 		return;
 	}
 
@@ -2700,7 +2699,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
 	}
 
-	I915_WRITE(reg, dspcntr);
+	I915_WRITE(DSPCNTR(plane), dspcntr);
 
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
 	if (INTEL_INFO(dev)->gen >= 4) {
@@ -2710,7 +2709,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		I915_WRITE(DSPLINOFF(plane), linear_offset);
 	} else
 		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
-	POSTING_READ(reg);
+	POSTING_READ(DSPCNTR(plane));
 }
 
 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
@@ -2726,13 +2725,12 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	unsigned long linear_offset;
 	u32 dspcntr;
-	u32 reg = DSPCNTR(plane);
 	int pixel_size;
 
 	if (!visible || !fb) {
-		I915_WRITE(reg, 0);
+		I915_WRITE(DSPCNTR(plane), 0);
 		I915_WRITE(DSPSURF(plane), 0);
-		POSTING_READ(reg);
+		POSTING_READ(DSPCNTR(plane));
 		return;
 	}
 
@@ -2800,7 +2798,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		}
 	}
 
-	I915_WRITE(reg, dspcntr);
+	I915_WRITE(DSPCNTR(plane), dspcntr);
 
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
 	I915_WRITE(DSPSURF(plane),
@@ -2811,7 +2809,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE(DSPLINOFF(plane), linear_offset);
 	}
-	POSTING_READ(reg);
+	POSTING_READ(DSPCNTR(plane));
 }
 
 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
@@ -3289,7 +3287,8 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
+	struct i915_reg reg;
+	u32 temp;
 
 	/* enable normal train */
 	reg = FDI_TX_CTL(pipe);
@@ -3331,7 +3330,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp, tries;
+	struct i915_reg reg;
+	u32 temp, tries;
 
 	/* FDI needs bits from pipe first */
 	assert_pipe_enabled(dev_priv, pipe);
@@ -3431,7 +3431,8 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp, i, retry;
+	struct i915_reg reg;
+	u32 temp, i, retry;
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
@@ -3563,7 +3564,8 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp, i, j;
+	struct i915_reg reg;
+	u32 temp, i, j;
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
@@ -3680,8 +3682,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
-
+	struct i915_reg reg;
+	u32 temp;
 
 	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
 	reg = FDI_RX_CTL(pipe);
@@ -3717,7 +3719,8 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
+	struct i915_reg reg;
+	u32 temp;
 
 	/* Switch from PCDclk to Rawclk */
 	reg = FDI_RX_CTL(pipe);
@@ -3747,7 +3750,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
+	struct i915_reg reg;
+	u32 temp;
 
 	/* disable CPU FDI tx and PCH FDI rx */
 	reg = FDI_TX_CTL(pipe);
@@ -4037,7 +4041,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
+	u32 temp;
 
 	assert_pch_transcoder_disabled(dev_priv, pipe);
 
@@ -4085,8 +4089,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
-		reg = TRANS_DP_CTL(pipe);
-		temp = I915_READ(reg);
+		temp = I915_READ(TRANS_DP_CTL(pipe));
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
 			  TRANS_DP_SYNC_MASK |
 			  TRANS_DP_BPC_MASK);
@@ -4099,20 +4102,20 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
 		switch (intel_trans_dp_port_sel(crtc)) {
-		case PCH_DP_B:
+		case _PCH_DP_B:
 			temp |= TRANS_DP_PORT_SEL_B;
 			break;
-		case PCH_DP_C:
+		case _PCH_DP_C:
 			temp |= TRANS_DP_PORT_SEL_C;
 			break;
-		case PCH_DP_D:
+		case _PCH_DP_D:
 			temp |= TRANS_DP_PORT_SEL_D;
 			break;
 		default:
 			BUG();
 		}
 
-		I915_WRITE(reg, temp);
+		I915_WRITE(TRANS_DP_CTL(pipe), temp);
 	}
 
 	ironlake_enable_pch_transcoder(dev_priv, pipe);
@@ -4242,7 +4245,7 @@ static void intel_shared_dpll_commit(struct drm_atomic_state *state)
 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int dslreg = PIPEDSL(pipe);
+	struct i915_reg dslreg = PIPEDSL(pipe);
 	u32 temp;
 
 	temp = I915_READ(dslreg);
@@ -4553,7 +4556,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
 	}
 
 	for (i = 0; i < 256; i++) {
-		u32 palreg;
+		struct i915_reg palreg;
 
 		if (HAS_GMCH_DISPLAY(dev))
 			palreg = PALETTE(pipe, i);
@@ -4961,7 +4964,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->disable(encoder);
@@ -4987,6 +4989,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 		ironlake_disable_pch_transcoder(dev_priv, pipe);
 
 		if (HAS_PCH_CPT(dev)) {
+			struct i915_reg reg;
+			u32 temp;
+
 			/* disable TRANS_DP_CTL */
 			reg = TRANS_DP_CTL(pipe);
 			temp = I915_READ(reg);
@@ -7288,7 +7293,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = crtc->pipe;
-	int dpll_reg = DPLL(crtc->pipe);
+	struct i915_reg dpll_reg = DPLL(crtc->pipe);
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 loopfilter, tribuf_calcntr;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
@@ -9826,7 +9831,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 	}
 
 	if (intel_crtc->cursor_base != base) {
-		I915_WRITE(_CURABASE, base);
+		I915_WRITE(CURBASE(PIPE_A), base);
 		intel_crtc->cursor_base = base;
 	}
 
@@ -10984,7 +10989,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 	 */
 	if (ring->id == RCS) {
 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-		intel_ring_emit(ring, DERRMR);
+		intel_ring_emit(ring, DERRMR.reg);
 		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
 					DERRMR_PIPEB_PRI_FLIP_DONE |
 					DERRMR_PIPEC_PRI_FLIP_DONE));
@@ -10994,7 +10999,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 		else
 			intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
 					      MI_SRM_LRM_GLOBAL_GTT);
-		intel_ring_emit(ring, DERRMR);
+		intel_ring_emit(ring, DERRMR.reg);
 		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 		if (IS_GEN8(dev)) {
 			intel_ring_emit(ring, 0);
@@ -11090,10 +11095,9 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct intel_framebuffer *intel_fb =
 		to_intel_framebuffer(intel_crtc->base.primary->fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
+	struct i915_reg reg = DSPCNTR(intel_crtc->plane);
 	u32 dspcntr;
-	u32 reg;
 
-	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
 	if (obj->tiling_mode != I915_TILING_NONE)
@@ -11106,7 +11110,6 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 	I915_WRITE(DSPSURF(intel_crtc->plane),
 		   intel_crtc->unpin_work->gtt_offset);
 	POSTING_READ(DSPSURF(intel_crtc->plane));
-
 }
 
 /*
@@ -14661,7 +14664,7 @@ static void i915_disable_vga(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u8 sr1;
-	u32 vga_reg = i915_vgacntrl_reg(dev);
+	struct i915_reg vga_reg = i915_vgacntrl_reg(dev);
 
 	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
 	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
@@ -14834,13 +14837,12 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg, val;
+	u32 val;
 
 	if (INTEL_INFO(dev)->num_pipes == 1)
 		return true;
 
-	reg = DSPCNTR(!crtc->plane);
-	val = I915_READ(reg);
+	val = I915_READ(DSPCNTR(!crtc->plane));
 
 	if ((val & DISPLAY_PLANE_ENABLE) &&
 	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
@@ -14864,10 +14866,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg;
+	struct i915_reg reg = PIPECONF(crtc->config->cpu_transcoder);
 
 	/* Clear any frame start delays used for debugging left by the BIOS */
-	reg = PIPECONF(crtc->config->cpu_transcoder);
 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 
 	/* restore vblank interrupts to correct state */
@@ -15013,7 +15014,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 void i915_redisable_vga_power_on(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 vga_reg = i915_vgacntrl_reg(dev);
+	struct i915_reg vga_reg = i915_vgacntrl_reg(dev);
 
 	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
 		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0e5f674..6d7a3af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -541,7 +541,8 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 	}
 }
 
-static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
+static struct i915_reg
+_pp_ctrl_reg(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
@@ -553,7 +554,8 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 }
 
-static u32 _pp_stat_reg(struct intel_dp *intel_dp)
+static struct i915_reg
+_pp_stat_reg(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
@@ -574,8 +576,6 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 						 edp_notifier);
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 pp_div;
-	u32 pp_ctrl_reg, pp_div_reg;
 
 	if (!is_edp(intel_dp) || code != SYS_RESTART)
 		return 0;
@@ -584,6 +584,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 	if (IS_VALLEYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+		struct i915_reg pp_ctrl_reg, pp_div_reg;
+		u32 pp_div;
 
 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
@@ -652,7 +654,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
+	struct i915_reg ch_ctl = intel_dp->aux_ch_ctl_reg;
 	uint32_t status;
 	bool done;
 
@@ -751,7 +753,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 	else
 		precharge = 5;
 
-	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
+	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg.reg == DP_AUX_CH_CTL(PORT_A).reg)
 		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 	else
 		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -790,7 +792,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
+	struct i915_reg ch_ctl = intel_dp->aux_ch_ctl_reg;
 	uint32_t aux_clock_divider;
 	int i, ret, recv_bytes;
 	uint32_t status;
@@ -1008,15 +1010,15 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 	return ret;
 }
 
-static uint32_t g4x_aux_reg(struct drm_i915_private *dev_priv,
-			    enum port port, int index)
+static struct i915_reg g4x_aux_reg(struct drm_i915_private *dev_priv,
+				   enum port port, int index)
 {
 	return index < 0 ? DP_AUX_CH_CTL(port) :
 		DP_AUX_CH_DATA(port, index);
 }
 
-static uint32_t ilk_aux_reg(struct drm_i915_private *dev_priv,
-			    enum port port, int index)
+static struct i915_reg ilk_aux_reg(struct drm_i915_private *dev_priv,
+				   enum port port, int index)
 {
 	if (port == PORT_A)
 		return index < 0 ? DP_AUX_CH_CTL(port) :
@@ -1050,8 +1052,8 @@ static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
 	}
 }
 
-static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
-			    enum port port, int index)
+static struct i915_reg skl_aux_reg(struct drm_i915_private *dev_priv,
+				   enum port port, int index)
 {
 	if (port == PORT_E)
 		port = skl_porte_aux_port(dev_priv);
@@ -1061,8 +1063,8 @@ static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
 }
 
 static void aux_reg_init(struct intel_dp *intel_dp,
-			 uint32_t (*aux_reg)(struct drm_i915_private *dev_priv,
-					     enum port port, int index))
+			 struct i915_reg (*aux_reg)(struct drm_i915_private *dev_priv,
+						    enum port port, int index))
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 	enum port port = dp_to_dig_port(intel_dp)->port;
@@ -1702,7 +1704,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 pp_stat_reg, pp_ctrl_reg;
+	struct i915_reg pp_stat_reg, pp_ctrl_reg;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -1792,7 +1794,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
 	u32 pp;
-	u32 pp_stat_reg, pp_ctrl_reg;
+	struct i915_reg pp_stat_reg, pp_ctrl_reg;
 	bool need_to_disable = !intel_dp->want_panel_vdd;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
@@ -1868,7 +1870,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	struct intel_encoder *intel_encoder = &intel_dig_port->base;
 	enum intel_display_power_domain power_domain;
 	u32 pp;
-	u32 pp_stat_reg, pp_ctrl_reg;
+	struct i915_reg pp_stat_reg, pp_ctrl_reg;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -1955,7 +1957,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
-	u32 pp_ctrl_reg;
+	struct i915_reg pp_ctrl_reg;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -2017,7 +2019,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
 	u32 pp;
-	u32 pp_ctrl_reg;
+	struct i915_reg pp_ctrl_reg;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -2068,7 +2070,7 @@ static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
-	u32 pp_ctrl_reg;
+	struct i915_reg pp_ctrl_reg;
 
 	/*
 	 * If we enable the backlight right away following a panel power
@@ -2109,7 +2111,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
-	u32 pp_ctrl_reg;
+	struct i915_reg pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -2283,7 +2285,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 		}
 
 		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
-			      intel_dp->output_reg);
+			      intel_dp->output_reg.reg);
 	} else if (IS_CHERRYVIEW(dev)) {
 		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
 	} else {
@@ -2671,7 +2673,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
 	enum pipe pipe = intel_dp->pps_pipe;
-	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
+	struct i915_reg pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
 
 	edp_panel_vdd_off_sync(intel_dp);
 
@@ -5256,7 +5258,7 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
 
 		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 		    intel_encoder->type == INTEL_OUTPUT_EDP)
-			return intel_dp->output_reg;
+			return intel_dp->output_reg.reg;
 	}
 
 	return -1;
@@ -5326,7 +5328,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 	struct edp_power_seq cur, vbt, spec,
 		*final = &intel_dp->pps_delays;
 	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
-	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
+	struct i915_reg pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -5448,7 +5450,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp_on, pp_off, pp_div, port_sel = 0;
 	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
-	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
+	struct i915_reg pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
 	enum port port = dp_to_dig_port(intel_dp)->port;
 	const struct edp_power_seq *seq = &intel_dp->pps_delays;
 
@@ -5548,7 +5550,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	struct intel_dp *intel_dp = dev_priv->drrs.dp;
 	struct intel_crtc_state *config = NULL;
 	struct intel_crtc *intel_crtc = NULL;
-	u32 reg, val;
 	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
 
 	if (refresh_rate <= 0) {
@@ -5610,8 +5611,9 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 			DRM_ERROR("Unsupported refreshrate type\n");
 		}
 	} else if (INTEL_INFO(dev)->gen > 6) {
-		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
-		val = I915_READ(reg);
+		struct i915_reg reg =
+			PIPECONF(intel_crtc->config->cpu_transcoder);
+		u32 val = I915_READ(reg);
 
 		if (index > DRRS_HIGH_RR) {
 			if (IS_VALLEYVIEW(dev))
@@ -6167,7 +6169,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 }
 
 void
-intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
+intel_dp_init(struct drm_device *dev,
+	      struct i915_reg output_reg, enum port port)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3fea039..afd8ac8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -666,7 +666,7 @@ struct cxsr_latency {
 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 
 struct intel_hdmi {
-	u32 hdmi_reg;
+	struct i915_reg hdmi_reg;
 	int ddc_bus;
 	bool limited_color_range;
 	bool color_range_auto;
@@ -715,9 +715,9 @@ struct sink_crc {
 };
 
 struct intel_dp {
-	uint32_t output_reg;
-	uint32_t aux_ch_ctl_reg;
-	uint32_t aux_ch_data_reg[5];
+	struct i915_reg output_reg;
+	struct i915_reg aux_ch_ctl_reg;
+	struct i915_reg aux_ch_data_reg[5];
 	uint32_t DP;
 	int link_rate;
 	uint8_t lane_count;
@@ -1182,7 +1182,7 @@ void intel_csr_ucode_fini(struct drm_device *dev);
 void assert_csr_loaded(struct drm_i915_private *dev_priv);
 
 /* intel_dp.c */
-void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
+void intel_dp_init(struct drm_device *dev, struct i915_reg output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 			     struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
@@ -1276,7 +1276,7 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
 
 /* intel_hdmi.c */
-void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
+void intel_hdmi_init(struct drm_device *dev, struct i915_reg hdmi_reg, enum port port);
 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 			       struct intel_connector *intel_connector);
 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
@@ -1415,7 +1415,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 
 /* intel_sdvo.c */
-bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
+bool intel_sdvo_init(struct drm_device *dev,
+		     struct i915_reg reg, bool is_sdvob);
 
 
 /* intel_sprite.c */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8f9c814..5b5a1c6 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -60,7 +60,8 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
 		DRM_ERROR("DPI FIFOs are not empty\n");
 }
 
-static void write_data(struct drm_i915_private *dev_priv, u32 reg,
+static void write_data(struct drm_i915_private *dev_priv,
+		       struct i915_reg reg,
 		       const u8 *data, u32 len)
 {
 	u32 i, j;
@@ -75,7 +76,8 @@ static void write_data(struct drm_i915_private *dev_priv, u32 reg,
 	}
 }
 
-static void read_data(struct drm_i915_private *dev_priv, u32 reg,
+static void read_data(struct drm_i915_private *dev_priv,
+		      struct i915_reg reg,
 		      u8 *data, u32 len)
 {
 	u32 i, j;
@@ -98,7 +100,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 	struct mipi_dsi_packet packet;
 	ssize_t ret;
 	const u8 *header, *data;
-	u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
+	struct i915_reg data_reg, ctrl_reg;
+	u32 data_mask, ctrl_mask;
 
 	ret = mipi_dsi_create_packet(&packet, msg);
 	if (ret < 0)
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index c80fe1f..7739dd7 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -170,7 +170,7 @@ static void intel_disable_dvo(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-	u32 dvo_reg = intel_dvo->dev.dvo_reg;
+	struct i915_reg dvo_reg = intel_dvo->dev.dvo_reg;
 	u32 temp = I915_READ(dvo_reg);
 
 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
@@ -183,7 +183,7 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-	u32 dvo_reg = intel_dvo->dev.dvo_reg;
+	struct i915_reg dvo_reg = intel_dvo->dev.dvo_reg;
 	u32 temp = I915_READ(dvo_reg);
 
 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
@@ -263,17 +263,17 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	int pipe = crtc->pipe;
 	u32 dvo_val;
-	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
+	struct i915_reg dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
 
-	switch (dvo_reg) {
-	case DVOA:
+	switch (dvo_reg.reg) {
+	case _DVOA:
 	default:
 		dvo_srcdim_reg = DVOA_SRCDIM;
 		break;
-	case DVOB:
+	case _DVOB:
 		dvo_srcdim_reg = DVOB_SRCDIM;
 		break;
-	case DVOC:
+	case _DVOC:
 		dvo_srcdim_reg = DVOC_SRCDIM;
 		break;
 	}
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 54daa66..4ae3458 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -99,7 +99,7 @@ void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	for_each_intel_crtc(dev_priv->dev, crtc) {
-		u32 reg = PIPESTAT(crtc->pipe);
+		struct i915_reg reg = PIPESTAT(crtc->pipe);
 		u32 pipestat;
 
 		if (crtc->cpu_fifo_underrun_disabled)
@@ -123,7 +123,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
 					     bool enable, bool old)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg = PIPESTAT(pipe);
+	struct i915_reg reg = PIPESTAT(pipe);
 	u32 pipestat = I915_READ(reg) & 0xffff0000;
 
 	assert_spin_locked(&dev_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6b16292..88d4eb0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -113,10 +113,11 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 	}
 }
 
-static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
-			    enum transcoder cpu_transcoder,
-			    enum hdmi_infoframe_type type,
-			    int i)
+static struct i915_reg
+hsw_dip_data_reg(struct drm_i915_private *dev_priv,
+		 enum transcoder cpu_transcoder,
+		 enum hdmi_infoframe_type type,
+		 int i)
 {
 	switch (type) {
 	case HDMI_INFOFRAME_TYPE_AVI:
@@ -127,7 +128,7 @@ static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 	default:
 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
-		return 0;
+		return _REG(0);
 	}
 }
 
@@ -193,8 +194,9 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	int i;
 
 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
@@ -229,7 +231,7 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
-	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 
 	if ((val & VIDEO_DIP_ENABLE) == 0)
@@ -251,8 +253,9 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	int i;
 
 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
@@ -289,8 +292,7 @@ static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
-	u32 val = I915_READ(reg);
+	u32 val = I915_READ(TVIDEO_DIP_CTL(intel_crtc->pipe));
 
 	if ((val & VIDEO_DIP_ENABLE) == 0)
 		return false;
@@ -308,8 +310,9 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	int i;
 
 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
@@ -344,8 +347,7 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
-	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
-	u32 val = I915_READ(reg);
+	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(intel_crtc->pipe));
 
 	if ((val & VIDEO_DIP_ENABLE) == 0)
 		return false;
@@ -367,13 +369,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
-	u32 data_reg;
+	struct i915_reg ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
+	struct i915_reg data_reg;
 	int i;
 	u32 val = I915_READ(ctl_reg);
 
 	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
-	if (data_reg == 0)
+	if (data_reg.reg == 0)
 		return;
 
 	val &= ~hsw_infoframe_enable(type);
@@ -401,8 +403,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
-	u32 val = I915_READ(ctl_reg);
+	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder));
 
 	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
@@ -516,7 +517,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
-	u32 reg = VIDEO_DIP_CTL;
+	struct i915_reg reg = VIDEO_DIP_CTL;
 	u32 val = I915_READ(reg);
 	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 
@@ -636,7 +637,8 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
-	u32 reg, val = 0;
+	struct i915_reg reg;
+	u32 val = 0;
 
 	if (HAS_DDI(dev_priv))
 		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
@@ -669,7 +671,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
-	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 
@@ -720,7 +722,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 
 	assert_hdmi_port_disabled(intel_hdmi);
@@ -763,7 +765,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	struct i915_reg reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 
@@ -814,7 +816,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
+	struct i915_reg reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 	u32 val = I915_READ(reg);
 
 	assert_hdmi_port_disabled(intel_hdmi);
@@ -2134,7 +2136,8 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 	}
 }
 
-void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
+void intel_hdmi_init(struct drm_device *dev,
+		     struct i915_reg hdmi_reg, enum port port)
 {
 	struct intel_digital_port *intel_dig_port;
 	struct intel_encoder *intel_encoder;
@@ -2205,7 +2208,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 
 	intel_dig_port->port = port;
 	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
-	intel_dig_port->dp.output_reg = 0;
+	intel_dig_port->dp.output_reg = _REG(0);
 
 	intel_hdmi_init_connector(intel_dig_port, intel_connector);
 }
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1369fc4..1e59be6 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -36,7 +36,7 @@
 
 struct gmbus_pin {
 	const char *name;
-	int reg;
+	struct i915_reg reg;
 };
 
 /* Map gmbus pin pairs to names and registers. */
@@ -96,7 +96,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 	else
 		size = ARRAY_SIZE(gmbus_pins);
 
-	return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
+	return pin < size && get_gmbus_pin(dev_priv, pin)->reg.reg;
 }
 
 /* Intel GPIO access functions */
@@ -240,8 +240,8 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 
 	algo = &bus->bit_algo;
 
-	bus->gpio_reg = dev_priv->gpio_mmio_base +
-		get_gmbus_pin(dev_priv, pin)->reg;
+	bus->gpio_reg = get_gmbus_pin(dev_priv, pin)->reg;
+	bus->gpio_reg.reg += dev_priv->gpio_mmio_base;
 
 	bus->adapter.algo_data = algo;
 	algo->setsda = set_data;
@@ -627,7 +627,7 @@ int intel_setup_gmbus(struct drm_device *dev)
 	if (HAS_PCH_NOP(dev))
 		return 0;
 	else if (HAS_PCH_SPLIT(dev))
-		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
+		dev_priv->gpio_mmio_base = PCH_GPIOA.reg - GPIOA.reg;
 	else if (IS_VALLEYVIEW(dev))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ca9f161..b254260 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -934,7 +934,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
 
 		intel_logical_ring_emit(ringbuf, MI_NOOP);
 		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
-		intel_logical_ring_emit(ringbuf, INSTPM);
+		intel_logical_ring_emit(ringbuf, INSTPM.reg);
 		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 		intel_logical_ring_advance(ringbuf);
 
@@ -1109,7 +1109,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
 
 	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
 	for (i = 0; i < w->count; i++) {
-		intel_logical_ring_emit(ringbuf, w->reg[i].addr);
+		intel_logical_ring_emit(ringbuf, w->reg[i].addr.reg);
 		intel_logical_ring_emit(ringbuf, w->reg[i].value);
 	}
 	intel_logical_ring_emit(ringbuf, MI_NOOP);
@@ -1167,12 +1167,12 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
 
 	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
 				   MI_SRM_LRM_GLOBAL_GTT));
-	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+	wa_ctx_emit(batch, index, GEN8_L3SQCREG4.reg);
 	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
 	wa_ctx_emit(batch, index, 0);
 
 	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+	wa_ctx_emit(batch, index, GEN8_L3SQCREG4.reg);
 	wa_ctx_emit(batch, index, l3sqc4_flush);
 
 	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
@@ -1185,7 +1185,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
 
 	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
 				   MI_SRM_LRM_GLOBAL_GTT));
-	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+	wa_ctx_emit(batch, index, GEN8_L3SQCREG4.reg);
 	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
 	wa_ctx_emit(batch, index, 0);
 
@@ -1355,7 +1355,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
 	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
+		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0.reg);
 		wa_ctx_emit(batch, index,
 			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
 		wa_ctx_emit(batch, index, MI_NOOP);
@@ -1551,9 +1551,9 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
 	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 
-		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
+		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i).reg);
 		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
-		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
+		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i).reg);
 		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
 	}
 
@@ -2256,20 +2256,20 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
 	else
 		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
 	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
-	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
+	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring).reg;
 	reg_state[CTX_CONTEXT_CONTROL+1] =
 		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
 				   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
 				   CTX_CTRL_RS_CTX_ENABLE);
-	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
+	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base).reg;
 	reg_state[CTX_RING_HEAD+1] = 0;
-	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
+	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base).reg;
 	reg_state[CTX_RING_TAIL+1] = 0;
-	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
+	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base).reg;
 	/* Ring buffer start address is not known until the buffer is pinned.
 	 * It is written to the context image in execlists_update_context()
 	 */
-	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
+	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base).reg;
 	reg_state[CTX_RING_BUFFER_CONTROL+1] =
 			((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
 	reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
@@ -2311,14 +2311,14 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
 	reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
 	reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
 	reg_state[CTX_CTX_TIMESTAMP+1] = 0;
-	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
-	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
-	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
-	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
-	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
-	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
-	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
-	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
+	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3).reg;
+	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3).reg;
+	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2).reg;
+	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2).reg;
+	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1).reg;
+	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1).reg;
+	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0).reg;
+	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0).reg;
 
 	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
 		/* 64b PPGTT (48bit canonical)
@@ -2340,7 +2340,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
 
 	if (ring->id == RCS) {
 		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
-		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
+		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE.reg;
 		reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 8a08a27..28d6c26b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -26,18 +26,6 @@
 
 #define GEN8_LR_CONTEXT_ALIGN 4096
 
-/* Execlists regs */
-#define RING_ELSP(ring)			((ring)->mmio_base+0x230)
-#define RING_EXECLIST_STATUS_LO(ring)	((ring)->mmio_base+0x234)
-#define RING_EXECLIST_STATUS_HI(ring)	((ring)->mmio_base+0x234 + 4)
-#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
-#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
-#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
-#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
-#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	((ring)->mmio_base+0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	((ring)->mmio_base+0x370 + (i) * 8 + 4)
-#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
-
 /* Logical Rings */
 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 35bad71..387359c 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -51,7 +51,7 @@ struct intel_lvds_encoder {
 	struct intel_encoder base;
 
 	bool is_dual_link;
-	u32 reg;
+	struct i915_reg reg;
 	u32 a3_power;
 
 	struct intel_lvds_connector *attached_connector;
@@ -211,7 +211,7 @@ static void intel_enable_lvds(struct intel_encoder *encoder)
 	struct intel_connector *intel_connector =
 		&lvds_encoder->attached_connector->base;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 ctl_reg, stat_reg;
+	struct i915_reg ctl_reg, stat_reg;
 
 	if (HAS_PCH_SPLIT(dev)) {
 		ctl_reg = PCH_PP_CONTROL;
@@ -236,7 +236,7 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
 	struct drm_device *dev = encoder->base.dev;
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 ctl_reg, stat_reg;
+	struct i915_reg ctl_reg, stat_reg;
 
 	if (HAS_PCH_SPLIT(dev)) {
 		ctl_reg = PCH_PP_CONTROL;
@@ -940,7 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
 	struct drm_display_mode *downclock_mode = NULL;
 	struct edid *edid;
 	struct drm_crtc *crtc;
-	u32 lvds_reg;
+	struct i915_reg lvds_reg;
 	u32 lvds;
 	int pipe;
 	u8 pin;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0d43d51..11780c1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3431,7 +3431,8 @@ static void skl_compute_wm_results(struct drm_device *dev,
 	r->wm_linetime[pipe] = p_wm->linetime;
 }
 
-static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
+static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
+				struct i915_reg reg,
 				const struct skl_ddb_entry *entry)
 {
 	if (entry->end)
@@ -3936,7 +3937,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_pipe_wm *active = &intel_crtc->wm.active;
 	enum pipe pipe = intel_crtc->pipe;
-	static const unsigned int wm0_pipe_reg[] = {
+	static const struct i915_reg wm0_pipe_reg[] = {
 		[PIPE_A] = WM0_PIPEA_ILK,
 		[PIPE_B] = WM0_PIPEB_ILK,
 		[PIPE_C] = WM0_PIPEC_IVB,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0f944e2..a54c5a6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -80,7 +80,7 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
+	struct i915_reg ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 	uint32_t *data = (uint32_t *) vsc_psr;
 	unsigned int i;
 
@@ -151,8 +151,8 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 }
 
-static uint32_t psr_aux_reg(struct drm_i915_private *dev_priv,
-			    enum port port, int index)
+static struct i915_reg psr_aux_reg(struct drm_i915_private *dev_priv,
+				   enum port port, int index)
 {
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		return index < 0 ? DP_AUX_CH_CTL(port) :
@@ -168,7 +168,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t aux_clock_divider;
-	uint32_t aux_ctl_reg;
+	struct i915_reg aux_ctl_reg;
 	int precharge = 0x3;
 	static const uint8_t aux_msg[] = {
 		[0] = DP_AUX_NATIVE_WRITE << 4,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 16a4ead..04af256 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -479,7 +479,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
-	u32 mmio = 0;
+	struct i915_reg mmio;
 
 	/* The ring status page addresses are no longer next to the rest of
 	 * the ring registers as of gen7.
@@ -522,7 +522,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 	 * invalidating the TLB?
 	 */
 	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
-		u32 reg = RING_INSTPM(ring->mmio_base);
+		struct i915_reg reg = RING_INSTPM(ring->mmio_base);
 
 		/* ring should be idle before issuing a sync flush*/
 		WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
@@ -731,7 +731,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 	for (i = 0; i < w->count; i++) {
-		intel_ring_emit(ring, w->reg[i].addr);
+		intel_ring_emit(ring, w->reg[i].addr.reg);
 		intel_ring_emit(ring, w->reg[i].value);
 	}
 	intel_ring_emit(ring, MI_NOOP);
@@ -764,7 +764,8 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 }
 
 static int wa_add(struct drm_i915_private *dev_priv,
-		  const u32 addr, const u32 mask, const u32 val)
+		  struct i915_reg addr,
+		  const u32 mask, const u32 val)
 {
 	const u32 idx = dev_priv->workarounds.count;
 
@@ -1289,11 +1290,11 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
 		return ret;
 
 	for_each_ring(useless, dev_priv, i) {
-		u32 mbox_reg = signaller->semaphore.mbox.signal[i];
-		if (mbox_reg != GEN6_NOSYNC) {
+		struct i915_reg mbox_reg = signaller->semaphore.mbox.signal[i];
+		if (mbox_reg.reg != GEN6_NOSYNC.reg) {
 			u32 seqno = i915_gem_request_get_seqno(signaller_req);
 			intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
-			intel_ring_emit(signaller, mbox_reg);
+			intel_ring_emit(signaller, mbox_reg.reg);
 			intel_ring_emit(signaller, seqno);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 49fa41d..96315aa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -247,7 +247,7 @@ struct  intel_engine_cs {
 				/* our mbox written by others */
 				u32		wait[I915_NUM_RINGS];
 				/* mboxes this ring signals to */
-				u32		signal[I915_NUM_RINGS];
+				struct i915_reg	signal[I915_NUM_RINGS];
 			} mbox;
 			u64		signal_ggtt[I915_NUM_RINGS];
 		};
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 05521b5..43e53a3 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -74,7 +74,7 @@ struct intel_sdvo {
 	struct i2c_adapter ddc;
 
 	/* Register for the SDVO device: SDVOB or SDVOC */
-	uint32_t sdvo_reg;
+	struct i915_reg sdvo_reg;
 
 	/* Active outputs controlled by this SDVO output */
 	uint16_t controlled_output;
@@ -240,7 +240,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 	u32 bval = val, cval = val;
 	int i;
 
-	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
+	if (intel_sdvo->sdvo_reg.reg == PCH_SDVOB.reg) {
 		I915_WRITE(intel_sdvo->sdvo_reg, val);
 		POSTING_READ(intel_sdvo->sdvo_reg);
 		/*
@@ -254,7 +254,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 		return;
 	}
 
-	if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
+	if (intel_sdvo->sdvo_reg.reg == GEN3_SDVOB.reg)
 		cval = I915_READ(GEN3_SDVOC);
 	else
 		bval = I915_READ(GEN3_SDVOB);
@@ -1274,11 +1274,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
 			sdvox |= SDVO_BORDER_ENABLE;
 	} else {
 		sdvox = I915_READ(intel_sdvo->sdvo_reg);
-		switch (intel_sdvo->sdvo_reg) {
-		case GEN3_SDVOB:
+		switch (intel_sdvo->sdvo_reg.reg) {
+		case _GEN3_SDVOB:
 			sdvox &= SDVOB_PRESERVE_MASK;
 			break;
-		case GEN3_SDVOC:
+		case _GEN3_SDVOC:
 			sdvox &= SDVOC_PRESERVE_MASK;
 			break;
 		}
@@ -2912,7 +2912,8 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
 	return i2c_add_adapter(&sdvo->ddc) == 0;
 }
 
-bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
+bool intel_sdvo_init(struct drm_device *dev,
+		     struct i915_reg sdvo_reg, bool is_sdvob)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *intel_encoder;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index acf9b4b..9254dd9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -58,7 +58,7 @@ assert_device_not_suspended(struct drm_i915_private *dev_priv)
 static inline void
 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
 {
-	WARN_ON(d->reg_set == 0);
+	WARN_ON(d->reg_set.reg == 0);
 	__raw_i915_write32(d->i915, d->reg_set, d->val_reset);
 }
 
@@ -104,7 +104,7 @@ static inline void
 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 {
 	/* something from same cacheline, but not from the set register */
-	if (d->reg_post)
+	if (d->reg_post.reg)
 		__raw_posting_read(d->i915, d->reg_post);
 }
 
@@ -511,10 +511,11 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 }
 
 /* We give fast paths for the really cool registers */
-#define NEEDS_FORCE_WAKE(reg) \
-	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
+#define NEEDS_FORCE_WAKE(r) \
+	((r).reg < 0x40000 && (r).reg != FORCEWAKE.reg)
 
-#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
+#define REG_RANGE(r, start, end) \
+	((r).reg >= (start) && (r).reg < (end))
 
 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 	(REG_RANGE((reg), 0x2000, 0x4000) || \
@@ -574,12 +575,12 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 	REG_RANGE((reg), 0x9400, 0x9800)
 
-#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
-	((reg) < 0x40000 &&\
-	 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
-	 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
-	 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
-	 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
+#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(r) \
+	((r).reg < 0x40000 && \
+	 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(r) && \
+	 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(r) && \
+	 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(r) && \
+	 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(r))
 
 static void
 ilk_dummy_write(struct drm_i915_private *dev_priv)
@@ -591,8 +592,8 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
 }
 
 static void
-hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
-			bool before)
+hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+			struct i915_reg reg, bool read, bool before)
 {
 	const char *op = read ? "reading" : "writing to";
 	const char *when = before ? "before" : "after";
@@ -602,7 +603,7 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 
 	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 		WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
-		     when, op, reg);
+		     when, op, reg.reg);
 		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 		i915.mmio_debug--; /* Only report the first N failures */
 	}
@@ -635,7 +636,7 @@ hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 
 #define __gen2_read(x) \
 static u##x \
-gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+gen2_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	GEN2_READ_HEADER(x); \
 	val = __raw_i915_read##x(dev_priv, reg); \
 	GEN2_READ_FOOTER; \
@@ -643,7 +644,7 @@ gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 
 #define __gen5_read(x) \
 static u##x \
-gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+gen5_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	GEN2_READ_HEADER(x); \
 	ilk_dummy_write(dev_priv); \
 	val = __raw_i915_read##x(dev_priv, reg); \
@@ -702,7 +703,7 @@ static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 
 #define __vgpu_read(x) \
 static u##x \
-vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+vgpu_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	GEN6_READ_HEADER(x); \
 	val = __raw_i915_read##x(dev_priv, reg); \
 	GEN6_READ_FOOTER; \
@@ -710,7 +711,7 @@ vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 
 #define __gen6_read(x) \
 static u##x \
-gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+gen6_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	GEN6_READ_HEADER(x); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 	if (NEEDS_FORCE_WAKE(reg)) \
@@ -722,7 +723,7 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 
 #define __vlv_read(x) \
 static u##x \
-vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+vlv_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	GEN6_READ_HEADER(x); \
 	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
@@ -734,7 +735,7 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 
 #define __chv_read(x) \
 static u##x \
-chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+chv_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	GEN6_READ_HEADER(x); \
 	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
@@ -747,12 +748,12 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	GEN6_READ_FOOTER; \
 }
 
-#define SKL_NEEDS_FORCE_WAKE(reg) \
-	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
+#define SKL_NEEDS_FORCE_WAKE(r) \
+	((r).reg < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(r))
 
 #define __gen9_read(x) \
 static u##x \
-gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+gen9_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
 	enum forcewake_domains fw_engine; \
 	GEN6_READ_HEADER(x); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
@@ -810,7 +811,7 @@ __gen6_read(64)
 
 #define __gen2_write(x) \
 static void \
-gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+gen2_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
 	GEN2_WRITE_HEADER; \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	GEN2_WRITE_FOOTER; \
@@ -818,7 +819,7 @@ gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
 
 #define __gen5_write(x) \
 static void \
-gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+gen5_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
 	GEN2_WRITE_HEADER; \
 	ilk_dummy_write(dev_priv); \
 	__raw_i915_write##x(dev_priv, reg, val); \
@@ -851,7 +852,7 @@ __gen2_write(64)
 
 #define __gen6_write(x) \
 static void \
-gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+gen6_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
 	u32 __fifo_ret = 0; \
 	GEN6_WRITE_HEADER; \
 	if (NEEDS_FORCE_WAKE(reg)) { \
@@ -866,7 +867,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
 
 #define __hsw_write(x) \
 static void \
-hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+hsw_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
 	u32 __fifo_ret = 0; \
 	GEN6_WRITE_HEADER; \
 	if (NEEDS_FORCE_WAKE(reg)) { \
@@ -884,13 +885,13 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
 
 #define __vgpu_write(x) \
 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
-			  off_t reg, u##x val, bool trace) { \
+			  struct i915_reg reg, u##x val, bool trace) { \
 	GEN6_WRITE_HEADER; \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	GEN6_WRITE_FOOTER; \
 }
 
-static const u32 gen8_shadowed_regs[] = {
+static const struct i915_reg gen8_shadowed_regs[] = {
 	FORCEWAKE_MT,
 	GEN6_RPNSWREQ,
 	GEN6_RC_VIDEO_FREQ,
@@ -901,11 +902,12 @@ static const u32 gen8_shadowed_regs[] = {
 	/* TODO: Other registers are not yet used */
 };
 
-static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
+static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
+			     struct i915_reg reg)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
-		if (reg == gen8_shadowed_regs[i])
+		if (reg.reg == gen8_shadowed_regs[i].reg)
 			return true;
 
 	return false;
@@ -913,10 +915,10 @@ static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 
 #define __gen8_write(x) \
 static void \
-gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+gen8_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
 	GEN6_WRITE_HEADER; \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
-	if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
+	if (reg.reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 	__raw_i915_write##x(dev_priv, reg, val); \
 	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
@@ -926,7 +928,7 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
 
 #define __chv_write(x) \
 static void \
-chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+chv_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
 	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 	GEN6_WRITE_HEADER; \
 	if (!shadowed) { \
@@ -941,7 +943,7 @@ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
 	GEN6_WRITE_FOOTER; \
 }
 
-static const u32 gen9_shadowed_regs[] = {
+static const struct i915_reg gen9_shadowed_regs[] = {
 	RING_TAIL(RENDER_RING_BASE),
 	RING_TAIL(GEN6_BSD_RING_BASE),
 	RING_TAIL(VEBOX_RING_BASE),
@@ -954,11 +956,12 @@ static const u32 gen9_shadowed_regs[] = {
 	/* TODO: Other registers are not yet used */
 };
 
-static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
+static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
+			     struct i915_reg reg)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
-		if (reg == gen9_shadowed_regs[i])
+		if (reg.reg == gen9_shadowed_regs[i].reg)
 			return true;
 
 	return false;
@@ -966,7 +969,7 @@ static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 
 #define __gen9_write(x) \
 static void \
-gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
+gen9_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, \
 		bool trace) { \
 	enum forcewake_domains fw_engine; \
 	GEN6_WRITE_HEADER; \
@@ -1043,7 +1046,8 @@ do { \
 
 static void fw_domain_init(struct drm_i915_private *dev_priv,
 			   enum forcewake_domain_id domain_id,
-			   u32 reg_set, u32 reg_ack)
+			   struct i915_reg reg_set,
+			   struct i915_reg reg_ack)
 {
 	struct intel_uncore_forcewake_domain *d;
 
@@ -1073,8 +1077,6 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 		d->reg_post = FORCEWAKE_ACK_VLV;
 	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
 		d->reg_post = ECOBUS;
-	else
-		d->reg_post = 0;
 
 	d->i915 = dev_priv;
 	d->id = domain_id;
@@ -1248,7 +1250,7 @@ void intel_uncore_fini(struct drm_device *dev)
 #define GEN_RANGE(l, h) GENMASK(h, l)
 
 static const struct register_whitelist {
-	uint64_t offset;
+	struct i915_reg offset;
 	uint32_t size;
 	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
 	uint32_t gen_bitmask;
@@ -1263,11 +1265,11 @@ int i915_reg_read_ioctl(struct drm_device *dev,
 	struct drm_i915_reg_read *reg = data;
 	struct register_whitelist const *entry = whitelist;
 	unsigned size;
-	u64 offset;
+	struct i915_reg offset, offset_hi;
 	int i, ret = 0;
 
 	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
-		if (entry->offset == (reg->offset & -entry->size) &&
+		if (entry->offset.reg == (reg->offset & -entry->size) &&
 		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
 			break;
 	}
@@ -1280,14 +1282,15 @@ int i915_reg_read_ioctl(struct drm_device *dev,
 	 * limit the available flags for that register).
 	 */
 	offset = entry->offset;
+	offset_hi.reg = offset.reg + 4;
 	size = entry->size;
-	size |= reg->offset ^ offset;
+	size |= reg->offset ^ offset.reg;
 
 	intel_runtime_pm_get(dev_priv);
 
 	switch (size) {
 	case 8 | 1:
-		reg->val = I915_READ64_2x32(offset, offset+4);
+		reg->val = I915_READ64_2x32(offset, offset_hi);
 		break;
 	case 8:
 		reg->val = I915_READ64(offset);
@@ -1456,7 +1459,7 @@ static int gen6_do_reset(struct drm_device *dev)
 }
 
 static int wait_for_register(struct drm_i915_private *dev_priv,
-			     const u32 reg,
+			     struct i915_reg reg,
 			     const u32 mask,
 			     const u32 value,
 			     const unsigned long timeout_ms)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6a30252..127598d 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3414,14 +3414,14 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe)
 	 * the bits have been set by i915 previously, so we clobber
 	 * SOUTH_CHICKEN2 register directly here.
 	 */
-	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
+	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2.reg);
 
-	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
-	iowrite32(val, mmio_base + PCH_PP_CONTROL);
+	val = ioread32(mmio_base + PCH_PP_CONTROL.reg) & 0xfffffffe;
+	iowrite32(val, mmio_base + PCH_PP_CONTROL.reg);
 
 	timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
 	do {
-		val = ioread32(mmio_base + PCH_PP_STATUS);
+		val = ioread32(mmio_base + PCH_PP_STATUS.reg);
 		if ((val & 0xb0000000) == 0)
 			goto reset_complete;
 		msleep(10);
-- 
2.4.6

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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Chris Wilson]

On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 140076d..0589aba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,16 +25,28 @@
>  #ifndef _I915_REG_H_
>  #define _I915_REG_H_
>  
> +struct i915_reg {
> +	uint32_t reg;
> +};

Fundamental objection averted. Maybe even typedef it to hide the struct,
ignornace is bliss.  i915_reg_t reg; looks reasonable in this instance.

For sanity's sake could you disassemble a simple function and include the
diff in the changelog. It will be reasuring to know that gcc handles the
struct-in-register just fine.

Once upon a time the plan was to use sparse for detecting type
mismatches, hence enum plane and enum pipe, but I know I don't run make
C=1 regularly at all, so using gcc itself is a win.

The downside with this patch is that we have a lot of places that cares
about the reg.reg, and even more where we make up reg on the fly, so it
looks like we are just doing I915_WRITE(_REG(old_u32), x) i.e. more or
less subverting the extra safety, and we would still want something like

	i915_write16(reg) { WARN_ON(reg & 1); }
	i915_write32(reg) { WARN_ON(reg & 3); }

to catch the class of bug where we create an invalid reg address.
-Chris

-- 
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 06:33:38PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 140076d..0589aba 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -25,16 +25,28 @@
> >  #ifndef _I915_REG_H_
> >  #define _I915_REG_H_
> >  
> > +struct i915_reg {
> > +	uint32_t reg;
> > +};
> 
> Fundamental objection averted. Maybe even typedef it to hide the struct,
> ignornace is bliss.  i915_reg_t reg; looks reasonable in this instance.

Yeah typedef would make it less ugly. Maybe i915_mmio_reg_t or something,
so we can add other register types?

> For sanity's sake could you disassemble a simple function and include the
> diff in the changelog. It will be reasuring to know that gcc handles the
> struct-in-register just fine.

Oh right. I did actually mean to look at the generated code, but it then
slipped my mind. I'll definitely have to do that before we consider
actually merging this.

> 
> Once upon a time the plan was to use sparse for detecting type
> mismatches, hence enum plane and enum pipe, but I know I don't run make
> C=1 regularly at all, so using gcc itself is a win.
> 
> The downside with this patch is that we have a lot of places that cares
> about the reg.reg,

That is a bit annoying, yes. I think most of those are in the ring code
where we emit LRIs. I suppose we could add a special version of ring_emit
that takes the struct and thus hides the reg.reg part from the calling
code?

> and even more where we make up reg on the fly, so it
> looks like we are just doing I915_WRITE(_REG(old_u32), x) i.e. more or
> less subverting the extra safety, and we would still want something like
> 
> 	i915_write16(reg) { WARN_ON(reg & 1); }
> 	i915_write32(reg) { WARN_ON(reg & 3); }
> 
> to catch the class of bug where we create an invalid reg address.

I've killed off almost all of the "make up regs on the fly" in the prep
work. I think what was left were vgpu and the 2x32 register read ioctl.
I don't recall any other significant places off the top of my head.

-- 
Ville Syrjälä
Intel OTC
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Chris Wilson]

On Fri, Sep 18, 2015 at 08:43:27PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 06:33:38PM +0100, Chris Wilson wrote:
> > On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 140076d..0589aba 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -25,16 +25,28 @@
> > >  #ifndef _I915_REG_H_
> > >  #define _I915_REG_H_
> > >  
> > > +struct i915_reg {
> > > +	uint32_t reg;
> > > +};
> > 
> > Fundamental objection averted. Maybe even typedef it to hide the struct,
> > ignornace is bliss.  i915_reg_t reg; looks reasonable in this instance.
> 
> Yeah typedef would make it less ugly. Maybe i915_mmio_reg_t or something,
> so we can add other register types?

Yes. Separating out the display/mmio/gpio registers would be nice, that
should spawn a few functions that can check we don't add the wrong base
(if any such remain!). It would mean we end up with a construct like
union i915_reg {
	i915_gt_reg_t gt;
	i915_mmio_reg_t mmio;
	i915_gpio_reg_t gpio;
	i915_display_reg_t display;
};
and typecasting when we try to write a register. Or maybe we just have
more typesafe helpers that call the private vfuncs. It may even be a net
reduction in code size, since we move all the addition of display
offsets into a central location. However, it looks like it may just be
an inconvenient mess.

> > The downside with this patch is that we have a lot of places that cares
> > about the reg.reg,
> 
> That is a bit annoying, yes. I think most of those are in the ring code
> where we emit LRIs. I suppose we could add a special version of ring_emit
> that takes the struct and thus hides the reg.reg part from the calling
> code?

Right, even just adding an inline can be down in a preceding patch and
so reduce churn here and extends the typesafety argument for LRI as
well (and SRM).

I half considered a function to return the raw offset from a struct i915_reg,
that is only marginally better than adding .reg (but only in the case
where we end up with a few very similar i915_reg structs). But it
doesn't actually reduce the churn... unless you add a stub in a previous
patch such that any location that wants to use the register offset as a
value is converted first.
 
> > and even more where we make up reg on the fly, so it
> > looks like we are just doing I915_WRITE(_REG(old_u32), x) i.e. more or
> > less subverting the extra safety, and we would still want something like
> > 
> > 	i915_write16(reg) { WARN_ON(reg & 1); }
> > 	i915_write32(reg) { WARN_ON(reg & 3); }
> > 
> > to catch the class of bug where we create an invalid reg address.
> 
> I've killed off almost all of the "make up regs on the fly" in the prep
> work. I think what was left were vgpu and the 2x32 register read ioctl.
> I don't recall any other significant places off the top of my head.

Never underestimate the cunning of the lazy programmer. Not that I want
to add any more instructions to register access. Going forward, I guess
the rule is to scrutinize _REG() etc very careful and limit them to headers?
-Chris

-- 
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 07:12:30PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 08:43:27PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 06:33:38PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 140076d..0589aba 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -25,16 +25,28 @@
> > > >  #ifndef _I915_REG_H_
> > > >  #define _I915_REG_H_
> > > >  
> > > > +struct i915_reg {
> > > > +	uint32_t reg;
> > > > +};
> > > 
> > > Fundamental objection averted. Maybe even typedef it to hide the struct,
> > > ignornace is bliss.  i915_reg_t reg; looks reasonable in this instance.
> > 
> > Yeah typedef would make it less ugly. Maybe i915_mmio_reg_t or something,
> > so we can add other register types?
> 
> Yes. Separating out the display/mmio/gpio registers would be nice, that
> should spawn a few functions that can check we don't add the wrong base
> (if any such remain!). It would mean we end up with a construct like
> union i915_reg {
> 	i915_gt_reg_t gt;
> 	i915_mmio_reg_t mmio;
> 	i915_gpio_reg_t gpio;
> 	i915_display_reg_t display;
> };
> and typecasting when we try to write a register. Or maybe we just have
> more typesafe helpers that call the private vfuncs. It may even be a net
> reduction in code size, since we move all the addition of display
> offsets into a central location. However, it looks like it may just be
> an inconvenient mess.

I don't think I'll go as far as having different classes of mmio regs.

I was thinking more about sideband stuff. We had at least one case on
CHV where we read the register from a totally wrong sideband port.

I was somewhat thinking of VGA registers too since those are a bit
special (either mmio or port io depending on the gen). Though we have so
little interaction with them that I'm not sure it's worth the effort.

> 
> > > The downside with this patch is that we have a lot of places that cares
> > > about the reg.reg,
> > 
> > That is a bit annoying, yes. I think most of those are in the ring code
> > where we emit LRIs. I suppose we could add a special version of ring_emit
> > that takes the struct and thus hides the reg.reg part from the calling
> > code?
> 
> Right, even just adding an inline can be down in a preceding patch and
> so reduce churn here and extends the typesafety argument for LRI as
> well (and SRM).
> 
> I half considered a function to return the raw offset from a struct i915_reg,
> that is only marginally better than adding .reg (but only in the case
> where we end up with a few very similar i915_reg structs). But it
> doesn't actually reduce the churn... unless you add a stub in a previous
> patch such that any location that wants to use the register offset as a
> value is converted first.
>  
> > > and even more where we make up reg on the fly, so it
> > > looks like we are just doing I915_WRITE(_REG(old_u32), x) i.e. more or
> > > less subverting the extra safety, and we would still want something like
> > > 
> > > 	i915_write16(reg) { WARN_ON(reg & 1); }
> > > 	i915_write32(reg) { WARN_ON(reg & 3); }
> > > 
> > > to catch the class of bug where we create an invalid reg address.
> > 
> > I've killed off almost all of the "make up regs on the fly" in the prep
> > work. I think what was left were vgpu and the 2x32 register read ioctl.
> > I don't recall any other significant places off the top of my head.
> 
> Never underestimate the cunning of the lazy programmer. Not that I want
> to add any more instructions to register access. Going forward, I guess
> the rule is to scrutinize _REG() etc very careful and limit them to headers?

Yeah I wanted to undef _REG() at the end of the header so it can't be
abused, but someone had gone and added register defines to other files
too so I left out the undef for now. And I guess I even abused it myself
in one place myself. So there are still some things to clean up.

-- 
Ville Syrjälä
Intel OTC
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Daniel Vetter]

On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make I915_READ and I915_WRITE more type safe by wrapping the register
> offset in a struct. This should eliminate most of the fumbles we've had
> with misplaced parens.
> 
> This only takes care of normal mmio registers. We could extend the idea
> to other register types and define each with its own struct. That way
> you wouldn't be able to accidentally pass the wrong thing to a specific
> register access function.
> 
> There are a few uglies left:
> - switch statements don't like structs as case values, even if
>   you case 'case DEADBEEF.reg:'. Fortunately we don't have too many
>   of those so can maybe switch them to use some port enums or such,
>   or if all else fails if ladders
> - cmd parser is still iffed out. I was just tool lazy to do that
>   for an RFC
> - the vgpu stuff is ugly cause I didn't spend any time figuring out
>   what it really wants to do
> - maybe something else I'm overlooking?
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I like this very much, which is also why I started pulling in prep patches already.

One bikeshed though: I think this is one of the very few exceptions where
coding style says typedefs are ok, since this really is just an opaque
datatype that gets passed around and only opened-up in low-level code
similar to ptes. So my vote is on i915_reg_t. And since we might want to
extend this to other register io functions maybe call it i915_mmio_reg_t.
-Daniel

> ---
>  drivers/gpu/drm/i915/dvo.h                 |    2 +-
>  drivers/gpu/drm/i915/i915_cmd_parser.c     |   17 +-
>  drivers/gpu/drm/i915/i915_debugfs.c        |    5 +-
>  drivers/gpu/drm/i915/i915_drv.h            |   42 +-
>  drivers/gpu/drm/i915/i915_gem_context.c    |    4 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |    2 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c      |    5 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c        |   27 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c      |    4 +-
>  drivers/gpu/drm/i915/i915_guc_reg.h        |   50 +-
>  drivers/gpu/drm/i915/i915_guc_submission.c |    2 +-
>  drivers/gpu/drm/i915/i915_irq.c            |   32 +-
>  drivers/gpu/drm/i915/i915_reg.h            | 2391 ++++++++++++++--------------
>  drivers/gpu/drm/i915/i915_sysfs.c          |    6 +-
>  drivers/gpu/drm/i915/i915_trace.h          |    4 +-
>  drivers/gpu/drm/i915/i915_vgpu.c           |    6 +-
>  drivers/gpu/drm/i915/i915_vgpu.h           |    2 +-
>  drivers/gpu/drm/i915/intel_audio.c         |   14 +-
>  drivers/gpu/drm/i915/intel_crt.c           |   14 +-
>  drivers/gpu/drm/i915/intel_csr.c           |   12 +-
>  drivers/gpu/drm/i915/intel_ddi.c           |   28 +-
>  drivers/gpu/drm/i915/intel_display.c       |  123 +-
>  drivers/gpu/drm/i915/intel_dp.c            |   65 +-
>  drivers/gpu/drm/i915/intel_drv.h           |   15 +-
>  drivers/gpu/drm/i915/intel_dsi.c           |    9 +-
>  drivers/gpu/drm/i915/intel_dvo.c           |   14 +-
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |    4 +-
>  drivers/gpu/drm/i915/intel_hdmi.c          |   55 +-
>  drivers/gpu/drm/i915/intel_i2c.c           |   10 +-
>  drivers/gpu/drm/i915/intel_lrc.c           |   44 +-
>  drivers/gpu/drm/i915/intel_lrc.h           |   12 -
>  drivers/gpu/drm/i915/intel_lvds.c          |    8 +-
>  drivers/gpu/drm/i915/intel_pm.c            |    5 +-
>  drivers/gpu/drm/i915/intel_psr.c           |    8 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c    |   15 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.h    |    2 +-
>  drivers/gpu/drm/i915/intel_sdvo.c          |   15 +-
>  drivers/gpu/drm/i915/intel_uncore.c        |   97 +-
>  drivers/pci/quirks.c                       |    8 +-
>  39 files changed, 1567 insertions(+), 1611 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/dvo.h b/drivers/gpu/drm/i915/dvo.h
> index 3121633..81626cd 100644
> --- a/drivers/gpu/drm/i915/dvo.h
> +++ b/drivers/gpu/drm/i915/dvo.h
> @@ -32,7 +32,7 @@ struct intel_dvo_device {
>  	const char *name;
>  	int type;
>  	/* DVOA/B/C output register */
> -	u32 dvo_reg;
> +	struct i915_reg dvo_reg;
>  	/* GPIO register used for i2c bus to control this device */
>  	u32 gpio;
>  	int slave_addr;
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 09932ca..9c22f40 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -414,7 +414,7 @@ struct drm_i915_reg_descriptor {
>  
>  /* Convenience macro for adding 32-bit registers. */
>  #define REG32(address, ...)                             \
> -	{ .addr = address, __VA_ARGS__ }
> +	{ .addr = (address).reg, __VA_ARGS__ }
>  
>  /*
>   * Convenience macro for adding 64-bit registers.
> @@ -423,10 +423,12 @@ struct drm_i915_reg_descriptor {
>   * access commands only allow 32-bit accesses. Hence, we have to include
>   * entries for both halves of the 64-bit registers.
>   */
> -#define REG64(addr)                                     \
> -	REG32(addr), REG32(addr + sizeof(u32))
> +#define REG64(address)                                     \
> +	{ .addr = (address).reg },			   \
> +	{ .addr = (address).reg + sizeof(u32) }
>  
>  static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> +#if 0
>  	REG64(GPGPU_THREADS_DISPATCHED),
>  	REG64(HS_INVOCATION_COUNT),
>  	REG64(DS_INVOCATION_COUNT),
> @@ -470,23 +472,30 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
>  	      .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
>                          HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
>  	      .value = 0),
> +#endif
>  };
>  
>  static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
> +#if 0
>  	REG32(BCS_SWCTRL),
> +#endif
>  };
>  
>  static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
> +#if 0
>  	REG32(FORCEWAKE_MT),
>  	REG32(DERRMR),
>  	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
>  	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
>  	REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
> +#endif
>  };
>  
>  static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
> +#if 0
>  	REG32(FORCEWAKE_MT),
>  	REG32(DERRMR),
> +#endif
>  };
>  
>  #undef REG64
> @@ -1020,7 +1029,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
>  			 * to the register. Hence, limit OACONTROL writes to
>  			 * only MI_LOAD_REGISTER_IMM commands.
>  			 */
> -			if (reg_addr == OACONTROL) {
> +			if (reg_addr == OACONTROL.reg) {
>  				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
>  					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
>  					return false;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 38b0e38..94808d4 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3096,7 +3096,8 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
>  
>  	seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
>  	for (i = 0; i < dev_priv->workarounds.count; ++i) {
> -		u32 addr, mask, value, read;
> +		struct i915_reg addr;
> +		u32 mask, value, read;
>  		bool ok;
>  
>  		addr = dev_priv->workarounds.reg[i].addr;
> @@ -3105,7 +3106,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
>  		read = I915_READ(addr);
>  		ok = (value & mask) == (read & mask);
>  		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
> -			   addr, value, mask, read, ok ? "OK" : "FAIL");
> +			   addr.reg, value, mask, read, ok ? "OK" : "FAIL");
>  	}
>  
>  	intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4359af1..40d9741 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -698,18 +698,18 @@ struct intel_uncore_funcs {
>  	void (*force_wake_put)(struct drm_i915_private *dev_priv,
>  							enum forcewake_domains domains);
>  
> -	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
> -	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
> -	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
> -	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
> +	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
> +	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
> +	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
> +	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, struct i915_reg r, bool trace);
>  
> -	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
> +	void (*mmio_writeb)(struct drm_i915_private *dev_priv, struct i915_reg r,
>  				uint8_t val, bool trace);
> -	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
> +	void (*mmio_writew)(struct drm_i915_private *dev_priv, struct i915_reg r,
>  				uint16_t val, bool trace);
> -	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
> +	void (*mmio_writel)(struct drm_i915_private *dev_priv, struct i915_reg r,
>  				uint32_t val, bool trace);
> -	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
> +	void (*mmio_writeq)(struct drm_i915_private *dev_priv, struct i915_reg r,
>  				uint64_t val, bool trace);
>  };
>  
> @@ -726,11 +726,11 @@ struct intel_uncore {
>  		enum forcewake_domain_id id;
>  		unsigned wake_count;
>  		struct timer_list timer;
> -		u32 reg_set;
> +		struct i915_reg reg_set;
>  		u32 val_set;
>  		u32 val_clear;
> -		u32 reg_ack;
> -		u32 reg_post;
> +		struct i915_reg reg_ack;
> +		struct i915_reg reg_post;
>  		u32 val_reset;
>  	} fw_domain[FW_DOMAIN_ID_COUNT];
>  };
> @@ -756,7 +756,7 @@ struct intel_csr {
>  	uint32_t *dmc_payload;
>  	uint32_t dmc_fw_size;
>  	uint32_t mmio_count;
> -	uint32_t mmioaddr[8];
> +	struct i915_reg mmioaddr[8];
>  	uint32_t mmiodata[8];
>  	enum csr_state state;
>  };
> @@ -1022,7 +1022,7 @@ struct intel_gmbus {
>  	struct i2c_adapter adapter;
>  	u32 force_bit;
>  	u32 reg0;
> -	u32 gpio_reg;
> +	struct i915_reg gpio_reg;
>  	struct i2c_algo_bit_data bit_algo;
>  	struct drm_i915_private *dev_priv;
>  };
> @@ -1678,7 +1678,7 @@ struct i915_frontbuffer_tracking {
>  };
>  
>  struct i915_wa_reg {
> -	u32 addr;
> +	struct i915_reg addr;
>  	u32 value;
>  	/* bitmask representing WA bits */
>  	u32 mask;
> @@ -3426,8 +3426,8 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>   * Note: Should only be used between intel_uncore_forcewake_irqlock() and
>   * intel_uncore_forcewake_irqunlock().
>   */
> -#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
> -#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
> +#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__).reg)
> +#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__).reg)
>  #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
>  
>  /* "Broadcast RGB" property */
> @@ -3435,7 +3435,7 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  #define INTEL_BROADCAST_RGB_FULL 1
>  #define INTEL_BROADCAST_RGB_LIMITED 2
>  
> -static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
> +static inline struct i915_reg i915_vgacntrl_reg(struct drm_device *dev)
>  {
>  	if (IS_VALLEYVIEW(dev))
>  		return VLV_VGACNTRL;
> @@ -3506,16 +3506,16 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
>  
>  #define __raw_read(x, s) \
>  static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
> -					     uint32_t reg) \
> +					     struct i915_reg reg) \
>  { \
> -	return read##s(dev_priv->regs + reg); \
> +	return read##s(dev_priv->regs + reg.reg); \
>  }
>  
>  #define __raw_write(x, s) \
>  static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
> -				       uint32_t reg, uint##x##_t val) \
> +				       struct i915_reg reg, uint##x##_t val) \
>  { \
> -	write##s(val, dev_priv->regs + reg); \
> +	write##s(val, dev_priv->regs + reg.reg); \
>  }
>  __raw_read(8, b)
>  __raw_read(16, w)
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 74aa0c9..5799c3a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -532,7 +532,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>  				if (signaller == ring)
>  					continue;
>  
> -				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
> +				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base).reg);
>  				intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
>  			}
>  		}
> @@ -557,7 +557,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>  				if (signaller == ring)
>  					continue;
>  
> -				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
> +				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base).reg);
>  				intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
>  			}
>  		}
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 67ef118..5c4908a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1305,7 +1305,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
>  
>  		intel_ring_emit(ring, MI_NOOP);
>  		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> -		intel_ring_emit(ring, INSTPM);
> +		intel_ring_emit(ring, INSTPM.reg);
>  		intel_ring_emit(ring, instp_mask << 16 | instp_mode);
>  		intel_ring_advance(ring);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index ff94560..bdb9bfe 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -59,7 +59,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int fence_reg_lo, fence_reg_hi;
> +	struct i915_reg fence_reg_lo, fence_reg_hi;
>  	int fence_pitch_shift;
>  
>  	if (INTEL_INFO(dev)->gen >= 6) {
> @@ -118,7 +118,8 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 fence_reg, val;
> +	struct i915_reg fence_reg;
> +	u32 val;
>  
>  	if (obj) {
>  		u32 size = i915_gem_obj_ggtt_size(obj);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 2b6dd70..abe9250 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -661,10 +661,10 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
>  		return ret;
>  
>  	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> -	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
> +	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry).reg);
>  	intel_ring_emit(ring, upper_32_bits(addr));
>  	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> -	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
> +	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry).reg);
>  	intel_ring_emit(ring, lower_32_bits(addr));
>  	intel_ring_advance(ring);
>  
> @@ -904,25 +904,26 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
>  	enum vgt_g2v_type msg;
>  	struct drm_device *dev = ppgtt->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	unsigned int offset = vgtif_reg(pdp0_lo);
>  	int i;
>  
>  	if (USES_FULL_48BIT_PPGTT(dev)) {
>  		u64 daddr = px_dma(&ppgtt->pml4);
> +		struct i915_reg offset_lo = vgtif_reg(pdp0_lo);
> +		struct i915_reg offset_hi = vgtif_reg(pdp0_lo + 4);
>  
> -		I915_WRITE(offset, lower_32_bits(daddr));
> -		I915_WRITE(offset + 4, upper_32_bits(daddr));
> +		I915_WRITE(offset_lo, lower_32_bits(daddr));
> +		I915_WRITE(offset_hi, upper_32_bits(daddr));
>  
>  		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
>  				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
>  	} else {
>  		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
>  			u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
> +			struct i915_reg offset_lo = vgtif_reg(pdp0_lo + i * 8);
> +			struct i915_reg offset_hi = vgtif_reg(pdp0_lo + i * 8 + 4);
>  
> -			I915_WRITE(offset, lower_32_bits(daddr));
> -			I915_WRITE(offset + 4, upper_32_bits(daddr));
> -
> -			offset += 8;
> +			I915_WRITE(offset_lo, lower_32_bits(daddr));
> +			I915_WRITE(offset_hi, upper_32_bits(daddr));
>  		}
>  
>  		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
> @@ -1662,9 +1663,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
>  		return ret;
>  
>  	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
> -	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
> +	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring).reg);
>  	intel_ring_emit(ring, PP_DIR_DCLV_2G);
> -	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
> +	intel_ring_emit(ring, RING_PP_DIR_BASE(ring).reg);
>  	intel_ring_emit(ring, get_pd_offset(ppgtt));
>  	intel_ring_emit(ring, MI_NOOP);
>  	intel_ring_advance(ring);
> @@ -1699,9 +1700,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>  		return ret;
>  
>  	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
> -	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
> +	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring).reg);
>  	intel_ring_emit(ring, PP_DIR_DCLV_2G);
> -	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
> +	intel_ring_emit(ring, RING_PP_DIR_BASE(ring).reg);
>  	intel_ring_emit(ring, get_pd_offset(ppgtt));
>  	intel_ring_emit(ring, MI_NOOP);
>  	intel_ring_advance(ring);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index e873eb4..33bd507 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -858,7 +858,7 @@ static void i915_record_ring_state(struct drm_device *dev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	if (INTEL_INFO(dev)->gen >= 6) {
> -		ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
> +		ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
>  		ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
>  		if (INTEL_INFO(dev)->gen >= 8)
>  			gen8_record_semaphore_state(dev_priv, error, ring, ering);
> @@ -895,7 +895,7 @@ static void i915_record_ring_state(struct drm_device *dev,
>  	ering->ctl = I915_READ_CTL(ring);
>  
>  	if (I915_NEED_GFX_HWS(dev)) {
> -		int mmio;
> +		struct i915_reg mmio;
>  
>  		if (IS_GEN7(dev)) {
>  			switch (ring->id) {
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 848a563..334f58c 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -26,7 +26,7 @@
>  
>  /* Definitions of GuC H/W registers, bits, etc */
>  
> -#define GUC_STATUS			0xc000
> +#define GUC_STATUS			_REG(0xc000)
>  #define   GS_BOOTROM_SHIFT		1
>  #define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
>  #define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
> @@ -38,39 +38,39 @@
>  #define   GS_MIA_SHIFT			16
>  #define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
>  
> -#define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
> +#define SOFT_SCRATCH(n)			_REG(0xc180 + (n) * 4)
>  
> -#define UOS_RSA_SCRATCH(i)		(0xc200 + (i) * 4)
> -#define DMA_ADDR_0_LOW			0xc300
> -#define DMA_ADDR_0_HIGH			0xc304
> -#define DMA_ADDR_1_LOW			0xc308
> -#define DMA_ADDR_1_HIGH			0xc30c
> +#define UOS_RSA_SCRATCH(i)		_REG(0xc200 + (i) * 4)
> +#define DMA_ADDR_0_LOW			_REG(0xc300)
> +#define DMA_ADDR_0_HIGH			_REG(0xc304)
> +#define DMA_ADDR_1_LOW			_REG(0xc308)
> +#define DMA_ADDR_1_HIGH			_REG(0xc30c)
>  #define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
>  #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
> -#define DMA_COPY_SIZE			0xc310
> -#define DMA_CTRL			0xc314
> +#define DMA_COPY_SIZE			_REG(0xc310)
> +#define DMA_CTRL			_REG(0xc314)
>  #define   UOS_MOVE			  (1<<4)
>  #define   START_DMA			  (1<<0)
> -#define DMA_GUC_WOPCM_OFFSET		0xc340
> +#define DMA_GUC_WOPCM_OFFSET		_REG(0xc340)
>  #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>  
> -#define GUC_WOPCM_SIZE			0xc050
> +#define GUC_WOPCM_SIZE			_REG(0xc050)
>  #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
>  
>  /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>  #define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
>  
> -#define GEN8_GT_PM_CONFIG		0x138140
> -#define GEN9LP_GT_PM_CONFIG		0x138140
> -#define GEN9_GT_PM_CONFIG		0x13816c
> +#define GEN8_GT_PM_CONFIG		_REG(0x138140)
> +#define GEN9LP_GT_PM_CONFIG		_REG(0x138140)
> +#define GEN9_GT_PM_CONFIG		_REG(0x13816c)
>  #define   GT_DOORBELL_ENABLE		  (1<<0)
>  
> -#define GEN8_GTCR			0x4274
> +#define GEN8_GTCR			_REG(0x4274)
>  #define   GEN8_GTCR_INVALIDATE		  (1<<0)
>  
> -#define GUC_ARAT_C6DIS			0xA178
> +#define GUC_ARAT_C6DIS			_REG(0xA178)
>  
> -#define GUC_SHIM_CONTROL		0xc064
> +#define GUC_SHIM_CONTROL		_REG(0xc064)
>  #define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
>  #define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
>  #define   GUC_ENABLE_MIA_CACHING		(1<<2)
> @@ -87,21 +87,21 @@
>  				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \
>  				 GUC_ENABLE_MIA_CLOCK_GATING)
>  
> -#define HOST2GUC_INTERRUPT		0xc4c8
> +#define HOST2GUC_INTERRUPT		_REG(0xc4c8)
>  #define   HOST2GUC_TRIGGER		  (1<<0)
>  
>  #define DRBMISC1			0x1984
>  #define   DOORBELL_ENABLE		  (1<<0)
>  
> -#define GEN8_DRBREGL(x)			(0x1000 + (x) * 8)
> +#define GEN8_DRBREGL(x)			_REG(0x1000 + (x) * 8)
>  #define   GEN8_DRB_VALID		  (1<<0)
> -#define GEN8_DRBREGU(x)			(GEN8_DRBREGL(x) + 4)
> +#define GEN8_DRBREGU(x)			_REG(0x1000 + (x) * 8 + 4)
>  
> -#define DE_GUCRMR			0x44054
> +#define DE_GUCRMR			_REG(0x44054)
>  
> -#define GUC_BCS_RCS_IER			0xC550
> -#define GUC_VCS2_VCS1_IER		0xC554
> -#define GUC_WD_VECS_IER			0xC558
> -#define GUC_PM_P24C_IER			0xC55C
> +#define GUC_BCS_RCS_IER			_REG(0xC550)
> +#define GUC_VCS2_VCS1_IER		_REG(0xC554)
> +#define GUC_WD_VECS_IER			_REG(0xC558)
> +#define GUC_PM_P24C_IER			_REG(0xC55C)
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 792d0b9..336a1e70 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -249,7 +249,7 @@ static void guc_disable_doorbell(struct intel_guc *guc,
>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>  	struct guc_doorbell_info *doorbell;
>  	void *base;
> -	int drbreg = GEN8_DRBREGL(client->doorbell_id);
> +	struct i915_reg drbreg = GEN8_DRBREGL(client->doorbell_id);
>  	int value;
>  
>  	base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a6c23b2..61d2c73 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -139,7 +139,8 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
>  /*
>   * We should clear IMR at preinstall/uninstall, and just check at postinstall.
>   */
> -static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
> +static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
> +				    struct i915_reg reg)
>  {
>  	u32 val = I915_READ(reg);
>  
> @@ -147,7 +148,7 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
>  		return;
>  
>  	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
> -	     reg, val);
> +	     reg.reg, val);
>  	I915_WRITE(reg, 0xffffffff);
>  	POSTING_READ(reg);
>  	I915_WRITE(reg, 0xffffffff);
> @@ -245,17 +246,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>  	ilk_update_gt_irq(dev_priv, mask, 0);
>  }
>  
> -static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
> +static struct i915_reg gen6_pm_iir(struct drm_i915_private *dev_priv)
>  {
>  	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>  }
>  
> -static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
> +static struct i915_reg gen6_pm_imr(struct drm_i915_private *dev_priv)
>  {
>  	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
>  }
>  
> -static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
> +static struct i915_reg gen6_pm_ier(struct drm_i915_private *dev_priv)
>  {
>  	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
>  }
> @@ -312,7 +313,7 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>  void gen6_reset_rps_interrupts(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint32_t reg = gen6_pm_iir(dev_priv);
> +	struct i915_reg reg = gen6_pm_iir(dev_priv);
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	I915_WRITE(reg, dev_priv->pm_rps_events);
> @@ -439,7 +440,7 @@ static void
>  __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  		       u32 enable_mask, u32 status_mask)
>  {
> -	u32 reg = PIPESTAT(pipe);
> +	struct i915_reg reg = PIPESTAT(pipe);
>  	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
>  
>  	assert_spin_locked(&dev_priv->irq_lock);
> @@ -466,7 +467,7 @@ static void
>  __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  		        u32 enable_mask, u32 status_mask)
>  {
> -	u32 reg = PIPESTAT(pipe);
> +	struct i915_reg reg = PIPESTAT(pipe);
>  	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
>  
>  	assert_spin_locked(&dev_priv->irq_lock);
> @@ -626,8 +627,7 @@ static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
>  static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	unsigned long high_frame;
> -	unsigned long low_frame;
> +	struct i915_reg high_frame, low_frame;
>  	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
>  	struct intel_crtc *intel_crtc =
>  		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> @@ -1118,7 +1118,7 @@ static void ivybridge_parity_work(struct work_struct *work)
>  	POSTING_READ(GEN7_MISCCPCTL);
>  
>  	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
> -		u32 reg;
> +		struct i915_reg reg;
>  
>  		slice--;
>  		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
> @@ -1126,7 +1126,7 @@ static void ivybridge_parity_work(struct work_struct *work)
>  
>  		dev_priv->l3_parity.which_slice &= ~(1<<slice);
>  
> -		reg = GEN7_L3CDERRST1 + (slice * 0x200);
> +		reg = GEN7_L3CDERRST1(slice);
>  
>  		error_status = I915_READ(reg);
>  		row = GEN7_PARITY_ERROR_ROW(error_status);
> @@ -1555,7 +1555,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
>  
>  	spin_lock(&dev_priv->irq_lock);
>  	for_each_pipe(dev_priv, pipe) {
> -		int reg;
> +		struct i915_reg reg;
>  		u32 mask, iir_bit = 0;
>  
>  		/*
> @@ -3778,7 +3778,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
>  			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
>  
>  		for_each_pipe(dev_priv, pipe) {
> -			int reg = PIPESTAT(pipe);
> +			struct i915_reg reg = PIPESTAT(pipe);
>  			pipe_stats[pipe] = I915_READ(reg);
>  
>  			/*
> @@ -3959,7 +3959,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>  			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
>  
>  		for_each_pipe(dev_priv, pipe) {
> -			int reg = PIPESTAT(pipe);
> +			struct i915_reg reg = PIPESTAT(pipe);
>  			pipe_stats[pipe] = I915_READ(reg);
>  
>  			/* Clear the PIPE*STAT regs before the IIR */
> @@ -4180,7 +4180,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
>  
>  		for_each_pipe(dev_priv, pipe) {
> -			int reg = PIPESTAT(pipe);
> +			struct i915_reg reg = PIPESTAT(pipe);
>  			pipe_stats[pipe] = I915_READ(reg);
>  
>  			/*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 140076d..0589aba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,16 +25,28 @@
>  #ifndef _I915_REG_H_
>  #define _I915_REG_H_
>  
> +struct i915_reg {
> +	uint32_t reg;
> +};
> +
> +#define _REG(r) ((const struct i915_reg){ .reg = (r) })
> +
>  #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
> +#define _REG_PIPE(pipe, a, b) _REG(_PIPE(pipe, a, b))
>  #define _PLANE(plane, a, b) _PIPE(plane, a, b)
> -#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
> +#define _REG_PLANE(plane, a, b) _REG_PIPE(plane, a, b)
> +#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
> +#define _REG_TRANS(tran, a, b) _REG(_TRANS(tran, a, b))
>  #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
> +#define _REG_PORT(port, a, b) _REG(_PORT(port, a, b))
>  #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
>  			       (pipe) == PIPE_B ? (b) : (c))
> +#define _REG_PIPE3(pipe, a, b, c) _REG(_PIPE3(pipe, a, b, c))
>  #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
>  			       (port) == PORT_B ? (b) : (c))
> +#define _REG_PORT3(pipe, a, b, c) _REG(_PORT3(pipe, a, b, c))
>  
> -#define _MASKED_FIELD(mask, value) ({					   \
> +#define _MASKED_FIELD(mask, value) ({					\
>  	if (__builtin_constant_p(mask))					   \
>  		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
>  	if (__builtin_constant_p(value))				   \
> @@ -105,14 +117,14 @@
>  #define  GRDOM_RESET_STATUS (1<<1)
>  #define  GRDOM_RESET_ENABLE (1<<0)
>  
> -#define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
> +#define ILK_GDSR _REG(MCHBAR_MIRROR_BASE + 0x2ca4)
>  #define  ILK_GRDOM_FULL		(0<<1)
>  #define  ILK_GRDOM_RENDER	(1<<1)
>  #define  ILK_GRDOM_MEDIA	(3<<1)
>  #define  ILK_GRDOM_MASK		(3<<1)
>  #define  ILK_GRDOM_RESET_ENABLE (1<<0)
>  
> -#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
> +#define GEN6_MBCUNIT_SNPCR	_REG(0x900c) /* for LLC config */
>  #define   GEN6_MBC_SNPCR_SHIFT	21
>  #define   GEN6_MBC_SNPCR_MASK	(3<<21)
>  #define   GEN6_MBC_SNPCR_MAX	(0<<21)
> @@ -120,31 +132,31 @@
>  #define   GEN6_MBC_SNPCR_LOW	(2<<21)
>  #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
>  
> -#define VLV_G3DCTL		0x9024
> -#define VLV_GSCKGCTL		0x9028
> +#define VLV_G3DCTL		_REG(0x9024)
> +#define VLV_GSCKGCTL		_REG(0x9028)
>  
> -#define GEN6_MBCTL		0x0907c
> +#define GEN6_MBCTL		_REG(0x0907c)
>  #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
>  #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
>  #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
>  #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
>  #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
>  
> -#define GEN6_GDRST	0x941c
> +#define GEN6_GDRST	_REG(0x941c)
>  #define  GEN6_GRDOM_FULL		(1 << 0)
>  #define  GEN6_GRDOM_RENDER		(1 << 1)
>  #define  GEN6_GRDOM_MEDIA		(1 << 2)
>  #define  GEN6_GRDOM_BLT			(1 << 3)
>  
> -#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
> -#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
> -#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
> +#define RING_PP_DIR_BASE(ring)		_REG((ring)->mmio_base+0x228)
> +#define RING_PP_DIR_BASE_READ(ring)	_REG((ring)->mmio_base+0x518)
> +#define RING_PP_DIR_DCLV(ring)		_REG((ring)->mmio_base+0x220)
>  #define   PP_DIR_DCLV_2G		0xffffffff
>  
> -#define GEN8_RING_PDP_UDW(ring, n)	((ring)->mmio_base+0x270 + ((n) * 8 + 4))
> -#define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)
> +#define GEN8_RING_PDP_UDW(ring, n)	_REG((ring)->mmio_base+0x270 + (n) * 8 + 4)
> +#define GEN8_RING_PDP_LDW(ring, n)	_REG((ring)->mmio_base+0x270 + (n) * 8)
>  
> -#define GEN8_R_PWR_CLK_STATE		0x20C8
> +#define GEN8_R_PWR_CLK_STATE		_REG(0x20C8)
>  #define   GEN8_RPCS_ENABLE		(1 << 31)
>  #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
>  #define   GEN8_RPCS_S_CNT_SHIFT		15
> @@ -157,7 +169,7 @@
>  #define   GEN8_RPCS_EU_MIN_SHIFT	0
>  #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
>  
> -#define GAM_ECOCHK			0x4090
> +#define GAM_ECOCHK			_REG(0x4090)
>  #define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
>  #define   ECOCHK_SNB_BIT		(1<<10)
>  #define   ECOCHK_DIS_TLB		(1<<8)
> @@ -170,15 +182,15 @@
>  #define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
>  #define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
>  
> -#define GAC_ECO_BITS			0x14090
> +#define GAC_ECO_BITS			_REG(0x14090)
>  #define   ECOBITS_SNB_BIT		(1<<13)
>  #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
>  #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
>  
> -#define GAB_CTL				0x24000
> +#define GAB_CTL				_REG(0x24000)
>  #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
>  
> -#define GEN6_STOLEN_RESERVED		0x1082C0
> +#define GEN6_STOLEN_RESERVED		_REG(0x1082C0)
>  #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
>  #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
>  #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
> @@ -200,6 +212,7 @@
>  #define VGA_ST01_MDA 0x3ba
>  #define VGA_ST01_CGA 0x3da
>  
> +#define _VGA_MSR_WRITE _REG(0x3c2)
>  #define VGA_MSR_WRITE 0x3c2
>  #define VGA_MSR_READ 0x3cc
>  #define   VGA_MSR_MEM_EN (1<<1)
> @@ -377,10 +390,10 @@
>  #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
>  #define   MI_BATCH_RESOURCE_STREAMER (1<<10)
>  
> -#define MI_PREDICATE_SRC0	(0x2400)
> -#define MI_PREDICATE_SRC1	(0x2408)
> +#define MI_PREDICATE_SRC0	_REG(0x2400)
> +#define MI_PREDICATE_SRC1	_REG(0x2408)
>  
> -#define MI_PREDICATE_RESULT_2	(0x2214)
> +#define MI_PREDICATE_RESULT_2	_REG(0x2214)
>  #define  LOWER_SLICE_ENABLED	(1<<0)
>  #define  LOWER_SLICE_DISABLED	(0<<0)
>  
> @@ -509,45 +522,43 @@
>  /*
>   * Registers used only by the command parser
>   */
> -#define BCS_SWCTRL 0x22200
> -
> -#define GPGPU_THREADS_DISPATCHED        0x2290
> -#define HS_INVOCATION_COUNT             0x2300
> -#define DS_INVOCATION_COUNT             0x2308
> -#define IA_VERTICES_COUNT               0x2310
> -#define IA_PRIMITIVES_COUNT             0x2318
> -#define VS_INVOCATION_COUNT             0x2320
> -#define GS_INVOCATION_COUNT             0x2328
> -#define GS_PRIMITIVES_COUNT             0x2330
> -#define CL_INVOCATION_COUNT             0x2338
> -#define CL_PRIMITIVES_COUNT             0x2340
> -#define PS_INVOCATION_COUNT             0x2348
> -#define PS_DEPTH_COUNT                  0x2350
> +#define BCS_SWCTRL _REG(0x22200)
> +
> +#define GPGPU_THREADS_DISPATCHED        _REG(0x2290)
> +#define HS_INVOCATION_COUNT             _REG(0x2300)
> +#define DS_INVOCATION_COUNT             _REG(0x2308)
> +#define IA_VERTICES_COUNT               _REG(0x2310)
> +#define IA_PRIMITIVES_COUNT             _REG(0x2318)
> +#define VS_INVOCATION_COUNT             _REG(0x2320)
> +#define GS_INVOCATION_COUNT             _REG(0x2328)
> +#define GS_PRIMITIVES_COUNT             _REG(0x2330)
> +#define CL_INVOCATION_COUNT             _REG(0x2338)
> +#define CL_PRIMITIVES_COUNT             _REG(0x2340)
> +#define PS_INVOCATION_COUNT             _REG(0x2348)
> +#define PS_DEPTH_COUNT                  _REG(0x2350)
>  
>  /* There are the 4 64-bit counter registers, one for each stream output */
> -#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
> +#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _REG(0x5200 + (n) * 8)
>  
> -#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
> +#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  _REG(0x5240 + (n) * 8)
>  
> -#define GEN7_3DPRIM_END_OFFSET          0x2420
> -#define GEN7_3DPRIM_START_VERTEX        0x2430
> -#define GEN7_3DPRIM_VERTEX_COUNT        0x2434
> -#define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
> -#define GEN7_3DPRIM_START_INSTANCE      0x243C
> -#define GEN7_3DPRIM_BASE_VERTEX         0x2440
> +#define GEN7_3DPRIM_END_OFFSET          _REG(0x2420)
> +#define GEN7_3DPRIM_START_VERTEX        _REG(0x2430)
> +#define GEN7_3DPRIM_VERTEX_COUNT        _REG(0x2434)
> +#define GEN7_3DPRIM_INSTANCE_COUNT      _REG(0x2438)
> +#define GEN7_3DPRIM_START_INSTANCE      _REG(0x243C)
> +#define GEN7_3DPRIM_BASE_VERTEX         _REG(0x2440)
>  
> -#define OACONTROL 0x2360
> +#define OACONTROL _REG(0x2360)
>  
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
>  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
> -#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
> -					 _GEN7_PIPEA_DE_LOAD_SL, \
> -					 _GEN7_PIPEB_DE_LOAD_SL)
> +#define GEN7_PIPE_DE_LOAD_SL(pipe) _REG_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL))
>  
>  /*
>   * Reset registers
>   */
> -#define DEBUG_RESET_I830		0x6070
> +#define DEBUG_RESET_I830		_REG(0x6070)
>  #define  DEBUG_RESET_FULL		(1<<7)
>  #define  DEBUG_RESET_RENDER		(1<<8)
>  #define  DEBUG_RESET_DISPLAY		(1<<9)
> @@ -555,7 +566,7 @@
>  /*
>   * IOSF sideband
>   */
> -#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
> +#define VLV_IOSF_DOORBELL_REQ			_REG(VLV_DISPLAY_BASE + 0x2100)
>  #define   IOSF_DEVFN_SHIFT			24
>  #define   IOSF_OPCODE_SHIFT			16
>  #define   IOSF_PORT_SHIFT			8
> @@ -572,8 +583,8 @@
>  #define   IOSF_PORT_CCU				0xA9
>  #define   IOSF_PORT_GPS_CORE			0x48
>  #define   IOSF_PORT_FLISDSI			0x1B
> -#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
> -#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
> +#define VLV_IOSF_DATA				_REG(VLV_DISPLAY_BASE + 0x2104)
> +#define VLV_IOSF_ADDR				_REG(VLV_DISPLAY_BASE + 0x2108)
>  
>  /* See configdb bunit SB addr map */
>  #define BUNIT_REG_BISOC				0x11
> @@ -827,7 +838,7 @@ enum skl_disp_power_wells {
>   */
>  #define DPIO_DEVFN			0
>  
> -#define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
> +#define DPIO_CTL			_REG(VLV_DISPLAY_BASE + 0x2110)
>  #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
>  #define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
>  #define  DPIO_SFR_BYPASS		(1<<1)
> @@ -1180,9 +1191,9 @@ enum skl_disp_power_wells {
>  #define   DPIO_UPAR_SHIFT		30
>  
>  /* BXT PHY registers */
> -#define _BXT_PHY(phy, a, b)		_PIPE((phy), (a), (b))
> +#define _BXT_PHY(phy, a, b)		_REG_PIPE((phy), (a), (b))
>  
> -#define BXT_P_CR_GT_DISP_PWRON		0x138090
> +#define BXT_P_CR_GT_DISP_PWRON		_REG(0x138090)
>  #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
>  
>  #define _PHY_CTL_FAMILY_EDP		0x64C80
> @@ -1198,7 +1209,7 @@ enum skl_disp_power_wells {
>  #define   PORT_PLL_ENABLE		(1 << 31)
>  #define   PORT_PLL_LOCK			(1 << 30)
>  #define   PORT_PLL_REF_SEL		(1 << 27)
> -#define BXT_PORT_PLL_ENABLE(port)	_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
> +#define BXT_PORT_PLL_ENABLE(port)	_REG_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
>  
>  #define _PORT_PLL_EBB_0_A		0x162034
>  #define _PORT_PLL_EBB_0_B		0x6C034
> @@ -1209,7 +1220,7 @@ enum skl_disp_power_wells {
>  #define   PORT_PLL_P2_SHIFT		8
>  #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
>  #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
> -#define BXT_PORT_PLL_EBB_0(port)	_PORT3(port, _PORT_PLL_EBB_0_A, \
> +#define BXT_PORT_PLL_EBB_0(port)	_REG_PORT3(port, _PORT_PLL_EBB_0_A, \
>  						_PORT_PLL_EBB_0_B,	\
>  						_PORT_PLL_EBB_0_C)
>  
> @@ -1218,7 +1229,7 @@ enum skl_disp_power_wells {
>  #define _PORT_PLL_EBB_4_C		0x6C344
>  #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
>  #define   PORT_PLL_RECALIBRATE		(1 << 14)
> -#define BXT_PORT_PLL_EBB_4(port)	_PORT3(port, _PORT_PLL_EBB_4_A, \
> +#define BXT_PORT_PLL_EBB_4(port)	_REG_PORT3(port, _PORT_PLL_EBB_4_A, \
>  						_PORT_PLL_EBB_4_B,	\
>  						_PORT_PLL_EBB_4_C)
>  
> @@ -1254,7 +1265,7 @@ enum skl_disp_power_wells {
>  #define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
>  						_PORT_PLL_0_B,		\
>  						_PORT_PLL_0_C)
> -#define BXT_PORT_PLL(port, idx)		(_PORT_PLL_BASE(port) + (idx) * 4)
> +#define BXT_PORT_PLL(port, idx)		_REG(_PORT_PLL_BASE(port) + (idx) * 4)
>  
>  /* BXT PHY common lane registers */
>  #define _PORT_CL1CM_DW0_A		0x162000
> @@ -1292,7 +1303,7 @@ enum skl_disp_power_wells {
>  							_PORT_CL1CM_DW30_A)
>  
>  /* Defined for PHY0 only */
> -#define BXT_PORT_CL2CM_DW6_BC		0x6C358
> +#define BXT_PORT_CL2CM_DW6_BC		_REG(0x6C358)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
>  /* BXT PHY Ref registers */
> @@ -1332,10 +1343,10 @@ enum skl_disp_power_wells {
>  #define _PORT_PCS_DW10_GRP_A		0x162C28
>  #define _PORT_PCS_DW10_GRP_B		0x6CC28
>  #define _PORT_PCS_DW10_GRP_C		0x6CE28
> -#define BXT_PORT_PCS_DW10_LN01(port)	_PORT3(port, _PORT_PCS_DW10_LN01_A, \
> +#define BXT_PORT_PCS_DW10_LN01(port)	_REG_PORT3(port, _PORT_PCS_DW10_LN01_A, \
>  						     _PORT_PCS_DW10_LN01_B, \
>  						     _PORT_PCS_DW10_LN01_C)
> -#define BXT_PORT_PCS_DW10_GRP(port)	_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
> +#define BXT_PORT_PCS_DW10_GRP(port)	_REG_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
>  						     _PORT_PCS_DW10_GRP_B,  \
>  						     _PORT_PCS_DW10_GRP_C)
>  #define   TX2_SWING_CALC_INIT		(1 << 31)
> @@ -1352,13 +1363,13 @@ enum skl_disp_power_wells {
>  #define _PORT_PCS_DW12_GRP_C		0x6CE30
>  #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
>  #define   LANE_STAGGER_MASK		0x1F
> -#define BXT_PORT_PCS_DW12_LN01(port)	_PORT3(port, _PORT_PCS_DW12_LN01_A, \
> +#define BXT_PORT_PCS_DW12_LN01(port)	_REG_PORT3(port, _PORT_PCS_DW12_LN01_A, \
>  						     _PORT_PCS_DW12_LN01_B, \
>  						     _PORT_PCS_DW12_LN01_C)
> -#define BXT_PORT_PCS_DW12_LN23(port)	_PORT3(port, _PORT_PCS_DW12_LN23_A, \
> +#define BXT_PORT_PCS_DW12_LN23(port)	_REG_PORT3(port, _PORT_PCS_DW12_LN23_A, \
>  						     _PORT_PCS_DW12_LN23_B, \
>  						     _PORT_PCS_DW12_LN23_C)
> -#define BXT_PORT_PCS_DW12_GRP(port)	_PORT3(port, _PORT_PCS_DW12_GRP_A, \
> +#define BXT_PORT_PCS_DW12_GRP(port)	_REG_PORT3(port, _PORT_PCS_DW12_GRP_A, \
>  						     _PORT_PCS_DW12_GRP_B, \
>  						     _PORT_PCS_DW12_GRP_C)
>  
> @@ -1372,10 +1383,10 @@ enum skl_disp_power_wells {
>  #define _PORT_TX_DW2_GRP_A		0x162D08
>  #define _PORT_TX_DW2_GRP_B		0x6CD08
>  #define _PORT_TX_DW2_GRP_C		0x6CF08
> -#define BXT_PORT_TX_DW2_GRP(port)	_PORT3(port, _PORT_TX_DW2_GRP_A,  \
> +#define BXT_PORT_TX_DW2_GRP(port)	_REG_PORT3(port, _PORT_TX_DW2_GRP_A,  \
>  						     _PORT_TX_DW2_GRP_B,  \
>  						     _PORT_TX_DW2_GRP_C)
> -#define BXT_PORT_TX_DW2_LN0(port)	_PORT3(port, _PORT_TX_DW2_LN0_A,  \
> +#define BXT_PORT_TX_DW2_LN0(port)	_REG_PORT3(port, _PORT_TX_DW2_LN0_A,  \
>  						     _PORT_TX_DW2_LN0_B,  \
>  						     _PORT_TX_DW2_LN0_C)
>  #define   MARGIN_000_SHIFT		16
> @@ -1389,10 +1400,10 @@ enum skl_disp_power_wells {
>  #define _PORT_TX_DW3_GRP_A		0x162D0C
>  #define _PORT_TX_DW3_GRP_B		0x6CD0C
>  #define _PORT_TX_DW3_GRP_C		0x6CF0C
> -#define BXT_PORT_TX_DW3_GRP(port)	_PORT3(port, _PORT_TX_DW3_GRP_A,  \
> +#define BXT_PORT_TX_DW3_GRP(port)	_REG_PORT3(port, _PORT_TX_DW3_GRP_A,  \
>  						     _PORT_TX_DW3_GRP_B,  \
>  						     _PORT_TX_DW3_GRP_C)
> -#define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> +#define BXT_PORT_TX_DW3_LN0(port)	_REG_PORT3(port, _PORT_TX_DW3_LN0_A,  \
>  						     _PORT_TX_DW3_LN0_B,  \
>  						     _PORT_TX_DW3_LN0_C)
>  #define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> @@ -1403,10 +1414,10 @@ enum skl_disp_power_wells {
>  #define _PORT_TX_DW4_GRP_A		0x162D10
>  #define _PORT_TX_DW4_GRP_B		0x6CD10
>  #define _PORT_TX_DW4_GRP_C		0x6CF10
> -#define BXT_PORT_TX_DW4_LN0(port)	_PORT3(port, _PORT_TX_DW4_LN0_A,  \
> +#define BXT_PORT_TX_DW4_LN0(port)	_REG_PORT3(port, _PORT_TX_DW4_LN0_A,  \
>  						     _PORT_TX_DW4_LN0_B,  \
>  						     _PORT_TX_DW4_LN0_C)
> -#define BXT_PORT_TX_DW4_GRP(port)	_PORT3(port, _PORT_TX_DW4_GRP_A,  \
> +#define BXT_PORT_TX_DW4_GRP(port)	_REG_PORT3(port, _PORT_TX_DW4_GRP_A,  \
>  						     _PORT_TX_DW4_GRP_B,  \
>  						     _PORT_TX_DW4_GRP_C)
>  #define   DEEMPH_SHIFT			24
> @@ -1417,17 +1428,17 @@ enum skl_disp_power_wells {
>  #define _PORT_TX_DW14_LN0_C		0x6C938
>  #define   LATENCY_OPTIM_SHIFT		30
>  #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
> -#define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
> +#define BXT_PORT_TX_DW14_LN(port, lane)	_REG(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
>  							_PORT_TX_DW14_LN0_B,   \
>  							_PORT_TX_DW14_LN0_C) + \
>  					 _BXT_LANE_OFFSET(lane))
>  
>  /* UAIMI scratch pad register 1 */
> -#define UAIMI_SPR1			0x4F074
> +#define UAIMI_SPR1			_REG(0x4F074)
>  /* SKL VccIO mask */
>  #define SKL_VCCIO_MASK			0x1
>  /* SKL balance leg register */
> -#define DISPIO_CR_TX_BMU_CR0		0x6C00C
> +#define DISPIO_CR_TX_BMU_CR0		_REG(0x6C00C)
>  /* I_boost values */
>  #define BALANCE_LEG_SHIFT(port)		(8+3*(port))
>  #define BALANCE_LEG_MASK(port)		(7<<(8+3*(port)))
> @@ -1437,8 +1448,8 @@ enum skl_disp_power_wells {
>  /*
>   * Fence registers
>   */
> -#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> -#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
> +#define FENCE_REG_830(i)		_REG(0x2000 + (i) * 4) /* 8 registers */
> +#define FENCE_REG_945_8(i)		_REG(0x3000 + ((i) - 8) * 4) /* 8 registers */
>  #define   I830_FENCE_START_MASK		0x07f80000
>  #define   I830_FENCE_TILING_Y_SHIFT	12
>  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> @@ -1451,21 +1462,21 @@ enum skl_disp_power_wells {
>  #define   I915_FENCE_START_MASK		0x0ff00000
>  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
>  
> -#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> -#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
> +#define FENCE_REG_965_LO(i)		_REG(0x03000 + (i) * 8)
> +#define FENCE_REG_965_HI(i)		_REG(0x03000 + (i) * 8 + 4)
>  #define   I965_FENCE_PITCH_SHIFT	2
>  #define   I965_FENCE_TILING_Y_SHIFT	1
>  #define   I965_FENCE_REG_VALID		(1<<0)
>  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
>  
> -#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> -#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> +#define FENCE_REG_GEN6_LO(i)		_REG(0x100000 + (i) * 8)
> +#define FENCE_REG_GEN6_HI(i)		_REG(0x100000 + (i) * 8 + 4)
>  #define   GEN6_FENCE_PITCH_SHIFT	32
>  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
>  
>  
>  /* control register for cpu gtt access */
> -#define TILECTL				0x101000
> +#define TILECTL				_REG(0x101000)
>  #define   TILECTL_SWZCTL			(1 << 0)
>  #define   TILECTL_TLBPF			(1 << 1)
>  #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
> @@ -1474,30 +1485,30 @@ enum skl_disp_power_wells {
>  /*
>   * Instruction and interrupt control regs
>   */
> -#define PGTBL_CTL	0x02020
> +#define PGTBL_CTL	_REG(0x02020)
>  #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
>  #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
> -#define PGTBL_ER	0x02024
> -#define PRB0_BASE (0x2030-0x30)
> -#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
> -#define PRB2_BASE (0x2050-0x30) /* gen3 */
> -#define SRB0_BASE (0x2100-0x30) /* gen2 */
> -#define SRB1_BASE (0x2110-0x30) /* gen2 */
> -#define SRB2_BASE (0x2120-0x30) /* 830 */
> -#define SRB3_BASE (0x2130-0x30) /* 830 */
> +#define PGTBL_ER	_REG(0x02024)
> +#define PRB0_BASE	(0x2030-0x30)
> +#define PRB1_BASE	(0x2040-0x30) /* 830,gen3 */
> +#define PRB2_BASE	(0x2050-0x30) /* gen3 */
> +#define SRB0_BASE	(0x2100-0x30) /* gen2 */
> +#define SRB1_BASE	(0x2110-0x30) /* gen2 */
> +#define SRB2_BASE	(0x2120-0x30) /* 830 */
> +#define SRB3_BASE	(0x2130-0x30) /* 830 */
>  #define RENDER_RING_BASE	0x02000
>  #define BSD_RING_BASE		0x04000
>  #define GEN6_BSD_RING_BASE	0x12000
>  #define GEN8_BSD2_RING_BASE	0x1c000
>  #define VEBOX_RING_BASE		0x1a000
>  #define BLT_RING_BASE		0x22000
> -#define RING_TAIL(base)		((base)+0x30)
> -#define RING_HEAD(base)		((base)+0x34)
> -#define RING_START(base)	((base)+0x38)
> -#define RING_CTL(base)		((base)+0x3c)
> -#define RING_SYNC_0(base)	((base)+0x40)
> -#define RING_SYNC_1(base)	((base)+0x44)
> -#define RING_SYNC_2(base)	((base)+0x48)
> +#define RING_TAIL(base)		_REG((base)+0x30)
> +#define RING_HEAD(base)		_REG((base)+0x34)
> +#define RING_START(base)	_REG((base)+0x38)
> +#define RING_CTL(base)		_REG((base)+0x3c)
> +#define RING_SYNC_0(base)	_REG((base)+0x40)
> +#define RING_SYNC_1(base)	_REG((base)+0x44)
> +#define RING_SYNC_2(base)	_REG((base)+0x48)
>  #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
>  #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
>  #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
> @@ -1510,51 +1521,51 @@ enum skl_disp_power_wells {
>  #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
>  #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
>  #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
> -#define GEN6_NOSYNC 0
> -#define RING_PSMI_CTL(base)	((base)+0x50)
> -#define RING_MAX_IDLE(base)	((base)+0x54)
> -#define RING_HWS_PGA(base)	((base)+0x80)
> -#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
> -#define RING_RESET_CTL(base)	((base)+0xd0)
> +#define GEN6_NOSYNC _REG(0)
> +#define RING_PSMI_CTL(base)	_REG((base)+0x50)
> +#define RING_MAX_IDLE(base)	_REG((base)+0x54)
> +#define RING_HWS_PGA(base)	_REG((base)+0x80)
> +#define RING_HWS_PGA_GEN6(base)	_REG((base)+0x2080)
> +#define RING_RESET_CTL(base)	_REG((base)+0xd0)
>  #define   RESET_CTL_REQUEST_RESET  (1 << 0)
>  #define   RESET_CTL_READY_TO_RESET (1 << 1)
>  
> -#define HSW_GTT_CACHE_EN	0x4024
> +#define HSW_GTT_CACHE_EN	_REG(0x4024)
>  #define   GTT_CACHE_EN_ALL	0xF0007FFF
> -#define GEN7_WR_WATERMARK	0x4028
> -#define GEN7_GFX_PRIO_CTRL	0x402C
> -#define ARB_MODE		0x4030
> +#define GEN7_WR_WATERMARK	_REG(0x4028)
> +#define GEN7_GFX_PRIO_CTRL	_REG(0x402C)
> +#define ARB_MODE		_REG(0x4030)
>  #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
>  #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
> -#define GEN7_GFX_PEND_TLB0	0x4034
> -#define GEN7_GFX_PEND_TLB1	0x4038
> +#define GEN7_GFX_PEND_TLB0	_REG(0x4034)
> +#define GEN7_GFX_PEND_TLB1	_REG(0x4038)
>  /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
> -#define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
> +#define GEN7_LRA_LIMITS(i)	_REG(0x403C + (i) * 4)
>  #define GEN7_LRA_LIMITS_REG_NUM	13
> -#define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
> -#define GEN7_GFX_MAX_REQ_COUNT		0x4074
> +#define GEN7_MEDIA_MAX_REQ_COUNT	_REG(0x4070)
> +#define GEN7_GFX_MAX_REQ_COUNT		_REG(0x4074)
>  
> -#define GAMTARBMODE		0x04a08
> +#define GAMTARBMODE		_REG(0x04a08)
>  #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
>  #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
> -#define RENDER_HWS_PGA_GEN7	(0x04080)
> -#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
> +#define RENDER_HWS_PGA_GEN7	_REG(0x04080)
> +#define RING_FAULT_REG(ring)	_REG(0x4094 + 0x100*(ring)->id)
>  #define   RING_FAULT_GTTSEL_MASK (1<<11)
>  #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
>  #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
>  #define   RING_FAULT_VALID	(1<<0)
> -#define DONE_REG		0x40b0
> -#define GEN8_PRIVATE_PAT_LO	0x40e0
> -#define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
> -#define BSD_HWS_PGA_GEN7	(0x04180)
> -#define BLT_HWS_PGA_GEN7	(0x04280)
> -#define VEBOX_HWS_PGA_GEN7	(0x04380)
> -#define RING_ACTHD(base)	((base)+0x74)
> -#define RING_ACTHD_UDW(base)	((base)+0x5c)
> -#define RING_NOPID(base)	((base)+0x94)
> -#define RING_IMR(base)		((base)+0xa8)
> -#define RING_HWSTAM(base)	((base)+0x98)
> -#define RING_TIMESTAMP(base)	((base)+0x358)
> +#define DONE_REG		_REG(0x40b0)
> +#define GEN8_PRIVATE_PAT_LO	_REG(0x40e0)
> +#define GEN8_PRIVATE_PAT_HI	_REG(0x40e0 + 4)
> +#define BSD_HWS_PGA_GEN7	_REG(0x04180)
> +#define BLT_HWS_PGA_GEN7	_REG(0x04280)
> +#define VEBOX_HWS_PGA_GEN7	_REG(0x04380)
> +#define RING_ACTHD(base)	_REG((base)+0x74)
> +#define RING_ACTHD_UDW(base)	_REG((base)+0x5c)
> +#define RING_NOPID(base)	_REG((base)+0x94)
> +#define RING_IMR(base)		_REG((base)+0xa8)
> +#define RING_HWSTAM(base)	_REG((base)+0x98)
> +#define RING_TIMESTAMP(base)	_REG((base)+0x358)
>  #define   TAIL_ADDR		0x001FFFF8
>  #define   HEAD_WRAP_COUNT	0xFFE00000
>  #define   HEAD_WRAP_ONE		0x00200000
> @@ -1571,54 +1582,54 @@ enum skl_disp_power_wells {
>  #define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
>  #define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
>  
> -#define GEN7_TLB_RD_ADDR	0x4700
> +#define GEN7_TLB_RD_ADDR	_REG(0x4700)
>  
>  #if 0
> -#define PRB0_TAIL	0x02030
> -#define PRB0_HEAD	0x02034
> -#define PRB0_START	0x02038
> -#define PRB0_CTL	0x0203c
> -#define PRB1_TAIL	0x02040 /* 915+ only */
> -#define PRB1_HEAD	0x02044 /* 915+ only */
> -#define PRB1_START	0x02048 /* 915+ only */
> -#define PRB1_CTL	0x0204c /* 915+ only */
> +#define PRB0_TAIL	_REG(0x2030)
> +#define PRB0_HEAD	_REG(0x2034)
> +#define PRB0_START	_REG(0x2038)
> +#define PRB0_CTL	_REG(0x203c)
> +#define PRB1_TAIL	_REG(0x2040) /* 915+ only */
> +#define PRB1_HEAD	_REG(0x2044) /* 915+ only */
> +#define PRB1_START	_REG(0x2048) /* 915+ only */
> +#define PRB1_CTL	_REG(0x204c) /* 915+ only */
>  #endif
> -#define IPEIR_I965	0x02064
> -#define IPEHR_I965	0x02068
> -#define INSTDONE_I965	0x0206c
> -#define GEN7_INSTDONE_1		0x0206c
> -#define GEN7_SC_INSTDONE	0x07100
> -#define GEN7_SAMPLER_INSTDONE	0x0e160
> -#define GEN7_ROW_INSTDONE	0x0e164
> +#define IPEIR_I965	_REG(0x2064)
> +#define IPEHR_I965	_REG(0x2068)
> +#define INSTDONE_I965	_REG(0x206c)
> +#define GEN7_INSTDONE_1		_REG(0x206c)
> +#define GEN7_SC_INSTDONE	_REG(0x7100)
> +#define GEN7_SAMPLER_INSTDONE	_REG(0xe160)
> +#define GEN7_ROW_INSTDONE	_REG(0xe164)
>  #define I915_NUM_INSTDONE_REG	4
> -#define RING_IPEIR(base)	((base)+0x64)
> -#define RING_IPEHR(base)	((base)+0x68)
> -#define RING_INSTDONE(base)	((base)+0x6c)
> -#define RING_INSTPS(base)	((base)+0x70)
> -#define RING_DMA_FADD(base)	((base)+0x78)
> -#define RING_DMA_FADD_UDW(base)	((base)+0x60) /* gen8+ */
> -#define RING_INSTPM(base)	((base)+0xc0)
> -#define RING_MI_MODE(base)	((base)+0x9c)
> -#define INSTPS		0x02070 /* 965+ only */
> -#define INSTDONE1	0x0207c /* 965+ only */
> -#define ACTHD_I965	0x02074
> -#define HWS_PGA		0x02080
> +#define RING_IPEIR(base)	_REG((base)+0x64)
> +#define RING_IPEHR(base)	_REG((base)+0x68)
> +#define RING_INSTDONE(base)	_REG((base)+0x6c)
> +#define RING_INSTPS(base)	_REG((base)+0x70)
> +#define RING_DMA_FADD(base)	_REG((base)+0x78)
> +#define RING_DMA_FADD_UDW(base) _REG((base)+0x60) /* gen8+ */
> +#define RING_INSTPM(base)	_REG((base)+0xc0)
> +#define RING_MI_MODE(base)	_REG((base)+0x9c)
> +#define INSTPS		_REG(0x2070) /* 965+ only */
> +#define INSTDONE1	_REG(0x207c) /* 965+ only */
> +#define ACTHD_I965	_REG(0x2074)
> +#define HWS_PGA		_REG(0x2080)
>  #define HWS_ADDRESS_MASK	0xfffff000
>  #define HWS_START_ADDRESS_SHIFT	4
> -#define PWRCTXA		0x2088 /* 965GM+ only */
> +#define PWRCTXA		_REG(0x2088) /* 965GM+ only */
>  #define   PWRCTX_EN	(1<<0)
> -#define IPEIR		0x02088
> -#define IPEHR		0x0208c
> -#define INSTDONE	0x02090
> -#define NOPID		0x02094
> -#define HWSTAM		0x02098
> -#define DMA_FADD_I8XX	0x020d0
> -#define RING_BBSTATE(base)	((base)+0x110)
> -#define RING_BBADDR(base)	((base)+0x140)
> -#define RING_BBADDR_UDW(base)	((base)+0x168) /* gen8+ */
> -
> -#define ERROR_GEN6	0x040a0
> -#define GEN7_ERR_INT	0x44040
> +#define IPEIR		_REG(0x2088)
> +#define IPEHR		_REG(0x208c)
> +#define INSTDONE	_REG(0x2090)
> +#define NOPID		_REG(0x2094)
> +#define HWSTAM		_REG(0x2098)
> +#define DMA_FADD_I8XX	_REG(0x20d0)
> +#define RING_BBSTATE(base)	_REG((base)+0x110)
> +#define RING_BBADDR(base)	_REG((base)+0x140)
> +#define RING_BBADDR_UDW(base)	_REG((base)+0x168) /* gen8+ */
> +
> +#define ERROR_GEN6	_REG(0x40a0)
> +#define GEN7_ERR_INT	_REG(0x44040)
>  #define   ERR_INT_POISON		(1<<31)
>  #define   ERR_INT_MMIO_UNCLAIMED	(1<<13)
>  #define   ERR_INT_PIPE_CRC_DONE_C	(1<<8)
> @@ -1630,13 +1641,13 @@ enum skl_disp_power_wells {
>  #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
>  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
>  
> -#define GEN8_FAULT_TLB_DATA0		0x04b10
> -#define GEN8_FAULT_TLB_DATA1		0x04b14
> +#define GEN8_FAULT_TLB_DATA0		_REG(0x4b10)
> +#define GEN8_FAULT_TLB_DATA1		_REG(0x4b14)
>  
> -#define FPGA_DBG		0x42300
> +#define FPGA_DBG		_REG(0x42300)
>  #define   FPGA_DBG_RM_NOCLAIM	(1<<31)
>  
> -#define DERRMR		0x44050
> +#define DERRMR		_REG(0x44050)
>  /* Note that HBLANK events are reserved on bdw+ */
>  #define   DERRMR_PIPEA_SCANLINE		(1<<0)
>  #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)
> @@ -1660,29 +1671,29 @@ enum skl_disp_power_wells {
>   * for various sorts of correct behavior.  The top 16 bits of each are
>   * the enables for writing to the corresponding low bit.
>   */
> -#define _3D_CHICKEN	0x02084
> +#define _3D_CHICKEN	_REG(0x2084)
>  #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
> -#define _3D_CHICKEN2	0x0208c
> +#define _3D_CHICKEN2	_REG(0x208c)
>  /* Disables pipelining of read flushes past the SF-WIZ interface.
>   * Required on all Ironlake steppings according to the B-Spec, but the
>   * particular danger of not doing so is not specified.
>   */
>  # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
> -#define _3D_CHICKEN3	0x02090
> +#define _3D_CHICKEN3	_REG(0x2090)
>  #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
>  #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
>  #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
>  #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
>  
> -#define MI_MODE		0x0209c
> +#define MI_MODE		_REG(0x209c)
>  # define VS_TIMER_DISPATCH				(1 << 6)
>  # define MI_FLUSH_ENABLE				(1 << 12)
>  # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
>  # define MODE_IDLE					(1 << 9)
>  # define STOP_RING					(1 << 8)
>  
> -#define GEN6_GT_MODE	0x20d0
> -#define GEN7_GT_MODE	0x7008
> +#define GEN6_GT_MODE	_REG(0x20d0)
> +#define GEN7_GT_MODE	_REG(0x7008)
>  #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
>  #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
>  #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
> @@ -1692,9 +1703,9 @@ enum skl_disp_power_wells {
>  #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
>  #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
>  
> -#define GFX_MODE	0x02520
> -#define GFX_MODE_GEN7	0x0229c
> -#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
> +#define GFX_MODE	_REG(0x2520)
> +#define GFX_MODE_GEN7	_REG(0x229c)
> +#define RING_MODE_GEN7(ring)	_REG((ring)->mmio_base+0x29c)
>  #define   GFX_RUN_LIST_ENABLE		(1<<15)
>  #define   GFX_INTERRUPT_STEERING	(1<<14)
>  #define   GFX_TLB_INVALIDATE_EXPLICIT	(1<<13)
> @@ -1712,36 +1723,36 @@ enum skl_disp_power_wells {
>  #define VLV_DISPLAY_BASE 0x180000
>  #define VLV_MIPI_BASE VLV_DISPLAY_BASE
>  
> -#define VLV_GU_CTL0	(VLV_DISPLAY_BASE + 0x2030)
> -#define VLV_GU_CTL1	(VLV_DISPLAY_BASE + 0x2034)
> -#define SCPD0		0x0209c /* 915+ only */
> -#define IER		0x020a0
> -#define IIR		0x020a4
> -#define IMR		0x020a8
> -#define ISR		0x020ac
> -#define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
> +#define VLV_GU_CTL0	_REG(VLV_DISPLAY_BASE + 0x2030)
> +#define VLV_GU_CTL1	_REG(VLV_DISPLAY_BASE + 0x2034)
> +#define SCPD0		_REG(0x209c) /* 915+ only */
> +#define IER		_REG(0x20a0)
> +#define IIR		_REG(0x20a4)
> +#define IMR		_REG(0x20a8)
> +#define ISR		_REG(0x20ac)
> +#define VLV_GUNIT_CLOCK_GATE	_REG(VLV_DISPLAY_BASE + 0x2060)
>  #define   GINT_DIS		(1<<22)
>  #define   GCFG_DIS		(1<<8)
> -#define VLV_GUNIT_CLOCK_GATE2	(VLV_DISPLAY_BASE + 0x2064)
> -#define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
> -#define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
> -#define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
> -#define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
> -#define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
> -#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
> +#define VLV_GUNIT_CLOCK_GATE2	_REG(VLV_DISPLAY_BASE + 0x2064)
> +#define VLV_IIR_RW	_REG(VLV_DISPLAY_BASE + 0x2084)
> +#define VLV_IER		_REG(VLV_DISPLAY_BASE + 0x20a0)
> +#define VLV_IIR		_REG(VLV_DISPLAY_BASE + 0x20a4)
> +#define VLV_IMR		_REG(VLV_DISPLAY_BASE + 0x20a8)
> +#define VLV_ISR		_REG(VLV_DISPLAY_BASE + 0x20ac)
> +#define VLV_PCBR	_REG(VLV_DISPLAY_BASE + 0x2120)
>  #define VLV_PCBR_ADDR_SHIFT	12
>  
>  #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
> -#define EIR		0x020b0
> -#define EMR		0x020b4
> -#define ESR		0x020b8
> +#define EIR		_REG(0x20b0)
> +#define EMR		_REG(0x20b4)
> +#define ESR		_REG(0x20b8)
>  #define   GM45_ERROR_PAGE_TABLE				(1<<5)
>  #define   GM45_ERROR_MEM_PRIV				(1<<4)
>  #define   I915_ERROR_PAGE_TABLE				(1<<4)
>  #define   GM45_ERROR_CP_PRIV				(1<<3)
>  #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
>  #define   I915_ERROR_INSTRUCTION			(1<<0)
> -#define INSTPM	        0x020c0
> +#define INSTPM	        _REG(0x20c0)
>  #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
>  #define   INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
>  					will not assert AGPBUSY# and will only
> @@ -1749,14 +1760,14 @@ enum skl_disp_power_wells {
>  #define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
>  #define   INSTPM_TLB_INVALIDATE	(1<<9)
>  #define   INSTPM_SYNC_FLUSH	(1<<5)
> -#define ACTHD	        0x020c8
> -#define MEM_MODE	0x020cc
> +#define ACTHD	        _REG(0x20c8)
> +#define MEM_MODE	_REG(0x20cc)
>  #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
>  #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
>  #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
> -#define FW_BLC		0x020d8
> -#define FW_BLC2		0x020dc
> -#define FW_BLC_SELF	0x020e0 /* 915+ only */
> +#define FW_BLC		_REG(0x20d8)
> +#define FW_BLC2		_REG(0x20dc)
> +#define FW_BLC_SELF	_REG(0x20e0) /* 915+ only */
>  #define   FW_BLC_SELF_EN_MASK      (1<<31)
>  #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
>  #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
> @@ -1764,7 +1775,7 @@ enum skl_disp_power_wells {
>  #define MM_FIFO_WATERMARK   0x0001F000
>  #define LM_BURST_LENGTH     0x00000700
>  #define LM_FIFO_WATERMARK   0x0000001F
> -#define MI_ARB_STATE	0x020e4 /* 915+ only */
> +#define MI_ARB_STATE	_REG(0x20e4) /* 915+ only */
>  
>  /* Make render/texture TLB fetches lower priorty than associated data
>   *   fetches. This is not turned on by default
> @@ -1828,11 +1839,11 @@ enum skl_disp_power_wells {
>  #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
>  #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
>  
> -#define MI_STATE	0x020e4 /* gen2 only */
> +#define MI_STATE	_REG(0x20e4) /* gen2 only */
>  #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
>  #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
>  
> -#define CACHE_MODE_0	0x02120 /* 915+ only */
> +#define CACHE_MODE_0	_REG(0x2120) /* 915+ only */
>  #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
>  #define   CM0_IZ_OPT_DISABLE      (1<<6)
>  #define   CM0_ZR_OPT_DISABLE      (1<<5)
> @@ -1841,32 +1852,32 @@ enum skl_disp_power_wells {
>  #define   CM0_COLOR_EVICT_DISABLE (1<<3)
>  #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
>  #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
> -#define GFX_FLSH_CNTL	0x02170 /* 915+ only */
> -#define GFX_FLSH_CNTL_GEN6	0x101008
> +#define GFX_FLSH_CNTL	_REG(0x2170) /* 915+ only */
> +#define GFX_FLSH_CNTL_GEN6	_REG(0x101008)
>  #define   GFX_FLSH_CNTL_EN	(1<<0)
> -#define ECOSKPD		0x021d0
> +#define ECOSKPD		_REG(0x21d0)
>  #define   ECO_GATING_CX_ONLY	(1<<3)
>  #define   ECO_FLIP_DONE		(1<<0)
>  
> -#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
> +#define CACHE_MODE_0_GEN7	_REG(0x7000) /* IVB+ */
>  #define RC_OP_FLUSH_ENABLE (1<<0)
>  #define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
> -#define CACHE_MODE_1		0x7004 /* IVB+ */
> +#define CACHE_MODE_1		_REG(0x7004) /* IVB+ */
>  #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
>  #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
>  #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
>  
> -#define GEN6_BLITTER_ECOSKPD	0x221d0
> +#define GEN6_BLITTER_ECOSKPD	_REG(0x221d0)
>  #define   GEN6_BLITTER_LOCK_SHIFT			16
>  #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
>  
> -#define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
> +#define GEN6_RC_SLEEP_PSMI_CONTROL	_REG(0x2050)
>  #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
>  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
>  #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
>  
>  /* Fuse readout registers for GT */
> -#define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
> +#define CHV_FUSE_GT			_REG(VLV_DISPLAY_BASE + 0x2168)
>  #define   CHV_FGT_DISABLE_SS0		(1 << 10)
>  #define   CHV_FGT_DISABLE_SS1		(1 << 11)
>  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
> @@ -1878,16 +1889,16 @@ enum skl_disp_power_wells {
>  #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
>  #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
>  
> -#define GEN8_FUSE2			0x9120
> +#define GEN8_FUSE2			_REG(0x9120)
>  #define   GEN8_F2_S_ENA_SHIFT		25
>  #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
>  
>  #define   GEN9_F2_SS_DIS_SHIFT		20
>  #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
>  
> -#define GEN9_EU_DISABLE(slice)		(0x9134 + (slice)*0x4)
> +#define GEN9_EU_DISABLE(slice)		_REG(0x9134 + (slice)*0x4)
>  
> -#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
> +#define GEN6_BSD_SLEEP_PSMI_CONTROL	_REG(0x12050)
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
>  #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
> @@ -1965,9 +1976,9 @@ enum skl_disp_power_wells {
>  #define I915_ASLE_INTERRUPT				(1<<0)
>  #define I915_BSD_USER_INTERRUPT				(1<<25)
>  
> -#define GEN6_BSD_RNCID			0x12198
> +#define GEN6_BSD_RNCID			_REG(0x12198)
>  
> -#define GEN7_FF_THREAD_MODE		0x20a0
> +#define GEN7_FF_THREAD_MODE		_REG(0x20a0)
>  #define   GEN7_FF_SCHED_MASK		0x0077070
>  #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
>  #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
> @@ -1988,9 +1999,9 @@ enum skl_disp_power_wells {
>   * Framebuffer compression (915+ only)
>   */
>  
> -#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
> -#define FBC_LL_BASE		0x03204 /* 4k page aligned */
> -#define FBC_CONTROL		0x03208
> +#define FBC_CFB_BASE		_REG(0x3200) /* 4k page aligned */
> +#define FBC_LL_BASE		_REG(0x3204) /* 4k page aligned */
> +#define FBC_CONTROL		_REG(0x3208)
>  #define   FBC_CTL_EN		(1<<31)
>  #define   FBC_CTL_PERIODIC	(1<<30)
>  #define   FBC_CTL_INTERVAL_SHIFT (16)
> @@ -1998,14 +2009,14 @@ enum skl_disp_power_wells {
>  #define   FBC_CTL_C3_IDLE	(1<<13)
>  #define   FBC_CTL_STRIDE_SHIFT	(5)
>  #define   FBC_CTL_FENCENO_SHIFT	(0)
> -#define FBC_COMMAND		0x0320c
> +#define FBC_COMMAND		_REG(0x320c)
>  #define   FBC_CMD_COMPRESS	(1<<0)
> -#define FBC_STATUS		0x03210
> +#define FBC_STATUS		_REG(0x3210)
>  #define   FBC_STAT_COMPRESSING	(1<<31)
>  #define   FBC_STAT_COMPRESSED	(1<<30)
>  #define   FBC_STAT_MODIFIED	(1<<29)
>  #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
> -#define FBC_CONTROL2		0x03214
> +#define FBC_CONTROL2		_REG(0x3214)
>  #define   FBC_CTL_FENCE_DBL	(0<<4)
>  #define   FBC_CTL_IDLE_IMM	(0<<2)
>  #define   FBC_CTL_IDLE_FULL	(1<<2)
> @@ -2013,17 +2024,17 @@ enum skl_disp_power_wells {
>  #define   FBC_CTL_IDLE_DEBUG	(3<<2)
>  #define   FBC_CTL_CPU_FENCE	(1<<1)
>  #define   FBC_CTL_PLANE(plane)	((plane)<<0)
> -#define FBC_FENCE_OFF		0x03218 /* BSpec typo has 321Bh */
> -#define FBC_TAG(i)		(0x03300 + (i) * 4)
> +#define FBC_FENCE_OFF		_REG(0x3218) /* BSpec typo has 321Bh */
> +#define FBC_TAG(i)		_REG(0x3300 + (i) * 4)
>  
> -#define FBC_STATUS2		0x43214
> +#define FBC_STATUS2		_REG(0x43214)
>  #define  FBC_COMPRESSION_MASK	0x7ff
>  
>  #define FBC_LL_SIZE		(1536)
>  
>  /* Framebuffer compression for GM45+ */
> -#define DPFC_CB_BASE		0x3200
> -#define DPFC_CONTROL		0x3208
> +#define DPFC_CB_BASE		_REG(0x3200)
> +#define DPFC_CONTROL		_REG(0x3208)
>  #define   DPFC_CTL_EN		(1<<31)
>  #define   DPFC_CTL_PLANE(plane)	((plane)<<30)
>  #define   IVB_DPFC_CTL_PLANE(plane)	((plane)<<29)
> @@ -2034,37 +2045,37 @@ enum skl_disp_power_wells {
>  #define   DPFC_CTL_LIMIT_1X	(0<<6)
>  #define   DPFC_CTL_LIMIT_2X	(1<<6)
>  #define   DPFC_CTL_LIMIT_4X	(2<<6)
> -#define DPFC_RECOMP_CTL		0x320c
> +#define DPFC_RECOMP_CTL		_REG(0x320c)
>  #define   DPFC_RECOMP_STALL_EN	(1<<27)
>  #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
>  #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
>  #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
>  #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
> -#define DPFC_STATUS		0x3210
> +#define DPFC_STATUS		_REG(0x3210)
>  #define   DPFC_INVAL_SEG_SHIFT  (16)
>  #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
>  #define   DPFC_COMP_SEG_SHIFT	(0)
>  #define   DPFC_COMP_SEG_MASK	(0x000003ff)
> -#define DPFC_STATUS2		0x3214
> -#define DPFC_FENCE_YOFF		0x3218
> -#define DPFC_CHICKEN		0x3224
> +#define DPFC_STATUS2		_REG(0x3214)
> +#define DPFC_FENCE_YOFF		_REG(0x3218)
> +#define DPFC_CHICKEN		_REG(0x3224)
>  #define   DPFC_HT_MODIFY	(1<<31)
>  
>  /* Framebuffer compression for Ironlake */
> -#define ILK_DPFC_CB_BASE	0x43200
> -#define ILK_DPFC_CONTROL	0x43208
> +#define ILK_DPFC_CB_BASE	_REG(0x43200)
> +#define ILK_DPFC_CONTROL	_REG(0x43208)
>  #define   FBC_CTL_FALSE_COLOR	(1<<10)
>  /* The bit 28-8 is reserved */
>  #define   DPFC_RESERVED		(0x1FFFFF00)
> -#define ILK_DPFC_RECOMP_CTL	0x4320c
> -#define ILK_DPFC_STATUS		0x43210
> -#define ILK_DPFC_FENCE_YOFF	0x43218
> -#define ILK_DPFC_CHICKEN	0x43224
> -#define ILK_FBC_RT_BASE		0x2128
> +#define ILK_DPFC_RECOMP_CTL	_REG(0x4320c)
> +#define ILK_DPFC_STATUS		_REG(0x43210)
> +#define ILK_DPFC_FENCE_YOFF	_REG(0x43218)
> +#define ILK_DPFC_CHICKEN	_REG(0x43224)
> +#define ILK_FBC_RT_BASE		_REG(0x2128)
>  #define   ILK_FBC_RT_VALID	(1<<0)
>  #define   SNB_FBC_FRONT_BUFFER	(1<<1)
>  
> -#define ILK_DISPLAY_CHICKEN1	0x42000
> +#define ILK_DISPLAY_CHICKEN1	_REG(0x42000)
>  #define   ILK_FBCQ_DIS		(1<<22)
>  #define	  ILK_PABSTRETCH_DIS	(1<<21)
>  
> @@ -2074,31 +2085,31 @@ enum skl_disp_power_wells {
>   *
>   * The following two registers are of type GTTMMADR
>   */
> -#define SNB_DPFC_CTL_SA		0x100100
> +#define SNB_DPFC_CTL_SA		_REG(0x100100)
>  #define   SNB_CPU_FENCE_ENABLE	(1<<29)
> -#define DPFC_CPU_FENCE_OFFSET	0x100104
> +#define DPFC_CPU_FENCE_OFFSET	_REG(0x100104)
>  
>  /* Framebuffer compression for Ivybridge */
> -#define IVB_FBC_RT_BASE			0x7020
> +#define IVB_FBC_RT_BASE			_REG(0x7020)
>  
> -#define IPS_CTL		0x43408
> +#define IPS_CTL		_REG(0x43408)
>  #define   IPS_ENABLE	(1 << 31)
>  
> -#define MSG_FBC_REND_STATE	0x50380
> +#define MSG_FBC_REND_STATE	_REG(0x50380)
>  #define   FBC_REND_NUKE		(1<<2)
>  #define   FBC_REND_CACHE_CLEAN	(1<<1)
>  
>  /*
>   * GPIO regs
>   */
> -#define GPIOA			0x5010
> -#define GPIOB			0x5014
> -#define GPIOC			0x5018
> -#define GPIOD			0x501c
> -#define GPIOE			0x5020
> -#define GPIOF			0x5024
> -#define GPIOG			0x5028
> -#define GPIOH			0x502c
> +#define GPIOA			_REG(0x5010)
> +#define GPIOB			_REG(0x5014)
> +#define GPIOC			_REG(0x5018)
> +#define GPIOD			_REG(0x501c)
> +#define GPIOE			_REG(0x5020)
> +#define GPIOF			_REG(0x5024)
> +#define GPIOG			_REG(0x5028)
> +#define GPIOH			_REG(0x502c)
>  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
>  # define GPIO_CLOCK_DIR_IN		(0 << 1)
>  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
> @@ -2114,7 +2125,7 @@ enum skl_disp_power_wells {
>  # define GPIO_DATA_VAL_IN		(1 << 12)
>  # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
>  
> -#define GMBUS0			(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
> +#define GMBUS0			_REG(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
>  #define   GMBUS_RATE_100KHZ	(0<<8)
>  #define   GMBUS_RATE_50KHZ	(1<<8)
>  #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
> @@ -2133,7 +2144,7 @@ enum skl_disp_power_wells {
>  #define   GMBUS_PIN_2_BXT	2
>  #define   GMBUS_PIN_3_BXT	3
>  #define   GMBUS_NUM_PINS	7 /* including 0 */
> -#define GMBUS1			(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
> +#define GMBUS1			_REG(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
>  #define   GMBUS_SW_CLR_INT	(1<<31)
>  #define   GMBUS_SW_RDY		(1<<30)
>  #define   GMBUS_ENT		(1<<29) /* enable timeout */
> @@ -2147,7 +2158,7 @@ enum skl_disp_power_wells {
>  #define   GMBUS_SLAVE_ADDR_SHIFT 1
>  #define   GMBUS_SLAVE_READ	(1<<0)
>  #define   GMBUS_SLAVE_WRITE	(0<<0)
> -#define GMBUS2			(dev_priv->gpio_mmio_base + 0x5108) /* status */
> +#define GMBUS2			_REG(dev_priv->gpio_mmio_base + 0x5108) /* status */
>  #define   GMBUS_INUSE		(1<<15)
>  #define   GMBUS_HW_WAIT_PHASE	(1<<14)
>  #define   GMBUS_STALL_TIMEOUT	(1<<13)
> @@ -2155,27 +2166,27 @@ enum skl_disp_power_wells {
>  #define   GMBUS_HW_RDY		(1<<11)
>  #define   GMBUS_SATOER		(1<<10)
>  #define   GMBUS_ACTIVE		(1<<9)
> -#define GMBUS3			(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
> -#define GMBUS4			(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
> +#define GMBUS3			_REG(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
> +#define GMBUS4			_REG(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
>  #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
>  #define   GMBUS_NAK_EN		(1<<3)
>  #define   GMBUS_IDLE_EN		(1<<2)
>  #define   GMBUS_HW_WAIT_EN	(1<<1)
>  #define   GMBUS_HW_RDY_EN	(1<<0)
> -#define GMBUS5			(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
> +#define GMBUS5			_REG(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
>  #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
>  
>  /*
>   * Clock control & power management
>   */
> -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
> -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
> -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
> +#define _DPLL_A _REG(dev_priv->info.display_mmio_offset + 0x6014)
> +#define _DPLL_B _REG(dev_priv->info.display_mmio_offset + 0x6018)
> +#define _CHV_DPLL_C _REG(dev_priv->info.display_mmio_offset + 0x6030)
>  #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
>  
> -#define VGA0	0x6000
> -#define VGA1	0x6004
> -#define VGA_PD	0x6010
> +#define VGA0	_REG(0x6000)
> +#define VGA1	_REG(0x6004)
> +#define VGA_PD	_REG(0x6010)
>  #define   VGA0_PD_P2_DIV_4	(1 << 7)
>  #define   VGA0_PD_P1_DIV_2	(1 << 5)
>  #define   VGA0_PD_P1_SHIFT	0
> @@ -2211,9 +2222,9 @@ enum skl_disp_power_wells {
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
>  
>  /* Additional CHV pll/phy registers */
> -#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
> +#define DPIO_PHY_STATUS			_REG(VLV_DISPLAY_BASE + 0x6240)
>  #define   DPLL_PORTD_READY_MASK		(0xf)
> -#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
> +#define DISPLAY_PHY_CONTROL _REG(VLV_DISPLAY_BASE + 0x60100)
>  #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2*(phy)+(ch)+27))
>  #define   PHY_LDO_DELAY_0NS			0x0
>  #define   PHY_LDO_DELAY_200NS			0x1
> @@ -2224,7 +2235,7 @@ enum skl_disp_power_wells {
>  #define   PHY_CH_DEEP_PSR			0x7
>  #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6*(phy)+3*(ch)+2))
>  #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
> -#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
> +#define DISPLAY_PHY_STATUS _REG(VLV_DISPLAY_BASE + 0x60104)
>  #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
>  #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6-(6*(phy)+3*(ch))))
>  #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8-(6*(phy)+3*(ch)+(spline))))
> @@ -2267,9 +2278,9 @@ enum skl_disp_power_wells {
>  #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
>  #define   SDVO_MULTIPLIER_SHIFT_VGA		0
>  
> -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
> -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
> -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
> +#define _DPLL_A_MD _REG(dev_priv->info.display_mmio_offset + 0x601c)
> +#define _DPLL_B_MD _REG(dev_priv->info.display_mmio_offset + 0x6020)
> +#define _CHV_DPLL_C_MD _REG(dev_priv->info.display_mmio_offset + 0x603c)
>  #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
>  
>  /*
> @@ -2309,12 +2320,12 @@ enum skl_disp_power_wells {
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
>  
> -#define _FPA0	0x06040
> -#define _FPA1	0x06044
> -#define _FPB0	0x06048
> -#define _FPB1	0x0604c
> -#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
> -#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
> +#define _FPA0	0x6040
> +#define _FPA1	0x6044
> +#define _FPB0	0x6048
> +#define _FPB1	0x604c
> +#define FP0(pipe) _REG_PIPE(pipe, _FPA0, _FPB0)
> +#define FP1(pipe) _REG_PIPE(pipe, _FPA1, _FPB1)
>  #define   FP_N_DIV_MASK		0x003f0000
>  #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
>  #define   FP_N_DIV_SHIFT		16
> @@ -2323,7 +2334,7 @@ enum skl_disp_power_wells {
>  #define   FP_M2_DIV_MASK	0x0000003f
>  #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
>  #define   FP_M2_DIV_SHIFT		 0
> -#define DPLL_TEST	0x606c
> +#define DPLL_TEST	_REG(0x606c)
>  #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
>  #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
>  #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
> @@ -2334,12 +2345,12 @@ enum skl_disp_power_wells {
>  #define   DPLLA_TEST_N_BYPASS		(1 << 3)
>  #define   DPLLA_TEST_M_BYPASS		(1 << 2)
>  #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
> -#define D_STATE		0x6104
> +#define D_STATE		_REG(0x6104)
>  #define  DSTATE_GFX_RESET_I830			(1<<6)
>  #define  DSTATE_PLL_D3_OFF			(1<<3)
>  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
>  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
> -#define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
> +#define DSPCLK_GATE_D	_REG(dev_priv->info.display_mmio_offset + 0x6200)
>  # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
>  # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
>  # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> @@ -2378,7 +2389,7 @@ enum skl_disp_power_wells {
>  # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
>  # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
>  
> -#define RENCLK_GATE_D1		0x6204
> +#define RENCLK_GATE_D1		_REG(0x6204)
>  # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
>  # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
>  # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
> @@ -2442,35 +2453,35 @@ enum skl_disp_power_wells {
>  # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
>  # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
>  
> -#define RENCLK_GATE_D2		0x6208
> +#define RENCLK_GATE_D2		_REG(0x6208)
>  #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
>  #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
>  #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
>  
> -#define VDECCLK_GATE_D		0x620C		/* g4x only */
> +#define VDECCLK_GATE_D		_REG(0x620C)		/* g4x only */
>  #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
>  
> -#define RAMCLK_GATE_D		0x6210		/* CRL only */
> -#define DEUC			0x6214          /* CRL only */
> +#define RAMCLK_GATE_D		_REG(0x6210)		/* CRL only */
> +#define DEUC			_REG(0x6214)          /* CRL only */
>  
> -#define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
> +#define FW_BLC_SELF_VLV		_REG(VLV_DISPLAY_BASE + 0x6500)
>  #define  FW_CSPWRDWNEN		(1<<15)
>  
> -#define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
> +#define MI_ARB_VLV		_REG(VLV_DISPLAY_BASE + 0x6504)
>  
> -#define CZCLK_CDCLK_FREQ_RATIO	(VLV_DISPLAY_BASE + 0x6508)
> +#define CZCLK_CDCLK_FREQ_RATIO	_REG(VLV_DISPLAY_BASE + 0x6508)
>  #define   CDCLK_FREQ_SHIFT	4
>  #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
>  #define   CZCLK_FREQ_MASK	0xf
>  
> -#define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
> +#define GCI_CONTROL		_REG(VLV_DISPLAY_BASE + 0x650C)
>  #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
>  #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
>  #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
>  #define   PFI_CREDIT_RESEND	(1 << 27)
>  #define   VGA_FAST_MODE_DISABLE	(1 << 14)
>  
> -#define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
> +#define GMBUSFREQ_VLV		_REG(VLV_DISPLAY_BASE + 0x6510)
>  
>  /*
>   * Palette regs
> @@ -2478,8 +2489,8 @@ enum skl_disp_power_wells {
>  #define PALETTE_A_OFFSET 0xa000
>  #define PALETTE_B_OFFSET 0xa800
>  #define CHV_PALETTE_C_OFFSET 0xc000
> -#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
> -			  dev_priv->info.display_mmio_offset + (i) * 4)
> +#define PALETTE(pipe, i) _REG(dev_priv->info.palette_offsets[pipe] +	\
> +			      dev_priv->info.display_mmio_offset + (i) * 4)
>  
>  /* MCH MMIO space */
>  
> @@ -2498,31 +2509,31 @@ enum skl_disp_power_wells {
>  #define MCHBAR_MIRROR_BASE_SNB	0x140000
>  
>  /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
> -#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
> +#define DCLK _REG(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
>  
>  /* 915-945 and GM965 MCH register controlling DRAM channel access */
> -#define DCC			0x10200
> +#define DCC			_REG(MCHBAR_MIRROR_BASE + 0x200)
>  #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
>  #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
>  #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
>  #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
>  #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
>  #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
> -#define DCC2			0x10204
> +#define DCC2			_REG(MCHBAR_MIRROR_BASE + 0x204)
>  #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
>  
>  /* Pineview MCH register contains DDR3 setting */
> -#define CSHRDDR3CTL            0x101a8
> +#define CSHRDDR3CTL            _REG(MCHBAR_MIRROR_BASE + 0x1a8)
>  #define CSHRDDR3CTL_DDR3       (1 << 2)
>  
>  /* 965 MCH register controlling DRAM channel configuration */
> -#define C0DRB3			0x10206
> -#define C1DRB3			0x10606
> +#define C0DRB3			_REG(MCHBAR_MIRROR_BASE + 0x206)
> +#define C1DRB3			_REG(MCHBAR_MIRROR_BASE + 0x606)
>  
>  /* snb MCH registers for reading the DRAM channel configuration */
> -#define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
> -#define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> -#define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> +#define MAD_DIMM_C0			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5004)
> +#define MAD_DIMM_C1			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> +#define MAD_DIMM_C2			_REG(MCHBAR_MIRROR_BASE_SNB + 0x500C)
>  #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
>  #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
>  #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
> @@ -2542,14 +2553,14 @@ enum skl_disp_power_wells {
>  #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
>  
>  /* snb MCH registers for priority tuning */
> -#define MCH_SSKPD			(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
> +#define MCH_SSKPD			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
>  #define   MCH_SSKPD_WM0_MASK		0x3f
>  #define   MCH_SSKPD_WM0_VAL		0xc
>  
> -#define MCH_SECP_NRG_STTS		(MCHBAR_MIRROR_BASE_SNB + 0x592c)
> +#define MCH_SECP_NRG_STTS		_REG(MCHBAR_MIRROR_BASE_SNB + 0x592c)
>  
>  /* Clocking configuration register */
> -#define CLKCFG			0x10c00
> +#define CLKCFG			_REG(MCHBAR_MIRROR_BASE + 0xc00)
>  #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
>  #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
>  #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
> @@ -2565,26 +2576,26 @@ enum skl_disp_power_wells {
>  #define CLKCFG_MEM_800					(3 << 4)
>  #define CLKCFG_MEM_MASK					(7 << 4)
>  
> -#define HPLLVCO                 (MCHBAR_MIRROR_BASE + 0xc38)
> -#define HPLLVCO_MOBILE          (MCHBAR_MIRROR_BASE + 0xc0f)
> +#define HPLLVCO                 _REG(MCHBAR_MIRROR_BASE + 0xc38)
> +#define HPLLVCO_MOBILE          _REG(MCHBAR_MIRROR_BASE + 0xc0f)
>  
> -#define TSC1			0x11001
> +#define TSC1			_REG(0x11001)
>  #define   TSE			(1<<0)
> -#define TR1			0x11006
> -#define TSFS			0x11020
> +#define TR1			_REG(0x11006)
> +#define TSFS			_REG(0x11020)
>  #define   TSFS_SLOPE_MASK	0x0000ff00
>  #define   TSFS_SLOPE_SHIFT	8
>  #define   TSFS_INTR_MASK	0x000000ff
>  
> -#define CRSTANDVID		0x11100
> -#define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
> +#define CRSTANDVID		_REG(0x11100)
> +#define PXVFREQ(fstart)		_REG(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
>  #define   PXVFREQ_PX_MASK	0x7f000000
>  #define   PXVFREQ_PX_SHIFT	24
> -#define VIDFREQ_BASE		0x11110
> -#define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
> -#define VIDFREQ2		0x11114
> -#define VIDFREQ3		0x11118
> -#define VIDFREQ4		0x1111c
> +#define VIDFREQ_BASE		_REG(0x11110)
> +#define VIDFREQ1		_REG(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
> +#define VIDFREQ2		_REG(0x11114)
> +#define VIDFREQ3		_REG(0x11118)
> +#define VIDFREQ4		_REG(0x1111c)
>  #define   VIDFREQ_P0_MASK	0x1f000000
>  #define   VIDFREQ_P0_SHIFT	24
>  #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
> @@ -2596,8 +2607,8 @@ enum skl_disp_power_wells {
>  #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
>  #define   VIDFREQ_P1_CSCLK_SHIFT 4
>  #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
> -#define INTTOEXT_BASE_ILK	0x11300
> -#define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
> +#define INTTOEXT_BASE_ILK	_REG(0x11300)
> +#define INTTOEXT_BASE		_REG(0x11120) /* INTTOEXT1-8 (0x1113c) */
>  #define   INTTOEXT_MAP3_SHIFT	24
>  #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
>  #define   INTTOEXT_MAP2_SHIFT	16
> @@ -2606,7 +2617,7 @@ enum skl_disp_power_wells {
>  #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
>  #define   INTTOEXT_MAP0_SHIFT	0
>  #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
> -#define MEMSWCTL		0x11170 /* Ironlake only */
> +#define MEMSWCTL		_REG(0x11170) /* Ironlake only */
>  #define   MEMCTL_CMD_MASK	0xe000
>  #define   MEMCTL_CMD_SHIFT	13
>  #define   MEMCTL_CMD_RCLK_OFF	0
> @@ -2621,8 +2632,8 @@ enum skl_disp_power_wells {
>  #define   MEMCTL_FREQ_SHIFT	8
>  #define   MEMCTL_SFCAVM		(1<<7)
>  #define   MEMCTL_TGT_VID_MASK	0x007f
> -#define MEMIHYST		0x1117c
> -#define MEMINTREN		0x11180 /* 16 bits */
> +#define MEMIHYST		_REG(0x1117c)
> +#define MEMINTREN		_REG(0x11180) /* 16 bits */
>  #define   MEMINT_RSEXIT_EN	(1<<8)
>  #define   MEMINT_CX_SUPR_EN	(1<<7)
>  #define   MEMINT_CONT_BUSY_EN	(1<<6)
> @@ -2632,7 +2643,7 @@ enum skl_disp_power_wells {
>  #define   MEMINT_UP_EVAL_EN	(1<<2)
>  #define   MEMINT_DOWN_EVAL_EN	(1<<1)
>  #define   MEMINT_SW_CMD_EN	(1<<0)
> -#define MEMINTRSTR		0x11182 /* 16 bits */
> +#define MEMINTRSTR		_REG(0x11182) /* 16 bits */
>  #define   MEM_RSEXIT_MASK	0xc000
>  #define   MEM_RSEXIT_SHIFT	14
>  #define   MEM_CONT_BUSY_MASK	0x3000
> @@ -2652,7 +2663,7 @@ enum skl_disp_power_wells {
>  #define   MEM_INT_STEER_CMR	1
>  #define   MEM_INT_STEER_SMI	2
>  #define   MEM_INT_STEER_SCI	3
> -#define MEMINTRSTS		0x11184
> +#define MEMINTRSTS		_REG(0x11184)
>  #define   MEMINT_RSEXIT		(1<<7)
>  #define   MEMINT_CONT_BUSY	(1<<6)
>  #define   MEMINT_AVG_BUSY	(1<<5)
> @@ -2661,7 +2672,7 @@ enum skl_disp_power_wells {
>  #define   MEMINT_UP_EVAL	(1<<2)
>  #define   MEMINT_DOWN_EVAL	(1<<1)
>  #define   MEMINT_SW_CMD		(1<<0)
> -#define MEMMODECTL		0x11190
> +#define MEMMODECTL		_REG(0x11190)
>  #define   MEMMODE_BOOST_EN	(1<<31)
>  #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
>  #define   MEMMODE_BOOST_FREQ_SHIFT 24
> @@ -2678,8 +2689,8 @@ enum skl_disp_power_wells {
>  #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
>  #define   MEMMODE_FMAX_SHIFT	4
>  #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
> -#define RCBMAXAVG		0x1119c
> -#define MEMSWCTL2		0x1119e /* Cantiga only */
> +#define RCBMAXAVG		_REG(0x1119c)
> +#define MEMSWCTL2		_REG(0x1119e) /* Cantiga only */
>  #define   SWMEMCMD_RENDER_OFF	(0 << 13)
>  #define   SWMEMCMD_RENDER_ON	(1 << 13)
>  #define   SWMEMCMD_SWFREQ	(2 << 13)
> @@ -2691,11 +2702,11 @@ enum skl_disp_power_wells {
>  #define   SWFREQ_MASK		0x0380 /* P0-7 */
>  #define   SWFREQ_SHIFT		7
>  #define   TARVID_MASK		0x001f
> -#define MEMSTAT_CTG		0x111a0
> -#define RCBMINAVG		0x111a0
> -#define RCUPEI			0x111b0
> -#define RCDNEI			0x111b4
> -#define RSTDBYCTL		0x111b8
> +#define MEMSTAT_CTG		_REG(0x111a0)
> +#define RCBMINAVG		_REG(0x111a0)
> +#define RCUPEI			_REG(0x111b0)
> +#define RCDNEI			_REG(0x111b4)
> +#define RSTDBYCTL		_REG(0x111b8)
>  #define   RS1EN			(1<<31)
>  #define   RS2EN			(1<<30)
>  #define   RS3EN			(1<<29)
> @@ -2739,10 +2750,10 @@ enum skl_disp_power_wells {
>  #define   RS_CSTATE_C367_RS2	(3<<4)
>  #define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
>  #define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
> -#define VIDCTL			0x111c0
> -#define VIDSTS			0x111c8
> -#define VIDSTART		0x111cc /* 8 bits */
> -#define MEMSTAT_ILK			0x111f8
> +#define VIDCTL			_REG(0x111c0)
> +#define VIDSTS			_REG(0x111c8)
> +#define VIDSTART		_REG(0x111cc) /* 8 bits */
> +#define MEMSTAT_ILK		_REG(0x111f8)
>  #define   MEMSTAT_VID_MASK	0x7f00
>  #define   MEMSTAT_VID_SHIFT	8
>  #define   MEMSTAT_PSTATE_MASK	0x00f8
> @@ -2753,55 +2764,55 @@ enum skl_disp_power_wells {
>  #define   MEMSTAT_SRC_CTL_TRB	1
>  #define   MEMSTAT_SRC_CTL_THM	2
>  #define   MEMSTAT_SRC_CTL_STDBY 3
> -#define RCPREVBSYTUPAVG		0x113b8
> -#define RCPREVBSYTDNAVG		0x113bc
> -#define PMMISC			0x11214
> +#define RCPREVBSYTUPAVG		_REG(0x113b8)
> +#define RCPREVBSYTDNAVG		_REG(0x113bc)
> +#define PMMISC			_REG(0x11214)
>  #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
> -#define SDEW			0x1124c
> -#define CSIEW0			0x11250
> -#define CSIEW1			0x11254
> -#define CSIEW2			0x11258
> -#define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */
> -#define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */
> -#define MCHAFE			0x112c0
> -#define CSIEC			0x112e0
> -#define DMIEC			0x112e4
> -#define DDREC			0x112e8
> -#define PEG0EC			0x112ec
> -#define PEG1EC			0x112f0
> -#define GFXEC			0x112f4
> -#define RPPREVBSYTUPAVG		0x113b8
> -#define RPPREVBSYTDNAVG		0x113bc
> -#define ECR			0x11600
> +#define SDEW			_REG(0x1124c)
> +#define CSIEW0			_REG(0x11250)
> +#define CSIEW1			_REG(0x11254)
> +#define CSIEW2			_REG(0x11258)
> +#define PEW(i)			_REG(0x1125c + (i) * 4) /* 5 registers */
> +#define DEW(i)			_REG(0x11270 + (i) * 4) /* 3 registers */
> +#define MCHAFE			_REG(0x112c0)
> +#define CSIEC			_REG(0x112e0)
> +#define DMIEC			_REG(0x112e4)
> +#define DDREC			_REG(0x112e8)
> +#define PEG0EC			_REG(0x112ec)
> +#define PEG1EC			_REG(0x112f0)
> +#define GFXEC			_REG(0x112f4)
> +#define RPPREVBSYTUPAVG		_REG(0x113b8)
> +#define RPPREVBSYTDNAVG		_REG(0x113bc)
> +#define ECR			_REG(0x11600)
>  #define   ECR_GPFE		(1<<31)
>  #define   ECR_IMONE		(1<<30)
>  #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
> -#define OGW0			0x11608
> -#define OGW1			0x1160c
> -#define EG0			0x11610
> -#define EG1			0x11614
> -#define EG2			0x11618
> -#define EG3			0x1161c
> -#define EG4			0x11620
> -#define EG5			0x11624
> -#define EG6			0x11628
> -#define EG7			0x1162c
> -#define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */
> -#define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */
> -#define LCFUSE02		0x116c0
> +#define OGW0			_REG(0x11608)
> +#define OGW1			_REG(0x1160c)
> +#define EG0			_REG(0x11610)
> +#define EG1			_REG(0x11614)
> +#define EG2			_REG(0x11618)
> +#define EG3			_REG(0x1161c)
> +#define EG4			_REG(0x11620)
> +#define EG5			_REG(0x11624)
> +#define EG6			_REG(0x11628)
> +#define EG7			_REG(0x1162c)
> +#define PXW(i)			_REG(0x11664 + (i) * 4) /* 4 registers */
> +#define PXWL(i)			_REG(0x11680 + (i) * 8) /* 8 registers */
> +#define LCFUSE02		_REG(0x116c0)
>  #define   LCFUSE_HIV_MASK	0x000000ff
> -#define CSIPLL0			0x12c10
> -#define DDRMPLL1		0X12c20
> -#define PEG_BAND_GAP_DATA	0x14d68
> +#define CSIPLL0			_REG(0x12c10)
> +#define DDRMPLL1		_REG(0X12c20)
> +#define PEG_BAND_GAP_DATA	_REG(0x14d68)
>  
> -#define GEN6_GT_THREAD_STATUS_REG 0x13805c
> +#define GEN6_GT_THREAD_STATUS_REG _REG(0x13805c)
>  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>  
> -#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> -#define BXT_GT_PERF_STATUS      (MCHBAR_MIRROR_BASE_SNB + 0x7070)
> -#define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
> -#define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
> -#define BXT_RP_STATE_CAP        0x138170
> +#define GEN6_GT_PERF_STATUS	_REG(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> +#define BXT_GT_PERF_STATUS      _REG(MCHBAR_MIRROR_BASE_SNB + 0x7070)
> +#define GEN6_RP_STATE_LIMITS	_REG(MCHBAR_MIRROR_BASE_SNB + 0x5994)
> +#define GEN6_RP_STATE_CAP	_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
> +#define BXT_RP_STATE_CAP        _REG(0x138170)
>  
>  #define INTERVAL_1_28_US(us)	(((us) * 100) >> 7)
>  #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
> @@ -2812,7 +2823,7 @@ enum skl_disp_power_wells {
>  /*
>   * Logical Context regs
>   */
> -#define CCID			0x2180
> +#define CCID			_REG(0x2180)
>  #define   CCID_EN		(1<<0)
>  /*
>   * Notes on SNB/IVB/VLV context size:
> @@ -2827,7 +2838,7 @@ enum skl_disp_power_wells {
>   * - GT1 size just indicates how much of render context
>   *   doesn't need saving on GT1
>   */
> -#define CXT_SIZE		0x21a0
> +#define CXT_SIZE		_REG(0x21a0)
>  #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
>  #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
>  #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
> @@ -2836,7 +2847,7 @@ enum skl_disp_power_wells {
>  #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
>  					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
>  					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
> -#define GEN7_CXT_SIZE		0x21a8
> +#define GEN7_CXT_SIZE		_REG(0x21a8)
>  #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
>  #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
>  #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
> @@ -2856,23 +2867,23 @@ enum skl_disp_power_wells {
>  /* Same as Haswell, but 72064 bytes now. */
>  #define GEN8_CXT_TOTAL_SIZE		(18 * PAGE_SIZE)
>  
> -#define CHV_CLK_CTL1			0x101100
> -#define VLV_CLK_CTL2			0x101104
> +#define CHV_CLK_CTL1			_REG(0x101100)
> +#define VLV_CLK_CTL2			_REG(0x101104)
>  #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
>  
>  /*
>   * Overlay regs
>   */
>  
> -#define OVADD			0x30000
> -#define DOVSTA			0x30008
> +#define OVADD			_REG(0x30000)
> +#define DOVSTA			_REG(0x30008)
>  #define OC_BUF			(0x3<<20)
> -#define OGAMC5			0x30010
> -#define OGAMC4			0x30014
> -#define OGAMC3			0x30018
> -#define OGAMC2			0x3001c
> -#define OGAMC1			0x30020
> -#define OGAMC0			0x30024
> +#define OGAMC5			_REG(0x30010)
> +#define OGAMC4			_REG(0x30014)
> +#define OGAMC3			_REG(0x30018)
> +#define OGAMC2			_REG(0x3001c)
> +#define OGAMC1			_REG(0x30020)
> +#define OGAMC0			_REG(0x30024)
>  
>  /*
>   * Display engine regs
> @@ -2932,28 +2943,18 @@ enum skl_disp_power_wells {
>  #define _PIPE_CRC_RES_4_B_IVB		0x61070
>  #define _PIPE_CRC_RES_5_B_IVB		0x61074
>  
> -#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
> -#define PIPE_CRC_RES_1_IVB(pipe)	\
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
> -#define PIPE_CRC_RES_2_IVB(pipe)	\
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
> -#define PIPE_CRC_RES_3_IVB(pipe)	\
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
> -#define PIPE_CRC_RES_4_IVB(pipe)	\
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
> -#define PIPE_CRC_RES_5_IVB(pipe)	\
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
> -
> -#define PIPE_CRC_RES_RED(pipe) \
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
> -#define PIPE_CRC_RES_GREEN(pipe) \
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
> -#define PIPE_CRC_RES_BLUE(pipe) \
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
> -#define PIPE_CRC_RES_RES1_I915(pipe) \
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
> -#define PIPE_CRC_RES_RES2_G4X(pipe) \
> -	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
> +#define PIPE_CRC_CTL(pipe)		_REG_TRANS2(pipe, _PIPE_CRC_CTL_A)
> +#define PIPE_CRC_RES_1_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
> +#define PIPE_CRC_RES_2_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
> +#define PIPE_CRC_RES_3_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
> +#define PIPE_CRC_RES_4_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
> +#define PIPE_CRC_RES_5_IVB(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
> +
> +#define PIPE_CRC_RES_RED(pipe)		_REG_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
> +#define PIPE_CRC_RES_GREEN(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
> +#define PIPE_CRC_RES_BLUE(pipe)		_REG_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
> +#define PIPE_CRC_RES_RES1_I915(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
> +#define PIPE_CRC_RES_RES2_G4X(pipe)	_REG_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
>  
>  /* Pipe A timing regs */
>  #define _HTOTAL_A	0x60000
> @@ -2985,20 +2986,20 @@ enum skl_disp_power_wells {
>  #define CHV_TRANSCODER_C_OFFSET 0x63000
>  #define TRANSCODER_EDP_OFFSET 0x6f000
>  
> -#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
> +#define _REG_TRANS2(pipe, reg) _REG(dev_priv->info.trans_offsets[(pipe)] - \
>  	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
>  	dev_priv->info.display_mmio_offset)
>  
> -#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
> -#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
> -#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
> -#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
> -#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
> -#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
> -#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
> -#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
> -#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
> -#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
> +#define HTOTAL(trans)		_REG_TRANS2(trans, _HTOTAL_A)
> +#define HBLANK(trans)		_REG_TRANS2(trans, _HBLANK_A)
> +#define HSYNC(trans)		_REG_TRANS2(trans, _HSYNC_A)
> +#define VTOTAL(trans)		_REG_TRANS2(trans, _VTOTAL_A)
> +#define VBLANK(trans)		_REG_TRANS2(trans, _VBLANK_A)
> +#define VSYNC(trans)		_REG_TRANS2(trans, _VSYNC_A)
> +#define BCLRPAT(trans)		_REG_TRANS2(trans, _BCLRPAT_A)
> +#define VSYNCSHIFT(trans)	_REG_TRANS2(trans, _VSYNCSHIFT_A)
> +#define PIPESRC(trans)		_REG_TRANS2(trans, _PIPEASRC)
> +#define PIPE_MULT(trans)	_REG_TRANS2(trans, _PIPE_MULT_A)
>  
>  /* VLV eDP PSR registers */
>  #define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
> @@ -3014,14 +3015,14 @@ enum skl_disp_power_wells {
>  #define  VLV_EDP_PSR_DBL_FRAME			(1<<10)
>  #define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff<<16)
>  #define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
> -#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
> +#define VLV_PSRCTL(pipe)	_REG_PIPE(pipe, _PSRCTLA, _PSRCTLB)
>  
>  #define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
>  #define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
>  #define  VLV_EDP_PSR_SDP_FREQ_MASK	(3<<30)
>  #define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1<<31)
>  #define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1<<30)
> -#define VLV_VSCSDP(pipe)	_PIPE(pipe, _VSCSDPA, _VSCSDPB)
> +#define VLV_VSCSDP(pipe)	_REG_PIPE(pipe, _VSCSDPA, _VSCSDPB)
>  
>  #define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
>  #define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
> @@ -3034,12 +3035,12 @@ enum skl_disp_power_wells {
>  #define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4<<0)
>  #define  VLV_EDP_PSR_EXIT		(5<<0)
>  #define  VLV_EDP_PSR_IN_TRANS		(1<<7)
> -#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
> +#define VLV_PSRSTAT(pipe)	_REG_PIPE(pipe, _PSRSTATA, _PSRSTATB)
>  
>  /* HSW+ eDP PSR registers */
>  #define HSW_EDP_PSR_BASE	0x64800
>  #define BDW_EDP_PSR_BASE	0x6f800
> -#define EDP_PSR_CTL				(dev_priv->psr_mmio_base + 0)
> +#define EDP_PSR_CTL				_REG(dev_priv->psr_mmio_base + 0)
>  #define   EDP_PSR_ENABLE			(1<<31)
>  #define   BDW_PSR_SINGLE_FRAME			(1<<30)
>  #define   EDP_PSR_LINK_STANDBY			(1<<27)
> @@ -3062,10 +3063,10 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_TP1_TIME_0us			(3<<4)
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
> -#define EDP_PSR_AUX_CTL				(dev_priv->psr_mmio_base + 0x10)
> -#define EDP_PSR_AUX_DATA(i)			(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
> +#define EDP_PSR_AUX_CTL				_REG(dev_priv->psr_mmio_base + 0x10)
> +#define EDP_PSR_AUX_DATA(i)			_REG(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>  
> -#define EDP_PSR_STATUS_CTL			(dev_priv->psr_mmio_base + 0x40)
> +#define EDP_PSR_STATUS_CTL			_REG(dev_priv->psr_mmio_base + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
>  #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
>  #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
> @@ -3089,15 +3090,15 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
>  #define   EDP_PSR_STATUS_IDLE_MASK		0xf
>  
> -#define EDP_PSR_PERF_CNT		(dev_priv->psr_mmio_base + 0x44)
> +#define EDP_PSR_PERF_CNT		_REG(dev_priv->psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
>  
> -#define EDP_PSR_DEBUG_CTL		(dev_priv->psr_mmio_base + 0x60)
> +#define EDP_PSR_DEBUG_CTL		_REG(dev_priv->psr_mmio_base + 0x60)
>  #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
>  #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
>  
> -#define EDP_PSR2_CTL			0x6f900
> +#define EDP_PSR2_CTL			_REG(0x6f900)
>  #define   EDP_PSR2_ENABLE		(1<<31)
>  #define   EDP_SU_TRACK_ENABLE		(1<<30)
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
> @@ -3112,9 +3113,9 @@ enum skl_disp_power_wells {
>  #define   EDP_PSR2_IDLE_MASK		0xf
>  
>  /* VGA port control */
> -#define ADPA			0x61100
> -#define PCH_ADPA                0xe1100
> -#define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
> +#define ADPA			_REG(0x61100)
> +#define PCH_ADPA                _REG(0xe1100)
> +#define VLV_ADPA		_REG(VLV_DISPLAY_BASE + 0x61100)
>  
>  #define   ADPA_DAC_ENABLE	(1<<31)
>  #define   ADPA_DAC_DISABLE	0
> @@ -3160,7 +3161,7 @@ enum skl_disp_power_wells {
>  
>  
>  /* Hotplug control (945+ only) */
> -#define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
> +#define PORT_HOTPLUG_EN		_REG(dev_priv->info.display_mmio_offset + 0x61110)
>  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
>  #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
>  #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
> @@ -3190,7 +3191,7 @@ enum skl_disp_power_wells {
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
>  
> -#define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
> +#define PORT_HOTPLUG_STAT	_REG(dev_priv->info.display_mmio_offset + 0x61114)
>  /*
>   * HDMI/DP bits are gen4+
>   *
> @@ -3255,21 +3256,23 @@ enum skl_disp_power_wells {
>  
>  /* SDVO and HDMI port control.
>   * The same register may be used for SDVO or HDMI */
> -#define GEN3_SDVOB	0x61140
> -#define GEN3_SDVOC	0x61160
> +#define _GEN3_SDVOB	0x61140
> +#define _GEN3_SDVOC	0x61160
> +#define GEN3_SDVOB	_REG(_GEN3_SDVOB)
> +#define GEN3_SDVOC	_REG(_GEN3_SDVOC)
>  #define GEN4_HDMIB	GEN3_SDVOB
>  #define GEN4_HDMIC	GEN3_SDVOC
> -#define VLV_HDMIB	(VLV_DISPLAY_BASE + GEN4_HDMIB)
> -#define VLV_HDMIC	(VLV_DISPLAY_BASE + GEN4_HDMIC)
> -#define CHV_HDMID	(VLV_DISPLAY_BASE + 0x6116C)
> -#define PCH_SDVOB	0xe1140
> +#define VLV_HDMIB	_REG(VLV_DISPLAY_BASE + 0x61140)
> +#define VLV_HDMIC	_REG(VLV_DISPLAY_BASE + 0x61160)
> +#define CHV_HDMID	_REG(VLV_DISPLAY_BASE + 0x6116C)
> +#define PCH_SDVOB	_REG(0xe1140)
>  #define PCH_HDMIB	PCH_SDVOB
> -#define PCH_HDMIC	0xe1150
> -#define PCH_HDMID	0xe1160
> +#define PCH_HDMIC	_REG(0xe1150)
> +#define PCH_HDMID	_REG(0xe1160)
>  
> -#define PORT_DFT_I9XX				0x61150
> +#define PORT_DFT_I9XX				_REG(0x61150)
>  #define   DC_BALANCE_RESET			(1 << 25)
> -#define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
> +#define PORT_DFT2_G4X		_REG(dev_priv->info.display_mmio_offset + 0x61154)
>  #define   DC_BALANCE_RESET_VLV			(1 << 31)
>  #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
>  #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
> @@ -3329,9 +3332,12 @@ enum skl_disp_power_wells {
>  
>  
>  /* DVO port control */
> -#define DVOA			0x61120
> -#define DVOB			0x61140
> -#define DVOC			0x61160
> +#define _DVOA			0x61120
> +#define DVOA			_REG(_DVOA)
> +#define _DVOB			0x61140
> +#define DVOB			_REG(_DVOB)
> +#define _DVOC			0x61160
> +#define DVOC			_REG(_DVOC)
>  #define   DVO_ENABLE			(1 << 31)
>  #define   DVO_PIPE_B_SELECT		(1 << 30)
>  #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
> @@ -3356,14 +3362,14 @@ enum skl_disp_power_wells {
>  #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
>  #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
>  #define   DVO_PRESERVE_MASK		(0x7<<24)
> -#define DVOA_SRCDIM		0x61124
> -#define DVOB_SRCDIM		0x61144
> -#define DVOC_SRCDIM		0x61164
> +#define DVOA_SRCDIM		_REG(0x61124)
> +#define DVOB_SRCDIM		_REG(0x61144)
> +#define DVOC_SRCDIM		_REG(0x61164)
>  #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
>  #define   DVO_SRCDIM_VERTICAL_SHIFT	0
>  
>  /* LVDS port control */
> -#define LVDS			0x61180
> +#define LVDS			_REG(0x61180)
>  /*
>   * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
>   * the DPLL semantics change when the LVDS is assigned to that pipe.
> @@ -3413,13 +3419,13 @@ enum skl_disp_power_wells {
>  #define   LVDS_B0B3_POWER_UP		(3 << 2)
>  
>  /* Video Data Island Packet control */
> -#define VIDEO_DIP_DATA		0x61178
> +#define VIDEO_DIP_DATA		_REG(0x61178)
>  /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
>   * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
>   * of the infoframe structure specified by CEA-861. */
>  #define   VIDEO_DIP_DATA_SIZE	32
>  #define   VIDEO_DIP_VSC_DATA_SIZE	36
> -#define VIDEO_DIP_CTL		0x61170
> +#define VIDEO_DIP_CTL		_REG(0x61170)
>  /* Pre HSW: */
>  #define   VIDEO_DIP_ENABLE		(1 << 31)
>  #define   VIDEO_DIP_PORT(port)		((port) << 29)
> @@ -3446,7 +3452,7 @@ enum skl_disp_power_wells {
>  #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
>  
>  /* Panel power sequencing */
> -#define PP_STATUS	0x61200
> +#define PP_STATUS	_REG(0x61200)
>  #define   PP_ON		(1 << 31)
>  /*
>   * Indicates that all dependencies of the panel are on:
> @@ -3472,14 +3478,14 @@ enum skl_disp_power_wells {
>  #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
>  #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
>  #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
> -#define PP_CONTROL	0x61204
> +#define PP_CONTROL	_REG(0x61204)
>  #define   POWER_TARGET_ON	(1 << 0)
> -#define PP_ON_DELAYS	0x61208
> -#define PP_OFF_DELAYS	0x6120c
> -#define PP_DIVISOR	0x61210
> +#define PP_ON_DELAYS	_REG(0x61208)
> +#define PP_OFF_DELAYS	_REG(0x6120c)
> +#define PP_DIVISOR	_REG(0x61210)
>  
>  /* Panel fitting */
> -#define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
> +#define PFIT_CONTROL	_REG(dev_priv->info.display_mmio_offset + 0x61230)
>  #define   PFIT_ENABLE		(1 << 31)
>  #define   PFIT_PIPE_MASK	(3 << 29)
>  #define   PFIT_PIPE_SHIFT	29
> @@ -3497,7 +3503,7 @@ enum skl_disp_power_wells {
>  #define   PFIT_SCALING_PROGRAMMED (1 << 26)
>  #define   PFIT_SCALING_PILLAR	(2 << 26)
>  #define   PFIT_SCALING_LETTER	(3 << 26)
> -#define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
> +#define PFIT_PGM_RATIOS _REG(dev_priv->info.display_mmio_offset + 0x61234)
>  /* Pre-965 */
>  #define		PFIT_VERT_SCALE_SHIFT		20
>  #define		PFIT_VERT_SCALE_MASK		0xfff00000
> @@ -3509,25 +3515,25 @@ enum skl_disp_power_wells {
>  #define		PFIT_HORIZ_SCALE_SHIFT_965	0
>  #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
>  
> -#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
> +#define PFIT_AUTO_RATIOS _REG(dev_priv->info.display_mmio_offset + 0x61238)
>  
>  #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
>  #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
> -#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
> -				     _VLV_BLC_PWM_CTL2_B)
> +#define VLV_BLC_PWM_CTL2(pipe) _REG_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
> +					 _VLV_BLC_PWM_CTL2_B)
>  
>  #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
>  #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
> -#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
> -				    _VLV_BLC_PWM_CTL_B)
> +#define VLV_BLC_PWM_CTL(pipe) _REG_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
> +					_VLV_BLC_PWM_CTL_B)
>  
>  #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
>  #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
> -#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
> -				     _VLV_BLC_HIST_CTL_B)
> +#define VLV_BLC_HIST_CTL(pipe) _REG_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
> +					 _VLV_BLC_HIST_CTL_B)
>  
>  /* Backlight control */
> -#define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
> +#define BLC_PWM_CTL2	_REG(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
>  #define   BLM_PWM_ENABLE		(1 << 31)
>  #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
>  #define   BLM_PIPE_SELECT		(1 << 29)
> @@ -3550,7 +3556,7 @@ enum skl_disp_power_wells {
>  #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
>  #define   BLM_PHASE_IN_INCR_SHIFT	(0)
>  #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
> -#define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
> +#define BLC_PWM_CTL	_REG(dev_priv->info.display_mmio_offset + 0x61254)
>  /*
>   * This is the most significant 15 bits of the number of backlight cycles in a
>   * complete cycle of the modulated backlight control.
> @@ -3572,44 +3578,44 @@ enum skl_disp_power_wells {
>  #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
>  #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
>  
> -#define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
> +#define BLC_HIST_CTL	_REG(dev_priv->info.display_mmio_offset + 0x61260)
>  #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
>  
>  /* New registers for PCH-split platforms. Safe where new bits show up, the
>   * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> -#define BLC_PWM_CPU_CTL2	0x48250
> -#define BLC_PWM_CPU_CTL		0x48254
> +#define BLC_PWM_CPU_CTL2	_REG(0x48250)
> +#define BLC_PWM_CPU_CTL		_REG(0x48254)
>  
> -#define HSW_BLC_PWM2_CTL	0x48350
> +#define HSW_BLC_PWM2_CTL	_REG(0x48350)
>  
>  /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
>   * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
> -#define BLC_PWM_PCH_CTL1	0xc8250
> +#define BLC_PWM_PCH_CTL1	_REG(0xc8250)
>  #define   BLM_PCH_PWM_ENABLE			(1 << 31)
>  #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
>  #define   BLM_PCH_POLARITY			(1 << 29)
> -#define BLC_PWM_PCH_CTL2	0xc8254
> +#define BLC_PWM_PCH_CTL2	_REG(0xc8254)
>  
> -#define UTIL_PIN_CTL		0x48400
> +#define UTIL_PIN_CTL		_REG(0x48400)
>  #define   UTIL_PIN_ENABLE	(1 << 31)
>  
>  /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1			0xC8250
> +#define BXT_BLC_PWM_CTL1			_REG(0xC8250)
>  #define   BXT_BLC_PWM_ENABLE			(1 << 31)
>  #define   BXT_BLC_PWM_POLARITY			(1 << 29)
> -#define BXT_BLC_PWM_FREQ1			0xC8254
> -#define BXT_BLC_PWM_DUTY1			0xC8258
> +#define BXT_BLC_PWM_FREQ1			_REG(0xC8254)
> +#define BXT_BLC_PWM_DUTY1			_REG(0xC8258)
>  
> -#define BXT_BLC_PWM_CTL2			0xC8350
> -#define BXT_BLC_PWM_FREQ2			0xC8354
> -#define BXT_BLC_PWM_DUTY2			0xC8358
> +#define BXT_BLC_PWM_CTL2			_REG(0xC8350)
> +#define BXT_BLC_PWM_FREQ2			_REG(0xC8354)
> +#define BXT_BLC_PWM_DUTY2			_REG(0xC8358)
>  
>  
> -#define PCH_GTC_CTL		0xe7000
> +#define PCH_GTC_CTL		_REG(0xe7000)
>  #define   PCH_GTC_ENABLE	(1 << 31)
>  
>  /* TV port control */
> -#define TV_CTL			0x68000
> +#define TV_CTL			_REG(0x68000)
>  /* Enables the TV encoder */
>  # define TV_ENC_ENABLE			(1 << 31)
>  /* Sources the TV encoder input from pipe B instead of A. */
> @@ -3676,7 +3682,7 @@ enum skl_disp_power_wells {
>  # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
>  # define TV_TEST_MODE_MASK		(7 << 0)
>  
> -#define TV_DAC			0x68004
> +#define TV_DAC			_REG(0x68004)
>  # define TV_DAC_SAVE		0x00ffff00
>  /*
>   * Reports that DAC state change logic has reported change (RO).
> @@ -3727,13 +3733,13 @@ enum skl_disp_power_wells {
>   * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
>   * -1 (0x3) being the only legal negative value.
>   */
> -#define TV_CSC_Y		0x68010
> +#define TV_CSC_Y		_REG(0x68010)
>  # define TV_RY_MASK			0x07ff0000
>  # define TV_RY_SHIFT			16
>  # define TV_GY_MASK			0x00000fff
>  # define TV_GY_SHIFT			0
>  
> -#define TV_CSC_Y2		0x68014
> +#define TV_CSC_Y2		_REG(0x68014)
>  # define TV_BY_MASK			0x07ff0000
>  # define TV_BY_SHIFT			16
>  /*
> @@ -3744,13 +3750,13 @@ enum skl_disp_power_wells {
>  # define TV_AY_MASK			0x000003ff
>  # define TV_AY_SHIFT			0
>  
> -#define TV_CSC_U		0x68018
> +#define TV_CSC_U		_REG(0x68018)
>  # define TV_RU_MASK			0x07ff0000
>  # define TV_RU_SHIFT			16
>  # define TV_GU_MASK			0x000007ff
>  # define TV_GU_SHIFT			0
>  
> -#define TV_CSC_U2		0x6801c
> +#define TV_CSC_U2		_REG(0x6801c)
>  # define TV_BU_MASK			0x07ff0000
>  # define TV_BU_SHIFT			16
>  /*
> @@ -3761,13 +3767,13 @@ enum skl_disp_power_wells {
>  # define TV_AU_MASK			0x000003ff
>  # define TV_AU_SHIFT			0
>  
> -#define TV_CSC_V		0x68020
> +#define TV_CSC_V		_REG(0x68020)
>  # define TV_RV_MASK			0x0fff0000
>  # define TV_RV_SHIFT			16
>  # define TV_GV_MASK			0x000007ff
>  # define TV_GV_SHIFT			0
>  
> -#define TV_CSC_V2		0x68024
> +#define TV_CSC_V2		_REG(0x68024)
>  # define TV_BV_MASK			0x07ff0000
>  # define TV_BV_SHIFT			16
>  /*
> @@ -3778,7 +3784,7 @@ enum skl_disp_power_wells {
>  # define TV_AV_MASK			0x000007ff
>  # define TV_AV_SHIFT			0
>  
> -#define TV_CLR_KNOBS		0x68028
> +#define TV_CLR_KNOBS		_REG(0x68028)
>  /* 2s-complement brightness adjustment */
>  # define TV_BRIGHTNESS_MASK		0xff000000
>  # define TV_BRIGHTNESS_SHIFT		24
> @@ -3792,7 +3798,7 @@ enum skl_disp_power_wells {
>  # define TV_HUE_MASK			0x000000ff
>  # define TV_HUE_SHIFT			0
>  
> -#define TV_CLR_LEVEL		0x6802c
> +#define TV_CLR_LEVEL		_REG(0x6802c)
>  /* Controls the DAC level for black */
>  # define TV_BLACK_LEVEL_MASK		0x01ff0000
>  # define TV_BLACK_LEVEL_SHIFT		16
> @@ -3800,7 +3806,7 @@ enum skl_disp_power_wells {
>  # define TV_BLANK_LEVEL_MASK		0x000001ff
>  # define TV_BLANK_LEVEL_SHIFT		0
>  
> -#define TV_H_CTL_1		0x68030
> +#define TV_H_CTL_1		_REG(0x68030)
>  /* Number of pixels in the hsync. */
>  # define TV_HSYNC_END_MASK		0x1fff0000
>  # define TV_HSYNC_END_SHIFT		16
> @@ -3808,7 +3814,7 @@ enum skl_disp_power_wells {
>  # define TV_HTOTAL_MASK			0x00001fff
>  # define TV_HTOTAL_SHIFT		0
>  
> -#define TV_H_CTL_2		0x68034
> +#define TV_H_CTL_2		_REG(0x68034)
>  /* Enables the colorburst (needed for non-component color) */
>  # define TV_BURST_ENA			(1 << 31)
>  /* Offset of the colorburst from the start of hsync, in pixels minus one. */
> @@ -3818,7 +3824,7 @@ enum skl_disp_power_wells {
>  # define TV_HBURST_LEN_SHIFT		0
>  # define TV_HBURST_LEN_MASK		0x0001fff
>  
> -#define TV_H_CTL_3		0x68038
> +#define TV_H_CTL_3		_REG(0x68038)
>  /* End of hblank, measured in pixels minus one from start of hsync */
>  # define TV_HBLANK_END_SHIFT		16
>  # define TV_HBLANK_END_MASK		0x1fff0000
> @@ -3826,7 +3832,7 @@ enum skl_disp_power_wells {
>  # define TV_HBLANK_START_SHIFT		0
>  # define TV_HBLANK_START_MASK		0x0001fff
>  
> -#define TV_V_CTL_1		0x6803c
> +#define TV_V_CTL_1		_REG(0x6803c)
>  /* XXX */
>  # define TV_NBR_END_SHIFT		16
>  # define TV_NBR_END_MASK		0x07ff0000
> @@ -3837,7 +3843,7 @@ enum skl_disp_power_wells {
>  # define TV_VI_END_F2_SHIFT		0
>  # define TV_VI_END_F2_MASK		0x0000003f
>  
> -#define TV_V_CTL_2		0x68040
> +#define TV_V_CTL_2		_REG(0x68040)
>  /* Length of vsync, in half lines */
>  # define TV_VSYNC_LEN_MASK		0x07ff0000
>  # define TV_VSYNC_LEN_SHIFT		16
> @@ -3853,7 +3859,7 @@ enum skl_disp_power_wells {
>  # define TV_VSYNC_START_F2_MASK		0x0000007f
>  # define TV_VSYNC_START_F2_SHIFT	0
>  
> -#define TV_V_CTL_3		0x68044
> +#define TV_V_CTL_3		_REG(0x68044)
>  /* Enables generation of the equalization signal */
>  # define TV_EQUAL_ENA			(1 << 31)
>  /* Length of vsync, in half lines */
> @@ -3871,7 +3877,7 @@ enum skl_disp_power_wells {
>  # define TV_VEQ_START_F2_MASK		0x000007f
>  # define TV_VEQ_START_F2_SHIFT		0
>  
> -#define TV_V_CTL_4		0x68048
> +#define TV_V_CTL_4		_REG(0x68048)
>  /*
>   * Offset to start of vertical colorburst, measured in one less than the
>   * number of lines from vertical start.
> @@ -3885,7 +3891,7 @@ enum skl_disp_power_wells {
>  # define TV_VBURST_END_F1_MASK		0x000000ff
>  # define TV_VBURST_END_F1_SHIFT		0
>  
> -#define TV_V_CTL_5		0x6804c
> +#define TV_V_CTL_5		_REG(0x6804c)
>  /*
>   * Offset to start of vertical colorburst, measured in one less than the
>   * number of lines from vertical start.
> @@ -3899,7 +3905,7 @@ enum skl_disp_power_wells {
>  # define TV_VBURST_END_F2_MASK		0x000000ff
>  # define TV_VBURST_END_F2_SHIFT		0
>  
> -#define TV_V_CTL_6		0x68050
> +#define TV_V_CTL_6		_REG(0x68050)
>  /*
>   * Offset to start of vertical colorburst, measured in one less than the
>   * number of lines from vertical start.
> @@ -3913,7 +3919,7 @@ enum skl_disp_power_wells {
>  # define TV_VBURST_END_F3_MASK		0x000000ff
>  # define TV_VBURST_END_F3_SHIFT		0
>  
> -#define TV_V_CTL_7		0x68054
> +#define TV_V_CTL_7		_REG(0x68054)
>  /*
>   * Offset to start of vertical colorburst, measured in one less than the
>   * number of lines from vertical start.
> @@ -3927,7 +3933,7 @@ enum skl_disp_power_wells {
>  # define TV_VBURST_END_F4_MASK		0x000000ff
>  # define TV_VBURST_END_F4_SHIFT		0
>  
> -#define TV_SC_CTL_1		0x68060
> +#define TV_SC_CTL_1		_REG(0x68060)
>  /* Turns on the first subcarrier phase generation DDA */
>  # define TV_SC_DDA1_EN			(1 << 31)
>  /* Turns on the first subcarrier phase generation DDA */
> @@ -3949,7 +3955,7 @@ enum skl_disp_power_wells {
>  # define TV_SCDDA1_INC_MASK		0x00000fff
>  # define TV_SCDDA1_INC_SHIFT		0
>  
> -#define TV_SC_CTL_2		0x68064
> +#define TV_SC_CTL_2		_REG(0x68064)
>  /* Sets the rollover for the second subcarrier phase generation DDA */
>  # define TV_SCDDA2_SIZE_MASK		0x7fff0000
>  # define TV_SCDDA2_SIZE_SHIFT		16
> @@ -3957,7 +3963,7 @@ enum skl_disp_power_wells {
>  # define TV_SCDDA2_INC_MASK		0x00007fff
>  # define TV_SCDDA2_INC_SHIFT		0
>  
> -#define TV_SC_CTL_3		0x68068
> +#define TV_SC_CTL_3		_REG(0x68068)
>  /* Sets the rollover for the third subcarrier phase generation DDA */
>  # define TV_SCDDA3_SIZE_MASK		0x7fff0000
>  # define TV_SCDDA3_SIZE_SHIFT		16
> @@ -3965,7 +3971,7 @@ enum skl_disp_power_wells {
>  # define TV_SCDDA3_INC_MASK		0x00007fff
>  # define TV_SCDDA3_INC_SHIFT		0
>  
> -#define TV_WIN_POS		0x68070
> +#define TV_WIN_POS		_REG(0x68070)
>  /* X coordinate of the display from the start of horizontal active */
>  # define TV_XPOS_MASK			0x1fff0000
>  # define TV_XPOS_SHIFT			16
> @@ -3973,7 +3979,7 @@ enum skl_disp_power_wells {
>  # define TV_YPOS_MASK			0x00000fff
>  # define TV_YPOS_SHIFT			0
>  
> -#define TV_WIN_SIZE		0x68074
> +#define TV_WIN_SIZE		_REG(0x68074)
>  /* Horizontal size of the display window, measured in pixels*/
>  # define TV_XSIZE_MASK			0x1fff0000
>  # define TV_XSIZE_SHIFT			16
> @@ -3985,7 +3991,7 @@ enum skl_disp_power_wells {
>  # define TV_YSIZE_MASK			0x00000fff
>  # define TV_YSIZE_SHIFT			0
>  
> -#define TV_FILTER_CTL_1		0x68080
> +#define TV_FILTER_CTL_1		_REG(0x68080)
>  /*
>   * Enables automatic scaling calculation.
>   *
> @@ -4018,7 +4024,7 @@ enum skl_disp_power_wells {
>  # define TV_HSCALE_FRAC_MASK		0x00003fff
>  # define TV_HSCALE_FRAC_SHIFT		0
>  
> -#define TV_FILTER_CTL_2		0x68084
> +#define TV_FILTER_CTL_2		_REG(0x68084)
>  /*
>   * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
>   *
> @@ -4034,7 +4040,7 @@ enum skl_disp_power_wells {
>  # define TV_VSCALE_FRAC_MASK		0x00007fff
>  # define TV_VSCALE_FRAC_SHIFT		0
>  
> -#define TV_FILTER_CTL_3		0x68088
> +#define TV_FILTER_CTL_3		_REG(0x68088)
>  /*
>   * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
>   *
> @@ -4054,7 +4060,7 @@ enum skl_disp_power_wells {
>  # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
>  # define TV_VSCALE_IP_FRAC_SHIFT		0
>  
> -#define TV_CC_CONTROL		0x68090
> +#define TV_CC_CONTROL		_REG(0x68090)
>  # define TV_CC_ENABLE			(1 << 31)
>  /*
>   * Specifies which field to send the CC data in.
> @@ -4070,7 +4076,7 @@ enum skl_disp_power_wells {
>  # define TV_CC_LINE_MASK		0x0000003f
>  # define TV_CC_LINE_SHIFT		0
>  
> -#define TV_CC_DATA		0x68094
> +#define TV_CC_DATA		_REG(0x68094)
>  # define TV_CC_RDY			(1 << 31)
>  /* Second word of CC data to be transmitted. */
>  # define TV_CC_DATA_2_MASK		0x007f0000
> @@ -4079,20 +4085,20 @@ enum skl_disp_power_wells {
>  # define TV_CC_DATA_1_MASK		0x0000007f
>  # define TV_CC_DATA_1_SHIFT		0
>  
> -#define TV_H_LUMA(i)		(0x68100 + (i) * 4) /* 60 registers */
> -#define TV_H_CHROMA(i)		(0x68200 + (i) * 4) /* 60 registers */
> -#define TV_V_LUMA(i)		(0x68300 + (i) * 4) /* 43 registers */
> -#define TV_V_CHROMA(i)		(0x68400 + (i) * 4) /* 43 registers */
> +#define TV_H_LUMA(i)		_REG(0x68100 + (i) * 4) /* 60 registers */
> +#define TV_H_CHROMA(i)		_REG(0x68200 + (i) * 4) /* 60 registers */
> +#define TV_V_LUMA(i)		_REG(0x68300 + (i) * 4) /* 43 registers */
> +#define TV_V_CHROMA(i)		_REG(0x68400 + (i) * 4) /* 43 registers */
>  
>  /* Display Port */
> -#define DP_A				0x64000 /* eDP */
> -#define DP_B				0x64100
> -#define DP_C				0x64200
> -#define DP_D				0x64300
> +#define DP_A			_REG(0x64000) /* eDP */
> +#define DP_B			_REG(0x64100)
> +#define DP_C			_REG(0x64200)
> +#define DP_D			_REG(0x64300)
>  
> -#define VLV_DP_B			(VLV_DISPLAY_BASE + DP_B)
> -#define VLV_DP_C			(VLV_DISPLAY_BASE + DP_C)
> -#define CHV_DP_D			(VLV_DISPLAY_BASE + DP_D)
> +#define VLV_DP_B		_REG(VLV_DISPLAY_BASE + 0x64100)
> +#define VLV_DP_C		_REG(VLV_DISPLAY_BASE + 0x64200)
> +#define CHV_DP_D		_REG(VLV_DISPLAY_BASE + 0x64300)
>  
>  #define   DP_PORT_EN			(1 << 31)
>  #define   DP_PIPEB_SELECT		(1 << 30)
> @@ -4207,8 +4213,8 @@ enum skl_disp_power_wells {
>  #define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
>  #define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
>  
> -#define DP_AUX_CH_CTL(port)	_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> -#define DP_AUX_CH_DATA(port, i)	(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> +#define DP_AUX_CH_CTL(port)	_REG_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> +#define DP_AUX_CH_DATA(port, i)	_REG(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
>  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
> @@ -4285,10 +4291,10 @@ enum skl_disp_power_wells {
>  #define _PIPEB_LINK_N_G4X	0x71064
>  #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
>  
> -#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
> -#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
> -#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
> -#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
> +#define PIPE_DATA_M_G4X(pipe) _REG_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
> +#define PIPE_DATA_N_G4X(pipe) _REG_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
> +#define PIPE_LINK_M_G4X(pipe) _REG_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
> +#define PIPE_LINK_N_G4X(pipe) _REG_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
>  
>  /* Display & cursor control */
>  
> @@ -4404,15 +4410,15 @@ enum skl_disp_power_wells {
>   */
>  #define PIPE_EDP_OFFSET	0x7f000
>  
> -#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
> +#define _REG_PIPE2(pipe, reg) _REG(dev_priv->info.pipe_offsets[pipe] - \
>  	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
>  	dev_priv->info.display_mmio_offset)
>  
> -#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
> -#define PIPEDSL(pipe)  _PIPE2(pipe, _PIPEADSL)
> -#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
> -#define PIPEFRAMEPIXEL(pipe)  _PIPE2(pipe, _PIPEAFRAMEPIXEL)
> -#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
> +#define PIPECONF(pipe)		_REG_PIPE2(pipe, _PIPEACONF)
> +#define PIPEDSL(pipe)		_REG_PIPE2(pipe, _PIPEADSL)
> +#define PIPEFRAME(pipe)		_REG_PIPE2(pipe, _PIPEAFRAMEHIGH)
> +#define PIPEFRAMEPIXEL(pipe)	_REG_PIPE2(pipe, _PIPEAFRAMEPIXEL)
> +#define PIPESTAT(pipe)		_REG_PIPE2(pipe, _PIPEASTAT)
>  
>  #define _PIPE_MISC_A			0x70030
>  #define _PIPE_MISC_B			0x71030
> @@ -4424,9 +4430,9 @@ enum skl_disp_power_wells {
>  #define   PIPEMISC_DITHER_ENABLE	(1<<4)
>  #define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)
>  #define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
> -#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
> +#define PIPEMISC(pipe)			_REG_PIPE2(pipe, _PIPE_MISC_A)
>  
> -#define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
> +#define VLV_DPFLIPSTAT				_REG(VLV_DISPLAY_BASE + 0x70028)
>  #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
>  #define   PIPEB_HLINE_INT_EN			(1<<28)
>  #define   PIPEB_VBLANK_INT_EN			(1<<27)
> @@ -4447,7 +4453,7 @@ enum skl_disp_power_wells {
>  #define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
>  #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
>  
> -#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
> +#define DPINVGTT				_REG(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>  #define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
>  #define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
>  #define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
> @@ -4477,7 +4483,7 @@ enum skl_disp_power_wells {
>  #define   DPINVGTT_STATUS_MASK			0xff
>  #define   DPINVGTT_STATUS_MASK_CHV		0xfff
>  
> -#define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
> +#define DSPARB			_REG(dev_priv->info.display_mmio_offset + 0x70030)
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
>  #define   DSPARB_BSTART_MASK	(0x7f)
> @@ -4492,7 +4498,7 @@ enum skl_disp_power_wells {
>  #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
>  #define   DSPARB_SPRITED_SHIFT_VLV	24
>  #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
> -#define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
> +#define DSPARB2				_REG(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
>  #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
>  #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
>  #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
> @@ -4505,14 +4511,14 @@ enum skl_disp_power_wells {
>  #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
>  #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
>  #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
> -#define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
> +#define DSPARB3				_REG(VLV_DISPLAY_BASE + 0x7006c) /* chv */
>  #define   DSPARB_SPRITEE_SHIFT_VLV	0
>  #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
>  #define   DSPARB_SPRITEF_SHIFT_VLV	8
>  #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
>  
>  /* pnv/gen4/g4x/vlv/chv */
> -#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
> +#define DSPFW1		_REG(dev_priv->info.display_mmio_offset + 0x70034)
>  #define   DSPFW_SR_SHIFT		23
>  #define   DSPFW_SR_MASK			(0x1ff<<23)
>  #define   DSPFW_CURSORB_SHIFT		16
> @@ -4523,7 +4529,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_PLANEA_SHIFT		0
>  #define   DSPFW_PLANEA_MASK		(0x7f<<0)
>  #define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
> -#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
> +#define DSPFW2		_REG(dev_priv->info.display_mmio_offset + 0x70038)
>  #define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
>  #define   DSPFW_FBC_SR_SHIFT		28
>  #define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
> @@ -4539,7 +4545,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_SPRITEA_SHIFT		0
>  #define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
>  #define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
> -#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
> +#define DSPFW3		_REG(dev_priv->info.display_mmio_offset + 0x7003c)
>  #define   DSPFW_HPLL_SR_EN		(1<<31)
>  #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
>  #define   DSPFW_CURSOR_SR_SHIFT		24
> @@ -4550,14 +4556,14 @@ enum skl_disp_power_wells {
>  #define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
>  
>  /* vlv/chv */
> -#define DSPFW4			(VLV_DISPLAY_BASE + 0x70070)
> +#define DSPFW4		_REG(VLV_DISPLAY_BASE + 0x70070)
>  #define   DSPFW_SPRITEB_WM1_SHIFT	16
>  #define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
>  #define   DSPFW_CURSORA_WM1_SHIFT	8
>  #define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
>  #define   DSPFW_SPRITEA_WM1_SHIFT	0
>  #define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
> -#define DSPFW5			(VLV_DISPLAY_BASE + 0x70074)
> +#define DSPFW5		_REG(VLV_DISPLAY_BASE + 0x70074)
>  #define   DSPFW_PLANEB_WM1_SHIFT	24
>  #define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
>  #define   DSPFW_PLANEA_WM1_SHIFT	16
> @@ -4566,11 +4572,11 @@ enum skl_disp_power_wells {
>  #define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
>  #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
>  #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
> -#define DSPFW6			(VLV_DISPLAY_BASE + 0x70078)
> +#define DSPFW6		_REG(VLV_DISPLAY_BASE + 0x70078)
>  #define   DSPFW_SR_WM1_SHIFT		0
>  #define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
> -#define DSPFW7			(VLV_DISPLAY_BASE + 0x7007c)
> -#define DSPFW7_CHV		(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
> +#define DSPFW7		_REG(VLV_DISPLAY_BASE + 0x7007c)
> +#define DSPFW7_CHV	_REG(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
>  #define   DSPFW_SPRITED_WM1_SHIFT	24
>  #define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
>  #define   DSPFW_SPRITED_SHIFT		16
> @@ -4579,7 +4585,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
>  #define   DSPFW_SPRITEC_SHIFT		0
>  #define   DSPFW_SPRITEC_MASK_VLV	(0xff<<0)
> -#define DSPFW8_CHV		(VLV_DISPLAY_BASE + 0x700b8)
> +#define DSPFW8_CHV	_REG(VLV_DISPLAY_BASE + 0x700b8)
>  #define   DSPFW_SPRITEF_WM1_SHIFT	24
>  #define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
>  #define   DSPFW_SPRITEF_SHIFT		16
> @@ -4588,7 +4594,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
>  #define   DSPFW_SPRITEE_SHIFT		0
>  #define   DSPFW_SPRITEE_MASK_VLV	(0xff<<0)
> -#define DSPFW9_CHV		(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
> +#define DSPFW9_CHV	_REG(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
>  #define   DSPFW_PLANEC_WM1_SHIFT	24
>  #define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
>  #define   DSPFW_PLANEC_SHIFT		16
> @@ -4599,7 +4605,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_CURSORC_MASK		(0x3f<<0)
>  
>  /* vlv/chv high order bits */
> -#define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
> +#define DSPHOWM		_REG(VLV_DISPLAY_BASE + 0x70064)
>  #define   DSPFW_SR_HI_SHIFT		24
>  #define   DSPFW_SR_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
>  #define   DSPFW_SPRITEF_HI_SHIFT	23
> @@ -4620,7 +4626,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_SPRITEA_HI_MASK		(1<<4)
>  #define   DSPFW_PLANEA_HI_SHIFT		0
>  #define   DSPFW_PLANEA_HI_MASK		(1<<0)
> -#define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70068)
> +#define DSPHOWM1	_REG(VLV_DISPLAY_BASE + 0x70068)
>  #define   DSPFW_SR_WM1_HI_SHIFT		24
>  #define   DSPFW_SR_WM1_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
>  #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
> @@ -4643,7 +4649,7 @@ enum skl_disp_power_wells {
>  #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
>  
>  /* drain latency register values*/
> -#define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
> +#define VLV_DDL(pipe)			_REG(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
>  #define DDL_CURSOR_SHIFT		24
>  #define DDL_SPRITE_SHIFT(sprite)	(8+8*(sprite))
>  #define DDL_PLANE_SHIFT			0
> @@ -4651,7 +4657,7 @@ enum skl_disp_power_wells {
>  #define DDL_PRECISION_LOW		(0<<7)
>  #define DRAIN_LATENCY_MASK		0x7f
>  
> -#define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
> +#define CBR1_VLV			_REG(VLV_DISPLAY_BASE + 0x70400)
>  #define  CBR_PND_DEADLINE_DISABLE	(1<<31)
>  #define  CBR_PWM_CLOCK_MUX_SELECT	(1<<30)
>  
> @@ -4707,33 +4713,33 @@ enum skl_disp_power_wells {
>  #define   PLANE_WM_BLOCKS_MASK	0x3ff
>  
>  #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> -#define CUR_WM(pipe, level) (_CUR_WM_0(pipe) + ((4) * (level)))
> -#define CUR_WM_TRANS(pipe) _PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
> +#define CUR_WM(pipe, level) _REG(_CUR_WM_0(pipe) + ((4) * (level)))
> +#define CUR_WM_TRANS(pipe) _REG_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
>  
>  #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
>  #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
>  #define _PLANE_WM_BASE(pipe, plane)	\
>  			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
>  #define PLANE_WM(pipe, plane, level)	\
> -			(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> +			_REG(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
>  #define _PLANE_WM_TRANS_1(pipe)	\
>  			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
>  #define _PLANE_WM_TRANS_2(pipe)	\
>  			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
>  #define PLANE_WM_TRANS(pipe, plane)	\
> -		_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
> +	_REG(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
>  
>  /* define the Watermark register on Ironlake */
> -#define WM0_PIPEA_ILK		0x45100
> +#define WM0_PIPEA_ILK		_REG(0x45100)
>  #define  WM0_PIPE_PLANE_MASK	(0xffff<<16)
>  #define  WM0_PIPE_PLANE_SHIFT	16
>  #define  WM0_PIPE_SPRITE_MASK	(0xff<<8)
>  #define  WM0_PIPE_SPRITE_SHIFT	8
>  #define  WM0_PIPE_CURSOR_MASK	(0xff)
>  
> -#define WM0_PIPEB_ILK		0x45104
> -#define WM0_PIPEC_IVB		0x45200
> -#define WM1_LP_ILK		0x45108
> +#define WM0_PIPEB_ILK		_REG(0x45104)
> +#define WM0_PIPEC_IVB		_REG(0x45200)
> +#define WM1_LP_ILK		_REG(0x45108)
>  #define  WM1_LP_SR_EN		(1<<31)
>  #define  WM1_LP_LATENCY_SHIFT	24
>  #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
> @@ -4743,13 +4749,13 @@ enum skl_disp_power_wells {
>  #define  WM1_LP_SR_MASK		(0x7ff<<8)
>  #define  WM1_LP_SR_SHIFT	8
>  #define  WM1_LP_CURSOR_MASK	(0xff)
> -#define WM2_LP_ILK		0x4510c
> +#define WM2_LP_ILK		_REG(0x4510c)
>  #define  WM2_LP_EN		(1<<31)
> -#define WM3_LP_ILK		0x45110
> +#define WM3_LP_ILK		_REG(0x45110)
>  #define  WM3_LP_EN		(1<<31)
> -#define WM1S_LP_ILK		0x45120
> -#define WM2S_LP_IVB		0x45124
> -#define WM3S_LP_IVB		0x45128
> +#define WM1S_LP_ILK		_REG(0x45120)
> +#define WM2S_LP_IVB		_REG(0x45124)
> +#define WM3S_LP_IVB		_REG(0x45128)
>  #define  WM1S_LP_EN		(1<<31)
>  
>  #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
> @@ -4757,7 +4763,7 @@ enum skl_disp_power_wells {
>  	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
>  
>  /* Memory latency timer register */
> -#define MLTR_ILK		0x11222
> +#define MLTR_ILK		_REG(0x11222)
>  #define  MLTR_WM1_SHIFT		0
>  #define  MLTR_WM2_SHIFT		8
>  /* the unit of memory self-refresh latency time is 0.5us */
> @@ -4765,7 +4771,7 @@ enum skl_disp_power_wells {
>  
>  
>  /* the address where we get all kinds of latency value */
> -#define SSKPD			0x5d10
> +#define SSKPD			_REG(0x5d10)
>  #define SSKPD_WM_MASK		0x3f
>  #define SSKPD_WM0_SHIFT		0
>  #define SSKPD_WM1_SHIFT		8
> @@ -4798,8 +4804,8 @@ enum skl_disp_power_wells {
>  /* GM45+ just has to be different */
>  #define _PIPEA_FRMCOUNT_G4X	0x70040
>  #define _PIPEA_FLIPCOUNT_G4X	0x70044
> -#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
> -#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
> +#define PIPE_FRMCOUNT_G4X(pipe) _REG_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
> +#define PIPE_FLIPCOUNT_G4X(pipe) _REG_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
>  
>  /* Cursor A & B regs */
>  #define _CURACNTR		0x70080
> @@ -4837,7 +4843,7 @@ enum skl_disp_power_wells {
>  #define   CURSOR_POS_SIGN       0x8000
>  #define   CURSOR_X_SHIFT        0
>  #define   CURSOR_Y_SHIFT        16
> -#define CURSIZE			0x700a0
> +#define CURSIZE			_REG(0x700a0)
>  #define _CURBCNTR		0x700c0
>  #define _CURBBASE		0x700c4
>  #define _CURBPOS		0x700c8
> @@ -4846,7 +4852,7 @@ enum skl_disp_power_wells {
>  #define _CURBBASE_IVB		0x71084
>  #define _CURBPOS_IVB		0x71088
>  
> -#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
> +#define _CURSOR2(pipe, reg) _REG(dev_priv->info.cursor_offsets[(pipe)] - \
>  	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
>  	dev_priv->info.display_mmio_offset)
>  
> @@ -4907,16 +4913,16 @@ enum skl_disp_power_wells {
>  #define _DSPAOFFSET				0x701A4 /* HSW */
>  #define _DSPASURFLIVE				0x701AC
>  
> -#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
> -#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
> -#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
> -#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
> -#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
> -#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
> -#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
> -#define DSPLINOFF(plane) DSPADDR(plane)
> -#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
> -#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
> +#define DSPCNTR(plane)		_REG_PIPE2(plane, _DSPACNTR)
> +#define DSPADDR(plane)		_REG_PIPE2(plane, _DSPAADDR)
> +#define DSPSTRIDE(plane)	_REG_PIPE2(plane, _DSPASTRIDE)
> +#define DSPPOS(plane)		_REG_PIPE2(plane, _DSPAPOS)
> +#define DSPSIZE(plane)		_REG_PIPE2(plane, _DSPASIZE)
> +#define DSPSURF(plane)		_REG_PIPE2(plane, _DSPASURF)
> +#define DSPTILEOFF(plane)	_REG_PIPE2(plane, _DSPATILEOFF)
> +#define DSPLINOFF(plane)	DSPADDR(plane)
> +#define DSPOFFSET(plane)	_REG_PIPE2(plane, _DSPAOFFSET)
> +#define DSPSURFLIVE(plane)	_REG_PIPE2(plane, _DSPASURFLIVE)
>  
>  /* CHV pipe B blender and primary plane */
>  #define _CHV_BLEND_A		0x60a00
> @@ -4930,11 +4936,11 @@ enum skl_disp_power_wells {
>  #define _PRIMCNSTALPHA_A	0x60a10
>  #define   PRIM_CONST_ALPHA_ENABLE	(1<<31)
>  
> -#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
> -#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
> -#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
> -#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
> -#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
> +#define CHV_BLEND(pipe)		_REG_TRANS2(pipe, _CHV_BLEND_A)
> +#define CHV_CANVAS(pipe)	_REG_TRANS2(pipe, _CHV_CANVAS_A)
> +#define PRIMPOS(plane)		_REG_TRANS2(plane, _PRIMPOS_A)
> +#define PRIMSIZE(plane)		_REG_TRANS2(plane, _PRIMSIZE_A)
> +#define PRIMCNSTALPHA(plane)	_REG_TRANS2(plane, _PRIMCNSTALPHA_A)
>  
>  /* Display/Sprite base address macros */
>  #define DISP_BASEADDR_MASK	(0xfffff000)
> @@ -4952,9 +4958,9 @@ enum skl_disp_power_wells {
>   * [10:1f] all
>   * [30:32] all
>   */
> -#define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> -#define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> -#define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
> +#define SWF0(i)	_REG(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> +#define SWF1(i)	_REG(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> +#define SWF3(i)	_REG(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
>  
>  /* Pipe B */
>  #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
> @@ -5036,18 +5042,18 @@ enum skl_disp_power_wells {
>  #define _DVSBSCALE		0x73204
>  #define _DVSBGAMC		0x73300
>  
> -#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> -#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
> -#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
> -#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
> -#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
> -#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
> -#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
> -#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
> -#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
> -#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> -#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> -#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
> +#define DVSCNTR(pipe) _REG_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> +#define DVSLINOFF(pipe) _REG_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
> +#define DVSSTRIDE(pipe) _REG_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
> +#define DVSPOS(pipe) _REG_PIPE(pipe, _DVSAPOS, _DVSBPOS)
> +#define DVSSURF(pipe) _REG_PIPE(pipe, _DVSASURF, _DVSBSURF)
> +#define DVSKEYMAX(pipe) _REG_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
> +#define DVSSIZE(pipe) _REG_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
> +#define DVSSCALE(pipe) _REG_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
> +#define DVSTILEOFF(pipe) _REG_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
> +#define DVSKEYVAL(pipe) _REG_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> +#define DVSKEYMSK(pipe) _REG_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> +#define DVSSURFLIVE(pipe) _REG_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
>  
>  #define _SPRA_CTL		0x70280
>  #define   SPRITE_ENABLE			(1<<31)
> @@ -5110,20 +5116,20 @@ enum skl_disp_power_wells {
>  #define _SPRB_SCALE		0x71304
>  #define _SPRB_GAMC		0x71400
>  
> -#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> -#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
> -#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
> -#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
> -#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
> -#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
> -#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
> -#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> -#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> -#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> -#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> -#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> -#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> -#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> +#define SPRCTL(pipe) _REG_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> +#define SPRLINOFF(pipe) _REG_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
> +#define SPRSTRIDE(pipe) _REG_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
> +#define SPRPOS(pipe) _REG_PIPE(pipe, _SPRA_POS, _SPRB_POS)
> +#define SPRSIZE(pipe) _REG_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
> +#define SPRKEYVAL(pipe) _REG_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
> +#define SPRKEYMSK(pipe) _REG_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
> +#define SPRSURF(pipe) _REG_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> +#define SPRKEYMAX(pipe) _REG_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> +#define SPRTILEOFF(pipe) _REG_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> +#define SPROFFSET(pipe) _REG_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> +#define SPRSCALE(pipe) _REG_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> +#define SPRGAMC(pipe) _REG_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> +#define SPRSURFLIVE(pipe) _REG_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>  
>  #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
>  #define   SP_ENABLE			(1<<31)
> @@ -5173,18 +5179,18 @@ enum skl_disp_power_wells {
>  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
>  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
>  
> -#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
> -#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
> +#define SPCNTR(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane) _REG_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
>  
>  /*
>   * CHV pipe B sprite CSC
> @@ -5193,29 +5199,29 @@ enum skl_disp_power_wells {
>   * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
>   * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
>   */
> -#define SPCSCYGOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
> -#define SPCSCCBOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
> -#define SPCSCCROFF(sprite)	(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
> +#define SPCSCYGOFF(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
> +#define SPCSCCBOFF(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
> +#define SPCSCCROFF(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
>  #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
>  #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
>  
> -#define SPCSCC01(sprite)	(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
> -#define SPCSCC23(sprite)	(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
> -#define SPCSCC45(sprite)	(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
> -#define SPCSCC67(sprite)	(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
> -#define SPCSCC8(sprite)		(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
> +#define SPCSCC01(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
> +#define SPCSCC23(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
> +#define SPCSCC45(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
> +#define SPCSCC67(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
> +#define SPCSCC8(sprite)		_REG(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
>  #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
>  #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
>  
> -#define SPCSCYGICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
> -#define SPCSCCBICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
> -#define SPCSCCRICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
> +#define SPCSCYGICLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
> +#define SPCSCCBICLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
> +#define SPCSCCRICLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
>  #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
>  #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
>  
> -#define SPCSCYGOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
> -#define SPCSCCBOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
> -#define SPCSCCROCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
> +#define SPCSCYGOCLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
> +#define SPCSCCBOCLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
> +#define SPCSCCROCLAMP(sprite)	_REG(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
>  #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
>  #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
>  
> @@ -5296,7 +5302,7 @@ enum skl_disp_power_wells {
>  #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
>  #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
>  #define PLANE_CTL(pipe, plane)	\
> -	_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> +	_REG_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
>  
>  #define _PLANE_STRIDE_1_B			0x71188
>  #define _PLANE_STRIDE_2_B			0x71288
> @@ -5308,7 +5314,7 @@ enum skl_disp_power_wells {
>  #define _PLANE_STRIDE_3(pipe)	\
>  	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
>  #define PLANE_STRIDE(pipe, plane)	\
> -	_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> +	_REG_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
>  
>  #define _PLANE_POS_1_B				0x7118c
>  #define _PLANE_POS_2_B				0x7128c
> @@ -5317,7 +5323,7 @@ enum skl_disp_power_wells {
>  #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
>  #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
>  #define PLANE_POS(pipe, plane)	\
> -	_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> +	_REG_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
>  
>  #define _PLANE_SIZE_1_B				0x71190
>  #define _PLANE_SIZE_2_B				0x71290
> @@ -5326,7 +5332,7 @@ enum skl_disp_power_wells {
>  #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
>  #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
>  #define PLANE_SIZE(pipe, plane)	\
> -	_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> +	_REG_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
>  
>  #define _PLANE_SURF_1_B				0x7119c
>  #define _PLANE_SURF_2_B				0x7129c
> @@ -5335,35 +5341,35 @@ enum skl_disp_power_wells {
>  #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
>  #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
>  #define PLANE_SURF(pipe, plane)	\
> -	_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +	_REG_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
>  
>  #define _PLANE_OFFSET_1_B			0x711a4
>  #define _PLANE_OFFSET_2_B			0x712a4
>  #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
>  #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
>  #define PLANE_OFFSET(pipe, plane)	\
> -	_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> +	_REG_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
>  
>  #define _PLANE_KEYVAL_1_B			0x71194
>  #define _PLANE_KEYVAL_2_B			0x71294
>  #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
>  #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
>  #define PLANE_KEYVAL(pipe, plane)	\
> -	_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> +	_REG_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
>  
>  #define _PLANE_KEYMSK_1_B			0x71198
>  #define _PLANE_KEYMSK_2_B			0x71298
>  #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
>  #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
>  #define PLANE_KEYMSK(pipe, plane)	\
> -	_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> +	_REG_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
>  
>  #define _PLANE_KEYMAX_1_B			0x711a0
>  #define _PLANE_KEYMAX_2_B			0x712a0
>  #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
>  #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
>  #define PLANE_KEYMAX(pipe, plane)	\
> -	_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> +	_REG_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
>  
>  #define _PLANE_BUF_CFG_1_B			0x7127c
>  #define _PLANE_BUF_CFG_2_B			0x7137c
> @@ -5372,7 +5378,7 @@ enum skl_disp_power_wells {
>  #define _PLANE_BUF_CFG_2(pipe)	\
>  	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
>  #define PLANE_BUF_CFG(pipe, plane)	\
> -	_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> +	_REG_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
>  
>  #define _PLANE_NV12_BUF_CFG_1_B		0x71278
>  #define _PLANE_NV12_BUF_CFG_2_B		0x71378
> @@ -5381,26 +5387,26 @@ enum skl_disp_power_wells {
>  #define _PLANE_NV12_BUF_CFG_2(pipe)	\
>  	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
>  #define PLANE_NV12_BUF_CFG(pipe, plane)	\
> -	_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +	_REG_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
>  
>  /* SKL new cursor registers */
>  #define _CUR_BUF_CFG_A				0x7017c
>  #define _CUR_BUF_CFG_B				0x7117c
> -#define CUR_BUF_CFG(pipe)	_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> +#define CUR_BUF_CFG(pipe)	_REG_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
>  
>  /* VBIOS regs */
> -#define VGACNTRL		0x71400
> +#define VGACNTRL		_REG(0x71400)
>  # define VGA_DISP_DISABLE			(1 << 31)
>  # define VGA_2X_MODE				(1 << 30)
>  # define VGA_PIPE_B_SELECT			(1 << 29)
>  
> -#define VLV_VGACNTRL		(VLV_DISPLAY_BASE + 0x71400)
> +#define VLV_VGACNTRL		_REG(VLV_DISPLAY_BASE + 0x71400)
>  
>  /* Ironlake */
>  
> -#define CPU_VGACNTRL	0x41000
> +#define CPU_VGACNTRL	_REG(0x41000)
>  
> -#define DIGITAL_PORT_HOTPLUG_CNTRL	0x44030
> +#define DIGITAL_PORT_HOTPLUG_CNTRL	_REG(0x44030)
>  #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
>  #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
>  #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
> @@ -5413,26 +5419,26 @@ enum skl_disp_power_wells {
>  #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
>  
>  /* refresh rate hardware control */
> -#define RR_HW_CTL       0x45300
> +#define RR_HW_CTL       _REG(0x45300)
>  #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
>  #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
>  
> -#define FDI_PLL_BIOS_0  0x46000
> +#define FDI_PLL_BIOS_0  _REG(0x46000)
>  #define  FDI_PLL_FB_CLOCK_MASK  0xff
> -#define FDI_PLL_BIOS_1  0x46004
> -#define FDI_PLL_BIOS_2  0x46008
> -#define DISPLAY_PORT_PLL_BIOS_0         0x4600c
> -#define DISPLAY_PORT_PLL_BIOS_1         0x46010
> -#define DISPLAY_PORT_PLL_BIOS_2         0x46014
> +#define FDI_PLL_BIOS_1  _REG(0x46004)
> +#define FDI_PLL_BIOS_2  _REG(0x46008)
> +#define DISPLAY_PORT_PLL_BIOS_0         _REG(0x4600c)
> +#define DISPLAY_PORT_PLL_BIOS_1         _REG(0x46010)
> +#define DISPLAY_PORT_PLL_BIOS_2         _REG(0x46014)
>  
> -#define PCH_3DCGDIS0		0x46020
> +#define PCH_3DCGDIS0		_REG(0x46020)
>  # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
>  # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
>  
> -#define PCH_3DCGDIS1		0x46024
> +#define PCH_3DCGDIS1		_REG(0x46024)
>  # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>  
> -#define FDI_PLL_FREQ_CTL        0x46030
> +#define FDI_PLL_FREQ_CTL        _REG(0x46030)
>  #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
>  #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
>  #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
> @@ -5469,14 +5475,14 @@ enum skl_disp_power_wells {
>  #define _PIPEB_LINK_M2		0x61048
>  #define _PIPEB_LINK_N2		0x6104c
>  
> -#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
> -#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
> -#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
> -#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
> -#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
> -#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
> -#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
> -#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
> +#define PIPE_DATA_M1(tran) _REG_TRANS2(tran, _PIPEA_DATA_M1)
> +#define PIPE_DATA_N1(tran) _REG_TRANS2(tran, _PIPEA_DATA_N1)
> +#define PIPE_DATA_M2(tran) _REG_TRANS2(tran, _PIPEA_DATA_M2)
> +#define PIPE_DATA_N2(tran) _REG_TRANS2(tran, _PIPEA_DATA_N2)
> +#define PIPE_LINK_M1(tran) _REG_TRANS2(tran, _PIPEA_LINK_M1)
> +#define PIPE_LINK_N1(tran) _REG_TRANS2(tran, _PIPEA_LINK_N1)
> +#define PIPE_LINK_M2(tran) _REG_TRANS2(tran, _PIPEA_LINK_M2)
> +#define PIPE_LINK_N2(tran) _REG_TRANS2(tran, _PIPEA_LINK_N2)
>  
>  /* CPU panel fitter */
>  /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> @@ -5499,11 +5505,11 @@ enum skl_disp_power_wells {
>  #define _PFA_HSCALE		0x68090
>  #define _PFB_HSCALE		0x68890
>  
> -#define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
> -#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
> -#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
> -#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
> -#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
> +#define PF_CTL(pipe)		_REG_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
> +#define PF_WIN_SZ(pipe)		_REG_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
> +#define PF_WIN_POS(pipe)	_REG_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
> +#define PF_VSCALE(pipe)		_REG_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
> +#define PF_HSCALE(pipe)		_REG_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
>  
>  #define _PSA_CTL		0x68180
>  #define _PSB_CTL		0x68980
> @@ -5513,9 +5519,9 @@ enum skl_disp_power_wells {
>  #define _PSA_WIN_POS		0x68170
>  #define _PSB_WIN_POS		0x68970
>  
> -#define PS_CTL(pipe)		_PIPE(pipe, _PSA_CTL, _PSB_CTL)
> -#define PS_WIN_SZ(pipe)		_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
> -#define PS_WIN_POS(pipe)	_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
> +#define PS_CTL(pipe)		_REG_PIPE(pipe, _PSA_CTL, _PSB_CTL)
> +#define PS_WIN_SZ(pipe)		_REG_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
> +#define PS_WIN_POS(pipe)	_REG_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
>  
>  /*
>   * Skylake scalers
> @@ -5604,42 +5610,42 @@ enum skl_disp_power_wells {
>  #define _PS_ECC_STAT_1C     0x691D0
>  
>  #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
> -#define SKL_PS_CTRL(pipe, id) _PIPE(pipe,        \
> +#define SKL_PS_CTRL(pipe, id) _REG_PIPE(pipe,        \
>  			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
>  			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
> -#define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe,    \
> +#define SKL_PS_PWR_GATE(pipe, id) _REG_PIPE(pipe,    \
>  			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
>  			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
> -#define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe,     \
> +#define SKL_PS_WIN_POS(pipe, id) _REG_PIPE(pipe,     \
>  			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
>  			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
> -#define SKL_PS_WIN_SZ(pipe, id)  _PIPE(pipe,     \
> +#define SKL_PS_WIN_SZ(pipe, id)  _REG_PIPE(pipe,     \
>  			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
>  			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
> -#define SKL_PS_VSCALE(pipe, id)  _PIPE(pipe,     \
> +#define SKL_PS_VSCALE(pipe, id)  _REG_PIPE(pipe,     \
>  			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
>  			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
> -#define SKL_PS_HSCALE(pipe, id)  _PIPE(pipe,     \
> +#define SKL_PS_HSCALE(pipe, id)  _REG_PIPE(pipe,     \
>  			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
>  			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
> -#define SKL_PS_VPHASE(pipe, id)  _PIPE(pipe,     \
> +#define SKL_PS_VPHASE(pipe, id)  _REG_PIPE(pipe,     \
>  			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
>  			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
> -#define SKL_PS_HPHASE(pipe, id)  _PIPE(pipe,     \
> +#define SKL_PS_HPHASE(pipe, id)  _REG_PIPE(pipe,     \
>  			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
>  			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
> -#define SKL_PS_ECC_STAT(pipe, id)  _PIPE(pipe,     \
> +#define SKL_PS_ECC_STAT(pipe, id)  _REG_PIPE(pipe,     \
>  			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
>  			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
>  
>  /* legacy palette */
>  #define _LGC_PALETTE_A           0x4a000
>  #define _LGC_PALETTE_B           0x4a800
> -#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
> +#define LGC_PALETTE(pipe, i) _REG(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
>  
>  #define _GAMMA_MODE_A		0x4a480
>  #define _GAMMA_MODE_B		0x4ac80
> -#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> +#define GAMMA_MODE(pipe) _REG_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
>  #define GAMMA_MODE_MODE_MASK	(3 << 0)
>  #define GAMMA_MODE_MODE_8BIT	(0 << 0)
>  #define GAMMA_MODE_MODE_10BIT	(1 << 0)
> @@ -5697,20 +5703,20 @@ enum skl_disp_power_wells {
>  #define DE_PIPEA_VBLANK_IVB		(1<<0)
>  #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
>  
> -#define VLV_MASTER_IER			0x4400c /* Gunit master IER */
> +#define VLV_MASTER_IER			_REG(0x4400c) /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1<<31)
>  
> -#define DEISR   0x44000
> -#define DEIMR   0x44004
> -#define DEIIR   0x44008
> -#define DEIER   0x4400c
> +#define DEISR   _REG(0x44000)
> +#define DEIMR   _REG(0x44004)
> +#define DEIIR   _REG(0x44008)
> +#define DEIER   _REG(0x4400c)
>  
> -#define GTISR   0x44010
> -#define GTIMR   0x44014
> -#define GTIIR   0x44018
> -#define GTIER   0x4401c
> +#define GTISR   _REG(0x44010)
> +#define GTIMR   _REG(0x44014)
> +#define GTIIR   _REG(0x44018)
> +#define GTIER   _REG(0x4401c)
>  
> -#define GEN8_MASTER_IRQ			0x44200
> +#define GEN8_MASTER_IRQ			_REG(0x44200)
>  #define  GEN8_MASTER_IRQ_CONTROL	(1<<31)
>  #define  GEN8_PCU_IRQ			(1<<30)
>  #define  GEN8_DE_PCH_IRQ		(1<<23)
> @@ -5727,10 +5733,10 @@ enum skl_disp_power_wells {
>  #define  GEN8_GT_BCS_IRQ		(1<<1)
>  #define  GEN8_GT_RCS_IRQ		(1<<0)
>  
> -#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
> -#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
> -#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
> -#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
> +#define GEN8_GT_ISR(which) _REG(0x44300 + (0x10 * (which)))
> +#define GEN8_GT_IMR(which) _REG(0x44304 + (0x10 * (which)))
> +#define GEN8_GT_IIR(which) _REG(0x44308 + (0x10 * (which)))
> +#define GEN8_GT_IER(which) _REG(0x4430c + (0x10 * (which)))
>  
>  #define GEN8_RCS_IRQ_SHIFT 0
>  #define GEN8_BCS_IRQ_SHIFT 16
> @@ -5739,10 +5745,10 @@ enum skl_disp_power_wells {
>  #define GEN8_VECS_IRQ_SHIFT 0
>  #define GEN8_WD_IRQ_SHIFT 16
>  
> -#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
> -#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
> -#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
> -#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_ISR(pipe) _REG(0x44400 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IMR(pipe) _REG(0x44404 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IIR(pipe) _REG(0x44408 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IER(pipe) _REG(0x4440c + (0x10 * (pipe)))
>  #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
>  #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
>  #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
> @@ -5775,10 +5781,10 @@ enum skl_disp_power_wells {
>  	 GEN9_PIPE_PLANE2_FAULT | \
>  	 GEN9_PIPE_PLANE1_FAULT)
>  
> -#define GEN8_DE_PORT_ISR 0x44440
> -#define GEN8_DE_PORT_IMR 0x44444
> -#define GEN8_DE_PORT_IIR 0x44448
> -#define GEN8_DE_PORT_IER 0x4444c
> +#define GEN8_DE_PORT_ISR _REG(0x44440)
> +#define GEN8_DE_PORT_IMR _REG(0x44444)
> +#define GEN8_DE_PORT_IIR _REG(0x44448)
> +#define GEN8_DE_PORT_IER _REG(0x4444c)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> @@ -5792,23 +5798,23 @@ enum skl_disp_power_wells {
>  #define  BXT_DE_PORT_GMBUS		(1 << 1)
>  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
>  
> -#define GEN8_DE_MISC_ISR 0x44460
> -#define GEN8_DE_MISC_IMR 0x44464
> -#define GEN8_DE_MISC_IIR 0x44468
> -#define GEN8_DE_MISC_IER 0x4446c
> +#define GEN8_DE_MISC_ISR _REG(0x44460)
> +#define GEN8_DE_MISC_IMR _REG(0x44464)
> +#define GEN8_DE_MISC_IIR _REG(0x44468)
> +#define GEN8_DE_MISC_IER _REG(0x4446c)
>  #define  GEN8_DE_MISC_GSE		(1 << 27)
>  
> -#define GEN8_PCU_ISR 0x444e0
> -#define GEN8_PCU_IMR 0x444e4
> -#define GEN8_PCU_IIR 0x444e8
> -#define GEN8_PCU_IER 0x444ec
> +#define GEN8_PCU_ISR _REG(0x444e0)
> +#define GEN8_PCU_IMR _REG(0x444e4)
> +#define GEN8_PCU_IIR _REG(0x444e8)
> +#define GEN8_PCU_IER _REG(0x444ec)
>  
> -#define ILK_DISPLAY_CHICKEN2	0x42004
> +#define ILK_DISPLAY_CHICKEN2	_REG(0x42004)
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define  ILK_ELPIN_409_SELECT	(1 << 25)
>  #define  ILK_DPARB_GATE	(1<<22)
>  #define  ILK_VSDPFD_FULL	(1<<21)
> -#define FUSE_STRAP			0x42014
> +#define FUSE_STRAP			_REG(0x42014)
>  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
>  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
>  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
> @@ -5817,18 +5823,18 @@ enum skl_disp_power_wells {
>  #define  HSW_CDCLK_LIMIT		(1 << 24)
>  #define  ILK_DESKTOP			(1 << 23)
>  
> -#define ILK_DSPCLK_GATE_D			0x42020
> +#define ILK_DSPCLK_GATE_D			_REG(0x42020)
>  #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
>  #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
>  #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
>  #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
>  #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
>  
> -#define IVB_CHICKEN3	0x4200c
> +#define IVB_CHICKEN3	_REG(0x4200c)
>  # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
>  
> -#define CHICKEN_PAR1_1		0x42080
> +#define CHICKEN_PAR1_1		_REG(0x42080)
>  #define  DPA_MASK_VBLANK_SRD	(1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
>  
> @@ -5836,70 +5842,70 @@ enum skl_disp_power_wells {
>  #define _CHICKEN_PIPESL_1_B	0x420b4
>  #define  HSW_FBCQ_DIS			(1 << 22)
>  #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
> -#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> +#define CHICKEN_PIPESL_1(pipe) _REG_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>  
> -#define DISP_ARB_CTL	0x45000
> +#define DISP_ARB_CTL	_REG(0x45000)
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
> -#define DISP_ARB_CTL2	0x45004
> +#define DISP_ARB_CTL2	_REG(0x45004)
>  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> -#define DBUF_CTL	0x45008
> +#define DBUF_CTL	_REG(0x45008)
>  #define  DBUF_POWER_REQUEST		(1<<31)
>  #define  DBUF_POWER_STATE		(1<<30)
> -#define GEN7_MSG_CTL	0x45010
> +#define GEN7_MSG_CTL	_REG(0x45010)
>  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
>  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
> -#define HSW_NDE_RSTWRN_OPT	0x46408
> +#define HSW_NDE_RSTWRN_OPT	_REG(0x46408)
>  #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
>  
> -#define SKL_DFSM			0x51000
> +#define SKL_DFSM			_REG(0x51000)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
>  
> -#define FF_SLICE_CS_CHICKEN2			0x20e4
> +#define FF_SLICE_CS_CHICKEN2			_REG(0x20e4)
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
>  
>  /* GEN7 chicken */
> -#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
> +#define GEN7_COMMON_SLICE_CHICKEN1		_REG(0x7010)
>  # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
>  # define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
> -#define COMMON_SLICE_CHICKEN2			0x7014
> +#define COMMON_SLICE_CHICKEN2			_REG(0x7014)
>  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
>  
> -#define HIZ_CHICKEN					0x7018
> +#define HIZ_CHICKEN					_REG(0x7018)
>  # define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
>  # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
>  
> -#define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
> +#define GEN9_SLICE_COMMON_ECO_CHICKEN0		_REG(0x7308)
>  #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
>  
> -#define GEN7_L3SQCREG1				0xB010
> +#define GEN7_L3SQCREG1				_REG(0xB010)
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> -#define GEN8_L3SQCREG1				0xB100
> +#define GEN8_L3SQCREG1				_REG(0xB100)
>  #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
>  
> -#define GEN7_L3CNTLREG1				0xB01C
> +#define GEN7_L3CNTLREG1				_REG(0xB01C)
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> -#define GEN7_L3CNTLREG2				0xB020
> -#define GEN7_L3CNTLREG3				0xB024
> +#define GEN7_L3CNTLREG2				_REG(0xB020)
> +#define GEN7_L3CNTLREG3				_REG(0xB024)
>  
> -#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> +#define GEN7_L3_CHICKEN_MODE_REGISTER		_REG(0xB030)
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
>  
> -#define GEN7_L3SQCREG4				0xb034
> +#define GEN7_L3SQCREG4				_REG(0xb034)
>  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
>  
> -#define GEN8_L3SQCREG4				0xb118
> +#define GEN8_L3SQCREG4				_REG(0xb118)
>  #define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
>  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
>  
>  /* GEN8 chicken */
> -#define HDC_CHICKEN0				0x7300
> +#define HDC_CHICKEN0				_REG(0x7300)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
> @@ -5908,17 +5914,17 @@ enum skl_disp_power_wells {
>  #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
>  
>  /* GEN9 chicken */
> -#define SLICE_ECO_CHICKEN0			0x7308
> +#define SLICE_ECO_CHICKEN0			_REG(0x7308)
>  #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
>  
>  /* WaCatErrorRejectionIssue */
> -#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> +#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_REG(0x9030)
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
>  
> -#define HSW_SCRATCH1				0xb038
> +#define HSW_SCRATCH1				_REG(0xb038)
>  #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
>  
> -#define BDW_SCRATCH1					0xb11c
> +#define BDW_SCRATCH1					_REG(0xb11c)
>  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1<<2)
>  
>  /* PCH */
> @@ -6012,12 +6018,12 @@ enum skl_disp_power_wells {
>  				 SDE_FDI_RXB_CPT | \
>  				 SDE_FDI_RXA_CPT)
>  
> -#define SDEISR  0xc4000
> -#define SDEIMR  0xc4004
> -#define SDEIIR  0xc4008
> -#define SDEIER  0xc400c
> +#define SDEISR  _REG(0xc4000)
> +#define SDEIMR  _REG(0xc4004)
> +#define SDEIIR  _REG(0xc4008)
> +#define SDEIER  _REG(0xc400c)
>  
> -#define SERR_INT			0xc4040
> +#define SERR_INT			_REG(0xc4040)
>  #define  SERR_INT_POISON		(1<<31)
>  #define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
>  #define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
> @@ -6025,7 +6031,7 @@ enum skl_disp_power_wells {
>  #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
>  
>  /* digital port hotplug */
> -#define PCH_PORT_HOTPLUG		0xc4030	/* SHOTPLUG_CTL */
> +#define PCH_PORT_HOTPLUG		_REG(0xc4030)	/* SHOTPLUG_CTL */
>  #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
>  #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
>  #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
> @@ -6062,42 +6068,42 @@ enum skl_disp_power_wells {
>  #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
>  #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
>  
> -#define PCH_PORT_HOTPLUG2		0xc403C	/* SHOTPLUG_CTL2 SPT+ */
> +#define PCH_PORT_HOTPLUG2		_REG(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
>  #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
>  #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
>  #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
>  #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
>  #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
>  
> -#define PCH_GPIOA               0xc5010
> -#define PCH_GPIOB               0xc5014
> -#define PCH_GPIOC               0xc5018
> -#define PCH_GPIOD               0xc501c
> -#define PCH_GPIOE               0xc5020
> -#define PCH_GPIOF               0xc5024
> +#define PCH_GPIOA               _REG(0xc5010)
> +#define PCH_GPIOB               _REG(0xc5014)
> +#define PCH_GPIOC               _REG(0xc5018)
> +#define PCH_GPIOD               _REG(0xc501c)
> +#define PCH_GPIOE               _REG(0xc5020)
> +#define PCH_GPIOF               _REG(0xc5024)
>  
> -#define PCH_GMBUS0		0xc5100
> -#define PCH_GMBUS1		0xc5104
> -#define PCH_GMBUS2		0xc5108
> -#define PCH_GMBUS3		0xc510c
> -#define PCH_GMBUS4		0xc5110
> -#define PCH_GMBUS5		0xc5120
> +#define PCH_GMBUS0		_REG(0xc5100)
> +#define PCH_GMBUS1		_REG(0xc5104)
> +#define PCH_GMBUS2		_REG(0xc5108)
> +#define PCH_GMBUS3		_REG(0xc510c)
> +#define PCH_GMBUS4		_REG(0xc5110)
> +#define PCH_GMBUS5		_REG(0xc5120)
>  
>  #define _PCH_DPLL_A              0xc6014
>  #define _PCH_DPLL_B              0xc6018
> -#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> +#define PCH_DPLL(pll) _REG(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>  
>  #define _PCH_FPA0                0xc6040
>  #define  FP_CB_TUNE		(0x3<<22)
>  #define _PCH_FPA1                0xc6044
>  #define _PCH_FPB0                0xc6048
>  #define _PCH_FPB1                0xc604c
> -#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
> -#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
> +#define PCH_FP0(pll) _REG(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
> +#define PCH_FP1(pll) _REG(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
>  
> -#define PCH_DPLL_TEST           0xc606c
> +#define PCH_DPLL_TEST           _REG(0xc606c)
>  
> -#define PCH_DREF_CONTROL        0xC6200
> +#define PCH_DREF_CONTROL        _REG(0xC6200)
>  #define  DREF_CONTROL_MASK      0x7fc3
>  #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
>  #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
> @@ -6120,19 +6126,19 @@ enum skl_disp_power_wells {
>  #define  DREF_SSC4_DISABLE                      (0)
>  #define  DREF_SSC4_ENABLE                       (1)
>  
> -#define PCH_RAWCLK_FREQ         0xc6204
> +#define PCH_RAWCLK_FREQ         _REG(0xc6204)
>  #define  FDL_TP1_TIMER_SHIFT    12
>  #define  FDL_TP1_TIMER_MASK     (3<<12)
>  #define  FDL_TP2_TIMER_SHIFT    10
>  #define  FDL_TP2_TIMER_MASK     (3<<10)
>  #define  RAWCLK_FREQ_MASK       0x3ff
>  
> -#define PCH_DPLL_TMR_CFG        0xc6208
> +#define PCH_DPLL_TMR_CFG        _REG(0xc6208)
>  
> -#define PCH_SSC4_PARMS          0xc6210
> -#define PCH_SSC4_AUX_PARMS      0xc6214
> +#define PCH_SSC4_PARMS          _REG(0xc6210)
> +#define PCH_SSC4_AUX_PARMS      _REG(0xc6214)
>  
> -#define PCH_DPLL_SEL		0xc7000
> +#define PCH_DPLL_SEL		_REG(0xc7000)
>  #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
>  #define	 TRANS_DPLLA_SEL(pipe)		0
>  #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
> @@ -6180,9 +6186,9 @@ enum skl_disp_power_wells {
>  #define _VIDEO_DIP_DATA_B        0xe1208
>  #define _VIDEO_DIP_GCP_B         0xe1210
>  
> -#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
> -#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
> -#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
> +#define TVIDEO_DIP_CTL(pipe) _REG_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
> +#define TVIDEO_DIP_DATA(pipe) _REG_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
> +#define TVIDEO_DIP_GCP(pipe) _REG_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>  
>  /* Per-transcoder DIP controls (VLV) */
>  #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
> @@ -6198,16 +6204,17 @@ enum skl_disp_power_wells {
>  #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
>  
>  #define VLV_TVIDEO_DIP_CTL(pipe) \
> -	_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
> +	_REG_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
>  	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
>  #define VLV_TVIDEO_DIP_DATA(pipe) \
> -	_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
> +	_REG_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
>  	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
>  #define VLV_TVIDEO_DIP_GCP(pipe) \
> -	_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
> +	_REG_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
>  		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
>  
>  /* Haswell DIP controls */
> +
>  #define _HSW_VIDEO_DIP_CTL_A		0x60200
>  #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
>  #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
> @@ -6234,25 +6241,18 @@ enum skl_disp_power_wells {
>  #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
>  #define _HSW_VIDEO_DIP_GCP_B		0x61210
>  
> -#define HSW_TVIDEO_DIP_CTL(trans) \
> -	 _TRANSCODER2(trans, _HSW_VIDEO_DIP_CTL_A)
> -#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
> -	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
> -#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
> -	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
> -#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
> -	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
> -#define HSW_TVIDEO_DIP_GCP(trans) \
> -	_TRANSCODER2(trans, _HSW_VIDEO_DIP_GCP_A)
> -#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
> -	(_TRANSCODER2(trans, _HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
> -
> -#define _HSW_STEREO_3D_CTL_A	0x70020
> -#define   S3D_ENABLE		(1<<31)
> -#define _HSW_STEREO_3D_CTL_B	0x71020
> -
> -#define HSW_STEREO_3D_CTL(trans) \
> -	_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
> +#define HSW_TVIDEO_DIP_CTL(trans)		_REG_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
> +#define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
> +#define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
> +#define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> +#define HSW_TVIDEO_DIP_GCP(trans) 		_REG_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
> +#define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_REG_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> +
> +#define _HSW_STEREO_3D_CTL_A		0x70020
> +#define   S3D_ENABLE			(1<<31)
> +#define _HSW_STEREO_3D_CTL_B		0x71020
> +
> +#define HSW_STEREO_3D_CTL(trans)	_REG_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
>  
>  #define _PCH_TRANS_HTOTAL_B          0xe1000
>  #define _PCH_TRANS_HBLANK_B          0xe1004
> @@ -6260,16 +6260,15 @@ enum skl_disp_power_wells {
>  #define _PCH_TRANS_VTOTAL_B          0xe100c
>  #define _PCH_TRANS_VBLANK_B          0xe1010
>  #define _PCH_TRANS_VSYNC_B           0xe1014
> -#define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028
> +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
>  
> -#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
> -#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
> -#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
> -#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
> -#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
> -#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
> -#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
> -					 _PCH_TRANS_VSYNCSHIFT_B)
> +#define PCH_TRANS_HTOTAL(pipe)		_REG_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
> +#define PCH_TRANS_HBLANK(pipe)		_REG_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
> +#define PCH_TRANS_HSYNC(pipe)		_REG_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
> +#define PCH_TRANS_VTOTAL(pipe)		_REG_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
> +#define PCH_TRANS_VBLANK(pipe)		_REG_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
> +#define PCH_TRANS_VSYNC(pipe)		_REG_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
> +#define PCH_TRANS_VSYNCSHIFT(pipe)	_REG_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
>  
>  #define _PCH_TRANSB_DATA_M1	0xe1030
>  #define _PCH_TRANSB_DATA_N1	0xe1034
> @@ -6280,19 +6279,19 @@ enum skl_disp_power_wells {
>  #define _PCH_TRANSB_LINK_M2	0xe1048
>  #define _PCH_TRANSB_LINK_N2	0xe104c
>  
> -#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
> -#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
> -#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
> -#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
> -#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
> -#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
> -#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
> -#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
> +#define PCH_TRANS_DATA_M1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
> +#define PCH_TRANS_DATA_N1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
> +#define PCH_TRANS_DATA_M2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
> +#define PCH_TRANS_DATA_N2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
> +#define PCH_TRANS_LINK_M1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
> +#define PCH_TRANS_LINK_N1(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
> +#define PCH_TRANS_LINK_M2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
> +#define PCH_TRANS_LINK_N2(pipe)	_REG_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
>  
>  #define _PCH_TRANSACONF              0xf0008
>  #define _PCH_TRANSBCONF              0xf1008
> -#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
> -#define LPT_TRANSCONF		_PCH_TRANSACONF /* lpt has only one transcoder */
> +#define PCH_TRANSCONF(pipe)	_REG_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
> +#define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
>  #define  TRANS_DISABLE          (0<<31)
>  #define  TRANS_ENABLE           (1<<31)
>  #define  TRANS_STATE_MASK       (1<<30)
> @@ -6313,47 +6312,47 @@ enum skl_disp_power_wells {
>  
>  #define _TRANSA_CHICKEN1	 0xf0060
>  #define _TRANSB_CHICKEN1	 0xf1060
> -#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> +#define TRANS_CHICKEN1(pipe)	_REG_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
>  #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1<<10)
>  #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
>  #define _TRANSA_CHICKEN2	 0xf0064
>  #define _TRANSB_CHICKEN2	 0xf1064
> -#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> +#define TRANS_CHICKEN2(pipe)	_REG_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
>  #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1<<31)
>  #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
>  #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
>  #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
>  #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
>  
> -#define SOUTH_CHICKEN1		0xc2000
> +#define SOUTH_CHICKEN1		_REG(0xc2000)
>  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
>  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
>  #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
>  #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
>  #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
>  #define  SPT_PWM_GRANULARITY		(1<<0)
> -#define SOUTH_CHICKEN2		0xc2004
> +#define SOUTH_CHICKEN2		_REG(0xc2004)
>  #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
>  #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
>  #define  LPT_PWM_GRANULARITY		(1<<5)
>  #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
>  
> -#define _FDI_RXA_CHICKEN         0xc200c
> -#define _FDI_RXB_CHICKEN         0xc2010
> +#define _FDI_RXA_CHICKEN        0xc200c
> +#define _FDI_RXB_CHICKEN        0xc2010
>  #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
>  #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
> -#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
> +#define FDI_RX_CHICKEN(pipe)	_REG_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
>  
> -#define SOUTH_DSPCLK_GATE_D	0xc2020
> +#define SOUTH_DSPCLK_GATE_D	_REG(0xc2020)
>  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
>  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
>  #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
>  #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
>  
>  /* CPU: FDI_TX */
> -#define _FDI_TXA_CTL             0x60100
> -#define _FDI_TXB_CTL             0x61100
> -#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
> +#define _FDI_TXA_CTL            0x60100
> +#define _FDI_TXB_CTL            0x61100
> +#define FDI_TX_CTL(pipe)	_REG_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
>  #define  FDI_TX_DISABLE         (0<<31)
>  #define  FDI_TX_ENABLE          (1<<31)
>  #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
> @@ -6403,7 +6402,7 @@ enum skl_disp_power_wells {
>  /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
>  #define _FDI_RXA_CTL             0xf000c
>  #define _FDI_RXB_CTL             0xf100c
> -#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
> +#define FDI_RX_CTL(pipe)	_REG_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
>  #define  FDI_RX_ENABLE          (1<<31)
>  /* train, dp width same as FDI_TX */
>  #define  FDI_FS_ERRC_ENABLE		(1<<27)
> @@ -6439,14 +6438,14 @@ enum skl_disp_power_wells {
>  #define  FDI_RX_TP1_TO_TP2_48		(2<<20)
>  #define  FDI_RX_TP1_TO_TP2_64		(3<<20)
>  #define  FDI_RX_FDI_DELAY_90		(0x90<<0)
> -#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
> +#define FDI_RX_MISC(pipe)	_REG_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
>  
> -#define _FDI_RXA_TUSIZE1         0xf0030
> -#define _FDI_RXA_TUSIZE2         0xf0038
> -#define _FDI_RXB_TUSIZE1         0xf1030
> -#define _FDI_RXB_TUSIZE2         0xf1038
> -#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
> -#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
> +#define _FDI_RXA_TUSIZE1        0xf0030
> +#define _FDI_RXA_TUSIZE2        0xf0038
> +#define _FDI_RXB_TUSIZE1        0xf1030
> +#define _FDI_RXB_TUSIZE2        0xf1038
> +#define FDI_RX_TUSIZE1(pipe)	_REG_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
> +#define FDI_RX_TUSIZE2(pipe)	_REG_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
>  
>  /* FDI_RX interrupt register format */
>  #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
> @@ -6461,44 +6460,41 @@ enum skl_disp_power_wells {
>  #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
>  #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
>  
> -#define _FDI_RXA_IIR             0xf0014
> -#define _FDI_RXA_IMR             0xf0018
> -#define _FDI_RXB_IIR             0xf1014
> -#define _FDI_RXB_IMR             0xf1018
> -#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
> -#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
> +#define _FDI_RXA_IIR            0xf0014
> +#define _FDI_RXA_IMR            0xf0018
> +#define _FDI_RXB_IIR            0xf1014
> +#define _FDI_RXB_IMR            0xf1018
> +#define FDI_RX_IIR(pipe)	_REG_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
> +#define FDI_RX_IMR(pipe)	_REG_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
>  
> -#define FDI_PLL_CTL_1           0xfe000
> -#define FDI_PLL_CTL_2           0xfe004
> +#define FDI_PLL_CTL_1           _REG(0xfe000)
> +#define FDI_PLL_CTL_2           _REG(0xfe004)
>  
> -#define PCH_LVDS	0xe1180
> +#define PCH_LVDS	_REG(0xe1180)
>  #define  LVDS_DETECTED	(1 << 1)
>  
>  /* vlv has 2 sets of panel control regs. */
> -#define _PIPEA_PP_STATUS	(VLV_DISPLAY_BASE + 0x61200)
> -#define _PIPEA_PP_CONTROL	(VLV_DISPLAY_BASE + 0x61204)
> -#define _PIPEA_PP_ON_DELAYS	(VLV_DISPLAY_BASE + 0x61208)
> +#define _PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
> +#define _PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
> +#define _PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
>  #define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
> -#define _PIPEA_PP_OFF_DELAYS	(VLV_DISPLAY_BASE + 0x6120c)
> -#define _PIPEA_PP_DIVISOR	(VLV_DISPLAY_BASE + 0x61210)
> -
> -#define _PIPEB_PP_STATUS	(VLV_DISPLAY_BASE + 0x61300)
> -#define _PIPEB_PP_CONTROL	(VLV_DISPLAY_BASE + 0x61304)
> -#define _PIPEB_PP_ON_DELAYS	(VLV_DISPLAY_BASE + 0x61308)
> -#define _PIPEB_PP_OFF_DELAYS	(VLV_DISPLAY_BASE + 0x6130c)
> -#define _PIPEB_PP_DIVISOR	(VLV_DISPLAY_BASE + 0x61310)
> -
> -#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
> -#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
> -#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> -		_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
> -#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> -		_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
> -#define VLV_PIPE_PP_DIVISOR(pipe) \
> -		_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
> -
> -#define PCH_PP_STATUS		0xc7200
> -#define PCH_PP_CONTROL		0xc7204
> +#define _PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
> +#define _PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
> +
> +#define _PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
> +#define _PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
> +#define _PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
> +#define _PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
> +#define _PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
> +
> +#define VLV_PIPE_PP_STATUS(pipe)	_REG_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
> +#define VLV_PIPE_PP_CONTROL(pipe)	_REG_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
> +#define VLV_PIPE_PP_ON_DELAYS(pipe)	_REG_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
> +#define VLV_PIPE_PP_OFF_DELAYS(pipe)	_REG_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
> +#define VLV_PIPE_PP_DIVISOR(pipe)	_REG_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
> +
> +#define _PCH_PP_STATUS		0xc7200
> +#define _PCH_PP_CONTROL		0xc7204
>  #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
>  #define  PANEL_UNLOCK_MASK	(0xffff << 16)
>  #define  BXT_POWER_CYCLE_DELAY_MASK	(0x1f0)
> @@ -6508,7 +6504,7 @@ enum skl_disp_power_wells {
>  #define  PANEL_POWER_RESET	(1 << 1)
>  #define  PANEL_POWER_OFF	(0 << 0)
>  #define  PANEL_POWER_ON		(1 << 0)
> -#define PCH_PP_ON_DELAYS	0xc7208
> +#define _PCH_PP_ON_DELAYS	0xc7208
>  #define  PANEL_PORT_SELECT_MASK	(3 << 30)
>  #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
>  #define  PANEL_PORT_SELECT_DPA	(1 << 30)
> @@ -6519,30 +6515,37 @@ enum skl_disp_power_wells {
>  #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
>  #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
>  
> -#define PCH_PP_OFF_DELAYS	0xc720c
> +#define _PCH_PP_OFF_DELAYS		0xc720c
>  #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
>  #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
>  #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
>  #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
>  
> -#define PCH_PP_DIVISOR		0xc7210
> +#define _PCH_PP_DIVISOR			0xc7210
>  #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
>  #define  PP_REFERENCE_DIVIDER_SHIFT	8
>  #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
>  #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
>  
> +#define PCH_PP_STATUS			_REG(_PCH_PP_STATUS)
> +#define PCH_PP_CONTROL			_REG(_PCH_PP_CONTROL)
> +#define PCH_PP_ON_DELAYS		_REG(_PCH_PP_ON_DELAYS)
> +#define PCH_PP_OFF_DELAYS		_REG(_PCH_PP_OFF_DELAYS)
> +#define PCH_PP_DIVISOR			_REG(_PCH_PP_DIVISOR)
> +
>  /* BXT PPS changes - 2nd set of PPS registers */
>  #define _BXT_PP_STATUS2 	0xc7300
>  #define _BXT_PP_CONTROL2 	0xc7304
>  #define _BXT_PP_ON_DELAYS2	0xc7308
>  #define _BXT_PP_OFF_DELAYS2	0xc730c
>  
> -#define BXT_PP_STATUS(n)	_PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
> -#define BXT_PP_CONTROL(n)	_PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
> -#define BXT_PP_ON_DELAYS(n)	_PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
> -#define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
> +#define BXT_PP_STATUS(n)	_REG_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2)
> +#define BXT_PP_CONTROL(n)	_REG_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2)
> +#define BXT_PP_ON_DELAYS(n)	_REG_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
> +#define BXT_PP_OFF_DELAYS(n)	_REG_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
>  
> -#define PCH_DP_B		0xe4100
> +#define _PCH_DP_B		0xe4100
> +#define PCH_DP_B		_REG(_PCH_DP_B)
>  #define _PCH_DPB_AUX_CH_CTL	0xe4110
>  #define _PCH_DPB_AUX_CH_DATA1	0xe4114
>  #define _PCH_DPB_AUX_CH_DATA2	0xe4118
> @@ -6550,7 +6553,8 @@ enum skl_disp_power_wells {
>  #define _PCH_DPB_AUX_CH_DATA4	0xe4120
>  #define _PCH_DPB_AUX_CH_DATA5	0xe4124
>  
> -#define PCH_DP_C		0xe4200
> +#define _PCH_DP_C		0xe4200
> +#define PCH_DP_C		_REG(_PCH_DP_C)
>  #define _PCH_DPC_AUX_CH_CTL	0xe4210
>  #define _PCH_DPC_AUX_CH_DATA1	0xe4214
>  #define _PCH_DPC_AUX_CH_DATA2	0xe4218
> @@ -6558,7 +6562,8 @@ enum skl_disp_power_wells {
>  #define _PCH_DPC_AUX_CH_DATA4	0xe4220
>  #define _PCH_DPC_AUX_CH_DATA5	0xe4224
>  
> -#define PCH_DP_D		0xe4300
> +#define _PCH_DP_D		0xe4300
> +#define PCH_DP_D		_REG(_PCH_DP_D)
>  #define _PCH_DPD_AUX_CH_CTL	0xe4310
>  #define _PCH_DPD_AUX_CH_DATA1	0xe4314
>  #define _PCH_DPD_AUX_CH_DATA2	0xe4318
> @@ -6566,8 +6571,8 @@ enum skl_disp_power_wells {
>  #define _PCH_DPD_AUX_CH_DATA4	0xe4320
>  #define _PCH_DPD_AUX_CH_DATA5	0xe4324
>  
> -#define PCH_DP_AUX_CH_CTL(port)		_PORT((port)-1, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> -#define PCH_DP_AUX_CH_DATA(port, i)	(_PORT((port)-1, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> +#define PCH_DP_AUX_CH_CTL(port)		_REG_PORT((port)-1, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> +#define PCH_DP_AUX_CH_DATA(port, i)	_REG(_PORT((port)-1, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  /* CPT */
>  #define  PORT_TRANS_A_SEL_CPT	0
> @@ -6583,7 +6588,7 @@ enum skl_disp_power_wells {
>  #define _TRANS_DP_CTL_A		0xe0300
>  #define _TRANS_DP_CTL_B		0xe1300
>  #define _TRANS_DP_CTL_C		0xe2300
> -#define TRANS_DP_CTL(pipe)	_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
> +#define TRANS_DP_CTL(pipe)	_REG_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
>  #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
>  #define  TRANS_DP_PORT_SEL_B	(0<<29)
>  #define  TRANS_DP_PORT_SEL_C	(1<<29)
> @@ -6636,40 +6641,40 @@ enum skl_disp_power_wells {
>  
>  #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
>  
> -#define  VLV_PMWGICZ				0x1300a4
> +#define  VLV_PMWGICZ				_REG(0x1300a4)
>  
> -#define  FORCEWAKE				0xA18C
> -#define  FORCEWAKE_VLV				0x1300b0
> -#define  FORCEWAKE_ACK_VLV			0x1300b4
> -#define  FORCEWAKE_MEDIA_VLV			0x1300b8
> -#define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
> -#define  FORCEWAKE_ACK_HSW			0x130044
> -#define  FORCEWAKE_ACK				0x130090
> -#define  VLV_GTLC_WAKE_CTRL			0x130090
> +#define  FORCEWAKE				_REG(0xA18C)
> +#define  FORCEWAKE_VLV				_REG(0x1300b0)
> +#define  FORCEWAKE_ACK_VLV			_REG(0x1300b4)
> +#define  FORCEWAKE_MEDIA_VLV			_REG(0x1300b8)
> +#define  FORCEWAKE_ACK_MEDIA_VLV		_REG(0x1300bc)
> +#define  FORCEWAKE_ACK_HSW			_REG(0x130044)
> +#define  FORCEWAKE_ACK				_REG(0x130090)
> +#define  VLV_GTLC_WAKE_CTRL			_REG(0x130090)
>  #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
>  #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
>  #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
>  
> -#define  VLV_GTLC_PW_STATUS			0x130094
> +#define  VLV_GTLC_PW_STATUS			_REG(0x130094)
>  #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
>  #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
>  #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
>  #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
> -#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
> -#define  FORCEWAKE_MEDIA_GEN9			0xa270
> -#define  FORCEWAKE_RENDER_GEN9			0xa278
> -#define  FORCEWAKE_BLITTER_GEN9			0xa188
> -#define  FORCEWAKE_ACK_MEDIA_GEN9		0x0D88
> -#define  FORCEWAKE_ACK_RENDER_GEN9		0x0D84
> -#define  FORCEWAKE_ACK_BLITTER_GEN9		0x130044
> +#define  FORCEWAKE_MT				_REG(0xa188) /* multi-threaded */
> +#define  FORCEWAKE_MEDIA_GEN9			_REG(0xa270)
> +#define  FORCEWAKE_RENDER_GEN9			_REG(0xa278)
> +#define  FORCEWAKE_BLITTER_GEN9			_REG(0xa188)
> +#define  FORCEWAKE_ACK_MEDIA_GEN9		_REG(0x0D88)
> +#define  FORCEWAKE_ACK_RENDER_GEN9		_REG(0x0D84)
> +#define  FORCEWAKE_ACK_BLITTER_GEN9		_REG(0x130044)
>  #define   FORCEWAKE_KERNEL			0x1
>  #define   FORCEWAKE_USER			0x2
> -#define  FORCEWAKE_MT_ACK			0x130040
> -#define  ECOBUS					0xa180
> +#define  FORCEWAKE_MT_ACK			_REG(0x130040)
> +#define  ECOBUS					_REG(0xa180)
>  #define    FORCEWAKE_MT_ENABLE			(1<<5)
> -#define  VLV_SPAREG2H				0xA194
> +#define  VLV_SPAREG2H				_REG(0xA194)
>  
> -#define  GTFIFODBG				0x120000
> +#define  GTFIFODBG				_REG(0x120000)
>  #define    GT_FIFO_SBDROPERR			(1<<6)
>  #define    GT_FIFO_BLOBDROPERR			(1<<5)
>  #define    GT_FIFO_SB_READ_ABORTERR		(1<<4)
> @@ -6678,23 +6683,23 @@ enum skl_disp_power_wells {
>  #define    GT_FIFO_IAWRERR			(1<<1)
>  #define    GT_FIFO_IARDERR			(1<<0)
>  
> -#define  GTFIFOCTL				0x120008
> +#define  GTFIFOCTL				_REG(0x120008)
>  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
>  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
>  #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
>  #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
>  
> -#define  HSW_IDICR				0x9008
> +#define  HSW_IDICR				_REG(0x9008)
>  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
> -#define  HSW_EDRAM_PRESENT			0x120010
> +#define  HSW_EDRAM_PRESENT			_REG(0x120010)
>  #define    EDRAM_ENABLED			0x1
>  
> -#define GEN6_UCGCTL1				0x9400
> +#define GEN6_UCGCTL1				_REG(0x9400)
>  # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
>  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
>  
> -#define GEN6_UCGCTL2				0x9404
> +#define GEN6_UCGCTL2				_REG(0x9404)
>  # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
>  # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
>  # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
> @@ -6702,30 +6707,30 @@ enum skl_disp_power_wells {
>  # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
>  # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>  
> -#define GEN6_UCGCTL3				0x9408
> +#define GEN6_UCGCTL3				_REG(0x9408)
>  
> -#define GEN7_UCGCTL4				0x940c
> +#define GEN7_UCGCTL4				_REG(0x940c)
>  #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
>  
> -#define GEN6_RCGCTL1				0x9410
> -#define GEN6_RCGCTL2				0x9414
> -#define GEN6_RSTCTL				0x9420
> +#define GEN6_RCGCTL1				_REG(0x9410)
> +#define GEN6_RCGCTL2				_REG(0x9414)
> +#define GEN6_RSTCTL				_REG(0x9420)
>  
> -#define GEN8_UCGCTL6				0x9430
> +#define GEN8_UCGCTL6				_REG(0x9430)
>  #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
>  #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
>  #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
>  
> -#define GEN6_GFXPAUSE				0xA000
> -#define GEN6_RPNSWREQ				0xA008
> +#define GEN6_GFXPAUSE				_REG(0xA000)
> +#define GEN6_RPNSWREQ				_REG(0xA008)
>  #define   GEN6_TURBO_DISABLE			(1<<31)
>  #define   GEN6_FREQUENCY(x)			((x)<<25)
>  #define   HSW_FREQUENCY(x)			((x)<<24)
>  #define   GEN9_FREQUENCY(x)			((x)<<23)
>  #define   GEN6_OFFSET(x)			((x)<<19)
>  #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
> -#define GEN6_RC_VIDEO_FREQ			0xA00C
> -#define GEN6_RC_CONTROL				0xA090
> +#define GEN6_RC_VIDEO_FREQ			_REG(0xA00C)
> +#define GEN6_RC_CONTROL				_REG(0xA090)
>  #define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
>  #define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
>  #define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
> @@ -6735,16 +6740,16 @@ enum skl_disp_power_wells {
>  #define   GEN7_RC_CTL_TO_MODE			(1<<28)
>  #define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
>  #define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
> -#define GEN6_RP_DOWN_TIMEOUT			0xA010
> -#define GEN6_RP_INTERRUPT_LIMITS		0xA014
> -#define GEN6_RPSTAT1				0xA01C
> +#define GEN6_RP_DOWN_TIMEOUT			_REG(0xA010)
> +#define GEN6_RP_INTERRUPT_LIMITS		_REG(0xA014)
> +#define GEN6_RPSTAT1				_REG(0xA01C)
>  #define   GEN6_CAGF_SHIFT			8
>  #define   HSW_CAGF_SHIFT			7
>  #define   GEN9_CAGF_SHIFT			23
>  #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
>  #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
>  #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
> -#define GEN6_RP_CONTROL				0xA024
> +#define GEN6_RP_CONTROL				_REG(0xA024)
>  #define   GEN6_RP_MEDIA_TURBO			(1<<11)
>  #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
>  #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
> @@ -6758,53 +6763,53 @@ enum skl_disp_power_wells {
>  #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
>  #define   GEN6_RP_DOWN_IDLE_AVG			(0x2<<0)
>  #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
> -#define GEN6_RP_UP_THRESHOLD			0xA02C
> -#define GEN6_RP_DOWN_THRESHOLD			0xA030
> -#define GEN6_RP_CUR_UP_EI			0xA050
> +#define GEN6_RP_UP_THRESHOLD			_REG(0xA02C)
> +#define GEN6_RP_DOWN_THRESHOLD			_REG(0xA030)
> +#define GEN6_RP_CUR_UP_EI			_REG(0xA050)
>  #define   GEN6_CURICONT_MASK			0xffffff
> -#define GEN6_RP_CUR_UP				0xA054
> +#define GEN6_RP_CUR_UP				_REG(0xA054)
>  #define   GEN6_CURBSYTAVG_MASK			0xffffff
> -#define GEN6_RP_PREV_UP				0xA058
> -#define GEN6_RP_CUR_DOWN_EI			0xA05C
> +#define GEN6_RP_PREV_UP				_REG(0xA058)
> +#define GEN6_RP_CUR_DOWN_EI			_REG(0xA05C)
>  #define   GEN6_CURIAVG_MASK			0xffffff
> -#define GEN6_RP_CUR_DOWN			0xA060
> -#define GEN6_RP_PREV_DOWN			0xA064
> -#define GEN6_RP_UP_EI				0xA068
> -#define GEN6_RP_DOWN_EI				0xA06C
> -#define GEN6_RP_IDLE_HYSTERSIS			0xA070
> -#define GEN6_RPDEUHWTC				0xA080
> -#define GEN6_RPDEUC				0xA084
> -#define GEN6_RPDEUCSW				0xA088
> -#define GEN6_RC_STATE				0xA094
> -#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
> -#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
> -#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
> -#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
> -#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
> -#define GEN6_RC_SLEEP				0xA0B0
> -#define GEN6_RCUBMABDTMR			0xA0B0
> -#define GEN6_RC1e_THRESHOLD			0xA0B4
> -#define GEN6_RC6_THRESHOLD			0xA0B8
> -#define GEN6_RC6p_THRESHOLD			0xA0BC
> -#define VLV_RCEDATA				0xA0BC
> -#define GEN6_RC6pp_THRESHOLD			0xA0C0
> -#define GEN6_PMINTRMSK				0xA168
> +#define GEN6_RP_CUR_DOWN			_REG(0xA060)
> +#define GEN6_RP_PREV_DOWN			_REG(0xA064)
> +#define GEN6_RP_UP_EI				_REG(0xA068)
> +#define GEN6_RP_DOWN_EI				_REG(0xA06C)
> +#define GEN6_RP_IDLE_HYSTERSIS			_REG(0xA070)
> +#define GEN6_RPDEUHWTC				_REG(0xA080)
> +#define GEN6_RPDEUC				_REG(0xA084)
> +#define GEN6_RPDEUCSW				_REG(0xA088)
> +#define GEN6_RC_STATE				_REG(0xA094)
> +#define GEN6_RC1_WAKE_RATE_LIMIT		_REG(0xA098)
> +#define GEN6_RC6_WAKE_RATE_LIMIT		_REG(0xA09C)
> +#define GEN6_RC6pp_WAKE_RATE_LIMIT		_REG(0xA0A0)
> +#define GEN6_RC_EVALUATION_INTERVAL		_REG(0xA0A8)
> +#define GEN6_RC_IDLE_HYSTERSIS			_REG(0xA0AC)
> +#define GEN6_RC_SLEEP				_REG(0xA0B0)
> +#define GEN6_RCUBMABDTMR			_REG(0xA0B0)
> +#define GEN6_RC1e_THRESHOLD			_REG(0xA0B4)
> +#define GEN6_RC6_THRESHOLD			_REG(0xA0B8)
> +#define GEN6_RC6p_THRESHOLD			_REG(0xA0BC)
> +#define VLV_RCEDATA				_REG(0xA0BC)
> +#define GEN6_RC6pp_THRESHOLD			_REG(0xA0C0)
> +#define GEN6_PMINTRMSK				_REG(0xA168)
>  #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
> -#define VLV_PWRDWNUPCTL				0xA294
> -#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		0xA0C4
> -#define GEN9_RENDER_PG_IDLE_HYSTERESIS		0xA0C8
> -#define GEN9_PG_ENABLE				0xA210
> +#define VLV_PWRDWNUPCTL				_REG(0xA294)
> +#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_REG(0xA0C4)
> +#define GEN9_RENDER_PG_IDLE_HYSTERESIS		_REG(0xA0C8)
> +#define GEN9_PG_ENABLE				_REG(0xA210)
>  #define GEN9_RENDER_PG_ENABLE			(1<<0)
>  #define GEN9_MEDIA_PG_ENABLE			(1<<1)
>  
> -#define VLV_CHICKEN_3				(VLV_DISPLAY_BASE + 0x7040C)
> +#define VLV_CHICKEN_3				_REG(VLV_DISPLAY_BASE + 0x7040C)
>  #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
>  #define  PIXEL_OVERLAP_CNT_SHIFT		30
>  
> -#define GEN6_PMISR				0x44020
> -#define GEN6_PMIMR				0x44024 /* rps_lock */
> -#define GEN6_PMIIR				0x44028
> -#define GEN6_PMIER				0x4402C
> +#define GEN6_PMISR				_REG(0x44020)
> +#define GEN6_PMIMR				_REG(0x44024) /* rps_lock */
> +#define GEN6_PMIIR				_REG(0x44028)
> +#define GEN6_PMIER				_REG(0x4402C)
>  #define  GEN6_PM_MBOX_EVENT			(1<<25)
>  #define  GEN6_PM_THERMAL_EVENT			(1<<24)
>  #define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
> @@ -6816,30 +6821,30 @@ enum skl_disp_power_wells {
>  						 GEN6_PM_RP_DOWN_THRESHOLD | \
>  						 GEN6_PM_RP_DOWN_TIMEOUT)
>  
> -#define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
> +#define GEN7_GT_SCRATCH(i)			_REG(0x4F100 + (i) * 4)
>  #define GEN7_GT_SCRATCH_REG_NUM			8
>  
> -#define VLV_GTLC_SURVIVABILITY_REG              0x130098
> +#define VLV_GTLC_SURVIVABILITY_REG              _REG(0x130098)
>  #define VLV_GFX_CLK_STATUS_BIT			(1<<3)
>  #define VLV_GFX_CLK_FORCE_ON_BIT		(1<<2)
>  
> -#define GEN6_GT_GFX_RC6_LOCKED			0x138104
> -#define VLV_COUNTER_CONTROL			0x138104
> +#define GEN6_GT_GFX_RC6_LOCKED			_REG(0x138104)
> +#define VLV_COUNTER_CONTROL			_REG(0x138104)
>  #define   VLV_COUNT_RANGE_HIGH			(1<<15)
>  #define   VLV_MEDIA_RC0_COUNT_EN		(1<<5)
>  #define   VLV_RENDER_RC0_COUNT_EN		(1<<4)
>  #define   VLV_MEDIA_RC6_COUNT_EN		(1<<1)
>  #define   VLV_RENDER_RC6_COUNT_EN		(1<<0)
> -#define GEN6_GT_GFX_RC6				0x138108
> -#define VLV_GT_RENDER_RC6			0x138108
> -#define VLV_GT_MEDIA_RC6			0x13810C
> +#define GEN6_GT_GFX_RC6				_REG(0x138108)
> +#define VLV_GT_RENDER_RC6			_REG(0x138108)
> +#define VLV_GT_MEDIA_RC6			_REG(0x13810C)
>  
> -#define GEN6_GT_GFX_RC6p			0x13810C
> -#define GEN6_GT_GFX_RC6pp			0x138110
> -#define VLV_RENDER_C0_COUNT			0x138118
> -#define VLV_MEDIA_C0_COUNT			0x13811C
> +#define GEN6_GT_GFX_RC6p			_REG(0x13810C)
> +#define GEN6_GT_GFX_RC6pp			_REG(0x138110)
> +#define VLV_RENDER_C0_COUNT			_REG(0x138118)
> +#define VLV_MEDIA_C0_COUNT			_REG(0x13811C)
>  
> -#define GEN6_PCODE_MAILBOX			0x138124
> +#define GEN6_PCODE_MAILBOX			_REG(0x138124)
>  #define   GEN6_PCODE_READY			(1<<31)
>  #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
>  #define	  GEN6_PCODE_READ_RC6VIDS		0x5
> @@ -6862,12 +6867,12 @@ enum skl_disp_power_wells {
>  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
>  #define   DISPLAY_IPS_CONTROL			0x19
>  #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> -#define GEN6_PCODE_DATA				0x138128
> +#define GEN6_PCODE_DATA				_REG(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> -#define GEN6_PCODE_DATA1			0x13812C
> +#define GEN6_PCODE_DATA1			_REG(0x13812C)
>  
> -#define GEN6_GT_CORE_STATUS		0x138060
> +#define GEN6_GT_CORE_STATUS		_REG(0x138060)
>  #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
>  #define   GEN6_RCn_MASK			7
>  #define   GEN6_RC0			0
> @@ -6875,23 +6880,23 @@ enum skl_disp_power_wells {
>  #define   GEN6_RC6			3
>  #define   GEN6_RC7			4
>  
> -#define CHV_POWER_SS0_SIG1		0xa720
> -#define CHV_POWER_SS1_SIG1		0xa728
> +#define CHV_POWER_SS0_SIG1		_REG(0xa720)
> +#define CHV_POWER_SS1_SIG1		_REG(0xa728)
>  #define   CHV_SS_PG_ENABLE		(1<<1)
>  #define   CHV_EU08_PG_ENABLE		(1<<9)
>  #define   CHV_EU19_PG_ENABLE		(1<<17)
>  #define   CHV_EU210_PG_ENABLE		(1<<25)
>  
> -#define CHV_POWER_SS0_SIG2		0xa724
> -#define CHV_POWER_SS1_SIG2		0xa72c
> +#define CHV_POWER_SS0_SIG2		_REG(0xa724)
> +#define CHV_POWER_SS1_SIG2		_REG(0xa72c)
>  #define   CHV_EU311_PG_ENABLE		(1<<1)
>  
> -#define GEN9_SLICE_PGCTL_ACK(slice)	(0x804c + (slice)*0x4)
> +#define GEN9_SLICE_PGCTL_ACK(slice)	_REG(0x804c + (slice)*0x4)
>  #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
>  #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
>  
> -#define GEN9_SS01_EU_PGCTL_ACK(slice)	(0x805c + (slice)*0x8)
> -#define GEN9_SS23_EU_PGCTL_ACK(slice)	(0x8060 + (slice)*0x8)
> +#define GEN9_SS01_EU_PGCTL_ACK(slice)	_REG(0x805c + (slice)*0x8)
> +#define GEN9_SS23_EU_PGCTL_ACK(slice)	_REG(0x8060 + (slice)*0x8)
>  #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
>  #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
>  #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
> @@ -6901,18 +6906,18 @@ enum skl_disp_power_wells {
>  #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
>  #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
>  
> -#define GEN7_MISCCPCTL			(0x9424)
> +#define GEN7_MISCCPCTL				_REG(0x9424)
>  #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
>  #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
>  #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
>  #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
>  
> -#define GEN8_GARBCNTL                   0xB004
> +#define GEN8_GARBCNTL                   _REG(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>  
>  /* IVYBRIDGE DPF */
> -#define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
> -#define HSW_L3CDERRST11			0xB208 /* L3CD Error Status register 1 slice 1 */
> +#define GEN7_L3CDERRST1(slice)		_REG(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> +#define HSW_L3CDERRST11			_REG(0xB208) /* L3CD Error Status register 1 slice 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
>  #define   GEN7_PARITY_ERROR_VALID	(1<<13)
>  #define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
> @@ -6929,93 +6934,83 @@ enum skl_disp_power_wells {
>  #define HSW_L3LOG_BASE_SLICE1		0xB270
>  #define GEN7_L3LOG_SIZE			0x80
>  
> -#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
> -#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
> +#define GEN7_HALF_SLICE_CHICKEN1	_REG(0xe100) /* IVB GT1 + VLV */
> +#define GEN7_HALF_SLICE_CHICKEN1_GT2	_REG(0xf100)
>  #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
>  #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
>  #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)
>  #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
>  
> -#define GEN9_HALF_SLICE_CHICKEN5	0xe188
> +#define GEN9_HALF_SLICE_CHICKEN5	_REG(0xe188)
>  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
>  #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
>  
> -#define GEN8_ROW_CHICKEN		0xe4f0
> +#define GEN8_ROW_CHICKEN		_REG(0xe4f0)
>  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>  #define   STALL_DOP_GATING_DISABLE		(1<<5)
>  
> -#define GEN7_ROW_CHICKEN2		0xe4f4
> -#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
> +#define GEN7_ROW_CHICKEN2		_REG(0xe4f4)
> +#define GEN7_ROW_CHICKEN2_GT2		_REG(0xf4f4)
>  #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
>  
> -#define HSW_ROW_CHICKEN3		0xe49c
> +#define HSW_ROW_CHICKEN3		_REG(0xe49c)
>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>  
> -#define HALF_SLICE_CHICKEN2		0xe180
> +#define HALF_SLICE_CHICKEN2		_REG(0xe180)
>  #define   GEN8_ST_PO_DISABLE		(1<<13)
>  
> -#define HALF_SLICE_CHICKEN3		0xe184
> +#define HALF_SLICE_CHICKEN3		_REG(0xe184)
>  #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
>  #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1<<5)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
>  
> -#define GEN9_HALF_SLICE_CHICKEN7	0xe194
> +#define GEN9_HALF_SLICE_CHICKEN7	_REG(0xe194)
>  #define   GEN9_ENABLE_YV12_BUGFIX	(1<<4)
>  
>  /* Audio */
> -#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
> +#define G4X_AUD_VID_DID			_REG(dev_priv->info.display_mmio_offset + 0x62020)
>  #define   INTEL_AUDIO_DEVCL		0x808629FB
>  #define   INTEL_AUDIO_DEVBLC		0x80862801
>  #define   INTEL_AUDIO_DEVCTG		0x80862802
>  
> -#define G4X_AUD_CNTL_ST			0x620B4
> +#define G4X_AUD_CNTL_ST			_REG(0x620B4)
>  #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
>  #define   G4X_ELDV_DEVCTG		(1 << 14)
>  #define   G4X_ELD_ADDR_MASK		(0xf << 5)
>  #define   G4X_ELD_ACK			(1 << 4)
> -#define G4X_HDMIW_HDMIEDID		0x6210C
> +#define G4X_HDMIW_HDMIEDID		_REG(0x6210C)
>  
>  #define _IBX_HDMIW_HDMIEDID_A		0xE2050
>  #define _IBX_HDMIW_HDMIEDID_B		0xE2150
> -#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
> -					_IBX_HDMIW_HDMIEDID_A, \
> -					_IBX_HDMIW_HDMIEDID_B)
> +#define IBX_HDMIW_HDMIEDID(pipe)	_REG_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
> +						  _IBX_HDMIW_HDMIEDID_B)
>  #define _IBX_AUD_CNTL_ST_A		0xE20B4
>  #define _IBX_AUD_CNTL_ST_B		0xE21B4
> -#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
> -					_IBX_AUD_CNTL_ST_A, \
> -					_IBX_AUD_CNTL_ST_B)
> +#define IBX_AUD_CNTL_ST(pipe)		_REG_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
> +						  _IBX_AUD_CNTL_ST_B)
>  #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
>  #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
>  #define   IBX_ELD_ACK			(1 << 4)
> -#define IBX_AUD_CNTL_ST2		0xE20C0
> +#define IBX_AUD_CNTL_ST2		_REG(0xE20C0)
>  #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
>  #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
>  
>  #define _CPT_HDMIW_HDMIEDID_A		0xE5050
>  #define _CPT_HDMIW_HDMIEDID_B		0xE5150
> -#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
> -					_CPT_HDMIW_HDMIEDID_A, \
> -					_CPT_HDMIW_HDMIEDID_B)
> +#define CPT_HDMIW_HDMIEDID(pipe)	_REG_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
>  #define _CPT_AUD_CNTL_ST_A		0xE50B4
>  #define _CPT_AUD_CNTL_ST_B		0xE51B4
> -#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
> -					_CPT_AUD_CNTL_ST_A, \
> -					_CPT_AUD_CNTL_ST_B)
> -#define CPT_AUD_CNTRL_ST2		0xE50C0
> +#define CPT_AUD_CNTL_ST(pipe)		_REG_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
> +#define CPT_AUD_CNTRL_ST2		_REG(0xE50C0)
>  
>  #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
>  #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
> -#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
> -					_VLV_HDMIW_HDMIEDID_A, \
> -					_VLV_HDMIW_HDMIEDID_B)
> +#define VLV_HDMIW_HDMIEDID(pipe)	_REG_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
>  #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
>  #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
> -#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
> -					_VLV_AUD_CNTL_ST_A, \
> -					_VLV_AUD_CNTL_ST_B)
> -#define VLV_AUD_CNTL_ST2		(VLV_DISPLAY_BASE + 0x620C0)
> +#define VLV_AUD_CNTL_ST(pipe)		_REG_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
> +#define VLV_AUD_CNTL_ST2		_REG(VLV_DISPLAY_BASE + 0x620C0)
>  
>  /* These are the 4 32-bit write offset registers for each stream
>   * output buffer.  It determines the offset from the
> @@ -7025,19 +7020,13 @@ enum skl_disp_power_wells {
>  
>  #define _IBX_AUD_CONFIG_A		0xe2000
>  #define _IBX_AUD_CONFIG_B		0xe2100
> -#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
> -					_IBX_AUD_CONFIG_A, \
> -					_IBX_AUD_CONFIG_B)
> +#define IBX_AUD_CFG(pipe)		_REG_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
>  #define _CPT_AUD_CONFIG_A		0xe5000
>  #define _CPT_AUD_CONFIG_B		0xe5100
> -#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
> -					_CPT_AUD_CONFIG_A, \
> -					_CPT_AUD_CONFIG_B)
> +#define CPT_AUD_CFG(pipe)		_REG_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
>  #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
>  #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
> -#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
> -					_VLV_AUD_CONFIG_A, \
> -					_VLV_AUD_CONFIG_B)
> +#define VLV_AUD_CFG(pipe)		_REG_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
>  
>  #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
>  #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
> @@ -7062,61 +7051,51 @@ enum skl_disp_power_wells {
>  /* HSW Audio */
>  #define _HSW_AUD_CONFIG_A		0x65000
>  #define _HSW_AUD_CONFIG_B		0x65100
> -#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
> -					_HSW_AUD_CONFIG_A, \
> -					_HSW_AUD_CONFIG_B)
> +#define HSW_AUD_CFG(pipe)		_REG_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
>  
>  #define _HSW_AUD_MISC_CTRL_A		0x65010
>  #define _HSW_AUD_MISC_CTRL_B		0x65110
> -#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
> -					_HSW_AUD_MISC_CTRL_A, \
> -					_HSW_AUD_MISC_CTRL_B)
> +#define HSW_AUD_MISC_CTRL(pipe)		_REG_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
>  
>  #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
>  #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
> -#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
> -					_HSW_AUD_DIP_ELD_CTRL_ST_A, \
> -					_HSW_AUD_DIP_ELD_CTRL_ST_B)
> +#define HSW_AUD_DIP_ELD_CTRL(pipe)	_REG_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
>  
>  /* Audio Digital Converter */
>  #define _HSW_AUD_DIG_CNVT_1		0x65080
>  #define _HSW_AUD_DIG_CNVT_2		0x65180
> -#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
> -					_HSW_AUD_DIG_CNVT_1, \
> -					_HSW_AUD_DIG_CNVT_2)
> +#define AUD_DIG_CNVT(pipe)		_REG_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
>  #define DIP_PORT_SEL_MASK		0x3
>  
>  #define _HSW_AUD_EDID_DATA_A		0x65050
>  #define _HSW_AUD_EDID_DATA_B		0x65150
> -#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
> -					_HSW_AUD_EDID_DATA_A, \
> -					_HSW_AUD_EDID_DATA_B)
> +#define HSW_AUD_EDID_DATA(pipe)		_REG_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
>  
> -#define HSW_AUD_PIPE_CONV_CFG		0x6507c
> -#define HSW_AUD_PIN_ELD_CP_VLD		0x650c0
> +#define HSW_AUD_PIPE_CONV_CFG		_REG(0x6507c)
> +#define HSW_AUD_PIN_ELD_CP_VLD		_REG(0x650c0)
>  #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
>  #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
>  #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
>  #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
>  
> -#define HSW_AUD_CHICKENBIT			0x65f10
> +#define HSW_AUD_CHICKENBIT			_REG(0x65f10)
>  #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
>  
>  /* HSW Power Wells */
> -#define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
> -#define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
> -#define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */
> -#define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */
> +#define HSW_PWR_WELL_BIOS			_REG(0x45400) /* CTL1 */
> +#define HSW_PWR_WELL_DRIVER			_REG(0x45404) /* CTL2 */
> +#define HSW_PWR_WELL_KVMR			_REG(0x45408) /* CTL3 */
> +#define HSW_PWR_WELL_DEBUG			_REG(0x4540C) /* CTL4 */
>  #define   HSW_PWR_WELL_ENABLE_REQUEST		(1<<31)
>  #define   HSW_PWR_WELL_STATE_ENABLED		(1<<30)
> -#define HSW_PWR_WELL_CTL5			0x45410
> +#define HSW_PWR_WELL_CTL5			_REG(0x45410)
>  #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
>  #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
>  #define   HSW_PWR_WELL_FORCE_ON			(1<<19)
> -#define HSW_PWR_WELL_CTL6			0x45414
> +#define HSW_PWR_WELL_CTL6			_REG(0x45414)
>  
>  /* SKL Fuse Status */
> -#define SKL_FUSE_STATUS				0x42000
> +#define SKL_FUSE_STATUS				_REG(0x42000)
>  #define  SKL_FUSE_DOWNLOAD_STATUS              (1<<31)
>  #define  SKL_FUSE_PG0_DIST_STATUS              (1<<27)
>  #define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)
> @@ -7127,7 +7106,7 @@ enum skl_disp_power_wells {
>  #define _TRANS_DDI_FUNC_CTL_B		0x61400
>  #define _TRANS_DDI_FUNC_CTL_C		0x62400
>  #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
> -#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, _TRANS_DDI_FUNC_CTL_A)
> +#define TRANS_DDI_FUNC_CTL(tran) _REG_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
>  
>  #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
>  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
> @@ -7159,7 +7138,7 @@ enum skl_disp_power_wells {
>  /* DisplayPort Transport Control */
>  #define _DP_TP_CTL_A			0x64040
>  #define _DP_TP_CTL_B			0x64140
> -#define DP_TP_CTL(port) _PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
> +#define DP_TP_CTL(port) _REG_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
>  #define  DP_TP_CTL_ENABLE			(1<<31)
>  #define  DP_TP_CTL_MODE_SST			(0<<27)
>  #define  DP_TP_CTL_MODE_MST			(1<<27)
> @@ -7177,7 +7156,7 @@ enum skl_disp_power_wells {
>  /* DisplayPort Transport Status */
>  #define _DP_TP_STATUS_A			0x64044
>  #define _DP_TP_STATUS_B			0x64144
> -#define DP_TP_STATUS(port) _PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
> +#define DP_TP_STATUS(port) _REG_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
>  #define  DP_TP_STATUS_IDLE_DONE			(1<<25)
>  #define  DP_TP_STATUS_ACT_SENT			(1<<24)
>  #define  DP_TP_STATUS_MODE_STATUS_MST		(1<<23)
> @@ -7189,7 +7168,7 @@ enum skl_disp_power_wells {
>  /* DDI Buffer Control */
>  #define _DDI_BUF_CTL_A				0x64000
>  #define _DDI_BUF_CTL_B				0x64100
> -#define DDI_BUF_CTL(port) _PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
> +#define DDI_BUF_CTL(port) _REG_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
>  #define  DDI_BUF_CTL_ENABLE			(1<<31)
>  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
>  #define  DDI_BUF_EMP_MASK			(0xf<<24)
> @@ -7204,15 +7183,15 @@ enum skl_disp_power_wells {
>  /* DDI Buffer Translations */
>  #define _DDI_BUF_TRANS_A		0x64E00
>  #define _DDI_BUF_TRANS_B		0x64E60
> -#define DDI_BUF_TRANS_LO(port, i)	 (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
> -#define DDI_BUF_TRANS_HI(port, i)	 (_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> +#define DDI_BUF_TRANS_LO(port, i)	_REG(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
> +#define DDI_BUF_TRANS_HI(port, i)	_REG(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>  
>  /* Sideband Interface (SBI) is programmed indirectly, via
>   * SBI_ADDR, which contains the register offset; and SBI_DATA,
>   * which contains the payload */
> -#define SBI_ADDR			0xC6000
> -#define SBI_DATA			0xC6004
> -#define SBI_CTL_STAT			0xC6008
> +#define SBI_ADDR			_REG(0xC6000)
> +#define SBI_DATA			_REG(0xC6004)
> +#define SBI_CTL_STAT			_REG(0xC6008)
>  #define  SBI_CTL_DEST_ICLK		(0x0<<16)
>  #define  SBI_CTL_DEST_MPHY		(0x1<<16)
>  #define  SBI_CTL_OP_IORD		(0x2<<8)
> @@ -7243,12 +7222,12 @@ enum skl_disp_power_wells {
>  #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1<<0)
>  
>  /* LPT PIXCLK_GATE */
> -#define PIXCLK_GATE			0xC6020
> +#define PIXCLK_GATE			_REG(0xC6020)
>  #define  PIXCLK_GATE_UNGATE		(1<<0)
>  #define  PIXCLK_GATE_GATE		(0<<0)
>  
>  /* SPLL */
> -#define SPLL_CTL			0x46020
> +#define SPLL_CTL			_REG(0x46020)
>  #define  SPLL_PLL_ENABLE		(1<<31)
>  #define  SPLL_PLL_SSC			(1<<28)
>  #define  SPLL_PLL_NON_SSC		(2<<28)
> @@ -7262,7 +7241,7 @@ enum skl_disp_power_wells {
>  /* WRPLL */
>  #define _WRPLL_CTL1			0x46040
>  #define _WRPLL_CTL2			0x46060
> -#define WRPLL_CTL(pll)			_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
> +#define WRPLL_CTL(pll)			_REG_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
>  #define  WRPLL_PLL_ENABLE		(1<<31)
>  #define  WRPLL_PLL_SSC			(1<<28)
>  #define  WRPLL_PLL_NON_SSC		(2<<28)
> @@ -7281,7 +7260,7 @@ enum skl_disp_power_wells {
>  /* Port clock selection */
>  #define _PORT_CLK_SEL_A			0x46100
>  #define _PORT_CLK_SEL_B			0x46104
> -#define PORT_CLK_SEL(port) _PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
> +#define PORT_CLK_SEL(port) _REG_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
>  #define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
>  #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
>  #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
> @@ -7295,7 +7274,7 @@ enum skl_disp_power_wells {
>  /* Transcoder clock selection */
>  #define _TRANS_CLK_SEL_A		0x46140
>  #define _TRANS_CLK_SEL_B		0x46144
> -#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
> +#define TRANS_CLK_SEL(tran) _REG_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
>  /* For each transcoder, we need to select the corresponding port clock */
>  #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
>  #define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
> @@ -7304,7 +7283,7 @@ enum skl_disp_power_wells {
>  #define _TRANSB_MSA_MISC		0x61410
>  #define _TRANSC_MSA_MISC		0x62410
>  #define _TRANS_EDP_MSA_MISC		0x6f410
> -#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, _TRANSA_MSA_MISC)
> +#define TRANS_MSA_MISC(tran) _REG_TRANS2(tran, _TRANSA_MSA_MISC)
>  
>  #define  TRANS_MSA_SYNC_CLK		(1<<0)
>  #define  TRANS_MSA_6_BPC		(0<<5)
> @@ -7314,7 +7293,7 @@ enum skl_disp_power_wells {
>  #define  TRANS_MSA_16_BPC		(4<<5)
>  
>  /* LCPLL Control */
> -#define LCPLL_CTL			0x130040
> +#define LCPLL_CTL			_REG(0x130040)
>  #define  LCPLL_PLL_DISABLE		(1<<31)
>  #define  LCPLL_PLL_LOCK			(1<<30)
>  #define  LCPLL_CLK_FREQ_MASK		(3<<26)
> @@ -7334,7 +7313,7 @@ enum skl_disp_power_wells {
>   */
>  
>  /* CDCLK_CTL */
> -#define CDCLK_CTL			0x46000
> +#define CDCLK_CTL			_REG(0x46000)
>  #define  CDCLK_FREQ_SEL_MASK		(3<<26)
>  #define  CDCLK_FREQ_450_432		(0<<26)
>  #define  CDCLK_FREQ_540			(1<<26)
> @@ -7350,12 +7329,12 @@ enum skl_disp_power_wells {
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
>  
>  /* LCPLL_CTL */
> -#define LCPLL1_CTL		0x46010
> -#define LCPLL2_CTL		0x46014
> +#define LCPLL1_CTL		_REG(0x46010)
> +#define LCPLL2_CTL		_REG(0x46014)
>  #define  LCPLL_PLL_ENABLE	(1<<31)
>  
>  /* DPLL control1 */
> -#define DPLL_CTRL1		0x6C058
> +#define DPLL_CTRL1		_REG(0x6C058)
>  #define  DPLL_CTRL1_HDMI_MODE(id)		(1<<((id)*6+5))
>  #define  DPLL_CTRL1_SSC(id)			(1<<((id)*6+4))
>  #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7<<((id)*6+1))
> @@ -7370,7 +7349,7 @@ enum skl_disp_power_wells {
>  #define  DPLL_CTRL1_LINK_RATE_2160		5
>  
>  /* DPLL control2 */
> -#define DPLL_CTRL2				0x6C05C
> +#define DPLL_CTRL2				_REG(0x6C05C)
>  #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<((port)+15))
>  #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
>  #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
> @@ -7378,7 +7357,7 @@ enum skl_disp_power_wells {
>  #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
>  
>  /* DPLL Status */
> -#define DPLL_STATUS	0x6C060
> +#define DPLL_STATUS	_REG(0x6C060)
>  #define  DPLL_LOCK(id) (1<<((id)*8))
>  
>  /* DPLL cfg */
> @@ -7410,32 +7389,32 @@ enum skl_disp_power_wells {
>  #define  DPLL_CFGCR2_PDIV_7 (4<<2)
>  #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
>  
> -#define DPLL_CFGCR1(id)	_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
> -#define DPLL_CFGCR2(id)	_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> +#define DPLL_CFGCR1(id)	_REG_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR2)
> +#define DPLL_CFGCR2(id)	_REG_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
>  
>  /* BXT display engine PLL */
> -#define BXT_DE_PLL_CTL			0x6d000
> +#define BXT_DE_PLL_CTL			_REG(0x6d000)
>  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
>  #define   BXT_DE_PLL_RATIO_MASK		0xff
>  
> -#define BXT_DE_PLL_ENABLE		0x46070
> +#define BXT_DE_PLL_ENABLE		_REG(0x46070)
>  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
>  #define   BXT_DE_PLL_LOCK		(1 << 30)
>  
>  /* GEN9 DC */
> -#define DC_STATE_EN			0x45504
> +#define DC_STATE_EN			_REG(0x45504)
>  #define  DC_STATE_EN_UPTO_DC5		(1<<0)
>  #define  DC_STATE_EN_DC9		(1<<3)
>  #define  DC_STATE_EN_UPTO_DC6		(2<<0)
>  #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
>  
> -#define  DC_STATE_DEBUG                  0x45520
> +#define  DC_STATE_DEBUG                  _REG(0x45520)
>  #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1<<1)
>  
>  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>   * since on HSW we can't write to it using I915_WRITE. */
> -#define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
> -#define D_COMP_BDW			0x138144
> +#define D_COMP_HSW			_REG(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
> +#define D_COMP_BDW			_REG(0x138144)
>  #define  D_COMP_RCOMP_IN_PROGRESS	(1<<9)
>  #define  D_COMP_COMP_FORCE		(1<<8)
>  #define  D_COMP_COMP_DISABLE		(1<<0)
> @@ -7443,25 +7422,24 @@ enum skl_disp_power_wells {
>  /* Pipe WM_LINETIME - watermark line time */
>  #define _PIPE_WM_LINETIME_A		0x45270
>  #define _PIPE_WM_LINETIME_B		0x45274
> -#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, _PIPE_WM_LINETIME_A, \
> -					   _PIPE_WM_LINETIME_B)
> +#define PIPE_WM_LINETIME(pipe) _REG_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
>  #define   PIPE_WM_LINETIME_MASK			(0x1ff)
>  #define   PIPE_WM_LINETIME_TIME(x)		((x))
>  #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
>  #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x)<<16)
>  
>  /* SFUSE_STRAP */
> -#define SFUSE_STRAP			0xc2014
> +#define SFUSE_STRAP			_REG(0xc2014)
>  #define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
>  #define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
>  #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
>  #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
>  #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
>  
> -#define WM_MISC				0x45260
> +#define WM_MISC				_REG(0x45260)
>  #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
>  
> -#define WM_DBG				0x45280
> +#define WM_DBG				_REG(0x45280)
>  #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
>  #define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
>  #define  WM_DBG_DISALLOW_SPRITE		(1<<2)
> @@ -7498,27 +7476,28 @@ enum skl_disp_power_wells {
>  #define _PIPE_B_CSC_POSTOFF_ME	0x49144
>  #define _PIPE_B_CSC_POSTOFF_LO	0x49148
>  
> -#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
> -#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
> -#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
> -#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
> -#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
> -#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
> -#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
> -#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
> -#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
> -#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
> -#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
> -#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> -#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
> +#define PIPE_CSC_COEFF_RY_GY(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
> +#define PIPE_CSC_COEFF_BY(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
> +#define PIPE_CSC_COEFF_RU_GU(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
> +#define PIPE_CSC_COEFF_BU(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
> +#define PIPE_CSC_COEFF_RV_GV(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
> +#define PIPE_CSC_COEFF_BV(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
> +#define PIPE_CSC_MODE(pipe)		_REG_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
> +#define PIPE_CSC_PREOFF_HI(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
> +#define PIPE_CSC_PREOFF_ME(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
> +#define PIPE_CSC_PREOFF_LO(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
> +#define PIPE_CSC_POSTOFF_HI(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
> +#define PIPE_CSC_POSTOFF_ME(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> +#define PIPE_CSC_POSTOFF_LO(pipe)	_REG_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>  
>  /* MIPI DSI registers */
>  
> -#define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
> +#define _MIPI(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
> +#define _REG_MIPI(port, a, c)	_REG(_MIPI(port, a, c))
>  
>  #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
>  #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
> -#define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
> +#define MIPI_PORT_CTRL(port)	_REG_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
>  #define  DPI_ENABLE					(1 << 31) /* A + C */
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
> @@ -7561,8 +7540,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
>  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
> -#define MIPI_TEARING_CTRL(port)			_MIPI_PORT(port, \
> -				_MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
> +#define MIPI_TEARING_CTRL(port)			_REG_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
>  #define  TEARING_EFFECT_DELAY_SHIFT			0
>  #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
>  
> @@ -7573,8 +7551,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
>  #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
> -#define MIPI_DEVICE_READY(port)		_MIPI_PORT(port, _MIPIA_DEVICE_READY, \
> -						_MIPIC_DEVICE_READY)
> +#define MIPI_DEVICE_READY(port)		_REG_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
>  #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
>  #define  ULPS_STATE_MASK				(3 << 1)
>  #define  ULPS_STATE_ENTER				(2 << 1)
> @@ -7584,12 +7561,10 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
>  #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
> -#define MIPI_INTR_STAT(port)		_MIPI_PORT(port, _MIPIA_INTR_STAT, \
> -					_MIPIC_INTR_STAT)
> +#define MIPI_INTR_STAT(port)		_REG_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
>  #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
>  #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
> -#define MIPI_INTR_EN(port)		_MIPI_PORT(port, _MIPIA_INTR_EN, \
> -					_MIPIC_INTR_EN)
> +#define MIPI_INTR_EN(port)		_REG_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
>  #define  TEARING_EFFECT					(1 << 31)
>  #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
>  #define  GEN_READ_DATA_AVAIL				(1 << 29)
> @@ -7625,8 +7600,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
>  #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
> -#define MIPI_DSI_FUNC_PRG(port)		_MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
> -						_MIPIC_DSI_FUNC_PRG)
> +#define MIPI_DSI_FUNC_PRG(port)		_REG_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
>  #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
>  #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
>  #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
> @@ -7649,32 +7623,27 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
>  #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
> -#define MIPI_HS_TX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
> -					_MIPIC_HS_TX_TIMEOUT)
> +#define MIPI_HS_TX_TIMEOUT(port)	_REG_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
>  #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
>  
>  #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
>  #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
> -#define MIPI_LP_RX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
> -					_MIPIC_LP_RX_TIMEOUT)
> +#define MIPI_LP_RX_TIMEOUT(port)	_REG_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
>  #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
>  
>  #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
>  #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
> -#define MIPI_TURN_AROUND_TIMEOUT(port)	_MIPI_PORT(port, \
> -			_MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
> +#define MIPI_TURN_AROUND_TIMEOUT(port)	_REG_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
>  #define  TURN_AROUND_TIMEOUT_MASK			0x3f
>  
>  #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
>  #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
> -#define MIPI_DEVICE_RESET_TIMER(port)	_MIPI_PORT(port, \
> -			_MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
> +#define MIPI_DEVICE_RESET_TIMER(port)	_REG_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
>  #define  DEVICE_RESET_TIMER_MASK			0xffff
>  
>  #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
>  #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
> -#define MIPI_DPI_RESOLUTION(port)	_MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
> -					_MIPIC_DPI_RESOLUTION)
> +#define MIPI_DPI_RESOLUTION(port)	_REG_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
>  #define  VERTICAL_ADDRESS_SHIFT				16
>  #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
>  #define  HORIZONTAL_ADDRESS_SHIFT			0
> @@ -7682,8 +7651,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
>  #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
> -#define MIPI_DBI_FIFO_THROTTLE(port)	_MIPI_PORT(port, \
> -			_MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
> +#define MIPI_DBI_FIFO_THROTTLE(port)	_REG_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
>  #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
>  #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
>  #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
> @@ -7691,50 +7659,41 @@ enum skl_disp_power_wells {
>  /* regs below are bits 15:0 */
>  #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
>  #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
> -#define MIPI_HSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \
> -			_MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
> +#define MIPI_HSYNC_PADDING_COUNT(port)	_REG_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
>  
>  #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
>  #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
> -#define MIPI_HBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HBP_COUNT, \
> -					_MIPIC_HBP_COUNT)
> +#define MIPI_HBP_COUNT(port)		_REG_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
>  
>  #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
>  #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
> -#define MIPI_HFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HFP_COUNT, \
> -					_MIPIC_HFP_COUNT)
> +#define MIPI_HFP_COUNT(port)		_REG_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
>  
>  #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
>  #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
> -#define MIPI_HACTIVE_AREA_COUNT(port)	_MIPI_PORT(port, \
> -			_MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
> +#define MIPI_HACTIVE_AREA_COUNT(port)	_REG_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
>  
>  #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
>  #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
> -#define MIPI_VSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \
> -			_MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
> +#define MIPI_VSYNC_PADDING_COUNT(port)	_REG_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
>  
>  #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
>  #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
> -#define MIPI_VBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VBP_COUNT, \
> -					_MIPIC_VBP_COUNT)
> +#define MIPI_VBP_COUNT(port)		_REG_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
>  
>  #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
>  #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
> -#define MIPI_VFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VFP_COUNT, \
> -					_MIPIC_VFP_COUNT)
> +#define MIPI_VFP_COUNT(port)		_REG_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
>  
>  #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
>  #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
> -#define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MIPI_PORT(port,	\
> -		_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
> +#define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_REG_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
>  
>  /* regs above are bits 15:0 */
>  
>  #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
>  #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
> -#define MIPI_DPI_CONTROL(port)		_MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
> -					_MIPIC_DPI_CONTROL)
> +#define MIPI_DPI_CONTROL(port)		_REG_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
>  #define  DPI_LP_MODE					(1 << 6)
>  #define  BACKLIGHT_OFF					(1 << 5)
>  #define  BACKLIGHT_ON					(1 << 4)
> @@ -7745,29 +7704,26 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
>  #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
> -#define MIPI_DPI_DATA(port)		_MIPI_PORT(port, _MIPIA_DPI_DATA, \
> -					_MIPIC_DPI_DATA)
> +#define MIPI_DPI_DATA(port)		_REG_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
>  #define  COMMAND_BYTE_SHIFT				0
>  #define  COMMAND_BYTE_MASK				(0x3f << 0)
>  
>  #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
>  #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
> -#define MIPI_INIT_COUNT(port)		_MIPI_PORT(port, _MIPIA_INIT_COUNT, \
> -					_MIPIC_INIT_COUNT)
> +#define MIPI_INIT_COUNT(port)		_REG_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
>  #define  MASTER_INIT_TIMER_SHIFT			0
>  #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
>  
>  #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
>  #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
> -#define MIPI_MAX_RETURN_PKT_SIZE(port)	_MIPI_PORT(port, \
> +#define MIPI_MAX_RETURN_PKT_SIZE(port)	_REG_MIPI(port, \
>  			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
>  #define  MAX_RETURN_PKT_SIZE_SHIFT			0
>  #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
>  
>  #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
>  #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
> -#define MIPI_VIDEO_MODE_FORMAT(port)	_MIPI_PORT(port, \
> -			_MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
> +#define MIPI_VIDEO_MODE_FORMAT(port)	_REG_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
>  #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
>  #define  DISABLE_VIDEO_BTA				(1 << 3)
>  #define  IP_TG_CONFIG					(1 << 2)
> @@ -7777,8 +7733,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
>  #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
> -#define MIPI_EOT_DISABLE(port)		_MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
> -					_MIPIC_EOT_DISABLE)
> +#define MIPI_EOT_DISABLE(port)		_REG_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
>  #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
>  #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
>  #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
> @@ -7790,31 +7745,26 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
>  #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
> -#define MIPI_LP_BYTECLK(port)		_MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
> -					_MIPIC_LP_BYTECLK)
> +#define MIPI_LP_BYTECLK(port)		_REG_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
>  #define  LP_BYTECLK_SHIFT				0
>  #define  LP_BYTECLK_MASK				(0xffff << 0)
>  
>  /* bits 31:0 */
>  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
>  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
> -#define MIPI_LP_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
> -					_MIPIC_LP_GEN_DATA)
> +#define MIPI_LP_GEN_DATA(port)		_REG_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
>  
>  /* bits 31:0 */
>  #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
>  #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
> -#define MIPI_HS_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
> -					_MIPIC_HS_GEN_DATA)
> +#define MIPI_HS_GEN_DATA(port)		_REG_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
>  
>  #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
>  #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
> -#define MIPI_LP_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
> -					_MIPIC_LP_GEN_CTRL)
> +#define MIPI_LP_GEN_CTRL(port)		_REG_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
>  #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
>  #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
> -#define MIPI_HS_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
> -					_MIPIC_HS_GEN_CTRL)
> +#define MIPI_HS_GEN_CTRL(port)		_REG_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
>  #define  LONG_PACKET_WORD_COUNT_SHIFT			8
>  #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
>  #define  SHORT_PACKET_PARAM_SHIFT			8
> @@ -7827,8 +7777,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
>  #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
> -#define MIPI_GEN_FIFO_STAT(port)	_MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
> -					_MIPIC_GEN_FIFO_STAT)
> +#define MIPI_GEN_FIFO_STAT(port)	_REG_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
>  #define  DPI_FIFO_EMPTY					(1 << 28)
>  #define  DBI_FIFO_EMPTY					(1 << 27)
>  #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
> @@ -7846,16 +7795,14 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
>  #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
> -#define MIPI_HS_LP_DBI_ENABLE(port)	_MIPI_PORT(port, \
> -			_MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
> +#define MIPI_HS_LP_DBI_ENABLE(port)	_REG_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
>  #define  DBI_HS_LP_MODE_MASK				(1 << 0)
>  #define  DBI_LP_MODE					(1 << 0)
>  #define  DBI_HS_MODE					(0 << 0)
>  
>  #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
>  #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
> -#define MIPI_DPHY_PARAM(port)		_MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
> -					_MIPIC_DPHY_PARAM)
> +#define MIPI_DPHY_PARAM(port)		_REG_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
>  #define  EXIT_ZERO_COUNT_SHIFT				24
>  #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
>  #define  TRAIL_COUNT_SHIFT				16
> @@ -7868,15 +7815,11 @@ enum skl_disp_power_wells {
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
> -#define MIPI_DBI_BW_CTRL(port)		_MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
> -					_MIPIC_DBI_BW_CTRL)
> -
> -#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \
> -							+ 0xb088)
> -#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \
> -							+ 0xb888)
> -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MIPI_PORT(port, \
> -	_MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
> +#define MIPI_DBI_BW_CTRL(port)		_REG_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
> +
> +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
> +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
> +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_REG_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
>  #define  LP_HS_SSW_CNT_SHIFT				16
>  #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
>  #define  HS_LP_PWR_SW_CNT_SHIFT				0
> @@ -7884,19 +7827,16 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
>  #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
> -#define MIPI_STOP_STATE_STALL(port)	_MIPI_PORT(port, \
> -			_MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
> +#define MIPI_STOP_STATE_STALL(port)	_REG_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
>  #define  STOP_STATE_STALL_COUNTER_SHIFT			0
>  #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
>  
>  #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
>  #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
> -#define MIPI_INTR_STAT_REG_1(port)	_MIPI_PORT(port, \
> -				_MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
> +#define MIPI_INTR_STAT_REG_1(port)	_REG_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
>  #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
>  #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
> -#define MIPI_INTR_EN_REG_1(port)	_MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
> -					_MIPIC_INTR_EN_REG_1)
> +#define MIPI_INTR_EN_REG_1(port)	_REG_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
>  #define  RX_CONTENTION_DETECTED				(1 << 0)
>  
>  /* XXX: only pipe A ?!? */
> @@ -7916,8 +7856,7 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
>  #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
> -#define MIPI_CTRL(port)			_MIPI_PORT(port, _MIPIA_CTRL, \
> -					_MIPIC_CTRL)
> +#define MIPI_CTRL(port)			_REG_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
>  #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
>  #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
>  #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
> @@ -7931,23 +7870,20 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
>  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
> -#define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
> -					_MIPIC_DATA_ADDRESS)
> +#define MIPI_DATA_ADDRESS(port)		_REG_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
>  #define  DATA_MEM_ADDRESS_SHIFT				5
>  #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
>  #define  DATA_VALID					(1 << 0)
>  
>  #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
>  #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
> -#define MIPI_DATA_LENGTH(port)		_MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
> -					_MIPIC_DATA_LENGTH)
> +#define MIPI_DATA_LENGTH(port)		_REG_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
>  #define  DATA_LENGTH_SHIFT				0
>  #define  DATA_LENGTH_MASK				(0xfffff << 0)
>  
>  #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
>  #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
> -#define MIPI_COMMAND_ADDRESS(port)	_MIPI_PORT(port, \
> -				_MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
> +#define MIPI_COMMAND_ADDRESS(port)	_REG_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
>  #define  COMMAND_MEM_ADDRESS_SHIFT			5
>  #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
>  #define  AUTO_PWG_ENABLE				(1 << 2)
> @@ -7956,21 +7892,17 @@ enum skl_disp_power_wells {
>  
>  #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
>  #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
> -#define MIPI_COMMAND_LENGTH(port)	_MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
> -					_MIPIC_COMMAND_LENGTH)
> +#define MIPI_COMMAND_LENGTH(port)	_REG_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
>  #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
>  #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
>  
>  #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
>  #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
> -#define MIPI_READ_DATA_RETURN(port, n) \
> -	(_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
> -					+ 4 * (n)) /* n: 0...7 */
> +#define MIPI_READ_DATA_RETURN(port, n) _REG(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
>  
>  #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
>  #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
> -#define MIPI_READ_DATA_VALID(port)	_MIPI_PORT(port, \
> -				_MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
> +#define MIPI_READ_DATA_VALID(port)	_REG_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
>  #define  READ_DATA_VALID(n)				(1 << (n))
>  
>  /* For UMS only (deprecated): */
> @@ -7986,4 +7918,27 @@ enum skl_disp_power_wells {
>  #define GEN9_VEBOX_MOCS_0	0xcb00	/* Video MOCS base register*/
>  #define GEN9_BLT_MOCS_0		0xcc00	/* Blitter MOCS base register*/
>  
> +/*
> +* SKL CSR registers for DC5 and DC6
> +*/
> +#define CSR_PROGRAM(i)			_REG(0x80000 + (i) * 4)
> +#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
> +#define CSR_HTP_ADDR_SKL		0x00500034
> +#define CSR_SSP_BASE			_REG(0x8F074)
> +#define CSR_HTP_SKL			_REG(0x8F004)
> +#define CSR_LAST_WRITE			_REG(0x8F034)
> +#define CSR_LAST_WRITE_VALUE		0xc003b400
> +
> +/* Execlists regs */
> +#define RING_ELSP(ring)				_REG((ring)->mmio_base + 0x230)
> +#define RING_EXECLIST_STATUS_LO(ring)		_REG((ring)->mmio_base + 0x234)
> +#define RING_EXECLIST_STATUS_HI(ring)		_REG((ring)->mmio_base + 0x234 + 4)
> +#define RING_CONTEXT_CONTROL(ring)		_REG((ring)->mmio_base + 0x244)
> +#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
> +#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
> +#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
> +#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_REG((ring)->mmio_base + 0x370 + (i) * 8)
> +#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_REG((ring)->mmio_base + 0x370 + (i) * 8 + 4)
> +#define RING_CONTEXT_STATUS_PTR(ring)		_REG((ring)->mmio_base + 0x3a0)
> +
>  #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 55bd04c..602d8a4 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -35,7 +35,8 @@
>  #define dev_to_drm_minor(d) dev_get_drvdata((d))
>  
>  #ifdef CONFIG_PM
> -static u32 calc_residency(struct drm_device *dev, const u32 reg)
> +static u32 calc_residency(struct drm_device *dev,
> +			  struct i915_reg reg)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u64 raw_time; /* 32b value may overflow during fixed point math */
> @@ -49,7 +50,8 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
>  
>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>  	if (IS_VALLEYVIEW(dev)) {
> -		u32 clk_reg, czcount_30ns;
> +		struct i915_reg clk_reg;
> +		u32 czcount_30ns;
>  
>  		if (IS_CHERRYVIEW(dev))
>  			clk_reg = CHV_CLK_CTL1;
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index d0993bc..9a5fa88 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -644,7 +644,7 @@ TRACE_EVENT(i915_flip_complete,
>  );
>  
>  TRACE_EVENT_CONDITION(i915_reg_rw,
> -	TP_PROTO(bool write, u32 reg, u64 val, int len, bool trace),
> +	TP_PROTO(bool write, struct i915_reg reg, u64 val, int len, bool trace),
>  
>  	TP_ARGS(write, reg, val, len, trace),
>  
> @@ -659,7 +659,7 @@ TRACE_EVENT_CONDITION(i915_reg_rw,
>  
>  	TP_fast_assign(
>  		__entry->val = (u64)val;
> -		__entry->reg = reg;
> +		__entry->reg = reg.reg;
>  		__entry->write = write;
>  		__entry->len = len;
>  		),
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 5eee75b..31edb68 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -69,13 +69,13 @@ void i915_check_vgpu(struct drm_device *dev)
>  	if (!IS_HASWELL(dev))
>  		return;
>  
> -	magic = readq(dev_priv->regs + vgtif_reg(magic));
> +	magic = readq(dev_priv->regs + vgtif_reg(magic).reg);
>  	if (magic != VGT_MAGIC)
>  		return;
>  
>  	version = INTEL_VGT_IF_VERSION_ENCODE(
> -		readw(dev_priv->regs + vgtif_reg(version_major)),
> -		readw(dev_priv->regs + vgtif_reg(version_minor)));
> +		readw(dev_priv->regs + vgtif_reg(version_major).reg),
> +		readw(dev_priv->regs + vgtif_reg(version_minor).reg));
>  	if (version != INTEL_VGT_IF_VERSION) {
>  		DRM_INFO("VGT interface version mismatch!\n");
>  		return;
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 21c97f4..25d4829 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -108,7 +108,7 @@ struct vgt_if {
>  } __packed;
>  
>  #define vgtif_reg(x) \
> -	(VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)
> +	_REG((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
>  
>  /* vGPU display status to be used by the host side */
>  #define VGT_DRV_DISPLAY_NOT_READY 0
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index e35997e..19711f7 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -91,9 +91,9 @@ static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
>  }
>  
>  static bool intel_eld_uptodate(struct drm_connector *connector,
> -			       int reg_eldv, uint32_t bits_eldv,
> -			       int reg_elda, uint32_t bits_elda,
> -			       int reg_edid)
> +			       struct i915_reg reg_eldv, uint32_t bits_eldv,
> +			       struct i915_reg reg_elda, uint32_t bits_elda,
> +			       struct i915_reg reg_edid)
>  {
>  	struct drm_i915_private *dev_priv = connector->dev->dev_private;
>  	uint8_t *eld = connector->eld;
> @@ -264,8 +264,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder)
>  	enum port port = intel_dig_port->port;
>  	enum pipe pipe = intel_crtc->pipe;
>  	uint32_t tmp, eldv;
> -	int aud_config;
> -	int aud_cntrl_st2;
> +	struct i915_reg aud_config, aud_cntrl_st2;
>  
>  	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
>  		      port_name(port), pipe_name(pipe));
> @@ -316,10 +315,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
>  	uint32_t eldv;
>  	uint32_t tmp;
>  	int len, i;
> -	int hdmiw_hdmiedid;
> -	int aud_config;
> -	int aud_cntl_st;
> -	int aud_cntrl_st2;
> +	struct i915_reg hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
>  
>  	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
>  		      port_name(port), pipe_name(pipe), drm_eld_size(eld));
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 086b5c5..588714c 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -50,7 +50,7 @@ struct intel_crt {
>  	 * encoder's enable/disable callbacks */
>  	struct intel_connector *connector;
>  	bool force_hotplug_required;
> -	u32 adpa_reg;
> +	struct i915_reg adpa_reg;
>  };
>  
>  static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
> @@ -502,12 +502,8 @@ intel_crt_load_detect(struct intel_crt *crt)
>  	uint32_t vsample;
>  	uint32_t vblank, vblank_start, vblank_end;
>  	uint32_t dsl;
> -	uint32_t bclrpat_reg;
> -	uint32_t vtotal_reg;
> -	uint32_t vblank_reg;
> -	uint32_t vsync_reg;
> -	uint32_t pipeconf_reg;
> -	uint32_t pipe_dsl_reg;
> +	struct i915_reg bclrpat_reg, vtotal_reg,
> +		vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
>  	uint8_t	st00;
>  	enum drm_connector_status status;
>  
> @@ -540,7 +536,7 @@ intel_crt_load_detect(struct intel_crt *crt)
>  		/* Wait for next Vblank to substitue
>  		 * border color for Color info */
>  		intel_wait_for_vblank(dev, pipe);
> -		st00 = I915_READ8(VGA_MSR_WRITE);
> +		st00 = I915_READ8(_VGA_MSR_WRITE);
>  		status = ((st00 & (1 << 4)) != 0) ?
>  			connector_status_connected :
>  			connector_status_disconnected;
> @@ -585,7 +581,7 @@ intel_crt_load_detect(struct intel_crt *crt)
>  		do {
>  			count++;
>  			/* Read the ST00 VGA status register */
> -			st00 = I915_READ8(VGA_MSR_WRITE);
> +			st00 = I915_READ8(_VGA_MSR_WRITE);
>  			if (st00 & (1 << 4))
>  				detect++;
>  		} while ((I915_READ(pipe_dsl_reg) == dsl));
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 8174335..4fa026ef 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -45,16 +45,6 @@
>  
>  MODULE_FIRMWARE(I915_CSR_SKL);
>  
> -/*
> -* SKL CSR registers for DC5 and DC6
> -*/
> -#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
> -#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
> -#define CSR_HTP_ADDR_SKL		0x00500034
> -#define CSR_SSP_BASE			0x8F074
> -#define CSR_HTP_SKL			0x8F004
> -#define CSR_LAST_WRITE			0x8F034
> -#define CSR_LAST_WRITE_VALUE		0xc003b400
>  /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
>  #define CSR_MAX_FW_SIZE			0x2FFF
>  #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
> @@ -355,7 +345,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  						dmc_header->mmioaddr[i]);
>  			goto out;
>  		}
> -		csr->mmioaddr[i] = dmc_header->mmioaddr[i];
> +		csr->mmioaddr[i].reg = dmc_header->mmioaddr[i];
>  		csr->mmiodata[i] = dmc_header->mmiodata[i];
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index fb456a4..ab7c156 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -329,7 +329,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
>  static bool
>  intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
>  {
> -	return intel_dig_port->hdmi.hdmi_reg;
> +	return intel_dig_port->hdmi.hdmi_reg.reg;
>  }
>  
>  static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
> @@ -558,12 +558,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>  static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
>  				    enum port port)
>  {
> -	uint32_t reg = DDI_BUF_CTL(port);
>  	int i;
>  
>  	for (i = 0; i < 16; i++) {
>  		udelay(1);
> -		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
> +		if (I915_READ(DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE)
>  			return;
>  	}
>  	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
> @@ -913,7 +912,8 @@ static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
>  	/* Otherwise a < c && b >= d, do nothing */
>  }
>  
> -static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
> +static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
> +				   struct i915_reg reg)
>  {
>  	int refclk = LC_FREQ;
>  	int n, p, r;
> @@ -949,7 +949,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
>  static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>  			       uint32_t dpll)
>  {
> -	uint32_t cfgcr1_reg, cfgcr2_reg;
> +	struct i915_reg cfgcr1_reg, cfgcr2_reg;
>  	uint32_t cfgcr1_val, cfgcr2_val;
>  	uint32_t p0, p1, p2, dco_freq;
>  
> @@ -1912,7 +1912,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
>  void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>  				       enum transcoder cpu_transcoder)
>  {
> -	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> +	struct i915_reg reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
>  	uint32_t val = I915_READ(reg);
>  
>  	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> @@ -2055,7 +2055,7 @@ static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
>  	uint8_t iboost;
>  	uint8_t dp_iboost, hdmi_iboost;
>  	int n_entries;
> -	u32 reg;
> +	u32 val;
>  
>  	/* VBT may override standard boost values */
>  	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
> @@ -2092,16 +2092,16 @@ static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
>  		return;
>  	}
>  
> -	reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
> -	reg &= ~BALANCE_LEG_MASK(port);
> -	reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
> +	val = I915_READ(DISPIO_CR_TX_BMU_CR0);
> +	val &= ~BALANCE_LEG_MASK(port);
> +	val &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
>  
>  	if (iboost)
> -		reg |= iboost << BALANCE_LEG_SHIFT(port);
> +		val |= iboost << BALANCE_LEG_SHIFT(port);
>  	else
> -		reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
> +		val |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
>  
> -	I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
> +	I915_WRITE(DISPIO_CR_TX_BMU_CR0, val);
>  }
>  
>  static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> @@ -2472,7 +2472,7 @@ static const char * const skl_ddi_pll_names[] = {
>  };
>  
>  struct skl_dpll_regs {
> -	u32 ctl, cfgcr1, cfgcr2;
> +	struct i915_reg ctl, cfgcr1, cfgcr2;
>  };
>  
>  /* this array is indexed by the *shared* pll id */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 16e204d..7bc6c92 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1048,7 +1048,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
>  static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg = PIPEDSL(pipe);
> +	struct i915_reg reg = PIPEDSL(pipe);
>  	u32 line1, line2;
>  	u32 line_mask;
>  
> @@ -1088,7 +1088,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
>  	enum pipe pipe = crtc->pipe;
>  
>  	if (INTEL_INFO(dev)->gen >= 4) {
> -		int reg = PIPECONF(cpu_transcoder);
> +		struct i915_reg reg = PIPECONF(cpu_transcoder);
>  
>  		/* Wait for the Pipe State to go off */
>  		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
> @@ -1238,7 +1238,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
>  			   enum pipe pipe)
>  {
>  	struct drm_device *dev = dev_priv->dev;
> -	int pp_reg;
> +	struct i915_reg pp_reg;
>  	u32 val;
>  	enum pipe panel_pipe = PIPE_A;
>  	bool locked = true;
> @@ -1433,8 +1433,7 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
>  		return false;
>  
>  	if (HAS_PCH_CPT(dev_priv->dev)) {
> -		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
> -		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
> +		u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
>  		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
>  			return false;
>  	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
> @@ -1498,12 +1497,13 @@ static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
>  }
>  
>  static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> -				   enum pipe pipe, int reg, u32 port_sel)
> +				   enum pipe pipe, struct i915_reg reg,
> +				   u32 port_sel)
>  {
>  	u32 val = I915_READ(reg);
>  	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
>  	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
> -	     reg, pipe_name(pipe));
> +	     reg.reg, pipe_name(pipe));
>  
>  	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
>  	     && (val & DP_PIPEB_SELECT),
> @@ -1511,12 +1511,12 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
>  }
>  
>  static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> -				     enum pipe pipe, int reg)
> +				     enum pipe pipe, struct i915_reg reg)
>  {
>  	u32 val = I915_READ(reg);
>  	I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
>  	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
> -	     reg, pipe_name(pipe));
> +	     reg.reg, pipe_name(pipe));
>  
>  	I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
>  	     && (val & SDVO_PIPE_B_SELECT),
> @@ -1552,7 +1552,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int reg = DPLL(crtc->pipe);
> +	struct i915_reg reg = DPLL(crtc->pipe);
>  	u32 dpll = pipe_config->dpll_hw_state.dpll;
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -1641,7 +1641,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int reg = DPLL(crtc->pipe);
> +	struct i915_reg reg = DPLL(crtc->pipe);
>  	u32 dpll = crtc->config->dpll_hw_state.dpll;
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -1781,7 +1781,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  			 unsigned int expected_mask)
>  {
>  	u32 port_mask;
> -	int dpll_reg;
> +	struct i915_reg dpll_reg;
>  
>  	switch (dport->port) {
>  	case PORT_B:
> @@ -1906,7 +1906,8 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	struct drm_device *dev = dev_priv->dev;
>  	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	uint32_t reg, val, pipeconf_val;
> +	struct i915_reg reg;
> +	uint32_t val, pipeconf_val;
>  
>  	/* PCH only available on ILK+ */
>  	BUG_ON(!HAS_PCH_SPLIT(dev));
> @@ -1995,7 +1996,8 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
>  					    enum pipe pipe)
>  {
>  	struct drm_device *dev = dev_priv->dev;
> -	uint32_t reg, val;
> +	struct i915_reg reg;
> +	uint32_t val;
>  
>  	/* FDI relies on the transcoder */
>  	assert_fdi_tx_disabled(dev_priv, pipe);
> @@ -2053,7 +2055,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
>  	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
>  								      pipe);
>  	enum pipe pch_transcoder;
> -	int reg;
> +	struct i915_reg reg;
>  	u32 val;
>  
>  	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
> @@ -2114,7 +2116,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
>  	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
>  	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>  	enum pipe pipe = crtc->pipe;
> -	int reg;
>  	u32 val;
>  
>  	DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
> @@ -2127,8 +2128,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
>  	assert_cursor_disabled(dev_priv, pipe);
>  	assert_sprites_disabled(dev_priv, pipe);
>  
> -	reg = PIPECONF(cpu_transcoder);
> -	val = I915_READ(reg);
> +	val = I915_READ(PIPECONF(cpu_transcoder));
>  	if ((val & PIPECONF_ENABLE) == 0)
>  		return;
>  
> @@ -2144,7 +2144,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
>  	    !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
>  		val &= ~PIPECONF_ENABLE;
>  
> -	I915_WRITE(reg, val);
> +	I915_WRITE(PIPECONF(cpu_transcoder), val);
>  	if ((val & PIPECONF_ENABLE) == 0)
>  		intel_wait_for_pipe_off(crtc);
>  }
> @@ -2599,16 +2599,15 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	unsigned long linear_offset;
>  	u32 dspcntr;
> -	u32 reg = DSPCNTR(plane);
>  	int pixel_size;
>  
>  	if (!visible || !fb) {
> -		I915_WRITE(reg, 0);
> +		I915_WRITE(DSPCNTR(plane), 0);
>  		if (INTEL_INFO(dev)->gen >= 4)
>  			I915_WRITE(DSPSURF(plane), 0);
>  		else
>  			I915_WRITE(DSPADDR(plane), 0);
> -		POSTING_READ(reg);
> +		POSTING_READ(DSPCNTR(plane));
>  		return;
>  	}
>  
> @@ -2700,7 +2699,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  			(intel_crtc->config->pipe_src_w - 1) * pixel_size;
>  	}
>  
> -	I915_WRITE(reg, dspcntr);
> +	I915_WRITE(DSPCNTR(plane), dspcntr);
>  
>  	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
>  	if (INTEL_INFO(dev)->gen >= 4) {
> @@ -2710,7 +2709,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  		I915_WRITE(DSPLINOFF(plane), linear_offset);
>  	} else
>  		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
> -	POSTING_READ(reg);
> +	POSTING_READ(DSPCNTR(plane));
>  }
>  
>  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> @@ -2726,13 +2725,12 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	unsigned long linear_offset;
>  	u32 dspcntr;
> -	u32 reg = DSPCNTR(plane);
>  	int pixel_size;
>  
>  	if (!visible || !fb) {
> -		I915_WRITE(reg, 0);
> +		I915_WRITE(DSPCNTR(plane), 0);
>  		I915_WRITE(DSPSURF(plane), 0);
> -		POSTING_READ(reg);
> +		POSTING_READ(DSPCNTR(plane));
>  		return;
>  	}
>  
> @@ -2800,7 +2798,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  		}
>  	}
>  
> -	I915_WRITE(reg, dspcntr);
> +	I915_WRITE(DSPCNTR(plane), dspcntr);
>  
>  	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
>  	I915_WRITE(DSPSURF(plane),
> @@ -2811,7 +2809,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
>  		I915_WRITE(DSPLINOFF(plane), linear_offset);
>  	}
> -	POSTING_READ(reg);
> +	POSTING_READ(DSPCNTR(plane));
>  }
>  
>  u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
> @@ -3289,7 +3287,8 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp;
> +	struct i915_reg reg;
> +	u32 temp;
>  
>  	/* enable normal train */
>  	reg = FDI_TX_CTL(pipe);
> @@ -3331,7 +3330,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp, tries;
> +	struct i915_reg reg;
> +	u32 temp, tries;
>  
>  	/* FDI needs bits from pipe first */
>  	assert_pipe_enabled(dev_priv, pipe);
> @@ -3431,7 +3431,8 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp, i, retry;
> +	struct i915_reg reg;
> +	u32 temp, i, retry;
>  
>  	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
>  	   for train result */
> @@ -3563,7 +3564,8 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp, i, j;
> +	struct i915_reg reg;
> +	u32 temp, i, j;
>  
>  	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
>  	   for train result */
> @@ -3680,8 +3682,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp;
> -
> +	struct i915_reg reg;
> +	u32 temp;
>  
>  	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
>  	reg = FDI_RX_CTL(pipe);
> @@ -3717,7 +3719,8 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp;
> +	struct i915_reg reg;
> +	u32 temp;
>  
>  	/* Switch from PCDclk to Rawclk */
>  	reg = FDI_RX_CTL(pipe);
> @@ -3747,7 +3750,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp;
> +	struct i915_reg reg;
> +	u32 temp;
>  
>  	/* disable CPU FDI tx and PCH FDI rx */
>  	reg = FDI_TX_CTL(pipe);
> @@ -4037,7 +4041,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp;
> +	u32 temp;
>  
>  	assert_pch_transcoder_disabled(dev_priv, pipe);
>  
> @@ -4085,8 +4089,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	/* For PCH DP, enable TRANS_DP_CTL */
>  	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
>  		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> -		reg = TRANS_DP_CTL(pipe);
> -		temp = I915_READ(reg);
> +		temp = I915_READ(TRANS_DP_CTL(pipe));
>  		temp &= ~(TRANS_DP_PORT_SEL_MASK |
>  			  TRANS_DP_SYNC_MASK |
>  			  TRANS_DP_BPC_MASK);
> @@ -4099,20 +4102,20 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
>  
>  		switch (intel_trans_dp_port_sel(crtc)) {
> -		case PCH_DP_B:
> +		case _PCH_DP_B:
>  			temp |= TRANS_DP_PORT_SEL_B;
>  			break;
> -		case PCH_DP_C:
> +		case _PCH_DP_C:
>  			temp |= TRANS_DP_PORT_SEL_C;
>  			break;
> -		case PCH_DP_D:
> +		case _PCH_DP_D:
>  			temp |= TRANS_DP_PORT_SEL_D;
>  			break;
>  		default:
>  			BUG();
>  		}
>  
> -		I915_WRITE(reg, temp);
> +		I915_WRITE(TRANS_DP_CTL(pipe), temp);
>  	}
>  
>  	ironlake_enable_pch_transcoder(dev_priv, pipe);
> @@ -4242,7 +4245,7 @@ static void intel_shared_dpll_commit(struct drm_atomic_state *state)
>  static void cpt_verify_modeset(struct drm_device *dev, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int dslreg = PIPEDSL(pipe);
> +	struct i915_reg dslreg = PIPEDSL(pipe);
>  	u32 temp;
>  
>  	temp = I915_READ(dslreg);
> @@ -4553,7 +4556,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
>  	}
>  
>  	for (i = 0; i < 256; i++) {
> -		u32 palreg;
> +		struct i915_reg palreg;
>  
>  		if (HAS_GMCH_DISPLAY(dev))
>  			palreg = PALETTE(pipe, i);
> @@ -4961,7 +4964,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	u32 reg, temp;
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		encoder->disable(encoder);
> @@ -4987,6 +4989,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  		ironlake_disable_pch_transcoder(dev_priv, pipe);
>  
>  		if (HAS_PCH_CPT(dev)) {
> +			struct i915_reg reg;
> +			u32 temp;
> +
>  			/* disable TRANS_DP_CTL */
>  			reg = TRANS_DP_CTL(pipe);
>  			temp = I915_READ(reg);
> @@ -7288,7 +7293,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int pipe = crtc->pipe;
> -	int dpll_reg = DPLL(crtc->pipe);
> +	struct i915_reg dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> @@ -9826,7 +9831,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
>  	}
>  
>  	if (intel_crtc->cursor_base != base) {
> -		I915_WRITE(_CURABASE, base);
> +		I915_WRITE(CURBASE(PIPE_A), base);
>  		intel_crtc->cursor_base = base;
>  	}
>  
> @@ -10984,7 +10989,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
>  	 */
>  	if (ring->id == RCS) {
>  		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> -		intel_ring_emit(ring, DERRMR);
> +		intel_ring_emit(ring, DERRMR.reg);
>  		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
>  					DERRMR_PIPEB_PRI_FLIP_DONE |
>  					DERRMR_PIPEC_PRI_FLIP_DONE));
> @@ -10994,7 +10999,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
>  		else
>  			intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
>  					      MI_SRM_LRM_GLOBAL_GTT);
> -		intel_ring_emit(ring, DERRMR);
> +		intel_ring_emit(ring, DERRMR.reg);
>  		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
>  		if (IS_GEN8(dev)) {
>  			intel_ring_emit(ring, 0);
> @@ -11090,10 +11095,9 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	struct intel_framebuffer *intel_fb =
>  		to_intel_framebuffer(intel_crtc->base.primary->fb);
>  	struct drm_i915_gem_object *obj = intel_fb->obj;
> +	struct i915_reg reg = DSPCNTR(intel_crtc->plane);
>  	u32 dspcntr;
> -	u32 reg;
>  
> -	reg = DSPCNTR(intel_crtc->plane);
>  	dspcntr = I915_READ(reg);
>  
>  	if (obj->tiling_mode != I915_TILING_NONE)
> @@ -11106,7 +11110,6 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	I915_WRITE(DSPSURF(intel_crtc->plane),
>  		   intel_crtc->unpin_work->gtt_offset);
>  	POSTING_READ(DSPSURF(intel_crtc->plane));
> -
>  }
>  
>  /*
> @@ -14661,7 +14664,7 @@ static void i915_disable_vga(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u8 sr1;
> -	u32 vga_reg = i915_vgacntrl_reg(dev);
> +	struct i915_reg vga_reg = i915_vgacntrl_reg(dev);
>  
>  	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>  	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
> @@ -14834,13 +14837,12 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg, val;
> +	u32 val;
>  
>  	if (INTEL_INFO(dev)->num_pipes == 1)
>  		return true;
>  
> -	reg = DSPCNTR(!crtc->plane);
> -	val = I915_READ(reg);
> +	val = I915_READ(DSPCNTR(!crtc->plane));
>  
>  	if ((val & DISPLAY_PLANE_ENABLE) &&
>  	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
> @@ -14864,10 +14866,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg;
> +	struct i915_reg reg = PIPECONF(crtc->config->cpu_transcoder);
>  
>  	/* Clear any frame start delays used for debugging left by the BIOS */
> -	reg = PIPECONF(crtc->config->cpu_transcoder);
>  	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
>  
>  	/* restore vblank interrupts to correct state */
> @@ -15013,7 +15014,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
>  void i915_redisable_vga_power_on(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 vga_reg = i915_vgacntrl_reg(dev);
> +	struct i915_reg vga_reg = i915_vgacntrl_reg(dev);
>  
>  	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
>  		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0e5f674..6d7a3af 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -541,7 +541,8 @@ void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> -static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
> +static struct i915_reg
> +_pp_ctrl_reg(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  
> @@ -553,7 +554,8 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
>  		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
>  }
>  
> -static u32 _pp_stat_reg(struct intel_dp *intel_dp)
> +static struct i915_reg
> +_pp_stat_reg(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  
> @@ -574,8 +576,6 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  						 edp_notifier);
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 pp_div;
> -	u32 pp_ctrl_reg, pp_div_reg;
>  
>  	if (!is_edp(intel_dp) || code != SYS_RESTART)
>  		return 0;
> @@ -584,6 +584,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
> +		struct i915_reg pp_ctrl_reg, pp_div_reg;
> +		u32 pp_div;
>  
>  		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
>  		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
> @@ -652,7 +654,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
> +	struct i915_reg ch_ctl = intel_dp->aux_ch_ctl_reg;
>  	uint32_t status;
>  	bool done;
>  
> @@ -751,7 +753,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
>  	else
>  		precharge = 5;
>  
> -	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DP_AUX_CH_CTL(PORT_A))
> +	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg.reg == DP_AUX_CH_CTL(PORT_A).reg)
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
>  	else
>  		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -790,7 +792,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
> +	struct i915_reg ch_ctl = intel_dp->aux_ch_ctl_reg;
>  	uint32_t aux_clock_divider;
>  	int i, ret, recv_bytes;
>  	uint32_t status;
> @@ -1008,15 +1010,15 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
>  	return ret;
>  }
>  
> -static uint32_t g4x_aux_reg(struct drm_i915_private *dev_priv,
> -			    enum port port, int index)
> +static struct i915_reg g4x_aux_reg(struct drm_i915_private *dev_priv,
> +				   enum port port, int index)
>  {
>  	return index < 0 ? DP_AUX_CH_CTL(port) :
>  		DP_AUX_CH_DATA(port, index);
>  }
>  
> -static uint32_t ilk_aux_reg(struct drm_i915_private *dev_priv,
> -			    enum port port, int index)
> +static struct i915_reg ilk_aux_reg(struct drm_i915_private *dev_priv,
> +				   enum port port, int index)
>  {
>  	if (port == PORT_A)
>  		return index < 0 ? DP_AUX_CH_CTL(port) :
> @@ -1050,8 +1052,8 @@ static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> -static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
> -			    enum port port, int index)
> +static struct i915_reg skl_aux_reg(struct drm_i915_private *dev_priv,
> +				   enum port port, int index)
>  {
>  	if (port == PORT_E)
>  		port = skl_porte_aux_port(dev_priv);
> @@ -1061,8 +1063,8 @@ static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
>  }
>  
>  static void aux_reg_init(struct intel_dp *intel_dp,
> -			 uint32_t (*aux_reg)(struct drm_i915_private *dev_priv,
> -					     enum port port, int index))
> +			 struct i915_reg (*aux_reg)(struct drm_i915_private *dev_priv,
> +						    enum port port, int index))
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  	enum port port = dp_to_dig_port(intel_dp)->port;
> @@ -1702,7 +1704,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
>  {
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 pp_stat_reg, pp_ctrl_reg;
> +	struct i915_reg pp_stat_reg, pp_ctrl_reg;
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> @@ -1792,7 +1794,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum intel_display_power_domain power_domain;
>  	u32 pp;
> -	u32 pp_stat_reg, pp_ctrl_reg;
> +	struct i915_reg pp_stat_reg, pp_ctrl_reg;
>  	bool need_to_disable = !intel_dp->want_panel_vdd;
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
> @@ -1868,7 +1870,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
>  	struct intel_encoder *intel_encoder = &intel_dig_port->base;
>  	enum intel_display_power_domain power_domain;
>  	u32 pp;
> -	u32 pp_stat_reg, pp_ctrl_reg;
> +	struct i915_reg pp_stat_reg, pp_ctrl_reg;
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> @@ -1955,7 +1957,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> -	u32 pp_ctrl_reg;
> +	struct i915_reg pp_ctrl_reg;
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> @@ -2017,7 +2019,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum intel_display_power_domain power_domain;
>  	u32 pp;
> -	u32 pp_ctrl_reg;
> +	struct i915_reg pp_ctrl_reg;
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> @@ -2068,7 +2070,7 @@ static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> -	u32 pp_ctrl_reg;
> +	struct i915_reg pp_ctrl_reg;
>  
>  	/*
>  	 * If we enable the backlight right away following a panel power
> @@ -2109,7 +2111,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp;
> -	u32 pp_ctrl_reg;
> +	struct i915_reg pp_ctrl_reg;
>  
>  	if (!is_edp(intel_dp))
>  		return;
> @@ -2283,7 +2285,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  		}
>  
>  		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
> -			      intel_dp->output_reg);
> +			      intel_dp->output_reg.reg);
>  	} else if (IS_CHERRYVIEW(dev)) {
>  		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
>  	} else {
> @@ -2671,7 +2673,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
>  	enum pipe pipe = intel_dp->pps_pipe;
> -	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
> +	struct i915_reg pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
>  
>  	edp_panel_vdd_off_sync(intel_dp);
>  
> @@ -5256,7 +5258,7 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
>  
>  		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>  		    intel_encoder->type == INTEL_OUTPUT_EDP)
> -			return intel_dp->output_reg;
> +			return intel_dp->output_reg.reg;
>  	}
>  
>  	return -1;
> @@ -5326,7 +5328,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
>  	struct edp_power_seq cur, vbt, spec,
>  		*final = &intel_dp->pps_delays;
>  	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
> -	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
> +	struct i915_reg pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> @@ -5448,7 +5450,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 pp_on, pp_off, pp_div, port_sel = 0;
>  	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
> -	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
> +	struct i915_reg pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
>  	enum port port = dp_to_dig_port(intel_dp)->port;
>  	const struct edp_power_seq *seq = &intel_dp->pps_delays;
>  
> @@ -5548,7 +5550,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  	struct intel_dp *intel_dp = dev_priv->drrs.dp;
>  	struct intel_crtc_state *config = NULL;
>  	struct intel_crtc *intel_crtc = NULL;
> -	u32 reg, val;
>  	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>  
>  	if (refresh_rate <= 0) {
> @@ -5610,8 +5611,9 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  			DRM_ERROR("Unsupported refreshrate type\n");
>  		}
>  	} else if (INTEL_INFO(dev)->gen > 6) {
> -		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> -		val = I915_READ(reg);
> +		struct i915_reg reg =
> +			PIPECONF(intel_crtc->config->cpu_transcoder);
> +		u32 val = I915_READ(reg);
>  
>  		if (index > DRRS_HIGH_RR) {
>  			if (IS_VALLEYVIEW(dev))
> @@ -6167,7 +6169,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  }
>  
>  void
> -intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> +intel_dp_init(struct drm_device *dev,
> +	      struct i915_reg output_reg, enum port port)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_digital_port *intel_dig_port;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3fea039..afd8ac8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -666,7 +666,7 @@ struct cxsr_latency {
>  #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
>  
>  struct intel_hdmi {
> -	u32 hdmi_reg;
> +	struct i915_reg hdmi_reg;
>  	int ddc_bus;
>  	bool limited_color_range;
>  	bool color_range_auto;
> @@ -715,9 +715,9 @@ struct sink_crc {
>  };
>  
>  struct intel_dp {
> -	uint32_t output_reg;
> -	uint32_t aux_ch_ctl_reg;
> -	uint32_t aux_ch_data_reg[5];
> +	struct i915_reg output_reg;
> +	struct i915_reg aux_ch_ctl_reg;
> +	struct i915_reg aux_ch_data_reg[5];
>  	uint32_t DP;
>  	int link_rate;
>  	uint8_t lane_count;
> @@ -1182,7 +1182,7 @@ void intel_csr_ucode_fini(struct drm_device *dev);
>  void assert_csr_loaded(struct drm_i915_private *dev_priv);
>  
>  /* intel_dp.c */
> -void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
> +void intel_dp_init(struct drm_device *dev, struct i915_reg output_reg, enum port port);
>  bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  			     struct intel_connector *intel_connector);
>  void intel_dp_set_link_params(struct intel_dp *intel_dp,
> @@ -1276,7 +1276,7 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
>  void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
>  
>  /* intel_hdmi.c */
> -void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
> +void intel_hdmi_init(struct drm_device *dev, struct i915_reg hdmi_reg, enum port port);
>  void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  			       struct intel_connector *intel_connector);
>  struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
> @@ -1415,7 +1415,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>  uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
>  
>  /* intel_sdvo.c */
> -bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
> +bool intel_sdvo_init(struct drm_device *dev,
> +		     struct i915_reg reg, bool is_sdvob);
>  
>  
>  /* intel_sprite.c */
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 8f9c814..5b5a1c6 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -60,7 +60,8 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>  		DRM_ERROR("DPI FIFOs are not empty\n");
>  }
>  
> -static void write_data(struct drm_i915_private *dev_priv, u32 reg,
> +static void write_data(struct drm_i915_private *dev_priv,
> +		       struct i915_reg reg,
>  		       const u8 *data, u32 len)
>  {
>  	u32 i, j;
> @@ -75,7 +76,8 @@ static void write_data(struct drm_i915_private *dev_priv, u32 reg,
>  	}
>  }
>  
> -static void read_data(struct drm_i915_private *dev_priv, u32 reg,
> +static void read_data(struct drm_i915_private *dev_priv,
> +		      struct i915_reg reg,
>  		      u8 *data, u32 len)
>  {
>  	u32 i, j;
> @@ -98,7 +100,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
>  	struct mipi_dsi_packet packet;
>  	ssize_t ret;
>  	const u8 *header, *data;
> -	u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
> +	struct i915_reg data_reg, ctrl_reg;
> +	u32 data_mask, ctrl_mask;
>  
>  	ret = mipi_dsi_create_packet(&packet, msg);
>  	if (ret < 0)
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index c80fe1f..7739dd7 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -170,7 +170,7 @@ static void intel_disable_dvo(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> -	u32 dvo_reg = intel_dvo->dev.dvo_reg;
> +	struct i915_reg dvo_reg = intel_dvo->dev.dvo_reg;
>  	u32 temp = I915_READ(dvo_reg);
>  
>  	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
> @@ -183,7 +183,7 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> -	u32 dvo_reg = intel_dvo->dev.dvo_reg;
> +	struct i915_reg dvo_reg = intel_dvo->dev.dvo_reg;
>  	u32 temp = I915_READ(dvo_reg);
>  
>  	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
> @@ -263,17 +263,17 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	int pipe = crtc->pipe;
>  	u32 dvo_val;
> -	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
> +	struct i915_reg dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
>  
> -	switch (dvo_reg) {
> -	case DVOA:
> +	switch (dvo_reg.reg) {
> +	case _DVOA:
>  	default:
>  		dvo_srcdim_reg = DVOA_SRCDIM;
>  		break;
> -	case DVOB:
> +	case _DVOB:
>  		dvo_srcdim_reg = DVOB_SRCDIM;
>  		break;
> -	case DVOC:
> +	case _DVOC:
>  		dvo_srcdim_reg = DVOC_SRCDIM;
>  		break;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 54daa66..4ae3458 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -99,7 +99,7 @@ void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)
>  	spin_lock_irq(&dev_priv->irq_lock);
>  
>  	for_each_intel_crtc(dev_priv->dev, crtc) {
> -		u32 reg = PIPESTAT(crtc->pipe);
> +		struct i915_reg reg = PIPESTAT(crtc->pipe);
>  		u32 pipestat;
>  
>  		if (crtc->cpu_fifo_underrun_disabled)
> @@ -123,7 +123,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
>  					     bool enable, bool old)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg = PIPESTAT(pipe);
> +	struct i915_reg reg = PIPESTAT(pipe);
>  	u32 pipestat = I915_READ(reg) & 0xffff0000;
>  
>  	assert_spin_locked(&dev_priv->irq_lock);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6b16292..88d4eb0 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -113,10 +113,11 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
>  	}
>  }
>  
> -static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> -			    enum transcoder cpu_transcoder,
> -			    enum hdmi_infoframe_type type,
> -			    int i)
> +static struct i915_reg
> +hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> +		 enum transcoder cpu_transcoder,
> +		 enum hdmi_infoframe_type type,
> +		 int i)
>  {
>  	switch (type) {
>  	case HDMI_INFOFRAME_TYPE_AVI:
> @@ -127,7 +128,7 @@ static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
>  		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
>  	default:
>  		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
> -		return 0;
> +		return _REG(0);
>  	}
>  }
>  
> @@ -193,8 +194,9 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> +	int i;
>  
>  	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
>  
> @@ -229,7 +231,7 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> -	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  
>  	if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -251,8 +253,9 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> +	int i;
>  
>  	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
>  
> @@ -289,8 +292,7 @@ static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> -	u32 val = I915_READ(reg);
> +	u32 val = I915_READ(TVIDEO_DIP_CTL(intel_crtc->pipe));
>  
>  	if ((val & VIDEO_DIP_ENABLE) == 0)
>  		return false;
> @@ -308,8 +310,9 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> +	int i;
>  
>  	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
>  
> @@ -344,8 +347,7 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> -	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> -	u32 val = I915_READ(reg);
> +	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(intel_crtc->pipe));
>  
>  	if ((val & VIDEO_DIP_ENABLE) == 0)
>  		return false;
> @@ -367,13 +369,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> -	u32 data_reg;
> +	struct i915_reg ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> +	struct i915_reg data_reg;
>  	int i;
>  	u32 val = I915_READ(ctl_reg);
>  
>  	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
> -	if (data_reg == 0)
> +	if (data_reg.reg == 0)
>  		return;
>  
>  	val &= ~hsw_infoframe_enable(type);
> @@ -401,8 +403,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> -	u32 val = I915_READ(ctl_reg);
> +	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder));
>  
>  	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
>  		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> @@ -516,7 +517,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
>  	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
>  	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
> -	u32 reg = VIDEO_DIP_CTL;
> +	struct i915_reg reg = VIDEO_DIP_CTL;
>  	u32 val = I915_READ(reg);
>  	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
>  
> @@ -636,7 +637,8 @@ static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>  	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
> -	u32 reg, val = 0;
> +	struct i915_reg reg;
> +	u32 val = 0;
>  
>  	if (HAS_DDI(dev_priv))
>  		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
> @@ -669,7 +671,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
>  	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
> -	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
>  
> @@ -720,7 +722,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
>  	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> -	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  
>  	assert_hdmi_port_disabled(intel_hdmi);
> @@ -763,7 +765,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> -	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	struct i915_reg reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
>  
> @@ -814,7 +816,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
>  	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> -	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
> +	struct i915_reg reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
>  	u32 val = I915_READ(reg);
>  
>  	assert_hdmi_port_disabled(intel_hdmi);
> @@ -2134,7 +2136,8 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  	}
>  }
>  
> -void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
> +void intel_hdmi_init(struct drm_device *dev,
> +		     struct i915_reg hdmi_reg, enum port port)
>  {
>  	struct intel_digital_port *intel_dig_port;
>  	struct intel_encoder *intel_encoder;
> @@ -2205,7 +2208,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  
>  	intel_dig_port->port = port;
>  	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
> -	intel_dig_port->dp.output_reg = 0;
> +	intel_dig_port->dp.output_reg = _REG(0);
>  
>  	intel_hdmi_init_connector(intel_dig_port, intel_connector);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 1369fc4..1e59be6 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -36,7 +36,7 @@
>  
>  struct gmbus_pin {
>  	const char *name;
> -	int reg;
> +	struct i915_reg reg;
>  };
>  
>  /* Map gmbus pin pairs to names and registers. */
> @@ -96,7 +96,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  	else
>  		size = ARRAY_SIZE(gmbus_pins);
>  
> -	return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
> +	return pin < size && get_gmbus_pin(dev_priv, pin)->reg.reg;
>  }
>  
>  /* Intel GPIO access functions */
> @@ -240,8 +240,8 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>  
>  	algo = &bus->bit_algo;
>  
> -	bus->gpio_reg = dev_priv->gpio_mmio_base +
> -		get_gmbus_pin(dev_priv, pin)->reg;
> +	bus->gpio_reg = get_gmbus_pin(dev_priv, pin)->reg;
> +	bus->gpio_reg.reg += dev_priv->gpio_mmio_base;
>  
>  	bus->adapter.algo_data = algo;
>  	algo->setsda = set_data;
> @@ -627,7 +627,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>  	if (HAS_PCH_NOP(dev))
>  		return 0;
>  	else if (HAS_PCH_SPLIT(dev))
> -		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
> +		dev_priv->gpio_mmio_base = PCH_GPIOA.reg - GPIOA.reg;
>  	else if (IS_VALLEYVIEW(dev))
>  		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>  	else
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ca9f161..b254260 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -934,7 +934,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
>  
>  		intel_logical_ring_emit(ringbuf, MI_NOOP);
>  		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
> -		intel_logical_ring_emit(ringbuf, INSTPM);
> +		intel_logical_ring_emit(ringbuf, INSTPM.reg);
>  		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
>  		intel_logical_ring_advance(ringbuf);
>  
> @@ -1109,7 +1109,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
>  
>  	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
>  	for (i = 0; i < w->count; i++) {
> -		intel_logical_ring_emit(ringbuf, w->reg[i].addr);
> +		intel_logical_ring_emit(ringbuf, w->reg[i].addr.reg);
>  		intel_logical_ring_emit(ringbuf, w->reg[i].value);
>  	}
>  	intel_logical_ring_emit(ringbuf, MI_NOOP);
> @@ -1167,12 +1167,12 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
>  
>  	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
>  				   MI_SRM_LRM_GLOBAL_GTT));
> -	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
> +	wa_ctx_emit(batch, index, GEN8_L3SQCREG4.reg);
>  	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
>  	wa_ctx_emit(batch, index, 0);
>  
>  	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> -	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
> +	wa_ctx_emit(batch, index, GEN8_L3SQCREG4.reg);
>  	wa_ctx_emit(batch, index, l3sqc4_flush);
>  
>  	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
> @@ -1185,7 +1185,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
>  
>  	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
>  				   MI_SRM_LRM_GLOBAL_GTT));
> -	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
> +	wa_ctx_emit(batch, index, GEN8_L3SQCREG4.reg);
>  	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
>  	wa_ctx_emit(batch, index, 0);
>  
> @@ -1355,7 +1355,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
>  	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
>  	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
>  		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> -		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
> +		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0.reg);
>  		wa_ctx_emit(batch, index,
>  			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
>  		wa_ctx_emit(batch, index, MI_NOOP);
> @@ -1551,9 +1551,9 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
>  	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
>  		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>  
> -		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
> +		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i).reg);
>  		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
> -		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
> +		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i).reg);
>  		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
>  	}
>  
> @@ -2256,20 +2256,20 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
>  	else
>  		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
>  	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
> -	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
> +	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring).reg;
>  	reg_state[CTX_CONTEXT_CONTROL+1] =
>  		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
>  				   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
>  				   CTX_CTRL_RS_CTX_ENABLE);
> -	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
> +	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base).reg;
>  	reg_state[CTX_RING_HEAD+1] = 0;
> -	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
> +	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base).reg;
>  	reg_state[CTX_RING_TAIL+1] = 0;
> -	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
> +	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base).reg;
>  	/* Ring buffer start address is not known until the buffer is pinned.
>  	 * It is written to the context image in execlists_update_context()
>  	 */
> -	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
> +	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base).reg;
>  	reg_state[CTX_RING_BUFFER_CONTROL+1] =
>  			((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
>  	reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
> @@ -2311,14 +2311,14 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
>  	reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
>  	reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
>  	reg_state[CTX_CTX_TIMESTAMP+1] = 0;
> -	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
> -	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
> -	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
> -	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
> -	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
> -	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
> -	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
> -	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
> +	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3).reg;
> +	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3).reg;
> +	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2).reg;
> +	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2).reg;
> +	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1).reg;
> +	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1).reg;
> +	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0).reg;
> +	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0).reg;
>  
>  	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
>  		/* 64b PPGTT (48bit canonical)
> @@ -2340,7 +2340,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
>  
>  	if (ring->id == RCS) {
>  		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
> -		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
> +		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE.reg;
>  		reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 8a08a27..28d6c26b 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -26,18 +26,6 @@
>  
>  #define GEN8_LR_CONTEXT_ALIGN 4096
>  
> -/* Execlists regs */
> -#define RING_ELSP(ring)			((ring)->mmio_base+0x230)
> -#define RING_EXECLIST_STATUS_LO(ring)	((ring)->mmio_base+0x234)
> -#define RING_EXECLIST_STATUS_HI(ring)	((ring)->mmio_base+0x234 + 4)
> -#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
> -#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
> -#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
> -#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
> -#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	((ring)->mmio_base+0x370 + (i) * 8)
> -#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	((ring)->mmio_base+0x370 + (i) * 8 + 4)
> -#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
> -
>  /* Logical Rings */
>  int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
>  int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 35bad71..387359c 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -51,7 +51,7 @@ struct intel_lvds_encoder {
>  	struct intel_encoder base;
>  
>  	bool is_dual_link;
> -	u32 reg;
> +	struct i915_reg reg;
>  	u32 a3_power;
>  
>  	struct intel_lvds_connector *attached_connector;
> @@ -211,7 +211,7 @@ static void intel_enable_lvds(struct intel_encoder *encoder)
>  	struct intel_connector *intel_connector =
>  		&lvds_encoder->attached_connector->base;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 ctl_reg, stat_reg;
> +	struct i915_reg ctl_reg, stat_reg;
>  
>  	if (HAS_PCH_SPLIT(dev)) {
>  		ctl_reg = PCH_PP_CONTROL;
> @@ -236,7 +236,7 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
>  	struct drm_device *dev = encoder->base.dev;
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 ctl_reg, stat_reg;
> +	struct i915_reg ctl_reg, stat_reg;
>  
>  	if (HAS_PCH_SPLIT(dev)) {
>  		ctl_reg = PCH_PP_CONTROL;
> @@ -940,7 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	struct drm_display_mode *downclock_mode = NULL;
>  	struct edid *edid;
>  	struct drm_crtc *crtc;
> -	u32 lvds_reg;
> +	struct i915_reg lvds_reg;
>  	u32 lvds;
>  	int pipe;
>  	u8 pin;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0d43d51..11780c1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3431,7 +3431,8 @@ static void skl_compute_wm_results(struct drm_device *dev,
>  	r->wm_linetime[pipe] = p_wm->linetime;
>  }
>  
> -static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
> +static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
> +				struct i915_reg reg,
>  				const struct skl_ddb_entry *entry)
>  {
>  	if (entry->end)
> @@ -3936,7 +3937,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_pipe_wm *active = &intel_crtc->wm.active;
>  	enum pipe pipe = intel_crtc->pipe;
> -	static const unsigned int wm0_pipe_reg[] = {
> +	static const struct i915_reg wm0_pipe_reg[] = {
>  		[PIPE_A] = WM0_PIPEA_ILK,
>  		[PIPE_B] = WM0_PIPEB_ILK,
>  		[PIPE_C] = WM0_PIPEC_IVB,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0f944e2..a54c5a6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -80,7 +80,7 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
>  	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> -	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> +	struct i915_reg ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
>  	uint32_t *data = (uint32_t *) vsc_psr;
>  	unsigned int i;
>  
> @@ -151,8 +151,8 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>  			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>  }
>  
> -static uint32_t psr_aux_reg(struct drm_i915_private *dev_priv,
> -			    enum port port, int index)
> +static struct i915_reg psr_aux_reg(struct drm_i915_private *dev_priv,
> +				   enum port port, int index)
>  {
>  	if (INTEL_INFO(dev_priv)->gen >= 9)
>  		return index < 0 ? DP_AUX_CH_CTL(port) :
> @@ -168,7 +168,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  	struct drm_device *dev = dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t aux_clock_divider;
> -	uint32_t aux_ctl_reg;
> +	struct i915_reg aux_ctl_reg;
>  	int precharge = 0x3;
>  	static const uint8_t aux_msg[] = {
>  		[0] = DP_AUX_NATIVE_WRITE << 4,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 16a4ead..04af256 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -479,7 +479,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
>  {
>  	struct drm_device *dev = ring->dev;
>  	struct drm_i915_private *dev_priv = ring->dev->dev_private;
> -	u32 mmio = 0;
> +	struct i915_reg mmio;
>  
>  	/* The ring status page addresses are no longer next to the rest of
>  	 * the ring registers as of gen7.
> @@ -522,7 +522,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
>  	 * invalidating the TLB?
>  	 */
>  	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
> -		u32 reg = RING_INSTPM(ring->mmio_base);
> +		struct i915_reg reg = RING_INSTPM(ring->mmio_base);
>  
>  		/* ring should be idle before issuing a sync flush*/
>  		WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
> @@ -731,7 +731,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
>  
>  	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
>  	for (i = 0; i < w->count; i++) {
> -		intel_ring_emit(ring, w->reg[i].addr);
> +		intel_ring_emit(ring, w->reg[i].addr.reg);
>  		intel_ring_emit(ring, w->reg[i].value);
>  	}
>  	intel_ring_emit(ring, MI_NOOP);
> @@ -764,7 +764,8 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
>  }
>  
>  static int wa_add(struct drm_i915_private *dev_priv,
> -		  const u32 addr, const u32 mask, const u32 val)
> +		  struct i915_reg addr,
> +		  const u32 mask, const u32 val)
>  {
>  	const u32 idx = dev_priv->workarounds.count;
>  
> @@ -1289,11 +1290,11 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
>  		return ret;
>  
>  	for_each_ring(useless, dev_priv, i) {
> -		u32 mbox_reg = signaller->semaphore.mbox.signal[i];
> -		if (mbox_reg != GEN6_NOSYNC) {
> +		struct i915_reg mbox_reg = signaller->semaphore.mbox.signal[i];
> +		if (mbox_reg.reg != GEN6_NOSYNC.reg) {
>  			u32 seqno = i915_gem_request_get_seqno(signaller_req);
>  			intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
> -			intel_ring_emit(signaller, mbox_reg);
> +			intel_ring_emit(signaller, mbox_reg.reg);
>  			intel_ring_emit(signaller, seqno);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 49fa41d..96315aa 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -247,7 +247,7 @@ struct  intel_engine_cs {
>  				/* our mbox written by others */
>  				u32		wait[I915_NUM_RINGS];
>  				/* mboxes this ring signals to */
> -				u32		signal[I915_NUM_RINGS];
> +				struct i915_reg	signal[I915_NUM_RINGS];
>  			} mbox;
>  			u64		signal_ggtt[I915_NUM_RINGS];
>  		};
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 05521b5..43e53a3 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -74,7 +74,7 @@ struct intel_sdvo {
>  	struct i2c_adapter ddc;
>  
>  	/* Register for the SDVO device: SDVOB or SDVOC */
> -	uint32_t sdvo_reg;
> +	struct i915_reg sdvo_reg;
>  
>  	/* Active outputs controlled by this SDVO output */
>  	uint16_t controlled_output;
> @@ -240,7 +240,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  	u32 bval = val, cval = val;
>  	int i;
>  
> -	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
> +	if (intel_sdvo->sdvo_reg.reg == PCH_SDVOB.reg) {
>  		I915_WRITE(intel_sdvo->sdvo_reg, val);
>  		POSTING_READ(intel_sdvo->sdvo_reg);
>  		/*
> @@ -254,7 +254,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  		return;
>  	}
>  
> -	if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
> +	if (intel_sdvo->sdvo_reg.reg == GEN3_SDVOB.reg)
>  		cval = I915_READ(GEN3_SDVOC);
>  	else
>  		bval = I915_READ(GEN3_SDVOB);
> @@ -1274,11 +1274,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
>  			sdvox |= SDVO_BORDER_ENABLE;
>  	} else {
>  		sdvox = I915_READ(intel_sdvo->sdvo_reg);
> -		switch (intel_sdvo->sdvo_reg) {
> -		case GEN3_SDVOB:
> +		switch (intel_sdvo->sdvo_reg.reg) {
> +		case _GEN3_SDVOB:
>  			sdvox &= SDVOB_PRESERVE_MASK;
>  			break;
> -		case GEN3_SDVOC:
> +		case _GEN3_SDVOC:
>  			sdvox &= SDVOC_PRESERVE_MASK;
>  			break;
>  		}
> @@ -2912,7 +2912,8 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
>  	return i2c_add_adapter(&sdvo->ddc) == 0;
>  }
>  
> -bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
> +bool intel_sdvo_init(struct drm_device *dev,
> +		     struct i915_reg sdvo_reg, bool is_sdvob)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_encoder *intel_encoder;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index acf9b4b..9254dd9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -58,7 +58,7 @@ assert_device_not_suspended(struct drm_i915_private *dev_priv)
>  static inline void
>  fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
>  {
> -	WARN_ON(d->reg_set == 0);
> +	WARN_ON(d->reg_set.reg == 0);
>  	__raw_i915_write32(d->i915, d->reg_set, d->val_reset);
>  }
>  
> @@ -104,7 +104,7 @@ static inline void
>  fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
>  {
>  	/* something from same cacheline, but not from the set register */
> -	if (d->reg_post)
> +	if (d->reg_post.reg)
>  		__raw_posting_read(d->i915, d->reg_post);
>  }
>  
> @@ -511,10 +511,11 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
>  }
>  
>  /* We give fast paths for the really cool registers */
> -#define NEEDS_FORCE_WAKE(reg) \
> -	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
> +#define NEEDS_FORCE_WAKE(r) \
> +	((r).reg < 0x40000 && (r).reg != FORCEWAKE.reg)
>  
> -#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
> +#define REG_RANGE(r, start, end) \
> +	((r).reg >= (start) && (r).reg < (end))
>  
>  #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
>  	(REG_RANGE((reg), 0x2000, 0x4000) || \
> @@ -574,12 +575,12 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
>  #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
>  	REG_RANGE((reg), 0x9400, 0x9800)
>  
> -#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
> -	((reg) < 0x40000 &&\
> -	 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
> -	 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
> -	 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
> -	 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
> +#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(r) \
> +	((r).reg < 0x40000 && \
> +	 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(r) && \
> +	 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(r) && \
> +	 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(r) && \
> +	 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(r))
>  
>  static void
>  ilk_dummy_write(struct drm_i915_private *dev_priv)
> @@ -591,8 +592,8 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
>  }
>  
>  static void
> -hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
> -			bool before)
> +hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> +			struct i915_reg reg, bool read, bool before)
>  {
>  	const char *op = read ? "reading" : "writing to";
>  	const char *when = before ? "before" : "after";
> @@ -602,7 +603,7 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
>  
>  	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
>  		WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
> -		     when, op, reg);
> +		     when, op, reg.reg);
>  		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>  		i915.mmio_debug--; /* Only report the first N failures */
>  	}
> @@ -635,7 +636,7 @@ hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
>  
>  #define __gen2_read(x) \
>  static u##x \
> -gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +gen2_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	GEN2_READ_HEADER(x); \
>  	val = __raw_i915_read##x(dev_priv, reg); \
>  	GEN2_READ_FOOTER; \
> @@ -643,7 +644,7 @@ gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  
>  #define __gen5_read(x) \
>  static u##x \
> -gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +gen5_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	GEN2_READ_HEADER(x); \
>  	ilk_dummy_write(dev_priv); \
>  	val = __raw_i915_read##x(dev_priv, reg); \
> @@ -702,7 +703,7 @@ static inline void __force_wake_get(struct drm_i915_private *dev_priv,
>  
>  #define __vgpu_read(x) \
>  static u##x \
> -vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +vgpu_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	GEN6_READ_HEADER(x); \
>  	val = __raw_i915_read##x(dev_priv, reg); \
>  	GEN6_READ_FOOTER; \
> @@ -710,7 +711,7 @@ vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  
>  #define __gen6_read(x) \
>  static u##x \
> -gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +gen6_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	GEN6_READ_HEADER(x); \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
>  	if (NEEDS_FORCE_WAKE(reg)) \
> @@ -722,7 +723,7 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  
>  #define __vlv_read(x) \
>  static u##x \
> -vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +vlv_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	GEN6_READ_HEADER(x); \
>  	if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
>  		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
> @@ -734,7 +735,7 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  
>  #define __chv_read(x) \
>  static u##x \
> -chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +chv_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	GEN6_READ_HEADER(x); \
>  	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
>  		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
> @@ -747,12 +748,12 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	GEN6_READ_FOOTER; \
>  }
>  
> -#define SKL_NEEDS_FORCE_WAKE(reg) \
> -	 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
> +#define SKL_NEEDS_FORCE_WAKE(r) \
> +	((r).reg < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(r))
>  
>  #define __gen9_read(x) \
>  static u##x \
> -gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +gen9_read##x(struct drm_i915_private *dev_priv, struct i915_reg reg, bool trace) { \
>  	enum forcewake_domains fw_engine; \
>  	GEN6_READ_HEADER(x); \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
> @@ -810,7 +811,7 @@ __gen6_read(64)
>  
>  #define __gen2_write(x) \
>  static void \
> -gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +gen2_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
>  	GEN2_WRITE_HEADER; \
>  	__raw_i915_write##x(dev_priv, reg, val); \
>  	GEN2_WRITE_FOOTER; \
> @@ -818,7 +819,7 @@ gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>  
>  #define __gen5_write(x) \
>  static void \
> -gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +gen5_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
>  	GEN2_WRITE_HEADER; \
>  	ilk_dummy_write(dev_priv); \
>  	__raw_i915_write##x(dev_priv, reg, val); \
> @@ -851,7 +852,7 @@ __gen2_write(64)
>  
>  #define __gen6_write(x) \
>  static void \
> -gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +gen6_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
>  	u32 __fifo_ret = 0; \
>  	GEN6_WRITE_HEADER; \
>  	if (NEEDS_FORCE_WAKE(reg)) { \
> @@ -866,7 +867,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>  
>  #define __hsw_write(x) \
>  static void \
> -hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +hsw_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
>  	u32 __fifo_ret = 0; \
>  	GEN6_WRITE_HEADER; \
>  	if (NEEDS_FORCE_WAKE(reg)) { \
> @@ -884,13 +885,13 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
>  
>  #define __vgpu_write(x) \
>  static void vgpu_write##x(struct drm_i915_private *dev_priv, \
> -			  off_t reg, u##x val, bool trace) { \
> +			  struct i915_reg reg, u##x val, bool trace) { \
>  	GEN6_WRITE_HEADER; \
>  	__raw_i915_write##x(dev_priv, reg, val); \
>  	GEN6_WRITE_FOOTER; \
>  }
>  
> -static const u32 gen8_shadowed_regs[] = {
> +static const struct i915_reg gen8_shadowed_regs[] = {
>  	FORCEWAKE_MT,
>  	GEN6_RPNSWREQ,
>  	GEN6_RC_VIDEO_FREQ,
> @@ -901,11 +902,12 @@ static const u32 gen8_shadowed_regs[] = {
>  	/* TODO: Other registers are not yet used */
>  };
>  
> -static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
> +static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
> +			     struct i915_reg reg)
>  {
>  	int i;
>  	for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
> -		if (reg == gen8_shadowed_regs[i])
> +		if (reg.reg == gen8_shadowed_regs[i].reg)
>  			return true;
>  
>  	return false;
> @@ -913,10 +915,10 @@ static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
>  
>  #define __gen8_write(x) \
>  static void \
> -gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +gen8_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
>  	GEN6_WRITE_HEADER; \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
> -	if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
> +	if (reg.reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
>  		__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
>  	__raw_i915_write##x(dev_priv, reg, val); \
>  	hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> @@ -926,7 +928,7 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>  
>  #define __chv_write(x) \
>  static void \
> -chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +chv_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, bool trace) { \
>  	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
>  	GEN6_WRITE_HEADER; \
>  	if (!shadowed) { \
> @@ -941,7 +943,7 @@ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
>  	GEN6_WRITE_FOOTER; \
>  }
>  
> -static const u32 gen9_shadowed_regs[] = {
> +static const struct i915_reg gen9_shadowed_regs[] = {
>  	RING_TAIL(RENDER_RING_BASE),
>  	RING_TAIL(GEN6_BSD_RING_BASE),
>  	RING_TAIL(VEBOX_RING_BASE),
> @@ -954,11 +956,12 @@ static const u32 gen9_shadowed_regs[] = {
>  	/* TODO: Other registers are not yet used */
>  };
>  
> -static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
> +static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
> +			     struct i915_reg reg)
>  {
>  	int i;
>  	for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
> -		if (reg == gen9_shadowed_regs[i])
> +		if (reg.reg == gen9_shadowed_regs[i].reg)
>  			return true;
>  
>  	return false;
> @@ -966,7 +969,7 @@ static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
>  
>  #define __gen9_write(x) \
>  static void \
> -gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
> +gen9_write##x(struct drm_i915_private *dev_priv, struct i915_reg reg, u##x val, \
>  		bool trace) { \
>  	enum forcewake_domains fw_engine; \
>  	GEN6_WRITE_HEADER; \
> @@ -1043,7 +1046,8 @@ do { \
>  
>  static void fw_domain_init(struct drm_i915_private *dev_priv,
>  			   enum forcewake_domain_id domain_id,
> -			   u32 reg_set, u32 reg_ack)
> +			   struct i915_reg reg_set,
> +			   struct i915_reg reg_ack)
>  {
>  	struct intel_uncore_forcewake_domain *d;
>  
> @@ -1073,8 +1077,6 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>  		d->reg_post = FORCEWAKE_ACK_VLV;
>  	else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
>  		d->reg_post = ECOBUS;
> -	else
> -		d->reg_post = 0;
>  
>  	d->i915 = dev_priv;
>  	d->id = domain_id;
> @@ -1248,7 +1250,7 @@ void intel_uncore_fini(struct drm_device *dev)
>  #define GEN_RANGE(l, h) GENMASK(h, l)
>  
>  static const struct register_whitelist {
> -	uint64_t offset;
> +	struct i915_reg offset;
>  	uint32_t size;
>  	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
>  	uint32_t gen_bitmask;
> @@ -1263,11 +1265,11 @@ int i915_reg_read_ioctl(struct drm_device *dev,
>  	struct drm_i915_reg_read *reg = data;
>  	struct register_whitelist const *entry = whitelist;
>  	unsigned size;
> -	u64 offset;
> +	struct i915_reg offset, offset_hi;
>  	int i, ret = 0;
>  
>  	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
> -		if (entry->offset == (reg->offset & -entry->size) &&
> +		if (entry->offset.reg == (reg->offset & -entry->size) &&
>  		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
>  			break;
>  	}
> @@ -1280,14 +1282,15 @@ int i915_reg_read_ioctl(struct drm_device *dev,
>  	 * limit the available flags for that register).
>  	 */
>  	offset = entry->offset;
> +	offset_hi.reg = offset.reg + 4;
>  	size = entry->size;
> -	size |= reg->offset ^ offset;
> +	size |= reg->offset ^ offset.reg;
>  
>  	intel_runtime_pm_get(dev_priv);
>  
>  	switch (size) {
>  	case 8 | 1:
> -		reg->val = I915_READ64_2x32(offset, offset+4);
> +		reg->val = I915_READ64_2x32(offset, offset_hi);
>  		break;
>  	case 8:
>  		reg->val = I915_READ64(offset);
> @@ -1456,7 +1459,7 @@ static int gen6_do_reset(struct drm_device *dev)
>  }
>  
>  static int wait_for_register(struct drm_i915_private *dev_priv,
> -			     const u32 reg,
> +			     struct i915_reg reg,
>  			     const u32 mask,
>  			     const u32 value,
>  			     const unsigned long timeout_ms)
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 6a30252..127598d 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -3414,14 +3414,14 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe)
>  	 * the bits have been set by i915 previously, so we clobber
>  	 * SOUTH_CHICKEN2 register directly here.
>  	 */
> -	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
> +	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2.reg);
>  
> -	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
> -	iowrite32(val, mmio_base + PCH_PP_CONTROL);
> +	val = ioread32(mmio_base + PCH_PP_CONTROL.reg) & 0xfffffffe;
> +	iowrite32(val, mmio_base + PCH_PP_CONTROL.reg);
>  
>  	timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
>  	do {
> -		val = ioread32(mmio_base + PCH_PP_STATUS);
> +		val = ioread32(mmio_base + PCH_PP_STATUS.reg);
>  		if ((val & 0xb0000000) == 0)
>  			goto reset_complete;
>  		msleep(10);
> -- 
> 2.4.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Ville Syrjälä]

On Wed, Sep 23, 2015 at 05:23:27PM +0200, Daniel Vetter wrote:
> On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Make I915_READ and I915_WRITE more type safe by wrapping the register
> > offset in a struct. This should eliminate most of the fumbles we've had
> > with misplaced parens.
> > 
> > This only takes care of normal mmio registers. We could extend the idea
> > to other register types and define each with its own struct. That way
> > you wouldn't be able to accidentally pass the wrong thing to a specific
> > register access function.
> > 
> > There are a few uglies left:
> > - switch statements don't like structs as case values, even if
> >   you case 'case DEADBEEF.reg:'. Fortunately we don't have too many
> >   of those so can maybe switch them to use some port enums or such,
> >   or if all else fails if ladders
> > - cmd parser is still iffed out. I was just tool lazy to do that
> >   for an RFC
> > - the vgpu stuff is ugly cause I didn't spend any time figuring out
> >   what it really wants to do
> > - maybe something else I'm overlooking?
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I like this very much, which is also why I started pulling in prep patches already.
> 
> One bikeshed though: I think this is one of the very few exceptions where
> coding style says typedefs are ok, since this really is just an opaque
> datatype that gets passed around and only opened-up in low-level code
> similar to ptes. So my vote is on i915_reg_t. And since we might want to
> extend this to other register io functions maybe call it i915_mmio_reg_t.

Chris wanted the same, and so I've made the change already. If you want to
take sneak peek, it's available in the update branch I mentioned in my earlier
reply to the cover letter.

-- 
Ville Syrjälä
Intel OTC
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Jani Nikula]

On Thu, 24 Sep 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Sep 23, 2015 at 05:23:27PM +0200, Daniel Vetter wrote:
>> On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > 
>> > Make I915_READ and I915_WRITE more type safe by wrapping the register
>> > offset in a struct. This should eliminate most of the fumbles we've had
>> > with misplaced parens.
>> > 
>> > This only takes care of normal mmio registers. We could extend the idea
>> > to other register types and define each with its own struct. That way
>> > you wouldn't be able to accidentally pass the wrong thing to a specific
>> > register access function.
>> > 
>> > There are a few uglies left:
>> > - switch statements don't like structs as case values, even if
>> >   you case 'case DEADBEEF.reg:'. Fortunately we don't have too many
>> >   of those so can maybe switch them to use some port enums or such,
>> >   or if all else fails if ladders
>> > - cmd parser is still iffed out. I was just tool lazy to do that
>> >   for an RFC
>> > - the vgpu stuff is ugly cause I didn't spend any time figuring out
>> >   what it really wants to do
>> > - maybe something else I'm overlooking?
>> > 
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> I like this very much, which is also why I started pulling in prep patches already.
>> 
>> One bikeshed though: I think this is one of the very few exceptions where
>> coding style says typedefs are ok, since this really is just an opaque
>> datatype that gets passed around and only opened-up in low-level code
>> similar to ptes. So my vote is on i915_reg_t. And since we might want to
>> extend this to other register io functions maybe call it i915_mmio_reg_t.
>
> Chris wanted the same, and so I've made the change already. If you want to
> take sneak peek, it's available in the update branch I mentioned in my earlier
> reply to the cover letter.

You're too fast, making the change already... ;) IMO the shorter the
better for the common case, and I'd argue we can use i915_reg_t for
mmio, and something else for the rest.

BR,
Jani.



>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Ville Syrjälä]

On Mon, Sep 28, 2015 at 03:56:14PM +0300, Jani Nikula wrote:
> On Thu, 24 Sep 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Wed, Sep 23, 2015 at 05:23:27PM +0200, Daniel Vetter wrote:
> >> On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > 
> >> > Make I915_READ and I915_WRITE more type safe by wrapping the register
> >> > offset in a struct. This should eliminate most of the fumbles we've had
> >> > with misplaced parens.
> >> > 
> >> > This only takes care of normal mmio registers. We could extend the idea
> >> > to other register types and define each with its own struct. That way
> >> > you wouldn't be able to accidentally pass the wrong thing to a specific
> >> > register access function.
> >> > 
> >> > There are a few uglies left:
> >> > - switch statements don't like structs as case values, even if
> >> >   you case 'case DEADBEEF.reg:'. Fortunately we don't have too many
> >> >   of those so can maybe switch them to use some port enums or such,
> >> >   or if all else fails if ladders
> >> > - cmd parser is still iffed out. I was just tool lazy to do that
> >> >   for an RFC
> >> > - the vgpu stuff is ugly cause I didn't spend any time figuring out
> >> >   what it really wants to do
> >> > - maybe something else I'm overlooking?
> >> > 
> >> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> 
> >> I like this very much, which is also why I started pulling in prep patches already.
> >> 
> >> One bikeshed though: I think this is one of the very few exceptions where
> >> coding style says typedefs are ok, since this really is just an opaque
> >> datatype that gets passed around and only opened-up in low-level code
> >> similar to ptes. So my vote is on i915_reg_t. And since we might want to
> >> extend this to other register io functions maybe call it i915_mmio_reg_t.
> >
> > Chris wanted the same, and so I've made the change already. If you want to
> > take sneak peek, it's available in the update branch I mentioned in my earlier
> > reply to the cover letter.
> 
> You're too fast, making the change already... ;) IMO the shorter the
> better for the common case, and I'd argue we can use i915_reg_t for
> mmio, and something else for the rest.

Easy sed job if we want to go that way.

-- 
Ville Syrjälä
Intel OTC
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Re: [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Daniel Vetter]

On Mon, Sep 28, 2015 at 04:03:09PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 28, 2015 at 03:56:14PM +0300, Jani Nikula wrote:
> > On Thu, 24 Sep 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > On Wed, Sep 23, 2015 at 05:23:27PM +0200, Daniel Vetter wrote:
> > >> On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrjala@linux.intel.com wrote:
> > >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >> > 
> > >> > Make I915_READ and I915_WRITE more type safe by wrapping the register
> > >> > offset in a struct. This should eliminate most of the fumbles we've had
> > >> > with misplaced parens.
> > >> > 
> > >> > This only takes care of normal mmio registers. We could extend the idea
> > >> > to other register types and define each with its own struct. That way
> > >> > you wouldn't be able to accidentally pass the wrong thing to a specific
> > >> > register access function.
> > >> > 
> > >> > There are a few uglies left:
> > >> > - switch statements don't like structs as case values, even if
> > >> >   you case 'case DEADBEEF.reg:'. Fortunately we don't have too many
> > >> >   of those so can maybe switch them to use some port enums or such,
> > >> >   or if all else fails if ladders
> > >> > - cmd parser is still iffed out. I was just tool lazy to do that
> > >> >   for an RFC
> > >> > - the vgpu stuff is ugly cause I didn't spend any time figuring out
> > >> >   what it really wants to do
> > >> > - maybe something else I'm overlooking?
> > >> > 
> > >> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >> 
> > >> I like this very much, which is also why I started pulling in prep patches already.
> > >> 
> > >> One bikeshed though: I think this is one of the very few exceptions where
> > >> coding style says typedefs are ok, since this really is just an opaque
> > >> datatype that gets passed around and only opened-up in low-level code
> > >> similar to ptes. So my vote is on i915_reg_t. And since we might want to
> > >> extend this to other register io functions maybe call it i915_mmio_reg_t.
> > >
> > > Chris wanted the same, and so I've made the change already. If you want to
> > > take sneak peek, it's available in the update branch I mentioned in my earlier
> > > reply to the cover letter.
> > 
> > You're too fast, making the change already... ;) IMO the shorter the
> > better for the common case, and I'd argue we can use i915_reg_t for
> > mmio, and something else for the rest.
> 
> Easy sed job if we want to go that way.

Ack on i915_reg_t from my side.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[Chris Wilson]

On Fri, Sep 18, 2015 at 08:03:13PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Inspired by the recent misplaced parenthesis fix from Damien, I decided to try
> and see what it would take to make our register access type safe. By that mean
> you shouldn't be able to pass in anything by a proper register offset in. After
> a couple of days of hacking, this series is the result.
> 
> I managed to split out all the cleanup stuff upfront, but there is quite a bit
> of it. I did include a few random patches no strictly needed, but as long as I
> was going through the register macros I tried to fix whatever was wrong.
> 
> The actual type safe stuff is in the last patch, and I'm posting that on as an
> RFC to see what other people think about the idea. I think most of the prep
> work would be nice to have even if we decide against the type safety. Oh, turns
> out I couldn't find any new "passing crap as the register offset" type of bugs
> with this work, but this would prevent them from sneaking in. As mentioned in
> the patch, I limited this only for mmio regs for now, but we could expand it
> cover other register types.
> 
> I've only smoke tested this on IVB, HSW and BSW.
> 
> The whole thing is available in my git repo:
> git://github.com/vsyrjala/linux.git type_safe_reg_access_3
> 
> Ville Syrjälä (43):
>   drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc,i2c}_bus()
>   drm/i915: Parametrize LRC registers
>   drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
>   drm/i915: Parametrize fence registers
>   drm/i915: Parametrize FBC_TAG registers
>   drm/i915: Parametrize ILK turbo registers
>   drm/i915: Replace raw numbers with the approproate register name in
>     ILK turbo code
>   drm/i915: Parametrize TV luma/chroma filter registers
>   drm/i915: Parametrize DDI_BUF_TRANS registers
>   drm/i915: Parametrize CSR_PROGRAM registers
>   drm/i915: Parametrize UOS_RSA_SCRATCH
>   drm/i915: Add LO/HI PRIVATE_PAT registers
>   drm/i915: Always use GEN8_RING_PDP_{LDW,UDW} instead of hand rolling
>     the register offsets
>   drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR
>   drm/i915: Parametrize PALETTE and LGC_PALETTE
>   drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/
>   drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/
>   drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
>   drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
>   drm/i915: Use paramtrized WRPLL_CTL()
>   drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE
>   drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/
>   drm/i915: Eliminate weird parameter inversion from BXT PPS registers
>   drm/i915: Parametrize HSW video DIP data registers
>   drm/i915: Include gpio_mmio_base in GMBUS reg defines
>   drm/i915: Protect register macro arguments
>   drm/i915: Fix a few bad hex numbers in register defines
>   drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
>   drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
>   drm/i915: Parametrize and fix SWF registers
>   drm/i915: Throw out some useless variables
>   drm/i915: Clean up LVDS register handling
>   drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
>   drm/i915: Turn __raw_i915_read8() & co. in to inline functions
>   drm/i915: Move __raw_i915_read8() & co. into i915_drv.h
>   drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
>   drm/i915: Replace the aux ddc name switch statement with a table
>   drm/i915: Parametrize AUX registes
>   drm/i915: Add dev_priv->psr_mmio_base
>   drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]
>   drm/i915: Model PSR AUX register selection more like the normal AUX
>     code
>   drm/i915: Prefix raw register defines with underscore
>   WIP: drm/i915: Type safe register read/write

I've read through the series, and it looks good. I commented in a couple
of places, and I have yet to scrutinize the parametrizations to check the
values are the same (except for where you think the original values are
bogus), but I like it and I think it is worthwhile.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 08:03:13PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Inspired by the recent misplaced parenthesis fix from Damien, I decided to try
> and see what it would take to make our register access type safe. By that mean
> you shouldn't be able to pass in anything by a proper register offset in. After
> a couple of days of hacking, this series is the result.
> 
> I managed to split out all the cleanup stuff upfront, but there is quite a bit
> of it. I did include a few random patches no strictly needed, but as long as I
> was going through the register macros I tried to fix whatever was wrong.
> 
> The actual type safe stuff is in the last patch, and I'm posting that on as an
> RFC to see what other people think about the idea. I think most of the prep
> work would be nice to have even if we decide against the type safety. Oh, turns
> out I couldn't find any new "passing crap as the register offset" type of bugs
> with this work, but this would prevent them from sneaking in. As mentioned in
> the patch, I limited this only for mmio regs for now, but we could expand it
> cover other register types.
> 
> I've only smoke tested this on IVB, HSW and BSW.
> 
> The whole thing is available in my git repo:
> git://github.com/vsyrjala/linux.git type_safe_reg_access_3

FYI I've pushed a more polished version
git://github.com/vsyrjala/linux.git type_safe_reg_access_4

I think I'll refrain from posting the extra patches (managed to accumulate
quite a few more) quite so soon to avoid too much flooding. But I figured
I'll give people a heads up in case someone is intersted what the (hopefully)
final version would look like.

> 
> Ville Syrjälä (43):
>   drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc,i2c}_bus()
>   drm/i915: Parametrize LRC registers
>   drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
>   drm/i915: Parametrize fence registers
>   drm/i915: Parametrize FBC_TAG registers
>   drm/i915: Parametrize ILK turbo registers
>   drm/i915: Replace raw numbers with the approproate register name in
>     ILK turbo code
>   drm/i915: Parametrize TV luma/chroma filter registers
>   drm/i915: Parametrize DDI_BUF_TRANS registers
>   drm/i915: Parametrize CSR_PROGRAM registers
>   drm/i915: Parametrize UOS_RSA_SCRATCH
>   drm/i915: Add LO/HI PRIVATE_PAT registers
>   drm/i915: Always use GEN8_RING_PDP_{LDW,UDW} instead of hand rolling
>     the register offsets
>   drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR
>   drm/i915: Parametrize PALETTE and LGC_PALETTE
>   drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/
>   drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/
>   drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
>   drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
>   drm/i915: Use paramtrized WRPLL_CTL()
>   drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE
>   drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/
>   drm/i915: Eliminate weird parameter inversion from BXT PPS registers
>   drm/i915: Parametrize HSW video DIP data registers
>   drm/i915: Include gpio_mmio_base in GMBUS reg defines
>   drm/i915: Protect register macro arguments
>   drm/i915: Fix a few bad hex numbers in register defines
>   drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
>   drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
>   drm/i915: Parametrize and fix SWF registers
>   drm/i915: Throw out some useless variables
>   drm/i915: Clean up LVDS register handling
>   drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
>   drm/i915: Turn __raw_i915_read8() & co. in to inline functions
>   drm/i915: Move __raw_i915_read8() & co. into i915_drv.h
>   drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
>   drm/i915: Replace the aux ddc name switch statement with a table
>   drm/i915: Parametrize AUX registes
>   drm/i915: Add dev_priv->psr_mmio_base
>   drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]
>   drm/i915: Model PSR AUX register selection more like the normal AUX
>     code
>   drm/i915: Prefix raw register defines with underscore
>   WIP: drm/i915: Type safe register read/write
> 
>  drivers/gpu/drm/i915/dvo.h                 |    2 +-
>  drivers/gpu/drm/i915/i915_cmd_parser.c     |   17 +-
>  drivers/gpu/drm/i915/i915_debugfs.c        |   26 +-
>  drivers/gpu/drm/i915/i915_drv.c            |    8 +-
>  drivers/gpu/drm/i915/i915_drv.h            |   66 +-
>  drivers/gpu/drm/i915/i915_gem_context.c    |    4 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |    2 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c      |   41 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c        |   35 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c      |   25 +-
>  drivers/gpu/drm/i915/i915_guc_reg.h        |   50 +-
>  drivers/gpu/drm/i915/i915_guc_submission.c |    2 +-
>  drivers/gpu/drm/i915/i915_irq.c            |   68 +-
>  drivers/gpu/drm/i915/i915_reg.h            | 2768 ++++++++++++++--------------
>  drivers/gpu/drm/i915/i915_suspend.c        |   45 +-
>  drivers/gpu/drm/i915/i915_sysfs.c          |    6 +-
>  drivers/gpu/drm/i915/i915_trace.h          |    4 +-
>  drivers/gpu/drm/i915/i915_vgpu.c           |    6 +-
>  drivers/gpu/drm/i915/i915_vgpu.h           |    2 +-
>  drivers/gpu/drm/i915/intel_audio.c         |   14 +-
>  drivers/gpu/drm/i915/intel_crt.c           |   16 +-
>  drivers/gpu/drm/i915/intel_csr.c           |   17 +-
>  drivers/gpu/drm/i915/intel_ddi.c           |  117 +-
>  drivers/gpu/drm/i915/intel_display.c       |  260 ++-
>  drivers/gpu/drm/i915/intel_dp.c            |  220 ++-
>  drivers/gpu/drm/i915/intel_drv.h           |   14 +-
>  drivers/gpu/drm/i915/intel_dsi.c           |    9 +-
>  drivers/gpu/drm/i915/intel_dvo.c           |   14 +-
>  drivers/gpu/drm/i915/intel_fbc.c           |    2 +-
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |    4 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c    |    2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c          |   71 +-
>  drivers/gpu/drm/i915/intel_i2c.c           |   64 +-
>  drivers/gpu/drm/i915/intel_lrc.c           |   52 +-
>  drivers/gpu/drm/i915/intel_lrc.h           |   10 -
>  drivers/gpu/drm/i915/intel_lvds.c          |   36 +-
>  drivers/gpu/drm/i915/intel_pm.c            |   29 +-
>  drivers/gpu/drm/i915/intel_psr.c           |   63 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c    |   15 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.h    |    2 +-
>  drivers/gpu/drm/i915/intel_sdvo.c          |   23 +-
>  drivers/gpu/drm/i915/intel_tv.c            |    8 +-
>  drivers/gpu/drm/i915/intel_uncore.c        |  133 +-
>  drivers/pci/quirks.c                       |    8 +-
>  44 files changed, 2189 insertions(+), 2191 deletions(-)
> 
> -- 
> 2.4.6

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[Jani Nikula]

On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> I managed to split out all the cleanup stuff upfront, but there is quite a bit
> of it. I did include a few random patches no strictly needed, but as long as I
> was going through the register macros I tried to fix whatever was wrong.

Please push the ones that have been reviewed, and resend (the
potentially rebased versions of) the patches as a clean series. I think
that would help us move forward with the series.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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