[PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[Caesar Wang]

This patchset to support reading the efuse info for more SoCs.
(Note: support 32 bits SoCs).

Meanwhile, cleanup sunxi/rockchip drivers for more readability.

You can easy to test for following:

cd /sys/bus/nvmem/devices/rockchip-efuse0
localhost rockchip-efuse0 # busybox hexdump -C nvmem



Caesar Wang (4):
  nvmem: sunxi: trivial: fix code style
  nvmem: rockchip: trivial: Make the driver more readability
  ARM: dts: rockchip: add eFuse node for rk3066a SoCs
  ARM: dts: rockchip: add eFuse node for rk3188 SoCs

 arch/arm/boot/dts/rk3066a.dtsi | 13 ++++++
 arch/arm/boot/dts/rk3188.dtsi  | 13 ++++++
 drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
 drivers/nvmem/sunxi_sid.c      |  9 ++---
 4 files changed, 71 insertions(+), 54 deletions(-)

-- 
1.9.1

[PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[Caesar Wang]

This patchset to support reading the efuse info for more SoCs.
(Note: support 32 bits SoCs).

Meanwhile, cleanup sunxi/rockchip drivers for more readability.

You can easy to test for following:

cd /sys/bus/nvmem/devices/rockchip-efuse0
localhost rockchip-efuse0 # busybox hexdump -C nvmem



Caesar Wang (4):
  nvmem: sunxi: trivial: fix code style
  nvmem: rockchip: trivial: Make the driver more readability
  ARM: dts: rockchip: add eFuse node for rk3066a SoCs
  ARM: dts: rockchip: add eFuse node for rk3188 SoCs

 arch/arm/boot/dts/rk3066a.dtsi | 13 ++++++
 arch/arm/boot/dts/rk3188.dtsi  | 13 ++++++
 drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
 drivers/nvmem/sunxi_sid.c      |  9 ++---
 4 files changed, 71 insertions(+), 54 deletions(-)

-- 
1.9.1

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[PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[Caesar Wang]

This patchset to support reading the efuse info for more SoCs.
(Note: support 32 bits SoCs).

Meanwhile, cleanup sunxi/rockchip drivers for more readability.

You can easy to test for following:

cd /sys/bus/nvmem/devices/rockchip-efuse0
localhost rockchip-efuse0 # busybox hexdump -C nvmem



Caesar Wang (4):
  nvmem: sunxi: trivial: fix code style
  nvmem: rockchip: trivial: Make the driver more readability
  ARM: dts: rockchip: add eFuse node for rk3066a SoCs
  ARM: dts: rockchip: add eFuse node for rk3188 SoCs

 arch/arm/boot/dts/rk3066a.dtsi | 13 ++++++
 arch/arm/boot/dts/rk3188.dtsi  | 13 ++++++
 drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
 drivers/nvmem/sunxi_sid.c      |  9 ++---
 4 files changed, 71 insertions(+), 54 deletions(-)

-- 
1.9.1

[PATCH 1/4] nvmem: sunxi: trivial: fix code style

[Caesar Wang]

this pacthset try to fix the code style for sunxi.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/nvmem/sunxi_sid.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index cfa3b85..bc88b40 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -13,10 +13,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
  */
 
-
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -27,7 +25,6 @@
 #include <linux/slab.h>
 #include <linux/random.h>
 
-
 static struct nvmem_config econfig = {
 	.name = "sunxi-sid",
 	.read_only = true,
@@ -55,8 +52,8 @@ static u8 sunxi_sid_read_byte(const struct sunxi_sid *sid,
 }
 
 static int sunxi_sid_read(void *context,
-			    const void *reg, size_t reg_size,
-			    void *val, size_t val_size)
+			  const void *reg, size_t reg_size,
+			  void *val, size_t val_size)
 {
 	struct sunxi_sid *sid = context;
 	unsigned int offset = *(u32 *)reg;
@@ -130,7 +127,7 @@ static int sunxi_sid_probe(struct platform_device *pdev)
 	if (IS_ERR(nvmem))
 		return PTR_ERR(nvmem);
 
-	randomness = kzalloc(sizeof(u8) * size, GFP_KERNEL);
+	randomness = kzalloc(sizeof(u8) * (size), GFP_KERNEL);
 	if (!randomness) {
 		ret = -EINVAL;
 		goto err_unreg_nvmem;
-- 
1.9.1

[PATCH 1/4] nvmem: sunxi: trivial: fix code style

[Caesar Wang]

this pacthset try to fix the code style for sunxi.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 drivers/nvmem/sunxi_sid.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index cfa3b85..bc88b40 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -13,10 +13,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
  */
 
-
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -27,7 +25,6 @@
 #include <linux/slab.h>
 #include <linux/random.h>
 
-
 static struct nvmem_config econfig = {
 	.name = "sunxi-sid",
 	.read_only = true,
@@ -55,8 +52,8 @@ static u8 sunxi_sid_read_byte(const struct sunxi_sid *sid,
 }
 
 static int sunxi_sid_read(void *context,
-			    const void *reg, size_t reg_size,
-			    void *val, size_t val_size)
+			  const void *reg, size_t reg_size,
+			  void *val, size_t val_size)
 {
 	struct sunxi_sid *sid = context;
 	unsigned int offset = *(u32 *)reg;
@@ -130,7 +127,7 @@ static int sunxi_sid_probe(struct platform_device *pdev)
 	if (IS_ERR(nvmem))
 		return PTR_ERR(nvmem);
 
-	randomness = kzalloc(sizeof(u8) * size, GFP_KERNEL);
+	randomness = kzalloc(sizeof(u8) * (size), GFP_KERNEL);
 	if (!randomness) {
 		ret = -EINVAL;
 		goto err_unreg_nvmem;
-- 
1.9.1

[PATCH 1/4] nvmem: sunxi: trivial: fix code style

[Caesar Wang]

this pacthset try to fix the code style for sunxi.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/nvmem/sunxi_sid.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index cfa3b85..bc88b40 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -13,10 +13,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
  */
 
-
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -27,7 +25,6 @@
 #include <linux/slab.h>
 #include <linux/random.h>
 
-
 static struct nvmem_config econfig = {
 	.name = "sunxi-sid",
 	.read_only = true,
@@ -55,8 +52,8 @@ static u8 sunxi_sid_read_byte(const struct sunxi_sid *sid,
 }
 
 static int sunxi_sid_read(void *context,
-			    const void *reg, size_t reg_size,
-			    void *val, size_t val_size)
+			  const void *reg, size_t reg_size,
+			  void *val, size_t val_size)
 {
 	struct sunxi_sid *sid = context;
 	unsigned int offset = *(u32 *)reg;
@@ -130,7 +127,7 @@ static int sunxi_sid_probe(struct platform_device *pdev)
 	if (IS_ERR(nvmem))
 		return PTR_ERR(nvmem);
 
-	randomness = kzalloc(sizeof(u8) * size, GFP_KERNEL);
+	randomness = kzalloc(sizeof(u8) * (size), GFP_KERNEL);
 	if (!randomness) {
 		ret = -EINVAL;
 		goto err_unreg_nvmem;
-- 
1.9.1

[PATCH 2/4] nvmem: rockchip: trivial: Make the driver more readability

[Caesar Wang]

1) Make the include file to sort from order
2) clean up the driver to make more readability

Let's clean up such trivial details.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
 1 file changed, 42 insertions(+), 48 deletions(-)

diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index f552134..a009795 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -14,16 +14,16 @@
  * more details.
  */
 
-#include <linux/platform_device.h>
-#include <linux/nvmem-provider.h>
-#include <linux/slab.h>
-#include <linux/regmap.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/delay.h>
+#include <linux/nvmem-provider.h>
+#include <linux/slab.h>
 #include <linux/of.h>
-#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #define EFUSE_A_SHIFT			6
 #define EFUSE_A_MASK			0x3ff
@@ -35,10 +35,10 @@
 #define REG_EFUSE_CTRL			0x0000
 #define REG_EFUSE_DOUT			0x0004
 
-struct rockchip_efuse_context {
+struct rockchip_efuse_chip {
 	struct device *dev;
 	void __iomem *base;
-	struct clk *efuse_clk;
+	struct clk *clk;
 };
 
 static int rockchip_efuse_write(void *context, const void *data, size_t count)
@@ -52,34 +52,32 @@ static int rockchip_efuse_read(void *context,
 			       void *val, size_t val_size)
 {
 	unsigned int offset = *(u32 *)reg;
-	struct rockchip_efuse_context *_context = context;
-	void __iomem *base = _context->base;
-	struct clk *clk = _context->efuse_clk;
+	struct rockchip_efuse_chip *efuse = context;
 	u8 *buf = val;
 	int ret;
 
-	ret = clk_prepare_enable(clk);
+	ret = clk_prepare_enable(efuse->clk);
 	if (ret < 0) {
-		dev_err(_context->dev, "failed to prepare/enable efuse clk\n");
+		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 		return ret;
 	}
 
-	writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL);
+	writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + REG_EFUSE_CTRL);
 	udelay(1);
 	while (val_size) {
-		writel(readl(base + REG_EFUSE_CTRL) &
+		writel(readl(efuse->base + REG_EFUSE_CTRL) &
 			     (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
-			     base + REG_EFUSE_CTRL);
-		writel(readl(base + REG_EFUSE_CTRL) |
+			     efuse->base + REG_EFUSE_CTRL);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) |
 			     ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT),
-			     base + REG_EFUSE_CTRL);
+			     efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
-		writel(readl(base + REG_EFUSE_CTRL) |
-			     EFUSE_STROBE, base + REG_EFUSE_CTRL);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) |
+			     EFUSE_STROBE, efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
-		*buf++ = readb(base + REG_EFUSE_DOUT);
-		writel(readl(base + REG_EFUSE_CTRL) &
-		     (~EFUSE_STROBE), base + REG_EFUSE_CTRL);
+		*buf++ = readb(efuse->base + REG_EFUSE_DOUT);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) &
+		     (~EFUSE_STROBE), efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
 
 		val_size -= 1;
@@ -87,9 +85,9 @@ static int rockchip_efuse_read(void *context,
 	}
 
 	/* Switch to standby mode */
-	writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL);
+	writel(EFUSE_PGENB | EFUSE_CSB, efuse->base + REG_EFUSE_CTRL);
 
-	clk_disable_unprepare(clk);
+	clk_disable_unprepare(efuse->clk);
 
 	return 0;
 }
@@ -114,48 +112,44 @@ static struct nvmem_config econfig = {
 };
 
 static const struct of_device_id rockchip_efuse_match[] = {
-	{ .compatible = "rockchip,rockchip-efuse",},
+	{ .compatible = "rockchip,rockchip-efuse", },
 	{ /* sentinel */},
 };
 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
 
 static int rockchip_efuse_probe(struct platform_device *pdev)
 {
-	struct device *dev = &pdev->dev;
 	struct resource *res;
 	struct nvmem_device *nvmem;
 	struct regmap *regmap;
-	void __iomem *base;
-	struct clk *clk;
-	struct rockchip_efuse_context *context;
+	struct rockchip_efuse_chip *efuse;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
+			     GFP_KERNEL);
+	if (!efuse)
+		return -ENOMEM;
 
-	context = devm_kzalloc(dev, sizeof(struct rockchip_efuse_context),
-			       GFP_KERNEL);
-	if (IS_ERR(context))
-		return PTR_ERR(context);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	efuse->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(efuse->base))
+		return PTR_ERR(efuse->base);
 
-	clk = devm_clk_get(dev, "pclk_efuse");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
+	efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
+	if (IS_ERR(efuse->clk))
+		return PTR_ERR(efuse->clk);
 
-	context->dev = dev;
-	context->base = base;
-	context->efuse_clk = clk;
+	efuse->dev = &pdev->dev;
 
 	rockchip_efuse_regmap_config.max_register = resource_size(res) - 1;
 
-	regmap = devm_regmap_init(dev, &rockchip_efuse_bus,
-				  context, &rockchip_efuse_regmap_config);
+	regmap = devm_regmap_init(efuse->dev, &rockchip_efuse_bus,
+				  efuse, &rockchip_efuse_regmap_config);
 	if (IS_ERR(regmap)) {
-		dev_err(dev, "regmap init failed\n");
+		dev_err(efuse->dev, "regmap init failed\n");
 		return PTR_ERR(regmap);
 	}
-	econfig.dev = dev;
+
+	econfig.dev = efuse->dev;
 	nvmem = nvmem_register(&econfig);
 	if (IS_ERR(nvmem))
 		return PTR_ERR(nvmem);
-- 
1.9.1

[PATCH 2/4] nvmem: rockchip: trivial: Make the driver more readability

[Caesar Wang]

1) Make the include file to sort from order
2) clean up the driver to make more readability

Let's clean up such trivial details.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
 1 file changed, 42 insertions(+), 48 deletions(-)

diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index f552134..a009795 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -14,16 +14,16 @@
  * more details.
  */
 
-#include <linux/platform_device.h>
-#include <linux/nvmem-provider.h>
-#include <linux/slab.h>
-#include <linux/regmap.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/delay.h>
+#include <linux/nvmem-provider.h>
+#include <linux/slab.h>
 #include <linux/of.h>
-#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #define EFUSE_A_SHIFT			6
 #define EFUSE_A_MASK			0x3ff
@@ -35,10 +35,10 @@
 #define REG_EFUSE_CTRL			0x0000
 #define REG_EFUSE_DOUT			0x0004
 
-struct rockchip_efuse_context {
+struct rockchip_efuse_chip {
 	struct device *dev;
 	void __iomem *base;
-	struct clk *efuse_clk;
+	struct clk *clk;
 };
 
 static int rockchip_efuse_write(void *context, const void *data, size_t count)
@@ -52,34 +52,32 @@ static int rockchip_efuse_read(void *context,
 			       void *val, size_t val_size)
 {
 	unsigned int offset = *(u32 *)reg;
-	struct rockchip_efuse_context *_context = context;
-	void __iomem *base = _context->base;
-	struct clk *clk = _context->efuse_clk;
+	struct rockchip_efuse_chip *efuse = context;
 	u8 *buf = val;
 	int ret;
 
-	ret = clk_prepare_enable(clk);
+	ret = clk_prepare_enable(efuse->clk);
 	if (ret < 0) {
-		dev_err(_context->dev, "failed to prepare/enable efuse clk\n");
+		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 		return ret;
 	}
 
-	writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL);
+	writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + REG_EFUSE_CTRL);
 	udelay(1);
 	while (val_size) {
-		writel(readl(base + REG_EFUSE_CTRL) &
+		writel(readl(efuse->base + REG_EFUSE_CTRL) &
 			     (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
-			     base + REG_EFUSE_CTRL);
-		writel(readl(base + REG_EFUSE_CTRL) |
+			     efuse->base + REG_EFUSE_CTRL);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) |
 			     ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT),
-			     base + REG_EFUSE_CTRL);
+			     efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
-		writel(readl(base + REG_EFUSE_CTRL) |
-			     EFUSE_STROBE, base + REG_EFUSE_CTRL);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) |
+			     EFUSE_STROBE, efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
-		*buf++ = readb(base + REG_EFUSE_DOUT);
-		writel(readl(base + REG_EFUSE_CTRL) &
-		     (~EFUSE_STROBE), base + REG_EFUSE_CTRL);
+		*buf++ = readb(efuse->base + REG_EFUSE_DOUT);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) &
+		     (~EFUSE_STROBE), efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
 
 		val_size -= 1;
@@ -87,9 +85,9 @@ static int rockchip_efuse_read(void *context,
 	}
 
 	/* Switch to standby mode */
-	writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL);
+	writel(EFUSE_PGENB | EFUSE_CSB, efuse->base + REG_EFUSE_CTRL);
 
-	clk_disable_unprepare(clk);
+	clk_disable_unprepare(efuse->clk);
 
 	return 0;
 }
@@ -114,48 +112,44 @@ static struct nvmem_config econfig = {
 };
 
 static const struct of_device_id rockchip_efuse_match[] = {
-	{ .compatible = "rockchip,rockchip-efuse",},
+	{ .compatible = "rockchip,rockchip-efuse", },
 	{ /* sentinel */},
 };
 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
 
 static int rockchip_efuse_probe(struct platform_device *pdev)
 {
-	struct device *dev = &pdev->dev;
 	struct resource *res;
 	struct nvmem_device *nvmem;
 	struct regmap *regmap;
-	void __iomem *base;
-	struct clk *clk;
-	struct rockchip_efuse_context *context;
+	struct rockchip_efuse_chip *efuse;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
+			     GFP_KERNEL);
+	if (!efuse)
+		return -ENOMEM;
 
-	context = devm_kzalloc(dev, sizeof(struct rockchip_efuse_context),
-			       GFP_KERNEL);
-	if (IS_ERR(context))
-		return PTR_ERR(context);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	efuse->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(efuse->base))
+		return PTR_ERR(efuse->base);
 
-	clk = devm_clk_get(dev, "pclk_efuse");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
+	efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
+	if (IS_ERR(efuse->clk))
+		return PTR_ERR(efuse->clk);
 
-	context->dev = dev;
-	context->base = base;
-	context->efuse_clk = clk;
+	efuse->dev = &pdev->dev;
 
 	rockchip_efuse_regmap_config.max_register = resource_size(res) - 1;
 
-	regmap = devm_regmap_init(dev, &rockchip_efuse_bus,
-				  context, &rockchip_efuse_regmap_config);
+	regmap = devm_regmap_init(efuse->dev, &rockchip_efuse_bus,
+				  efuse, &rockchip_efuse_regmap_config);
 	if (IS_ERR(regmap)) {
-		dev_err(dev, "regmap init failed\n");
+		dev_err(efuse->dev, "regmap init failed\n");
 		return PTR_ERR(regmap);
 	}
-	econfig.dev = dev;
+
+	econfig.dev = efuse->dev;
 	nvmem = nvmem_register(&econfig);
 	if (IS_ERR(nvmem))
 		return PTR_ERR(nvmem);
-- 
1.9.1

[PATCH 2/4] nvmem: rockchip: trivial: Make the driver more readability

[Caesar Wang]

1) Make the include file to sort from order
2) clean up the driver to make more readability

Let's clean up such trivial details.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
 1 file changed, 42 insertions(+), 48 deletions(-)

diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index f552134..a009795 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -14,16 +14,16 @@
  * more details.
  */
 
-#include <linux/platform_device.h>
-#include <linux/nvmem-provider.h>
-#include <linux/slab.h>
-#include <linux/regmap.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/delay.h>
+#include <linux/nvmem-provider.h>
+#include <linux/slab.h>
 #include <linux/of.h>
-#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #define EFUSE_A_SHIFT			6
 #define EFUSE_A_MASK			0x3ff
@@ -35,10 +35,10 @@
 #define REG_EFUSE_CTRL			0x0000
 #define REG_EFUSE_DOUT			0x0004
 
-struct rockchip_efuse_context {
+struct rockchip_efuse_chip {
 	struct device *dev;
 	void __iomem *base;
-	struct clk *efuse_clk;
+	struct clk *clk;
 };
 
 static int rockchip_efuse_write(void *context, const void *data, size_t count)
@@ -52,34 +52,32 @@ static int rockchip_efuse_read(void *context,
 			       void *val, size_t val_size)
 {
 	unsigned int offset = *(u32 *)reg;
-	struct rockchip_efuse_context *_context = context;
-	void __iomem *base = _context->base;
-	struct clk *clk = _context->efuse_clk;
+	struct rockchip_efuse_chip *efuse = context;
 	u8 *buf = val;
 	int ret;
 
-	ret = clk_prepare_enable(clk);
+	ret = clk_prepare_enable(efuse->clk);
 	if (ret < 0) {
-		dev_err(_context->dev, "failed to prepare/enable efuse clk\n");
+		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 		return ret;
 	}
 
-	writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL);
+	writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + REG_EFUSE_CTRL);
 	udelay(1);
 	while (val_size) {
-		writel(readl(base + REG_EFUSE_CTRL) &
+		writel(readl(efuse->base + REG_EFUSE_CTRL) &
 			     (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
-			     base + REG_EFUSE_CTRL);
-		writel(readl(base + REG_EFUSE_CTRL) |
+			     efuse->base + REG_EFUSE_CTRL);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) |
 			     ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT),
-			     base + REG_EFUSE_CTRL);
+			     efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
-		writel(readl(base + REG_EFUSE_CTRL) |
-			     EFUSE_STROBE, base + REG_EFUSE_CTRL);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) |
+			     EFUSE_STROBE, efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
-		*buf++ = readb(base + REG_EFUSE_DOUT);
-		writel(readl(base + REG_EFUSE_CTRL) &
-		     (~EFUSE_STROBE), base + REG_EFUSE_CTRL);
+		*buf++ = readb(efuse->base + REG_EFUSE_DOUT);
+		writel(readl(efuse->base + REG_EFUSE_CTRL) &
+		     (~EFUSE_STROBE), efuse->base + REG_EFUSE_CTRL);
 		udelay(1);
 
 		val_size -= 1;
@@ -87,9 +85,9 @@ static int rockchip_efuse_read(void *context,
 	}
 
 	/* Switch to standby mode */
-	writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL);
+	writel(EFUSE_PGENB | EFUSE_CSB, efuse->base + REG_EFUSE_CTRL);
 
-	clk_disable_unprepare(clk);
+	clk_disable_unprepare(efuse->clk);
 
 	return 0;
 }
@@ -114,48 +112,44 @@ static struct nvmem_config econfig = {
 };
 
 static const struct of_device_id rockchip_efuse_match[] = {
-	{ .compatible = "rockchip,rockchip-efuse",},
+	{ .compatible = "rockchip,rockchip-efuse", },
 	{ /* sentinel */},
 };
 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
 
 static int rockchip_efuse_probe(struct platform_device *pdev)
 {
-	struct device *dev = &pdev->dev;
 	struct resource *res;
 	struct nvmem_device *nvmem;
 	struct regmap *regmap;
-	void __iomem *base;
-	struct clk *clk;
-	struct rockchip_efuse_context *context;
+	struct rockchip_efuse_chip *efuse;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
+			     GFP_KERNEL);
+	if (!efuse)
+		return -ENOMEM;
 
-	context = devm_kzalloc(dev, sizeof(struct rockchip_efuse_context),
-			       GFP_KERNEL);
-	if (IS_ERR(context))
-		return PTR_ERR(context);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	efuse->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(efuse->base))
+		return PTR_ERR(efuse->base);
 
-	clk = devm_clk_get(dev, "pclk_efuse");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
+	efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
+	if (IS_ERR(efuse->clk))
+		return PTR_ERR(efuse->clk);
 
-	context->dev = dev;
-	context->base = base;
-	context->efuse_clk = clk;
+	efuse->dev = &pdev->dev;
 
 	rockchip_efuse_regmap_config.max_register = resource_size(res) - 1;
 
-	regmap = devm_regmap_init(dev, &rockchip_efuse_bus,
-				  context, &rockchip_efuse_regmap_config);
+	regmap = devm_regmap_init(efuse->dev, &rockchip_efuse_bus,
+				  efuse, &rockchip_efuse_regmap_config);
 	if (IS_ERR(regmap)) {
-		dev_err(dev, "regmap init failed\n");
+		dev_err(efuse->dev, "regmap init failed\n");
 		return PTR_ERR(regmap);
 	}
-	econfig.dev = dev;
+
+	econfig.dev = efuse->dev;
 	nvmem = nvmem_register(&econfig);
 	if (IS_ERR(nvmem))
 		return PTR_ERR(nvmem);
-- 
1.9.1

[PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Caesar Wang]

This patch add the eFuse dt node for rk3066a SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 946f187..f61bb8a 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -153,6 +153,19 @@
 		clock-names = "timer", "pclk";
 	};
 
+	efuse: efuse@20010000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0x20010000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	timer@20038000 {
 		compatible = "snps,dw-apb-timer-osc";
 		reg = <0x20038000 0x100>;
-- 
1.9.1

[PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Caesar Wang]

This patch add the eFuse dt node for rk3066a SoCs.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 946f187..f61bb8a 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -153,6 +153,19 @@
 		clock-names = "timer", "pclk";
 	};
 
+	efuse: efuse@20010000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0x20010000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	timer@20038000 {
 		compatible = "snps,dw-apb-timer-osc";
 		reg = <0x20038000 0x100>;
-- 
1.9.1

[PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Caesar Wang]

This patch add the eFuse dt node for rk3066a SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 946f187..f61bb8a 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -153,6 +153,19 @@
 		clock-names = "timer", "pclk";
 	};
 
+	efuse: efuse at 20010000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0x20010000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	timer at 20038000 {
 		compatible = "snps,dw-apb-timer-osc";
 		reg = <0x20038000 0x100>;
-- 
1.9.1

[PATCH 4/4] ARM: dts: rockchip: add eFuse node for rk3188 SoCs

[Caesar Wang]

This patch add the eFuse dt node for rk3188 SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

 arch/arm/boot/dts/rk3188.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 6399942..b01ef45 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -144,6 +144,19 @@
 		#reset-cells = <1>;
 	};
 
+	efuse: efuse@20010000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0x20010000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	usbphy: phy {
 		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 		rockchip,grf = <&grf>;
-- 
1.9.1

[PATCH 4/4] ARM: dts: rockchip: add eFuse node for rk3188 SoCs

[Caesar Wang]

This patch add the eFuse dt node for rk3188 SoCs.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

---

 arch/arm/boot/dts/rk3188.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 6399942..b01ef45 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -144,6 +144,19 @@
 		#reset-cells = <1>;
 	};
 
+	efuse: efuse@20010000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0x20010000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	usbphy: phy {
 		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 		rockchip,grf = <&grf>;
-- 
1.9.1

[PATCH 4/4] ARM: dts: rockchip: add eFuse node for rk3188 SoCs

[Caesar Wang]

This patch add the eFuse dt node for rk3188 SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

 arch/arm/boot/dts/rk3188.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 6399942..b01ef45 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -144,6 +144,19 @@
 		#reset-cells = <1>;
 	};
 
+	efuse: efuse at 20010000 {
+		compatible = "rockchip,rockchip-efuse";
+		reg = <0x20010000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru PCLK_EFUSE>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu_leakage {
+			reg = <0x17 0x1>;
+		};
+	};
+
 	usbphy: phy {
 		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 		rockchip,grf = <&grf>;
-- 
1.9.1

Re: [PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[Caesar Wang]

Hi Srinivas,

What's the think of this series patches?

Let me know if you have any suggestions or ideas.:-)

Thanks!

在 2015年11月11日 15:34, Caesar Wang 写道:
> This patchset to support reading the efuse info for more SoCs.
> (Note: support 32 bits SoCs).
>
> Meanwhile, cleanup sunxi/rockchip drivers for more readability.
>
> You can easy to test for following:
>
> cd /sys/bus/nvmem/devices/rockchip-efuse0
> localhost rockchip-efuse0 # busybox hexdump -C nvmem
>
>
>
> Caesar Wang (4):
>    nvmem: sunxi: trivial: fix code style
>    nvmem: rockchip: trivial: Make the driver more readability
>    ARM: dts: rockchip: add eFuse node for rk3066a SoCs
>    ARM: dts: rockchip: add eFuse node for rk3188 SoCs
>
>   arch/arm/boot/dts/rk3066a.dtsi | 13 ++++++
>   arch/arm/boot/dts/rk3188.dtsi  | 13 ++++++
>   drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
>   drivers/nvmem/sunxi_sid.c      |  9 ++---
>   4 files changed, 71 insertions(+), 54 deletions(-)
>


-- 
caesar wang | software engineer | wxt@rock-chip.com

Re: [PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[Caesar Wang]

Hi Srinivas,

What's the think of this series patches?

Let me know if you have any suggestions or ideas.:-)

Thanks!

在 2015年11月11日 15:34, Caesar Wang 写道:
> This patchset to support reading the efuse info for more SoCs.
> (Note: support 32 bits SoCs).
>
> Meanwhile, cleanup sunxi/rockchip drivers for more readability.
>
> You can easy to test for following:
>
> cd /sys/bus/nvmem/devices/rockchip-efuse0
> localhost rockchip-efuse0 # busybox hexdump -C nvmem
>
>
>
> Caesar Wang (4):
>    nvmem: sunxi: trivial: fix code style
>    nvmem: rockchip: trivial: Make the driver more readability
>    ARM: dts: rockchip: add eFuse node for rk3066a SoCs
>    ARM: dts: rockchip: add eFuse node for rk3188 SoCs
>
>   arch/arm/boot/dts/rk3066a.dtsi | 13 ++++++
>   arch/arm/boot/dts/rk3188.dtsi  | 13 ++++++
>   drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
>   drivers/nvmem/sunxi_sid.c      |  9 ++---
>   4 files changed, 71 insertions(+), 54 deletions(-)
>


-- 
caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org


--
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[PATCH 0/4] support the efuse for rk3188/rk3066a SoCs and cleanup driver on nvmem.

[Caesar Wang]

Hi Srinivas,

What's the think of this series patches?

Let me know if you have any suggestions or ideas.:-)

Thanks!

? 2015?11?11? 15:34, Caesar Wang ??:
> This patchset to support reading the efuse info for more SoCs.
> (Note: support 32 bits SoCs).
>
> Meanwhile, cleanup sunxi/rockchip drivers for more readability.
>
> You can easy to test for following:
>
> cd /sys/bus/nvmem/devices/rockchip-efuse0
> localhost rockchip-efuse0 # busybox hexdump -C nvmem
>
>
>
> Caesar Wang (4):
>    nvmem: sunxi: trivial: fix code style
>    nvmem: rockchip: trivial: Make the driver more readability
>    ARM: dts: rockchip: add eFuse node for rk3066a SoCs
>    ARM: dts: rockchip: add eFuse node for rk3188 SoCs
>
>   arch/arm/boot/dts/rk3066a.dtsi | 13 ++++++
>   arch/arm/boot/dts/rk3188.dtsi  | 13 ++++++
>   drivers/nvmem/rockchip-efuse.c | 90 ++++++++++++++++++++----------------------
>   drivers/nvmem/sunxi_sid.c      |  9 ++---
>   4 files changed, 71 insertions(+), 54 deletions(-)
>


-- 
caesar wang | software engineer | wxt at rock-chip.com

Re: [PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Srinivas Kandagatla]

Heiko,

Can you take the DT patches in this series via your tree.

I picked up nvmem patches from this series.

thanks,
srini

On 11/11/15 07:34, Caesar Wang wrote:
> This patch add the eFuse dt node for rk3066a SoCs.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index 946f187..f61bb8a 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -153,6 +153,19 @@
>   		clock-names = "timer", "pclk";
>   	};
>
> +	efuse: efuse@20010000 {
> +		compatible = "rockchip,rockchip-efuse";
> +		reg = <0x20010000 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		clocks = <&cru PCLK_EFUSE>;
> +		clock-names = "pclk_efuse";
> +
> +		cpu_leakage: cpu_leakage {
> +			reg = <0x17 0x1>;
> +		};
> +	};
> +
>   	timer@20038000 {
>   		compatible = "snps,dw-apb-timer-osc";
>   		reg = <0x20038000 0x100>;
>

Re: [PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Srinivas Kandagatla]

Heiko,

Can you take the DT patches in this series via your tree.

I picked up nvmem patches from this series.

thanks,
srini

On 11/11/15 07:34, Caesar Wang wrote:
> This patch add the eFuse dt node for rk3066a SoCs.
>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
>
>   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index 946f187..f61bb8a 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -153,6 +153,19 @@
>   		clock-names = "timer", "pclk";
>   	};
>
> +	efuse: efuse@20010000 {
> +		compatible = "rockchip,rockchip-efuse";
> +		reg = <0x20010000 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		clocks = <&cru PCLK_EFUSE>;
> +		clock-names = "pclk_efuse";
> +
> +		cpu_leakage: cpu_leakage {
> +			reg = <0x17 0x1>;
> +		};
> +	};
> +
>   	timer@20038000 {
>   		compatible = "snps,dw-apb-timer-osc";
>   		reg = <0x20038000 0x100>;
>
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[PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Srinivas Kandagatla]

Heiko,

Can you take the DT patches in this series via your tree.

I picked up nvmem patches from this series.

thanks,
srini

On 11/11/15 07:34, Caesar Wang wrote:
> This patch add the eFuse dt node for rk3066a SoCs.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index 946f187..f61bb8a 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -153,6 +153,19 @@
>   		clock-names = "timer", "pclk";
>   	};
>
> +	efuse: efuse at 20010000 {
> +		compatible = "rockchip,rockchip-efuse";
> +		reg = <0x20010000 0x4000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		clocks = <&cru PCLK_EFUSE>;
> +		clock-names = "pclk_efuse";
> +
> +		cpu_leakage: cpu_leakage {
> +			reg = <0x17 0x1>;
> +		};
> +	};
> +
>   	timer at 20038000 {
>   		compatible = "snps,dw-apb-timer-osc";
>   		reg = <0x20038000 0x100>;
>

Re: [PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Heiko Stübner]

Hi srini,

Am Montag, 14. Dezember 2015, 09:57:02 schrieb Srinivas Kandagatla:
> Heiko,
> 
> Can you take the DT patches in this series via your tree.
> 
> I picked up nvmem patches from this series.

yep that was my plan ... just needed to wait for the nvmem parts to be picked.


Thanks for the notifying me :-)
Heiko


> 
> thanks,
> srini
> 
> On 11/11/15 07:34, Caesar Wang wrote:
> > This patch add the eFuse dt node for rk3066a SoCs.
> > 
> > Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> > ---
> > 
> >   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
> >   1 file changed, 13 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/rk3066a.dtsi
> > b/arch/arm/boot/dts/rk3066a.dtsi index 946f187..f61bb8a 100644
> > --- a/arch/arm/boot/dts/rk3066a.dtsi
> > +++ b/arch/arm/boot/dts/rk3066a.dtsi
> > @@ -153,6 +153,19 @@
> > 
> >   		clock-names = "timer", "pclk";
> >   	
> >   	};
> > 
> > +	efuse: efuse@20010000 {
> > +		compatible = "rockchip,rockchip-efuse";
> > +		reg = <0x20010000 0x4000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		clocks = <&cru PCLK_EFUSE>;
> > +		clock-names = "pclk_efuse";
> > +
> > +		cpu_leakage: cpu_leakage {
> > +			reg = <0x17 0x1>;
> > +		};
> > +	};
> > +
> > 
> >   	timer@20038000 {
> >   	
> >   		compatible = "snps,dw-apb-timer-osc";
> >   		reg = <0x20038000 0x100>;

[PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Heiko Stübner]

Hi srini,

Am Montag, 14. Dezember 2015, 09:57:02 schrieb Srinivas Kandagatla:
> Heiko,
> 
> Can you take the DT patches in this series via your tree.
> 
> I picked up nvmem patches from this series.

yep that was my plan ... just needed to wait for the nvmem parts to be picked.


Thanks for the notifying me :-)
Heiko


> 
> thanks,
> srini
> 
> On 11/11/15 07:34, Caesar Wang wrote:
> > This patch add the eFuse dt node for rk3066a SoCs.
> > 
> > Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> > ---
> > 
> >   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
> >   1 file changed, 13 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/rk3066a.dtsi
> > b/arch/arm/boot/dts/rk3066a.dtsi index 946f187..f61bb8a 100644
> > --- a/arch/arm/boot/dts/rk3066a.dtsi
> > +++ b/arch/arm/boot/dts/rk3066a.dtsi
> > @@ -153,6 +153,19 @@
> > 
> >   		clock-names = "timer", "pclk";
> >   	
> >   	};
> > 
> > +	efuse: efuse at 20010000 {
> > +		compatible = "rockchip,rockchip-efuse";
> > +		reg = <0x20010000 0x4000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		clocks = <&cru PCLK_EFUSE>;
> > +		clock-names = "pclk_efuse";
> > +
> > +		cpu_leakage: cpu_leakage {
> > +			reg = <0x17 0x1>;
> > +		};
> > +	};
> > +
> > 
> >   	timer at 20038000 {
> >   	
> >   		compatible = "snps,dw-apb-timer-osc";
> >   		reg = <0x20038000 0x100>;

Re: [PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Heiko Stübner]

Am Montag, 14. Dezember 2015, 14:06:06 schrieb Heiko Stübner:
> Hi srini,
> 
> Am Montag, 14. Dezember 2015, 09:57:02 schrieb Srinivas Kandagatla:
> > Heiko,
> > 
> > Can you take the DT patches in this series via your tree.
> > 
> > I picked up nvmem patches from this series.
> 
> yep that was my plan ... just needed to wait for the nvmem parts to be
> picked.

after looking at the patch-series as a whole, I just noticed, that they don't 
even depend on each other ... so I could've picked them earlier easily.

Anyway, I'll do that now.

> > thanks,
> > srini
> > 
> > On 11/11/15 07:34, Caesar Wang wrote:
> > > This patch add the eFuse dt node for rk3066a SoCs.
> > > 
> > > Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> > > ---
> > > 
> > >   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
> > >   1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi
> > > b/arch/arm/boot/dts/rk3066a.dtsi index 946f187..f61bb8a 100644
> > > --- a/arch/arm/boot/dts/rk3066a.dtsi
> > > +++ b/arch/arm/boot/dts/rk3066a.dtsi
> > > @@ -153,6 +153,19 @@
> > > 
> > >   		clock-names = "timer", "pclk";
> > >   	
> > >   	};
> > > 
> > > +	efuse: efuse@20010000 {
> > > +		compatible = "rockchip,rockchip-efuse";
> > > +		reg = <0x20010000 0x4000>;
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		clocks = <&cru PCLK_EFUSE>;
> > > +		clock-names = "pclk_efuse";
> > > +
> > > +		cpu_leakage: cpu_leakage {
> > > +			reg = <0x17 0x1>;
> > > +		};
> > > +	};
> > > +
> > > 
> > >   	timer@20038000 {
> > >   	
> > >   		compatible = "snps,dw-apb-timer-osc";
> > >   		reg = <0x20038000 0x100>;

Re: [PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Heiko Stübner]

Am Montag, 14. Dezember 2015, 14:06:06 schrieb Heiko Stübner:
> Hi srini,
> 
> Am Montag, 14. Dezember 2015, 09:57:02 schrieb Srinivas Kandagatla:
> > Heiko,
> > 
> > Can you take the DT patches in this series via your tree.
> > 
> > I picked up nvmem patches from this series.
> 
> yep that was my plan ... just needed to wait for the nvmem parts to be
> picked.

after looking at the patch-series as a whole, I just noticed, that they don't 
even depend on each other ... so I could've picked them earlier easily.

Anyway, I'll do that now.

> > thanks,
> > srini
> > 
> > On 11/11/15 07:34, Caesar Wang wrote:
> > > This patch add the eFuse dt node for rk3066a SoCs.
> > > 
> > > Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> > > ---
> > > 
> > >   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
> > >   1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi
> > > b/arch/arm/boot/dts/rk3066a.dtsi index 946f187..f61bb8a 100644
> > > --- a/arch/arm/boot/dts/rk3066a.dtsi
> > > +++ b/arch/arm/boot/dts/rk3066a.dtsi
> > > @@ -153,6 +153,19 @@
> > > 
> > >   		clock-names = "timer", "pclk";
> > >   	
> > >   	};
> > > 
> > > +	efuse: efuse@20010000 {
> > > +		compatible = "rockchip,rockchip-efuse";
> > > +		reg = <0x20010000 0x4000>;
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		clocks = <&cru PCLK_EFUSE>;
> > > +		clock-names = "pclk_efuse";
> > > +
> > > +		cpu_leakage: cpu_leakage {
> > > +			reg = <0x17 0x1>;
> > > +		};
> > > +	};
> > > +
> > > 
> > >   	timer@20038000 {
> > >   	
> > >   		compatible = "snps,dw-apb-timer-osc";
> > >   		reg = <0x20038000 0x100>;

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[PATCH 3/4] ARM: dts: rockchip: add eFuse node for rk3066a SoCs

[Heiko Stübner]

Am Montag, 14. Dezember 2015, 14:06:06 schrieb Heiko St?bner:
> Hi srini,
> 
> Am Montag, 14. Dezember 2015, 09:57:02 schrieb Srinivas Kandagatla:
> > Heiko,
> > 
> > Can you take the DT patches in this series via your tree.
> > 
> > I picked up nvmem patches from this series.
> 
> yep that was my plan ... just needed to wait for the nvmem parts to be
> picked.

after looking at the patch-series as a whole, I just noticed, that they don't 
even depend on each other ... so I could've picked them earlier easily.

Anyway, I'll do that now.

> > thanks,
> > srini
> > 
> > On 11/11/15 07:34, Caesar Wang wrote:
> > > This patch add the eFuse dt node for rk3066a SoCs.
> > > 
> > > Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> > > ---
> > > 
> > >   arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
> > >   1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi
> > > b/arch/arm/boot/dts/rk3066a.dtsi index 946f187..f61bb8a 100644
> > > --- a/arch/arm/boot/dts/rk3066a.dtsi
> > > +++ b/arch/arm/boot/dts/rk3066a.dtsi
> > > @@ -153,6 +153,19 @@
> > > 
> > >   		clock-names = "timer", "pclk";
> > >   	
> > >   	};
> > > 
> > > +	efuse: efuse at 20010000 {
> > > +		compatible = "rockchip,rockchip-efuse";
> > > +		reg = <0x20010000 0x4000>;
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		clocks = <&cru PCLK_EFUSE>;
> > > +		clock-names = "pclk_efuse";
> > > +
> > > +		cpu_leakage: cpu_leakage {
> > > +			reg = <0x17 0x1>;
> > > +		};
> > > +	};
> > > +
> > > 
> > >   	timer at 20038000 {
> > >   	
> > >   		compatible = "snps,dw-apb-timer-osc";
> > >   		reg = <0x20038000 0x100>;