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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org, alexander.shishkin@linux.intel.com
Cc: zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com,
	al.grant@arm.com, pawel.moll@arm.com, fainelli@broadcom.com,
	linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Mathieu Poirier <mathieu.poirier@linaro.org>
Subject: [PATCH V5 11/26] coresight: etm3x: changing default trace configuration
Date: Sun, 29 Nov 2015 19:14:32 -0700	[thread overview]
Message-ID: <1448849687-5724-12-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1448849687-5724-1-git-send-email-mathieu.poirier@linaro.org>

Changing default configuration to include the entire address
range rather than just the kernel.  That way traces are more
inclusive and it is easier to narrow down if needed.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm.h   |  2 ++
 drivers/hwtracing/coresight/coresight-etm3x.c | 29 ++++++++++++---------------
 2 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index a8663780a908..f01862fc98dd 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -146,6 +146,7 @@
  * @startstop_ctrl: setting for register ETMTSSCR.
  * @enable_event: setting for register ETMTEEVR.
  * @enable_ctrl1: setting for register ETMTECR1.
+ * @enable_ctrl2: setting for register ETMTECR2.
  * @fifofull_level: setting for register ETMFFLR.
  * @addr_idx:	index for the address comparator selection.
  * @addr_val:	value for address comparator register.
@@ -179,6 +180,7 @@ struct etm_config {
 	u32				startstop_ctrl;
 	u32				enable_event;
 	u32				enable_ctrl1;
+	u32				enable_ctrl2;
 	u32				fifofull_level;
 	u8				addr_idx;
 	u32				addr_val[ETM_MAX_ADDR_CMP];
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index a0252ffb4ba7..cfaf8e840bd6 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -608,26 +608,23 @@ static void etm_init_arch_data(void *info)
 
 static void etm_init_default_data(struct etm_config *config)
 {
-	u32 flags = (1 << 0 | /* instruction execute*/
-		     3 << 3 | /* ARM instruction */
-		     0 << 5 | /* No data value comparison */
-		     0 << 7 | /* No exact mach */
-		     0 << 8 | /* Ignore context ID */
-		     0 << 10); /* Security ignored */
-
 	if (WARN_ON_ONCE(!config))
 		return;
 
-	config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
-	config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
-	config->addr_val[0] = (u32) _stext;
-	config->addr_val[1] = (u32) _etext;
-	config->addr_acctype[0] = flags;
-	config->addr_acctype[1] = flags;
-	config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
-	config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
-
 	etm_set_default(config);
+
+	/*
+	 * Taken verbatim from the TRM:
+	 *
+	 * To trace all memory:
+	 *  set bit [24] in register 0x009, the ETMTECR1, to 1
+	 *  set all other bits in register 0x009, the ETMTECR1, to 0
+	 *  set all bits in register 0x007, the ETMTECR2, to 0
+	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
+	 */
+	config->enable_ctrl1 = BIT(24);
+	config->enable_ctrl2 = 0x0;
+	config->enable_event = ETM_HARD_WIRE_RES_A;
 }
 
 static void etm_init_trace_id(struct etm_drvdata *drvdata)
-- 
2.1.4


WARNING: multiple messages have this Message-ID (diff)
From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V5 11/26] coresight: etm3x: changing default trace configuration
Date: Sun, 29 Nov 2015 19:14:32 -0700	[thread overview]
Message-ID: <1448849687-5724-12-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1448849687-5724-1-git-send-email-mathieu.poirier@linaro.org>

Changing default configuration to include the entire address
range rather than just the kernel.  That way traces are more
inclusive and it is easier to narrow down if needed.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm.h   |  2 ++
 drivers/hwtracing/coresight/coresight-etm3x.c | 29 ++++++++++++---------------
 2 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index a8663780a908..f01862fc98dd 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -146,6 +146,7 @@
  * @startstop_ctrl: setting for register ETMTSSCR.
  * @enable_event: setting for register ETMTEEVR.
  * @enable_ctrl1: setting for register ETMTECR1.
+ * @enable_ctrl2: setting for register ETMTECR2.
  * @fifofull_level: setting for register ETMFFLR.
  * @addr_idx:	index for the address comparator selection.
  * @addr_val:	value for address comparator register.
@@ -179,6 +180,7 @@ struct etm_config {
 	u32				startstop_ctrl;
 	u32				enable_event;
 	u32				enable_ctrl1;
+	u32				enable_ctrl2;
 	u32				fifofull_level;
 	u8				addr_idx;
 	u32				addr_val[ETM_MAX_ADDR_CMP];
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index a0252ffb4ba7..cfaf8e840bd6 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -608,26 +608,23 @@ static void etm_init_arch_data(void *info)
 
 static void etm_init_default_data(struct etm_config *config)
 {
-	u32 flags = (1 << 0 | /* instruction execute*/
-		     3 << 3 | /* ARM instruction */
-		     0 << 5 | /* No data value comparison */
-		     0 << 7 | /* No exact mach */
-		     0 << 8 | /* Ignore context ID */
-		     0 << 10); /* Security ignored */
-
 	if (WARN_ON_ONCE(!config))
 		return;
 
-	config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
-	config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
-	config->addr_val[0] = (u32) _stext;
-	config->addr_val[1] = (u32) _etext;
-	config->addr_acctype[0] = flags;
-	config->addr_acctype[1] = flags;
-	config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
-	config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
-
 	etm_set_default(config);
+
+	/*
+	 * Taken verbatim from the TRM:
+	 *
+	 * To trace all memory:
+	 *  set bit [24] in register 0x009, the ETMTECR1, to 1
+	 *  set all other bits in register 0x009, the ETMTECR1, to 0
+	 *  set all bits in register 0x007, the ETMTECR2, to 0
+	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
+	 */
+	config->enable_ctrl1 = BIT(24);
+	config->enable_ctrl2 = 0x0;
+	config->enable_event = ETM_HARD_WIRE_RES_A;
 }
 
 static void etm_init_trace_id(struct etm_drvdata *drvdata)
-- 
2.1.4

  parent reply	other threads:[~2015-11-30  2:22 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-30  2:14 [PATCH V5 00/26] Coresight integration with perf Mathieu Poirier
2015-11-30  2:14 ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 01/26] coresight: etm3x: moving etm_readl/writel to header file Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 02/26] coresight: etm3x: moving sysFS entries to dedicated file Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 03/26] coresight: etm3x: unlocking tracers in default arch init Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 04/26] coresight: etm3x: splitting struct etm_drvdata Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  6:54   ` kbuild test robot
2015-11-30  6:54     ` kbuild test robot
2015-11-30  2:14 ` [PATCH V5 05/26] coresight: etm3x: implementing 'cpu_id()' API Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 06/26] coresight: associating path with session rather than tracer Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 07/26] coresight: moving PM runtime operations to core framework Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 08/26] coresight: etm3x: adding operation mode for etm_enable() Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 09/26] coresight: add API to get sink from path Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 10/26] coresight: etm3x: set progbit to stop trace collection Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` Mathieu Poirier [this message]
2015-11-30  2:14   ` [PATCH V5 11/26] coresight: etm3x: changing default trace configuration Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 12/26] coresight: etm3x: consolidating initial config Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 13/26] coresight: etm3x: implementing user/kernel mode tracing Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 14/26] coresight: etm3x: adding perf_get/set_config() API Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 15/26] coresight: etm3x: implementing perf_enable/disable() API Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 16/26] coresight: etb10: moving to local atomic operations Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 17/26] coresight: adding operation mode for sink->enable() Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 18/26] coresight: etb10: implementing AUX space API Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 19/26] coresight: updating documentation to reflect integration with perf Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 20/26] perf: changing pmu::setup_aux() parameter to include event Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 21/26] coresight: etm-perf: new PMU driver for ETM tracers Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30 23:23   ` Alexander Shishkin
2015-11-30 23:23     ` Alexander Shishkin
2015-12-01 17:25     ` Mathieu Poirier
2015-12-01 17:25       ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 22/26] coresight: introducing a global trace ID function Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 23/26] perf tools: making function set_max_cpu_num() non static Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 24/26] perf tools: adding perf_session to *info_prive_size() Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30 16:15   ` Arnaldo Carvalho de Melo
2015-11-30 16:15     ` Arnaldo Carvalho de Melo
2015-11-30  2:14 ` [PATCH V5 25/26] perf tools: making coresight PMU listable Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier
2015-11-30  2:14 ` [PATCH V5 26/26] perf tools: adding coresight etm PMU record capabilities Mathieu Poirier
2015-11-30  2:14   ` Mathieu Poirier

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