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From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
	Russell King <linux@arm.linux.org.uk>,
	Rob Herring <robh+dt@kernel.org>, Rob Herring <robh@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Pawel Moll <pawel.moll@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Arnd Bergmann <arnd@arndb.de>, Jingoo Han <jingoohan1@gmail.com>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Bjorn Andersson <bjorn.andersson@sonymobile.com>,
	Stanimir Varbanov <stanimir.varbanov@linaro.org>
Subject: [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses
Date: Fri, 18 Dec 2015 14:38:55 +0200	[thread overview]
Message-ID: <1450442339-18765-2-git-send-email-stanimir.varbanov@linaro.org> (raw)
In-Reply-To: <1450442339-18765-1-git-send-email-stanimir.varbanov@linaro.org>

There is no guarantees that enabling ATU will hit the hardware
immediately, and subsequent accesses to configuration / IO spaces
are reliable. So fixing this by read back PCIE_ATU_CR2 register
just after writing.

Without such a fix the PCI device enumeration during kernel boot
is not reliable, and reading configuration space for particular
PCI device on the bus returns zero aka no device.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
---
 drivers/pci/host/pcie-designware.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 02a7452bdf23..7880de63895d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
 		int type, u64 cpu_addr, u64 pci_addr, u32 size)
 {
+	u32 val;
+
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
@@ -164,6 +166,11 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
 	dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
 	dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
 	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+	/*
+	 * ensure that the ATU enable has been happaned before accessing
+	 * pci configuration/io spaces through dw_pcie_cfg_[read|write].
+	 */
+	dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
 }
 
 static struct irq_chip dw_msi_irq_chip = {
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID
From: stanimir.varbanov@linaro.org (Stanimir Varbanov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses
Date: Fri, 18 Dec 2015 14:38:55 +0200	[thread overview]
Message-ID: <1450442339-18765-2-git-send-email-stanimir.varbanov@linaro.org> (raw)
In-Reply-To: <1450442339-18765-1-git-send-email-stanimir.varbanov@linaro.org>

There is no guarantees that enabling ATU will hit the hardware
immediately, and subsequent accesses to configuration / IO spaces
are reliable. So fixing this by read back PCIE_ATU_CR2 register
just after writing.

Without such a fix the PCI device enumeration during kernel boot
is not reliable, and reading configuration space for particular
PCI device on the bus returns zero aka no device.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
---
 drivers/pci/host/pcie-designware.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 02a7452bdf23..7880de63895d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
 		int type, u64 cpu_addr, u64 pci_addr, u32 size)
 {
+	u32 val;
+
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
@@ -164,6 +166,11 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
 	dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
 	dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
 	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+	/*
+	 * ensure that the ATU enable has been happaned before accessing
+	 * pci configuration/io spaces through dw_pcie_cfg_[read|write].
+	 */
+	dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
 }
 
 static struct irq_chip dw_msi_irq_chip = {
-- 
1.7.9.5

  reply	other threads:[~2015-12-18 12:38 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-18 12:38 [PATCH v5 0/5] Qualcomm PCIe driver and designware fixes Stanimir Varbanov
2015-12-18 12:38 ` Stanimir Varbanov
2015-12-18 12:38 ` Stanimir Varbanov [this message]
2015-12-18 12:38   ` [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses Stanimir Varbanov
2015-12-18 14:41   ` Pratyush Anand
2015-12-18 14:41     ` Pratyush Anand
2015-12-18 14:41     ` Pratyush Anand
2016-01-04 14:31     ` Stanimir Varbanov
2016-01-04 14:31       ` Stanimir Varbanov
2016-01-04 14:31       ` Stanimir Varbanov
2016-01-06 18:20   ` Bjorn Helgaas
2016-01-06 18:20     ` Bjorn Helgaas
2016-01-07  6:33     ` Jisheng Zhang
2016-01-07  6:33       ` Jisheng Zhang
2016-01-07  6:33       ` Jisheng Zhang
2015-12-18 12:38 ` [PATCH v5 2/5] DT: PCI: qcom: Document PCIe devicetree bindings Stanimir Varbanov
2015-12-18 12:38   ` Stanimir Varbanov
2015-12-18 12:38 ` [PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
2015-12-18 12:38   ` Stanimir Varbanov
2015-12-18 12:38   ` Stanimir Varbanov
2015-12-18 13:44   ` [PATCH] PCI: qcom: fix ptr_ret.cocci warnings kbuild test robot
2015-12-18 13:44     ` kbuild test robot
2015-12-18 13:44     ` kbuild test robot
2015-12-18 13:44   ` [PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver kbuild test robot
2015-12-18 13:44     ` kbuild test robot
2015-12-18 13:44     ` kbuild test robot
2015-12-20 23:10     ` Bjorn Andersson
2015-12-20 23:10       ` Bjorn Andersson
2015-12-20 23:10       ` Bjorn Andersson
2015-12-21 23:04       ` Arnd Bergmann
2015-12-21 23:04         ` Arnd Bergmann
2015-12-21 23:04         ` Arnd Bergmann
2015-12-18 12:38 ` [PATCH v5 4/5] ARM: dts: apq8064: add pcie devicetree node Stanimir Varbanov
2015-12-18 12:38   ` Stanimir Varbanov
2015-12-18 12:38 ` [PATCH v5 5/5] ARM: dts: ifc6410: enable pcie dt node for this board Stanimir Varbanov
2015-12-18 12:38   ` Stanimir Varbanov
2016-01-05 21:42 ` [PATCH v5 0/5] Qualcomm PCIe driver and designware fixes Bjorn Helgaas
2016-01-05 21:42   ` Bjorn Helgaas

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