* [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
@ 2015-12-18 13:45 ` Jon Hunter
0 siblings, 0 replies; 6+ messages in thread
From: Jon Hunter @ 2015-12-18 13:45 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: Rhyland Klein, linux-clk, linux-tegra, linux-kernel, Jon Hunter
The EMC clock sources for tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.
Also add the additional pll_p clock source for the EMC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 58514c44ea83..849be30b52bf 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
};
static const char *mux_pllmcp_clkm[] = {
- "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
+ "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
+ "pll_p",
};
#define mux_pllmcp_clkm_idx NULL
--
2.1.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
@ 2015-12-18 13:45 ` Jon Hunter
0 siblings, 0 replies; 6+ messages in thread
From: Jon Hunter @ 2015-12-18 13:45 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: Rhyland Klein, linux-clk, linux-tegra, linux-kernel, Jon Hunter
The EMC clock sources for tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.
Also add the additional pll_p clock source for the EMC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 58514c44ea83..849be30b52bf 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
};
static const char *mux_pllmcp_clkm[] = {
- "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
+ "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
+ "pll_p",
};
#define mux_pllmcp_clkm_idx NULL
--
2.1.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
2015-12-18 13:45 ` Jon Hunter
@ 2015-12-18 16:48 ` Rhyland Klein
-1 siblings, 0 replies; 6+ messages in thread
From: Rhyland Klein @ 2015-12-18 16:48 UTC (permalink / raw)
To: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 12/18/2015 8:45 AM, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as configured by the bootloader, then this will
> cause a system hang on boot. This is because the kernel will disable the
> pll_mb when disabling unused clock as it appears to be unused when it is
> not.
>
> Also add the additional pll_p clock source for the EMC.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 58514c44ea83..849be30b52bf 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
> };
>
> static const char *mux_pllmcp_clkm[] = {
> - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
> + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
> + "pll_p",
> };
> #define mux_pllmcp_clkm_idx NULL
>
>
Acked-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
-rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
@ 2015-12-18 16:48 ` Rhyland Klein
0 siblings, 0 replies; 6+ messages in thread
From: Rhyland Klein @ 2015-12-18 16:48 UTC (permalink / raw)
To: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-clk, linux-tegra, linux-kernel
On 12/18/2015 8:45 AM, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as configured by the bootloader, then this will
> cause a system hang on boot. This is because the kernel will disable the
> pll_mb when disabling unused clock as it appears to be unused when it is
> not.
>
> Also add the additional pll_p clock source for the EMC.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 58514c44ea83..849be30b52bf 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
> };
>
> static const char *mux_pllmcp_clkm[] = {
> - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
> + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
> + "pll_p",
> };
> #define mux_pllmcp_clkm_idx NULL
>
>
Acked-by: Rhyland Klein <rklein@nvidia.com>
-rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
2015-12-18 13:45 ` Jon Hunter
@ 2016-01-13 17:20 ` Thierry Reding
-1 siblings, 0 replies; 6+ messages in thread
From: Thierry Reding @ 2016-01-13 17:20 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 807 bytes --]
On Fri, Dec 18, 2015 at 01:45:28PM +0000, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as configured by the bootloader, then this will
> cause a system hang on boot. This is because the kernel will disable the
> pll_mb when disabling unused clock as it appears to be unused when it is
> not.
>
> Also add the additional pll_p clock source for the EMC.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied, thanks.
Thierry
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
@ 2016-01-13 17:20 ` Thierry Reding
0 siblings, 0 replies; 6+ messages in thread
From: Thierry Reding @ 2016-01-13 17:20 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 778 bytes --]
On Fri, Dec 18, 2015 at 01:45:28PM +0000, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as configured by the bootloader, then this will
> cause a system hang on boot. This is because the kernel will disable the
> pll_mb when disabling unused clock as it appears to be unused when it is
> not.
>
> Also add the additional pll_p clock source for the EMC.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied, thanks.
Thierry
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-13 17:20 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-18 13:45 [PATCH] clk: tegra: Fix clock sources for tegra210 EMC Jon Hunter
2015-12-18 13:45 ` Jon Hunter
[not found] ` <1450446328-6414-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-18 16:48 ` Rhyland Klein
2015-12-18 16:48 ` Rhyland Klein
2016-01-13 17:20 ` Thierry Reding
2016-01-13 17:20 ` Thierry Reding
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