[Qemu-devel] [PATCH 0/2] 64kiB page support for TCG guests with POWER8 CPU

[Qemu-devel] [PATCH 0/2] 64kiB page support for TCG guests with POWER8 CPU

[David Gibson]

This series enables 64kiB pages when using a TCG emulated POWER8 CPU.

This gets the emulated POWER8 MMU a little bit closer to what the real
POWER8 CPU supports.

David Gibson (2):
  ppc: Move HPTE size parsing code to target-ppc helper (and add 64kiB
    pages)
  ppc: Allow 64kiB pages for POWER8 in TCG

 hw/ppc/spapr_hcall.c        | 26 ++++++++------------------
 target-ppc/mmu-hash64.c     | 31 +++++++++++++++++++++++++++++++
 target-ppc/mmu-hash64.h     |  3 +++
 target-ppc/translate_init.c | 17 +++++++++++++++++
 4 files changed, 59 insertions(+), 18 deletions(-)

-- 
2.5.0

[Qemu-devel] [PATCH 1/2] ppc: Move HPTE size parsing code to target-ppc helper (and add 64kiB pages)

[David Gibson]

The h_enter() hypercall implementation in spapr_hcall.c contains some code
to determine the page size of the newly inserted hash PTE.  This is
surprisingly complex in the general case, because POWER CPUs can have
different implementation dependent ways of encoding page sizes.  The
current version assumes POWER7 or POWER8 and doesn't support all the
possibilities of even those (but this is advertised correctly in the device
tree and so works with guests).

To support the possibility of future CPUs with different options, however,
this really belongs in the core ppc mmu code, rather than the spapr
("pseries" machine type) specific code.

So, move this code to a helper in target-ppc.

At the same time, uncomment some code to allow 64kiB pages.  At the time
that was added, I believe other parts of the ppc mmu code didn't handle
64kiB pages, but that's since been fixed.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/spapr_hcall.c    | 26 ++++++++------------------
 target-ppc/mmu-hash64.c | 31 +++++++++++++++++++++++++++++++
 target-ppc/mmu-hash64.h |  3 +++
 3 files changed, 42 insertions(+), 18 deletions(-)

diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index cebceea..c346e97 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -93,28 +93,18 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
     target_ulong pte_index = args[1];
     target_ulong pteh = args[2];
     target_ulong ptel = args[3];
-    target_ulong page_shift = 12;
+    int page_shift;
+    uint64_t avpnm;
     target_ulong raddr;
     target_ulong index;
     uint64_t token;
 
-    /* only handle 4k and 16M pages for now */
-    if (pteh & HPTE64_V_LARGE) {
-#if 0 /* We don't support 64k pages yet */
-        if ((ptel & 0xf000) == 0x1000) {
-            /* 64k page */
-        } else
-#endif
-        if ((ptel & 0xff000) == 0) {
-            /* 16M page */
-            page_shift = 24;
-            /* lowest AVA bit must be 0 for 16M pages */
-            if (pteh & 0x80) {
-                return H_PARAMETER;
-            }
-        } else {
-            return H_PARAMETER;
-        }
+    if (ppc_hash64_hpte_shift(pteh, ptel, &page_shift, &avpnm) < 0) {
+        return H_PARAMETER;
+    }
+
+    if (HPTE64_V_AVPN_VAL(pteh) & avpnm) {
+        return H_PARAMETER;
     }
 
     raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 34e20fa..d3b895d 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -399,6 +399,37 @@ static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
     return epnshift;
 }
 
+/* Returns the page shift of the given hpte.  This is the "base"
+ * shift, used for hashing.  Although we don't implement it yet, the
+ * architecture allows the actuall mapped page to be larger, but
+ * determining that size requires information from the slb. */
+int ppc_hash64_hpte_shift(uint64_t pte0, uint64_t pte1,
+                          int *shift, uint64_t *avpnm)
+{
+    *shift = 12; /* 4kiB default */
+
+    /* only handle 4k and 16M pages for now */
+    if (pte0 & HPTE64_V_LARGE) {
+        if ((pte1 & 0xf000) == 0x1000) {
+            *shift = 16; /* 64 kiB */
+        } else if ((pte1 & 0xff000) == 0) {
+            *shift = 24; /* 16MiB */
+        } else {
+            return -EINVAL;
+        }
+    }
+
+    if (avpnm) {
+        if (*shift <= 23) {
+            *avpnm = 0;
+        } else {
+            *avpnm = (1ULL << (*shift - 23)) - 1;
+        }
+    }
+
+    return 0;
+}
+
 static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
                                      ppc_slb_t *slb, target_ulong eaddr,
                                      ppc_hash_pte64_t *pte)
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 291750f..71d2532 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -117,6 +117,9 @@ typedef struct {
     uint64_t pte0, pte1;
 } ppc_hash_pte64_t;
 
+int ppc_hash64_hpte_shift(uint64_t pte0, uint64_t pte1,
+                          int *shift, uint64_t *avpnm);
+
 #endif /* CONFIG_USER_ONLY */
 
 #endif /* !defined (__MMU_HASH64_H__) */
-- 
2.5.0

[Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[David Gibson]

Now that the spapr code has been extended to support 64kiB pages, we can
allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
"segment_page_sizes" structure which is advertised via the device tree.

For now we just add support for 64kiB pages in 64kiB page segments.  Real
POWER8 also supports 64kiB pages in 4kiB page segments, but that will
require more work to implement.

Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
however, I don't want to add support there without double checking if they
use the same HPTE and SLB encodings (in principle these are implementation
dependent).

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/translate_init.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e88dc7f..ae5a269 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+    static const struct ppc_segment_page_sizes POWER8_sps = {
+        .sps = {
+            { .page_shift = 12, /* 4K */
+              .slb_enc = 0,
+              .enc = { { .page_shift = 12, .pte_enc = 0 } }
+            },
+            { .page_shift = 16, /* 64K */
+              .slb_enc = 0x110,
+              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
+            },
+            { .page_shift = 24, /* 16M */
+              .slb_enc = 0x100,
+              .enc = { { .page_shift = 24, .pte_enc = 0 } }
+            },
+        }
+    };
 
     dc->fw_name = "PowerPC,POWER8";
     dc->desc = "POWER8";
@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->l1_dcache_size = 0x8000;
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+    pcc->sps = &POWER8_sps;
 }
 #endif /* defined (TARGET_PPC64) */
 
-- 
2.5.0

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[Benjamin Herrenschmidt]

On Mon, 2015-12-21 at 13:41 +1100, David Gibson wrote:
> Now that the spapr code has been extended to support 64kiB pages, we can
> allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> "segment_page_sizes" structure which is advertised via the device tree.
> 
> For now we just add support for 64kiB pages in 64kiB page segments.  Real
> POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> require more work to implement.
> 
> Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> however, I don't want to add support there without double checking if they
> use the same HPTE and SLB encodings (in principle these are implementation
> dependent).

Don't I have a patch for that in my series already ? IIRC, I had
another fix somewhere...

https://github.com/ozbenh/qemu/commit/6c9dc80db82ed87d5ee77852930348232
f5f9db2

Cheers,
Ben.


> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>  target-ppc/translate_init.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e88dc7f..ae5a269 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
>      PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +    static const struct ppc_segment_page_sizes POWER8_sps = {
> +        .sps = {
> +            { .page_shift = 12, /* 4K */
> +              .slb_enc = 0,
> +              .enc = { { .page_shift = 12, .pte_enc = 0 } }
> +            },
> +            { .page_shift = 16, /* 64K */
> +              .slb_enc = 0x110,
> +              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> +            },
> +            { .page_shift = 24, /* 16M */
> +              .slb_enc = 0x100,
> +              .enc = { { .page_shift = 24, .pte_enc = 0 } }
> +            },
> +        }
> +    };
>  
>      dc->fw_name = "PowerPC,POWER8";
>      dc->desc = "POWER8";
> @@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +    pcc->sps = &POWER8_sps;
>  }
>  #endif /* defined (TARGET_PPC64) */
>  

Re: [Qemu-devel] [PATCH 1/2] ppc: Move HPTE size parsing code to target-ppc helper (and add 64kiB pages)

[Alexey Kardashevskiy]

On 12/21/2015 01:41 PM, David Gibson wrote:
> The h_enter() hypercall implementation in spapr_hcall.c contains some code
> to determine the page size of the newly inserted hash PTE.  This is
> surprisingly complex in the general case, because POWER CPUs can have
> different implementation dependent ways of encoding page sizes.  The
> current version assumes POWER7 or POWER8 and doesn't support all the

s/and doesn't/doesn't/ ?


> possibilities of even those (but this is advertised correctly in the device
> tree and so works with guests).
>
> To support the possibility of future CPUs with different options, however,
> this really belongs in the core ppc mmu code, rather than the spapr
> ("pseries" machine type) specific code.
>
> So, move this code to a helper in target-ppc.
>
> At the same time, uncomment some code to allow 64kiB pages.  At the time
> that was added, I believe other parts of the ppc mmu code didn't handle
> 64kiB pages, but that's since been fixed.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>   hw/ppc/spapr_hcall.c    | 26 ++++++++------------------
>   target-ppc/mmu-hash64.c | 31 +++++++++++++++++++++++++++++++
>   target-ppc/mmu-hash64.h |  3 +++
>   3 files changed, 42 insertions(+), 18 deletions(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index cebceea..c346e97 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -93,28 +93,18 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>       target_ulong pte_index = args[1];
>       target_ulong pteh = args[2];
>       target_ulong ptel = args[3];
> -    target_ulong page_shift = 12;
> +    int page_shift;
> +    uint64_t avpnm;
>       target_ulong raddr;
>       target_ulong index;
>       uint64_t token;
>
> -    /* only handle 4k and 16M pages for now */
> -    if (pteh & HPTE64_V_LARGE) {
> -#if 0 /* We don't support 64k pages yet */
> -        if ((ptel & 0xf000) == 0x1000) {
> -            /* 64k page */
> -        } else
> -#endif
> -        if ((ptel & 0xff000) == 0) {
> -            /* 16M page */
> -            page_shift = 24;
> -            /* lowest AVA bit must be 0 for 16M pages */
> -            if (pteh & 0x80) {
> -                return H_PARAMETER;
> -            }
> -        } else {
> -            return H_PARAMETER;
> -        }
> +    if (ppc_hash64_hpte_shift(pteh, ptel, &page_shift, &avpnm) < 0) {
> +        return H_PARAMETER;
> +    }
> +
> +    if (HPTE64_V_AVPN_VAL(pteh) & avpnm) {


HPTE64_V_AVPN_VAL(pteh) & ((1ULL << page_shift) >> 23)
should do the same thing, no?



> +        return H_PARAMETER;
>       }
>
>       raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index 34e20fa..d3b895d 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -399,6 +399,37 @@ static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
>       return epnshift;
>   }
>
> +/* Returns the page shift of the given hpte.  This is the "base"
> + * shift, used for hashing.  Although we don't implement it yet, the
> + * architecture allows the actuall mapped page to be larger, but


s/actuall/actual/


> + * determining that size requires information from the slb. */
> +int ppc_hash64_hpte_shift(uint64_t pte0, uint64_t pte1,
> +                          int *shift, uint64_t *avpnm)
> +{
> +    *shift = 12; /* 4kiB default */
> +
> +    /* only handle 4k and 16M pages for now */
> +    if (pte0 & HPTE64_V_LARGE) {
> +        if ((pte1 & 0xf000) == 0x1000) {


Nit: it would improve readability of this code if HPTE64_R_KEY()&co was 
used. What does define these "key" bits meaning?


> +            *shift = 16; /* 64 kiB */
> +        } else if ((pte1 & 0xff000) == 0) {
> +            *shift = 24; /* 16MiB */
> +        } else {
> +            return -EINVAL;
> +        }
> +    }
> +
> +    if (avpnm) {
> +        if (*shift <= 23) {
> +            *avpnm = 0;
> +        } else {
> +            *avpnm = (1ULL << (*shift - 23)) - 1;
> +        }
> +    }


What does "avpnm" stand for? Abbreviated virtual page <something> mask?

If you dropped "if(avpnm)", you could move "*avpnm = 0;" to the beginning 
and "*avpnm = (1ULL << (*shift - 23)) - 1;" next to "*shift = 24;".



> +
> +    return 0;
> +}
> +
>   static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
>                                        ppc_slb_t *slb, target_ulong eaddr,
>                                        ppc_hash_pte64_t *pte)
> diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
> index 291750f..71d2532 100644
> --- a/target-ppc/mmu-hash64.h
> +++ b/target-ppc/mmu-hash64.h
> @@ -117,6 +117,9 @@ typedef struct {
>       uint64_t pte0, pte1;
>   } ppc_hash_pte64_t;
>
> +int ppc_hash64_hpte_shift(uint64_t pte0, uint64_t pte1,
> +                          int *shift, uint64_t *avpnm);
> +
>   #endif /* CONFIG_USER_ONLY */
>
>   #endif /* !defined (__MMU_HASH64_H__) */
>


-- 
Alexey

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[Alexey Kardashevskiy]

On 12/21/2015 01:41 PM, David Gibson wrote:
> Now that the spapr code has been extended to support 64kiB pages, we can
> allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> "segment_page_sizes" structure which is advertised via the device tree.
>
> For now we just add support for 64kiB pages in 64kiB page segments.  Real
> POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> require more work to implement.
>
> Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> however, I don't want to add support there without double checking if they
> use the same HPTE and SLB encodings (in principle these are implementation
> dependent).
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>   target-ppc/translate_init.c | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e88dc7f..ae5a269 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>   {
>       DeviceClass *dc = DEVICE_CLASS(oc);
>       PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +    static const struct ppc_segment_page_sizes POWER8_sps = {
> +        .sps = {
> +            { .page_shift = 12, /* 4K */
> +              .slb_enc = 0,
> +              .enc = { { .page_shift = 12, .pte_enc = 0 } }
> +            },
> +            { .page_shift = 16, /* 64K */
> +              .slb_enc = 0x110,
> +              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> +            },
> +            { .page_shift = 24, /* 16M */
> +              .slb_enc = 0x100,
> +              .enc = { { .page_shift = 24, .pte_enc = 0 } }
> +            },
> +        }
> +    };


In order to educate myself - where did 0x110/0x100 come from? Is not 0x110 
SLB_VSID_64K (which does not use SLB_VSID_L by accident?)? And is 0x100 
SLB_VSID_L?

I just wanted to double check if POWER7 uses the same encoding and it is 
not that simple to trace what came from where...



>
>       dc->fw_name = "PowerPC,POWER8";
>       dc->desc = "POWER8";
> @@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>       pcc->l1_dcache_size = 0x8000;
>       pcc->l1_icache_size = 0x8000;
>       pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +    pcc->sps = &POWER8_sps;
>   }
>   #endif /* defined (TARGET_PPC64) */
>
>


-- 
Alexey

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 3068 bytes --]

On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:
> On 12/21/2015 01:41 PM, David Gibson wrote:
> >Now that the spapr code has been extended to support 64kiB pages, we can
> >allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> >"segment_page_sizes" structure which is advertised via the device tree.
> >
> >For now we just add support for 64kiB pages in 64kiB page segments.  Real
> >POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> >require more work to implement.
> >
> >Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> >however, I don't want to add support there without double checking if they
> >use the same HPTE and SLB encodings (in principle these are implementation
> >dependent).
> >
> >Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> >---
> >  target-ppc/translate_init.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> >diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >index e88dc7f..ae5a269 100644
> >--- a/target-ppc/translate_init.c
> >+++ b/target-ppc/translate_init.c
> >@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >  {
> >      DeviceClass *dc = DEVICE_CLASS(oc);
> >      PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> >+    static const struct ppc_segment_page_sizes POWER8_sps = {
> >+        .sps = {
> >+            { .page_shift = 12, /* 4K */
> >+              .slb_enc = 0,
> >+              .enc = { { .page_shift = 12, .pte_enc = 0 } }
> >+            },
> >+            { .page_shift = 16, /* 64K */
> >+              .slb_enc = 0x110,
> >+              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> >+            },
> >+            { .page_shift = 24, /* 16M */
> >+              .slb_enc = 0x100,
> >+              .enc = { { .page_shift = 24, .pte_enc = 0 } }
> >+            },
> >+        }
> >+    };
> 
> 
> In order to educate myself - where did 0x110/0x100 come from?

These are the L and LP bit encodings used by actual POWER8 hardware -
IIRC I took the information from the kernel's mmu_psize_defs table.

> Is not 0x110
> SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?

Yes, it is

> And is 0x100
> SLB_VSID_L?

Yes.

> I just wanted to double check if POWER7 uses the same encoding and it is not
> that simple to trace what came from where...
> 
> 
> 
> >
> >      dc->fw_name = "PowerPC,POWER8";
> >      dc->desc = "POWER8";
> >@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >      pcc->l1_dcache_size = 0x8000;
> >      pcc->l1_icache_size = 0x8000;
> >      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> >+    pcc->sps = &POWER8_sps;
> >  }
> >  #endif /* defined (TARGET_PPC64) */
> >
> >
> 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[Alexey Kardashevskiy]

On 01/12/2016 11:26 AM, David Gibson wrote:
> On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:
>> On 12/21/2015 01:41 PM, David Gibson wrote:
>>> Now that the spapr code has been extended to support 64kiB pages, we can
>>> allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
>>> "segment_page_sizes" structure which is advertised via the device tree.
>>>
>>> For now we just add support for 64kiB pages in 64kiB page segments.  Real
>>> POWER8 also supports 64kiB pages in 4kiB page segments, but that will
>>> require more work to implement.
>>>
>>> Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
>>> however, I don't want to add support there without double checking if they
>>> use the same HPTE and SLB encodings (in principle these are implementation
>>> dependent).
>>>
>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>>> ---
>>>   target-ppc/translate_init.c | 17 +++++++++++++++++
>>>   1 file changed, 17 insertions(+)
>>>
>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>> index e88dc7f..ae5a269 100644
>>> --- a/target-ppc/translate_init.c
>>> +++ b/target-ppc/translate_init.c
>>> @@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>>>   {
>>>       DeviceClass *dc = DEVICE_CLASS(oc);
>>>       PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
>>> +    static const struct ppc_segment_page_sizes POWER8_sps = {
>>> +        .sps = {
>>> +            { .page_shift = 12, /* 4K */
>>> +              .slb_enc = 0,
>>> +              .enc = { { .page_shift = 12, .pte_enc = 0 } }
>>> +            },
>>> +            { .page_shift = 16, /* 64K */
>>> +              .slb_enc = 0x110,
>>> +              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
>>> +            },
>>> +            { .page_shift = 24, /* 16M */
>>> +              .slb_enc = 0x100,
>>> +              .enc = { { .page_shift = 24, .pte_enc = 0 } }
>>> +            },
>>> +        }
>>> +    };
>>
>>
>> In order to educate myself - where did 0x110/0x100 come from?
>
> These are the L and LP bit encodings used by actual POWER8 hardware -
> IIRC I took the information from the kernel's mmu_psize_defs table.


I found this in p8-book4. Paul suggested there is a public POWER8 user 
manual but I cannot neither google it nor find on 
http://openpowerfoundation.org/.


>> Is not 0x110
>> SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?
>
> Yes, it is
>
>> And is 0x100
>> SLB_VSID_L?
>
> Yes.

Cool, thanks.

btw why not to use those definitions then...


>
>> I just wanted to double check if POWER7 uses the same encoding and it is not
>> that simple to trace what came from where...
>>
>>
>>
>>>
>>>       dc->fw_name = "PowerPC,POWER8";
>>>       dc->desc = "POWER8";
>>> @@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>>>       pcc->l1_dcache_size = 0x8000;
>>>       pcc->l1_icache_size = 0x8000;
>>>       pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>>> +    pcc->sps = &POWER8_sps;
>>>   }
>>>   #endif /* defined (TARGET_PPC64) */
>>>
>>>
>>
>>
>


-- 
Alexey

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[David Gibson]

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On Tue, Jan 12, 2016 at 03:30:33PM +1100, Alexey Kardashevskiy wrote:
> On 01/12/2016 11:26 AM, David Gibson wrote:
> >On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:
> >>On 12/21/2015 01:41 PM, David Gibson wrote:
> >>>Now that the spapr code has been extended to support 64kiB pages, we can
> >>>allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> >>>"segment_page_sizes" structure which is advertised via the device tree.
> >>>
> >>>For now we just add support for 64kiB pages in 64kiB page segments.  Real
> >>>POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> >>>require more work to implement.
> >>>
> >>>Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> >>>however, I don't want to add support there without double checking if they
> >>>use the same HPTE and SLB encodings (in principle these are implementation
> >>>dependent).
> >>>
> >>>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> >>>---
> >>>  target-ppc/translate_init.c | 17 +++++++++++++++++
> >>>  1 file changed, 17 insertions(+)
> >>>
> >>>diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >>>index e88dc7f..ae5a269 100644
> >>>--- a/target-ppc/translate_init.c
> >>>+++ b/target-ppc/translate_init.c
> >>>@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >>>  {
> >>>      DeviceClass *dc = DEVICE_CLASS(oc);
> >>>      PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> >>>+    static const struct ppc_segment_page_sizes POWER8_sps = {
> >>>+        .sps = {
> >>>+            { .page_shift = 12, /* 4K */
> >>>+              .slb_enc = 0,
> >>>+              .enc = { { .page_shift = 12, .pte_enc = 0 } }
> >>>+            },
> >>>+            { .page_shift = 16, /* 64K */
> >>>+              .slb_enc = 0x110,
> >>>+              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> >>>+            },
> >>>+            { .page_shift = 24, /* 16M */
> >>>+              .slb_enc = 0x100,
> >>>+              .enc = { { .page_shift = 24, .pte_enc = 0 } }
> >>>+            },
> >>>+        }
> >>>+    };
> >>
> >>
> >>In order to educate myself - where did 0x110/0x100 come from?
> >
> >These are the L and LP bit encodings used by actual POWER8 hardware -
> >IIRC I took the information from the kernel's mmu_psize_defs table.
> 
> 
> I found this in p8-book4. Paul suggested there is a public POWER8 user
> manual but I cannot neither google it nor find on
> http://openpowerfoundation.org/.

Ok.

> 
> 
> >>Is not 0x110
> >>SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?
> >
> >Yes, it is
> >
> >>And is 0x100
> >>SLB_VSID_L?
> >
> >Yes.
> 
> Cool, thanks.
> 
> btw why not to use those definitions then...

I think I started trying to, but got into some #include complications
that weren't worth the hassling of sorting out at the time.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

[Alexey Kardashevskiy]

On 01/12/2016 03:33 PM, David Gibson wrote:
> On Tue, Jan 12, 2016 at 03:30:33PM +1100, Alexey Kardashevskiy wrote:
>> On 01/12/2016 11:26 AM, David Gibson wrote:
>>> On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:
>>>> On 12/21/2015 01:41 PM, David Gibson wrote:
>>>>> Now that the spapr code has been extended to support 64kiB pages, we can
>>>>> allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
>>>>> "segment_page_sizes" structure which is advertised via the device tree.
>>>>>
>>>>> For now we just add support for 64kiB pages in 64kiB page segments.  Real
>>>>> POWER8 also supports 64kiB pages in 4kiB page segments, but that will
>>>>> require more work to implement.
>>>>>
>>>>> Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
>>>>> however, I don't want to add support there without double checking if they
>>>>> use the same HPTE and SLB encodings (in principle these are implementation
>>>>> dependent).
>>>>>
>>>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>>>>> ---
>>>>>   target-ppc/translate_init.c | 17 +++++++++++++++++
>>>>>   1 file changed, 17 insertions(+)
>>>>>
>>>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>>>> index e88dc7f..ae5a269 100644
>>>>> --- a/target-ppc/translate_init.c
>>>>> +++ b/target-ppc/translate_init.c
>>>>> @@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>>>>>   {
>>>>>       DeviceClass *dc = DEVICE_CLASS(oc);
>>>>>       PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
>>>>> +    static const struct ppc_segment_page_sizes POWER8_sps = {
>>>>> +        .sps = {
>>>>> +            { .page_shift = 12, /* 4K */
>>>>> +              .slb_enc = 0,
>>>>> +              .enc = { { .page_shift = 12, .pte_enc = 0 } }
>>>>> +            },
>>>>> +            { .page_shift = 16, /* 64K */
>>>>> +              .slb_enc = 0x110,
>>>>> +              .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
>>>>> +            },
>>>>> +            { .page_shift = 24, /* 16M */
>>>>> +              .slb_enc = 0x100,
>>>>> +              .enc = { { .page_shift = 24, .pte_enc = 0 } }
>>>>> +            },
>>>>> +        }
>>>>> +    };
>>>>
>>>>
>>>> In order to educate myself - where did 0x110/0x100 come from?
>>>
>>> These are the L and LP bit encodings used by actual POWER8 hardware -
>>> IIRC I took the information from the kernel's mmu_psize_defs table.
>>
>>
>> I found this in p8-book4. Paul suggested there is a public POWER8 user
>> manual but I cannot neither google it nor find on
>> http://openpowerfoundation.org/.
>
> Ok.


Ah. Forgot the main point - this encoding is the same in P7_BookIV so this 
could be used for P7 as well.


>
>>
>>
>>>> Is not 0x110
>>>> SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?
>>>
>>> Yes, it is
>>>
>>>> And is 0x100
>>>> SLB_VSID_L?
>>>
>>> Yes.
>>
>> Cool, thanks.
>>
>> btw why not to use those definitions then...
>
> I think I started trying to, but got into some #include complications
> that weren't worth the hassling of sorting out at the time.

A bit weird but ok.


-- 
Alexey