From: Wan Zongshun <vincent.wan@amd.com> To: Joerg Roedel <joro@8bytes.org>, <iommu@lists.linux-foundation.org> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>, Borislav Petkov <bp@suse.de>, Ray Huang <ray.huang@amd.com>, <ken.xue@amd.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH 1/6] iommu/amd: Modify ivhd_header structure to support type 11h and 40h Date: Tue, 5 Jan 2016 05:07:19 -0500 [thread overview] Message-ID: <1451988444-4694-2-git-send-email-vincent.wan@amd.com> (raw) In-Reply-To: <1451988444-4694-1-git-send-email-vincent.wan@amd.com> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> This patch modifies the existing struct ivhd_header, which currently only support IVHD type 0x10, to add new fields from IVHD type 11h and 40h. It also modifies the pointer calculation to allow support for IVHD type 11h and 40h Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> --- drivers/iommu/amd_iommu_init.c | 47 +++++++++++++++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 013bdff..2ff7000 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -88,7 +88,7 @@ /* * structure describing one IOMMU in the ACPI table. Typically followed by one - * or more ivhd_entrys. + * or more ivhd_entrys. This struct supports both IVHD type 10h, 11h and 40h. */ struct ivhd_header { u8 type; @@ -99,7 +99,11 @@ struct ivhd_header { u64 mmio_phys; u16 pci_seg; u16 info; - u32 efr; + u32 efr_attr; + + /* Following only valid on IVHD type 11h and 40h */ + u64 efr_reg_img; /* Exact copy of MMIO_EXT_FEATURES */ + u64 res; } __attribute__((packed)); /* @@ -399,6 +403,22 @@ static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) * ****************************************************************************/ +static inline u32 get_ivhd_header_size(struct ivhd_header *h) +{ + u32 size = 0; + + switch (h->type) { + case 0x10: + size = 24; + break; + case 0x11: + case 0x40: + size = 40; + break; + } + return size; +} + /* * This function calculates the length of a given IVHD entry */ @@ -415,8 +435,14 @@ static int __init find_last_devid_from_ivhd(struct ivhd_header *h) { u8 *p = (void *)h, *end = (void *)h; struct ivhd_entry *dev; + u32 ivhd_size = get_ivhd_header_size(h); + + if (!ivhd_size) { + pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type); + return -EINVAL; + } - p += sizeof(*h); + p += ivhd_size; end += h->length; while (p < end) { @@ -781,6 +807,7 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu, u32 dev_i, ext_flags = 0; bool alias = false; struct ivhd_entry *e; + u32 ivhd_size; int ret; @@ -796,7 +823,13 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu, /* * Done. Now parse the device entries */ - p += sizeof(struct ivhd_header); + ivhd_size = get_ivhd_header_size(h); + if (!ivhd_size) { + pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type); + return -EINVAL; + } + + p += ivhd_size; end += h->length; @@ -1047,9 +1080,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) iommu->mmio_phys = h->mmio_phys; /* Check if IVHD EFR contains proper max banks/counters */ - if ((h->efr != 0) && - ((h->efr & (0xF << 13)) != 0) && - ((h->efr & (0x3F << 17)) != 0)) { + if ((h->efr_attr != 0) && + ((h->efr_attr & (0xF << 13)) != 0) && + ((h->efr_attr & (0x3F << 17)) != 0)) { iommu->mmio_phys_end = MMIO_REG_END_OFFSET; } else { iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Wan Zongshun <vincent.wan-5C7GfCeVMHo@public.gmane.org> To: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Cc: Borislav Petkov <bp-l3A5Bk7waGM@public.gmane.org>, Ray Huang <ray.huang-5C7GfCeVMHo@public.gmane.org>, ken.xue-5C7GfCeVMHo@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH 1/6] iommu/amd: Modify ivhd_header structure to support type 11h and 40h Date: Tue, 5 Jan 2016 05:07:19 -0500 [thread overview] Message-ID: <1451988444-4694-2-git-send-email-vincent.wan@amd.com> (raw) In-Reply-To: <1451988444-4694-1-git-send-email-vincent.wan-5C7GfCeVMHo@public.gmane.org> From: Suravee Suthikulpanit <Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> This patch modifies the existing struct ivhd_header, which currently only support IVHD type 0x10, to add new fields from IVHD type 11h and 40h. It also modifies the pointer calculation to allow support for IVHD type 11h and 40h Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> --- drivers/iommu/amd_iommu_init.c | 47 +++++++++++++++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 013bdff..2ff7000 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -88,7 +88,7 @@ /* * structure describing one IOMMU in the ACPI table. Typically followed by one - * or more ivhd_entrys. + * or more ivhd_entrys. This struct supports both IVHD type 10h, 11h and 40h. */ struct ivhd_header { u8 type; @@ -99,7 +99,11 @@ struct ivhd_header { u64 mmio_phys; u16 pci_seg; u16 info; - u32 efr; + u32 efr_attr; + + /* Following only valid on IVHD type 11h and 40h */ + u64 efr_reg_img; /* Exact copy of MMIO_EXT_FEATURES */ + u64 res; } __attribute__((packed)); /* @@ -399,6 +403,22 @@ static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) * ****************************************************************************/ +static inline u32 get_ivhd_header_size(struct ivhd_header *h) +{ + u32 size = 0; + + switch (h->type) { + case 0x10: + size = 24; + break; + case 0x11: + case 0x40: + size = 40; + break; + } + return size; +} + /* * This function calculates the length of a given IVHD entry */ @@ -415,8 +435,14 @@ static int __init find_last_devid_from_ivhd(struct ivhd_header *h) { u8 *p = (void *)h, *end = (void *)h; struct ivhd_entry *dev; + u32 ivhd_size = get_ivhd_header_size(h); + + if (!ivhd_size) { + pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type); + return -EINVAL; + } - p += sizeof(*h); + p += ivhd_size; end += h->length; while (p < end) { @@ -781,6 +807,7 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu, u32 dev_i, ext_flags = 0; bool alias = false; struct ivhd_entry *e; + u32 ivhd_size; int ret; @@ -796,7 +823,13 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu, /* * Done. Now parse the device entries */ - p += sizeof(struct ivhd_header); + ivhd_size = get_ivhd_header_size(h); + if (!ivhd_size) { + pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type); + return -EINVAL; + } + + p += ivhd_size; end += h->length; @@ -1047,9 +1080,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) iommu->mmio_phys = h->mmio_phys; /* Check if IVHD EFR contains proper max banks/counters */ - if ((h->efr != 0) && - ((h->efr & (0xF << 13)) != 0) && - ((h->efr & (0x3F << 17)) != 0)) { + if ((h->efr_attr != 0) && + ((h->efr_attr & (0xF << 13)) != 0) && + ((h->efr_attr & (0x3F << 17)) != 0)) { iommu->mmio_phys_end = MMIO_REG_END_OFFSET; } else { iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; -- 1.9.1
next prev parent reply other threads:[~2016-01-05 2:44 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-05 10:07 [PATCH 0/6] iommu/amd: enable ACPI hardware ID device support Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun [this message] 2016-01-05 10:07 ` [PATCH 1/6] iommu/amd: Modify ivhd_header structure to support type 11h and 40h Wan Zongshun 2016-01-05 10:07 ` [PATCH 2/6] iommu/amd: Use the most comprehensive IVHD type that the driver can support Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun 2016-01-05 10:07 ` [PATCH 3/6] iommu/amd: Add new map for storing IVHD dev entry type HID Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun 2016-01-05 10:07 ` [PATCH 4/6] iommu/amd: Introduces ivrs_acpihid kernel parameter Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun 2016-01-05 10:07 ` [PATCH 5/6] iommu/amd: Add support for non-pci devices Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun 2016-01-07 12:04 ` Joerg Roedel 2016-01-07 12:04 ` Joerg Roedel 2016-01-08 3:15 ` Wan ZongShun 2016-01-08 3:15 ` Wan ZongShun 2016-01-08 12:18 ` Joerg Roedel 2016-01-08 14:52 ` Wan Zongshun 2016-01-08 14:52 ` Wan Zongshun 2016-01-08 17:01 ` Joerg Roedel 2016-01-08 17:01 ` Joerg Roedel 2016-01-09 9:47 ` Wan Zongshun 2016-01-20 12:00 ` Joerg Roedel 2016-01-05 10:07 ` [PATCH 6/6] iommu/amd: Manage iommu_group " Wan Zongshun 2016-01-05 10:07 ` Wan Zongshun 2016-01-07 12:06 ` Joerg Roedel 2016-01-07 12:06 ` Joerg Roedel 2016-01-08 1:44 ` Wan ZongShun 2016-01-05 15:40 ` [PATCH 0/6] iommu/amd: enable ACPI hardware ID device support Suravee Suthikulpanit 2016-01-05 15:40 ` Suravee Suthikulpanit
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