From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
Date: Mon, 18 Jan 2016 15:59:36 +0000 [thread overview]
Message-ID: <1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com> (raw)
In GuC submission mode, driver has to provide a list of registers to be
save/restored during gpu reset, make the max no. of registers value consistent
with that of the value defined in FW. If they are not in sync then register
save/restore during gpu reset won't work as expected.
Cc: Alex Dai <yu.dai@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 130d94c..1d8048b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -370,7 +370,7 @@ struct guc_policies {
#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
-#define GUC_REGSET_MAX_REGISTERS 20
+#define GUC_REGSET_MAX_REGISTERS 25
#define GUC_MMIO_WHITE_LIST_START 0x24d0
#define GUC_MMIO_WHITE_LIST_MAX 12
#define GUC_S3_SAVE_SPACE_PAGES 10
--
1.9.1
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next reply other threads:[~2016-01-18 15:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-18 15:59 Arun Siluvery [this message]
2016-01-18 16:20 ` ✗ Fi.CI.BAT: warning for drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC Patchwork
2016-01-18 16:29 ` Arun Siluvery
2016-01-19 17:51 ` Arun Siluvery
2016-01-19 18:13 ` [PATCH] " Yu Dai
2016-01-19 19:38 ` Daniel Vetter
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