* [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
@ 2016-01-18 15:59 Arun Siluvery
2016-01-18 16:20 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-01-19 18:13 ` [PATCH] " Yu Dai
0 siblings, 2 replies; 6+ messages in thread
From: Arun Siluvery @ 2016-01-18 15:59 UTC (permalink / raw)
To: intel-gfx
In GuC submission mode, driver has to provide a list of registers to be
save/restored during gpu reset, make the max no. of registers value consistent
with that of the value defined in FW. If they are not in sync then register
save/restore during gpu reset won't work as expected.
Cc: Alex Dai <yu.dai@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 130d94c..1d8048b 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -370,7 +370,7 @@ struct guc_policies {
#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
-#define GUC_REGSET_MAX_REGISTERS 20
+#define GUC_REGSET_MAX_REGISTERS 25
#define GUC_MMIO_WHITE_LIST_START 0x24d0
#define GUC_MMIO_WHITE_LIST_MAX 12
#define GUC_S3_SAVE_SPACE_PAGES 10
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* ✗ Fi.CI.BAT: warning for drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
2016-01-18 15:59 [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC Arun Siluvery
@ 2016-01-18 16:20 ` Patchwork
2016-01-18 16:29 ` Arun Siluvery
2016-01-19 17:51 ` Arun Siluvery
2016-01-19 18:13 ` [PATCH] " Yu Dai
1 sibling, 2 replies; 6+ messages in thread
From: Patchwork @ 2016-01-18 16:20 UTC (permalink / raw)
To: arun.siluvery; +Cc: intel-gfx
== Summary ==
Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass -> DMESG-WARN (byt-nuc)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (snb-x220t)
bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:140 pass:132 dwarn:1 dfail:1 fail:0 skip:6
bsw-nuc-2 total:143 pass:117 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:143 pass:124 dwarn:4 dfail:0 fail:0 skip:15
hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:143 pass:102 dwarn:3 dfail:0 fail:0 skip:38
ivb-t430s total:137 pass:124 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:143 pass:124 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:143 pass:124 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1214/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: ✗ Fi.CI.BAT: warning for drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
2016-01-18 16:20 ` ✗ Fi.CI.BAT: warning for " Patchwork
@ 2016-01-18 16:29 ` Arun Siluvery
2016-01-19 17:51 ` Arun Siluvery
1 sibling, 0 replies; 6+ messages in thread
From: Arun Siluvery @ 2016-01-18 16:29 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
On 18/01/2016 16:20, Patchwork wrote:
> == Summary ==
>
> Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
> pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
This patch only changes a define that is used only when GuC submission
is enabled (which is disabled by default), this dmesg-warn is not
related to this patch.
regards
Arun
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b-frame-sequence:
> pass -> DMESG-WARN (byt-nuc)
> Subgroup suspend-read-crc-pipe-a:
> dmesg-warn -> PASS (snb-x220t)
>
> bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
> bdw-ultra total:140 pass:132 dwarn:1 dfail:1 fail:0 skip:6
> bsw-nuc-2 total:143 pass:117 dwarn:2 dfail:0 fail:0 skip:24
> byt-nuc total:143 pass:124 dwarn:4 dfail:0 fail:0 skip:15
> hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7
> hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4
> ilk-hp8440p total:143 pass:102 dwarn:3 dfail:0 fail:0 skip:38
> ivb-t430s total:137 pass:124 dwarn:3 dfail:4 fail:0 skip:6
> skl-i5k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
> skl-i7k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
> snb-dellxps total:143 pass:124 dwarn:5 dfail:0 fail:0 skip:14
> snb-x220t total:143 pass:124 dwarn:5 dfail:0 fail:1 skip:13
>
> Results at /archive/results/CI_IGT_test/Patchwork_1214/
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ Fi.CI.BAT: warning for drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
2016-01-18 16:20 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-01-18 16:29 ` Arun Siluvery
@ 2016-01-19 17:51 ` Arun Siluvery
1 sibling, 0 replies; 6+ messages in thread
From: Arun Siluvery @ 2016-01-19 17:51 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
On 18/01/2016 16:20, Patchwork wrote:
> == Summary ==
>
> Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
> pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
This patch updates a #define which is only relevant in GuC Submission
mode (which is disabled by default).
This dmesg-warn is because of an existing issue,
https://bugs.freedesktop.org/show_bug.cgi?id=93693
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b-frame-sequence:
> pass -> DMESG-WARN (byt-nuc)
This is because of https://bugs.freedesktop.org/show_bug.cgi?id=93121
regards
Arun
> Subgroup suspend-read-crc-pipe-a:
> dmesg-warn -> PASS (snb-x220t)
>
> bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
> bdw-ultra total:140 pass:132 dwarn:1 dfail:1 fail:0 skip:6
> bsw-nuc-2 total:143 pass:117 dwarn:2 dfail:0 fail:0 skip:24
> byt-nuc total:143 pass:124 dwarn:4 dfail:0 fail:0 skip:15
> hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7
> hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4
> ilk-hp8440p total:143 pass:102 dwarn:3 dfail:0 fail:0 skip:38
> ivb-t430s total:137 pass:124 dwarn:3 dfail:4 fail:0 skip:6
> skl-i5k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
> skl-i7k-2 total:143 pass:133 dwarn:2 dfail:0 fail:0 skip:8
> snb-dellxps total:143 pass:124 dwarn:5 dfail:0 fail:0 skip:14
> snb-x220t total:143 pass:124 dwarn:5 dfail:0 fail:1 skip:13
>
> Results at /archive/results/CI_IGT_test/Patchwork_1214/
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
2016-01-18 15:59 [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC Arun Siluvery
2016-01-18 16:20 ` ✗ Fi.CI.BAT: warning for " Patchwork
@ 2016-01-19 18:13 ` Yu Dai
2016-01-19 19:38 ` Daniel Vetter
1 sibling, 1 reply; 6+ messages in thread
From: Yu Dai @ 2016-01-19 18:13 UTC (permalink / raw)
To: Arun Siluvery, intel-gfx
Thanks for capture the typo. LGTM.
Reviewed-by: Alex Dai <yu.dai@intel.com>
On 01/18/2016 07:59 AM, Arun Siluvery wrote:
> In GuC submission mode, driver has to provide a list of registers to be
> save/restored during gpu reset, make the max no. of registers value consistent
> with that of the value defined in FW. If they are not in sync then register
> save/restore during gpu reset won't work as expected.
>
> Cc: Alex Dai <yu.dai@intel.com>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 130d94c..1d8048b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -370,7 +370,7 @@ struct guc_policies {
> #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
> #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
>
> -#define GUC_REGSET_MAX_REGISTERS 20
> +#define GUC_REGSET_MAX_REGISTERS 25
> #define GUC_MMIO_WHITE_LIST_START 0x24d0
> #define GUC_MMIO_WHITE_LIST_MAX 12
> #define GUC_S3_SAVE_SPACE_PAGES 10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
2016-01-19 18:13 ` [PATCH] " Yu Dai
@ 2016-01-19 19:38 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2016-01-19 19:38 UTC (permalink / raw)
To: Yu Dai; +Cc: intel-gfx
On Tue, Jan 19, 2016 at 10:13:43AM -0800, Yu Dai wrote:
> Thanks for capture the typo. LGTM.
>
> Reviewed-by: Alex Dai <yu.dai@intel.com>
>
> On 01/18/2016 07:59 AM, Arun Siluvery wrote:
> >In GuC submission mode, driver has to provide a list of registers to be
> >save/restored during gpu reset, make the max no. of registers value consistent
> >with that of the value defined in FW. If they are not in sync then register
> >save/restore during gpu reset won't work as expected.
> >
> >Cc: Alex Dai <yu.dai@intel.com>
> >Cc: Dave Gordon <david.s.gordon@intel.com>
> >Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
> >---
> > drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> >index 130d94c..1d8048b 100644
> >--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> >+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> >@@ -370,7 +370,7 @@ struct guc_policies {
> > #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
> > #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
> >-#define GUC_REGSET_MAX_REGISTERS 20
> >+#define GUC_REGSET_MAX_REGISTERS 25
> > #define GUC_MMIO_WHITE_LIST_START 0x24d0
> > #define GUC_MMIO_WHITE_LIST_MAX 12
> > #define GUC_S3_SAVE_SPACE_PAGES 10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-19 19:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-18 15:59 [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC Arun Siluvery
2016-01-18 16:20 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-01-18 16:29 ` Arun Siluvery
2016-01-19 17:51 ` Arun Siluvery
2016-01-19 18:13 ` [PATCH] " Yu Dai
2016-01-19 19:38 ` Daniel Vetter
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.