[Qemu-devel] [PULL 0/4] target-mips queue

[Qemu-devel] [PULL 0/4] target-mips queue

[Leon Alrae]

Hi,

Here's my target-mips queue, few fixes and includes clean-up.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 047e363b05679724d6b784c6ec6310697fe48ba0:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-softfloat-20160122' into staging (2016-01-22 15:19:21 +0000)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20160125

for you to fetch changes up to c684822ad29968af09735148f03a511bc514589d:

  mips: Clean up includes (2016-01-23 14:30:04 +0000)

----------------------------------------------------------------
MIPS patches 2016-01-25

Changes:
* fixes and includes clean-up

----------------------------------------------------------------
Aurelien Jarno (1):
      target-mips: silence NaNs for cvt.s.d and cvt.d.s

Dongxue Zhang (1):
      target-mips/cpu.h: Fix spell error

Miodrag Dinic (1):
      target-mips: Fix ALIGN instruction when bp=0

Peter Maydell (1):
      mips: Clean up includes

 disas/mips.c             |  1 +
 hw/mips/addr.c           |  1 +
 hw/mips/cputimer.c       |  1 +
 hw/mips/gt64xxx_pci.c    |  1 +
 hw/mips/mips_fulong2e.c  |  1 +
 hw/mips/mips_int.c       |  1 +
 hw/mips/mips_jazz.c      |  1 +
 hw/mips/mips_malta.c     |  1 +
 hw/mips/mips_mipssim.c   |  1 +
 hw/mips/mips_r4k.c       |  1 +
 target-mips/cpu.c        |  1 +
 target-mips/cpu.h        |  2 +-
 target-mips/dsp_helper.c |  1 +
 target-mips/gdbstub.c    |  2 +-
 target-mips/helper.c     |  6 +-----
 target-mips/kvm.c        |  2 +-
 target-mips/lmi_helper.c |  1 +
 target-mips/machine.c    |  1 +
 target-mips/mips-semi.c  |  2 +-
 target-mips/msa_helper.c |  1 +
 target-mips/op_helper.c  |  4 +++-
 target-mips/translate.c  | 12 +++++++++++-
 22 files changed, 34 insertions(+), 11 deletions(-)

[Qemu-devel] [PULL 1/4] target-mips/cpu.h: Fix spell error

[Leon Alrae]

From: Dongxue Zhang <elta.era@gmail.com>

CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.

Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 89c01f7..17817c3 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -358,7 +358,7 @@ struct CPUMIPSState {
 #define CP0St_IE    0
     int32_t CP0_IntCtl;
 #define CP0IntCtl_IPTI 29
-#define CP0IntCtl_IPPC1 26
+#define CP0IntCtl_IPPCI 26
 #define CP0IntCtl_VS 5
     int32_t CP0_SRSCtl;
 #define CP0SRSCtl_HSS 26
-- 
2.1.0

[Qemu-devel] [PULL 2/4] target-mips: silence NaNs for cvt.s.d and cvt.d.s

[Leon Alrae]

From: Aurelien Jarno <aurelien@aurel32.net>

cvt.s.d and cvt.d.s are FP operations and thus need to convert input
sNaN into corresponding qNaN. Explicitely use the floatXX_maybe_silence_nan
functions for that as the floatXX_to_floatXX functions do not do that.

Cc: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/op_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index d2c98c9..20e79be 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2545,6 +2545,7 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
     uint64_t fdt2;
 
     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
+    fdt2 = float64_maybe_silence_nan(fdt2);
     update_fcr31(env, GETPC());
     return fdt2;
 }
@@ -2634,6 +2635,7 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
     uint32_t fst2;
 
     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
+    fst2 = float32_maybe_silence_nan(fst2);
     update_fcr31(env, GETPC());
     return fst2;
 }
-- 
2.1.0

[Qemu-devel] [PULL 3/4] target-mips: Fix ALIGN instruction when bp=0

[Leon Alrae]

From: Miodrag Dinic <miodrag.dinic@imgtec.com>

If executing ALIGN with shift count bp=0 within mips64 emulation,
the result of the operation should be sign extended.

Taken from the official documentation (pseudo code) :

ALIGN:
	tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
	tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
	tmp = tmp_rt_hi || tmp_rt_lo
	GPR[rd] = sign_extend.32(tmp)

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 5626647..d2443d3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4630,7 +4630,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
     t0 = tcg_temp_new();
     gen_load_gpr(t0, rt);
     if (bp == 0) {
-        tcg_gen_mov_tl(cpu_gpr[rd], t0);
+        switch (opc) {
+        case OPC_ALIGN:
+            tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
+            break;
+#if defined(TARGET_MIPS64)
+        case OPC_DALIGN:
+            tcg_gen_mov_tl(cpu_gpr[rd], t0);
+            break;
+#endif
+        }
     } else {
         TCGv t1 = tcg_temp_new();
         gen_load_gpr(t1, rs);
-- 
2.1.0

[Qemu-devel] [PULL 4/4] mips: Clean up includes

[Leon Alrae]

From: Peter Maydell <peter.maydell@linaro.org>

Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 disas/mips.c             | 1 +
 hw/mips/addr.c           | 1 +
 hw/mips/cputimer.c       | 1 +
 hw/mips/gt64xxx_pci.c    | 1 +
 hw/mips/mips_fulong2e.c  | 1 +
 hw/mips/mips_int.c       | 1 +
 hw/mips/mips_jazz.c      | 1 +
 hw/mips/mips_malta.c     | 1 +
 hw/mips/mips_mipssim.c   | 1 +
 hw/mips/mips_r4k.c       | 1 +
 target-mips/cpu.c        | 1 +
 target-mips/dsp_helper.c | 1 +
 target-mips/gdbstub.c    | 2 +-
 target-mips/helper.c     | 6 +-----
 target-mips/kvm.c        | 2 +-
 target-mips/lmi_helper.c | 1 +
 target-mips/machine.c    | 1 +
 target-mips/mips-semi.c  | 2 +-
 target-mips/msa_helper.c | 1 +
 target-mips/op_helper.c  | 2 +-
 target-mips/translate.c  | 1 +
 21 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/disas/mips.c b/disas/mips.c
index bf0bbaf..0e488d8 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -19,6 +19,7 @@ GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
 
+#include "qemu/osdep.h"
 #include "disas/bfd.h"
 
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
diff --git a/hw/mips/addr.c b/hw/mips/addr.c
index ff3b952..e4e86b4 100644
--- a/hw/mips/addr.c
+++ b/hw/mips/addr.c
@@ -20,6 +20,7 @@
  * THE SOFTWARE.
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/cpudevs.h"
 
diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
index f046588..efb227d 100644
--- a/hw/mips/cputimer.c
+++ b/hw/mips/cputimer.c
@@ -20,6 +20,7 @@
  * THE SOFTWARE.
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/cpudevs.h"
 #include "qemu/timer.h"
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c1f3c9c..3f4523d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -22,6 +22,7 @@
  * THE SOFTWARE.
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/mips.h"
 #include "hw/pci/pci.h"
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index 5988a88..6748d89 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -18,6 +18,7 @@
  * http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/i386/pc.h"
 #include "hw/char/serial.h"
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index d740046..59081f9 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -20,6 +20,7 @@
  * THE SOFTWARE.
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/cpudevs.h"
 #include "cpu.h"
diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c
index 1cfbaa6..62527fd 100644
--- a/hw/mips/mips_jazz.c
+++ b/hw/mips/mips_jazz.c
@@ -22,6 +22,7 @@
  * THE SOFTWARE.
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/mips.h"
 #include "hw/mips/cpudevs.h"
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 91c36ba..c5da83f 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -22,6 +22,7 @@
  * THE SOFTWARE.
  */
 
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/i386/pc.h"
 #include "hw/char/serial.h"
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
index 23b35be..8951ae9 100644
--- a/hw/mips/mips_mipssim.c
+++ b/hw/mips/mips_mipssim.c
@@ -24,6 +24,7 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/mips.h"
 #include "hw/mips/cpudevs.h"
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index 2d4e038..b6625ae 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -7,6 +7,7 @@
  * All peripherial devices are attached to this "bus" with
  * the standard PC ISA addresses.
 */
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/mips/mips.h"
 #include "hw/mips/cpudevs.h"
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 639a24b..0b3f130 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -18,6 +18,7 @@
  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  */
 
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "kvm_mips.h"
 #include "qemu-common.h"
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 46528de..df7d220 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -17,6 +17,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "exec/helper-proto.h"
 #include "qemu/bitops.h"
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index 9845d88..b0b4a32 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -17,7 +17,7 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
-#include "config.h"
+#include "qemu/osdep.h"
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
 
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 118072a..f9c4c11 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -16,11 +16,7 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
-#include <stdarg.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <inttypes.h>
+#include "qemu/osdep.h"
 
 #include "cpu.h"
 #include "sysemu/kvm.h"
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index ffc120d..a8b8b32 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -9,7 +9,7 @@
  * Authors: Sanjay Lal <sanjayl@kymasys.com>
 */
 
-#include <sys/types.h>
+#include "qemu/osdep.h"
 #include <sys/ioctl.h>
 #include <sys/mman.h>
 
diff --git a/target-mips/lmi_helper.c b/target-mips/lmi_helper.c
index bbfcd59..fb1245b 100644
--- a/target-mips/lmi_helper.c
+++ b/target-mips/lmi_helper.c
@@ -17,6 +17,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "exec/helper-proto.h"
 
diff --git a/target-mips/machine.c b/target-mips/machine.c
index b15c43a..737f3c2 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -1,3 +1,4 @@
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 
 #include "cpu.h"
diff --git a/target-mips/mips-semi.c b/target-mips/mips-semi.c
index 5050940..ed235de 100644
--- a/target-mips/mips-semi.c
+++ b/target-mips/mips-semi.c
@@ -17,7 +17,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <sys/stat.h>
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "exec/helper-proto.h"
 #include "exec/softmmu-semi.h"
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c
index b8e2917..654a0d2 100644
--- a/target-mips/msa_helper.c
+++ b/target-mips/msa_helper.c
@@ -17,6 +17,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "exec/helper-proto.h"
 
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 20e79be..684ec92 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -16,7 +16,7 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
-#include <stdlib.h>
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d2443d3..383d4b5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -21,6 +21,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "qemu/osdep.h"
 #include "cpu.h"
 #include "disas/disas.h"
 #include "tcg-op.h"
-- 
2.1.0

Re: [Qemu-devel] [PULL 0/4] target-mips queue

[Peter Maydell]

On 25 January 2016 at 10:02, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Here's my target-mips queue, few fixes and includes clean-up.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit 047e363b05679724d6b784c6ec6310697fe48ba0:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-softfloat-20160122' into staging (2016-01-22 15:19:21 +0000)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20160125
>
> for you to fetch changes up to c684822ad29968af09735148f03a511bc514589d:
>
>   mips: Clean up includes (2016-01-23 14:30:04 +0000)
>
> ----------------------------------------------------------------
> MIPS patches 2016-01-25
>
> Changes:
> * fixes and includes clean-up

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 0/4] target-mips queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 1392 bytes --]

On Sun, Dec 04, 2016 at 02:00:13AM +0000, Yongbok Kim wrote:
> Hi,
> 
> This is pull-req for target-mips.
> 
> Regards,
> Yongbok
> 
> The following changes since commit bd8ef5060dd2124a54578241da9a572faf7658dd:
> 
>   Merge remote-tracking branch 'dgibson/tags/ppc-for-2.8-20161201' into staging (2016-12-01 13:39:29 +0000)
> 
> are available in the git repository at:
> 
>   git://github.com/yongbok/upstream-qemu.git tags/mips-20161204
> 
> for you to fetch changes up to e6e2784cacd4cfec149a7690976b9ff15e541c4d:
> 
>   target-mips: fix bad shifts in {dextp|dextpdp} (2016-12-04 00:57:06 +0000)
> 
> ----------------------------------------------------------------
> MIPS patches 2016-12-04
> 
> Changes:
> * Fix Loongson instructions
> * Fix bad shifts in {dextp|dextpdp}
> 
> ----------------------------------------------------------------
> Heiher (3):
>       target-mips: Fix Loongson pandn instruction.
>       target-mips: Fix Loongson multimedia 'or' instruction.
>       target-mips: Fix Loongson multimedia instructions.
> 
> Yongbok Kim (1):
>       target-mips: fix bad shifts in {dextp|dextpdp}
> 
>  target-mips/dsp_helper.c | 4 ++--
>  target-mips/translate.c  | 8 ++++++--
>  2 files changed, 8 insertions(+), 4 deletions(-)
> 
> 

Thanks, applied to my staging tree:
https://github.com/stefanha/qemu/commits/staging

Stefan

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 455 bytes --]

[Qemu-devel] [PULL 0/4] target-mips queue

[Yongbok Kim]

Hi,

This is pull-req for target-mips.

Regards,
Yongbok

The following changes since commit bd8ef5060dd2124a54578241da9a572faf7658dd:

  Merge remote-tracking branch 'dgibson/tags/ppc-for-2.8-20161201' into staging (2016-12-01 13:39:29 +0000)

are available in the git repository at:

  git://github.com/yongbok/upstream-qemu.git tags/mips-20161204

for you to fetch changes up to e6e2784cacd4cfec149a7690976b9ff15e541c4d:

  target-mips: fix bad shifts in {dextp|dextpdp} (2016-12-04 00:57:06 +0000)

----------------------------------------------------------------
MIPS patches 2016-12-04

Changes:
* Fix Loongson instructions
* Fix bad shifts in {dextp|dextpdp}

----------------------------------------------------------------
Heiher (3):
      target-mips: Fix Loongson pandn instruction.
      target-mips: Fix Loongson multimedia 'or' instruction.
      target-mips: Fix Loongson multimedia instructions.

Yongbok Kim (1):
      target-mips: fix bad shifts in {dextp|dextpdp}

 target-mips/dsp_helper.c | 4 ++--
 target-mips/translate.c  | 8 ++++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-mips queue

[Peter Maydell]

On 13 August 2015 at 17:45, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> First target-mips pull request for 2.5 consisting of patches sent during
> 2.4 freeze.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:
>
>   Open 2.5 development tree (2015-08-11 23:15:55 +0100)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20150813
>
> for you to fetch changes up to c85570163bdf1ba29cb52a63f22ff1c48f1b9398:
>
>   target-mips: Use CPU_LOG_INT for logging related to interrupts (2015-08-13 16:22:53 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2015-08-13
>
> Changes:
> * mips32r5-generic CPU updated and renamed to P5600
> * improvements in LWL/LDL, logging and fulong2e

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-mips queue

[Leon Alrae]

Hi,

First target-mips pull request for 2.5 consisting of patches sent during
2.4 freeze.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:

  Open 2.5 development tree (2015-08-11 23:15:55 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20150813

for you to fetch changes up to c85570163bdf1ba29cb52a63f22ff1c48f1b9398:

  target-mips: Use CPU_LOG_INT for logging related to interrupts (2015-08-13 16:22:53 +0100)

----------------------------------------------------------------
MIPS patches 2015-08-13

Changes:
* mips32r5-generic CPU updated and renamed to P5600
* improvements in LWL/LDL, logging and fulong2e

----------------------------------------------------------------
Aurelien Jarno (1):
      target-mips: simplify LWL/LDL mask generation

Peter Maydell (1):
      hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses

Richard Henderson (1):
      target-mips: Use CPU_LOG_INT for logging related to interrupts

Yongbok Kim (1):
      target-mips: update mips32r5-generic into P5600

 hw/pci-host/bonito.c         | 16 +++++++++++++
 target-mips/cpu.h            |  2 +-
 target-mips/helper.c         | 30 +++++++++----------------
 target-mips/op_helper.c      |  3 ++-
 target-mips/translate.c      | 14 +++++-------
 target-mips/translate_init.c | 53 ++++++++++++++++++++++++--------------------
 6 files changed, 65 insertions(+), 53 deletions(-)