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* [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller
@ 2016-03-15  9:59 Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
                   ` (10 more replies)
  0 siblings, 11 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Here's version 2 of the patchset providing minimal CPC implementation allowing
the guest to bring up other Virtual Processors (if more than 1 are present).
Guest can check if CPC is available by reading GCR's memory-mapped registers
and put VPs into run state by writing into CPC's memory-mapped registers.

I decided to remove the depenence on outstanding GIC patchset which still
requires updating, so I cherry-picked 2 patches which introduce GCR and also
implemented a container for a CPU with VPs, GCR and CPC. Version 2 has now
the following patches:

Patch 1 implements Coherent Processing System (CPS) container which
        initializes VPs
Patches 2-4 implement GCR and add it to CPS
Patches 5-6 implement CPC and add it to CPS
Patches 7-10 minor Malta board clean-up and adding CPS to it
Patch 11 enable CMGCR bit

The container with Coherent Processing System components is enabled only if
user specifies smp > 1 on Malta board and given CPU supports CMGCR.

This series applies on top of the "default-configs: add mips-softmmu-common.mak"
patch.

Comments are welcome.

Thanks,
Leon

v2:
* save CPC's state and make use of reset function (Peter)
* CPC is disabled on reset; guest is responsible for enabling it via GCR
* remove CPC_VP_PER_CORE_MAX constant and make VP Run mask depending on num-vp
* add vp-start-running property to indicate which VPs should run from reset
* cherry-picked 2 GCR patches from GIC patch series and fixed issues
  pointed out during the review:
  1) https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg06424.html
     * moved CP0C3_CMGCR bit enabling to a separate patch (James)
  2) https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg06423.html
     * removed GIC part as GIC doesn't exist yet at that point (James)
     * mips_gcr.{c,h} files renamed to mips_cmgcr.{c,h} (James)
     * remove whitespace before ";" after MIPSGCRState definition (James)
     * changed commit message
     * replace CONFIG_MIPS_GIC with CONFIG_MIPS_CPS which is used also for
       other CPS components
     * fixed format specifiers in qemu_log_mask (use PRIx64 instead of %lx)
* create a container for CPS components as it was suggested in the GIC patch
  series (Peter)

Leon Alrae (9):
  hw/mips: implement generic MIPS Coherent Processing System container
  hw/mips/cps: create GCR block inside CPS
  hw/mips: add initial Cluster Power Controller support
  hw/mips/cps: create CPC block inside CPS
  hw/mips_malta: remove CPUMIPSState from the write_bootloader()
  hw/mips_malta: remove redundant irq and clock init
  hw/mips_malta: move CPU creation to a separate function
  hw/mips_malta: add CPS to Malta board
  target-mips: enable CM GCR in MIPS64R6-generic CPU

Yongbok Kim (2):
  target-mips: add CMGCRBase register
  hw/mips: add initial Global Config Register support

 default-configs/mips-softmmu-common.mak |   1 +
 hw/mips/Makefile.objs                   |   1 +
 hw/mips/cps.c                           | 147 ++++++++++++++++++++++++++
 hw/mips/mips_malta.c                    | 118 ++++++++++++++-------
 hw/misc/Makefile.objs                   |   2 +
 hw/misc/mips_cmgcr.c                    | 159 +++++++++++++++++++++++++++++
 hw/misc/mips_cpc.c                      | 176 ++++++++++++++++++++++++++++++++
 include/hw/mips/cps.h                   |  44 ++++++++
 include/hw/misc/mips_cmgcr.h            |  59 +++++++++++
 include/hw/misc/mips_cpc.h              |  47 +++++++++
 target-mips/cpu.h                       |   4 +-
 target-mips/translate.c                 |  28 +++++
 target-mips/translate_init.c            |   3 +-
 13 files changed, 750 insertions(+), 39 deletions(-)
 create mode 100644 hw/mips/cps.c
 create mode 100644 hw/misc/mips_cmgcr.c
 create mode 100644 hw/misc/mips_cpc.c
 create mode 100644 include/hw/mips/cps.h
 create mode 100644 include/hw/misc/mips_cmgcr.h
 create mode 100644 include/hw/misc/mips_cpc.h

-- 
2.1.0

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 02/11] target-mips: add CMGCRBase register Leon Alrae
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Implement generic MIPS Coherent Processing System (CPS) which in this
commit just creates VPs, but it will serve as a container also for
other components like Global Configuration Registers and Cluster Power
Controller.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 default-configs/mips-softmmu-common.mak |   1 +
 hw/mips/Makefile.objs                   |   1 +
 hw/mips/cps.c                           | 108 ++++++++++++++++++++++++++++++++
 include/hw/mips/cps.h                   |  40 ++++++++++++
 4 files changed, 150 insertions(+)
 create mode 100644 hw/mips/cps.c
 create mode 100644 include/hw/mips/cps.h

diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips-softmmu-common.mak
index 37009a3..18e4beb 100644
--- a/default-configs/mips-softmmu-common.mak
+++ b/default-configs/mips-softmmu-common.mak
@@ -30,3 +30,4 @@ CONFIG_I8259=y
 CONFIG_MC146818RTC=y
 CONFIG_ISA_TESTDEV=y
 CONFIG_EMPTY_SLOT=y
+CONFIG_MIPS_CPS=y
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 9633f3a..9352a1c 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -3,3 +3,4 @@ obj-y += addr.o cputimer.o mips_int.o
 obj-$(CONFIG_JAZZ) += mips_jazz.o
 obj-$(CONFIG_FULONG) += mips_fulong2e.o
 obj-y += gt64xxx_pci.o
+obj-$(CONFIG_MIPS_CPS) += cps.o
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
new file mode 100644
index 0000000..782aa2b
--- /dev/null
+++ b/hw/mips/cps.c
@@ -0,0 +1,108 @@
+/*
+ * Coherent Processing System emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/mips/cps.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+
+qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
+{
+    MIPSCPU *cpu = MIPS_CPU(first_cpu);
+    CPUMIPSState *env = &cpu->env;
+
+    assert(pin_number < s->num_irq);
+
+    /* TODO: return GIC pins once implemented */
+    return env->irq[pin_number];
+}
+
+static void mips_cps_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    MIPSCPSState *s = MIPS_CPS(obj);
+
+    /* Cover entire address space as there do not seem to be any
+     * constraints for the base address of CPC and GIC. */
+    memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
+    sysbus_init_mmio(sbd, &s->container);
+}
+
+static void main_cpu_reset(void *opaque)
+{
+    MIPSCPU *cpu = opaque;
+    CPUState *cs = CPU(cpu);
+
+    cpu_reset(cs);
+
+    /* All VPs are halted on reset. Leave powering up to CPC. */
+    cs->halted = 1;
+}
+
+static void mips_cps_realize(DeviceState *dev, Error **errp)
+{
+    MIPSCPSState *s = MIPS_CPS(dev);
+    CPUMIPSState *env;
+    MIPSCPU *cpu;
+    int i;
+
+    for (i = 0; i < s->num_vp; i++) {
+        cpu = cpu_mips_init(s->cpu_model);
+        if (cpu == NULL) {
+            error_setg(errp, "%s: CPU initialization failed\n",  __func__);
+            return;
+        }
+        env = &cpu->env;
+
+        /* Init internal devices */
+        cpu_mips_irq_init_cpu(env);
+        cpu_mips_clock_init(env);
+        qemu_register_reset(main_cpu_reset, cpu);
+    }
+}
+
+static Property mips_cps_properties[] = {
+    DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
+    DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 8),
+    DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
+    DEFINE_PROP_END_OF_LIST()
+};
+
+static void mips_cps_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = mips_cps_realize;
+    dc->props = mips_cps_properties;
+}
+
+static const TypeInfo mips_cps_info = {
+    .name = TYPE_MIPS_CPS,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MIPSCPSState),
+    .instance_init = mips_cps_init,
+    .class_init = mips_cps_class_init,
+};
+
+static void mips_cps_register_types(void)
+{
+    type_register_static(&mips_cps_info);
+}
+
+type_init(mips_cps_register_types)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
new file mode 100644
index 0000000..fb3528a
--- /dev/null
+++ b/include/hw/mips/cps.h
@@ -0,0 +1,40 @@
+/*
+ * Coherent Processing System emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_CPS_H
+#define MIPS_CPS_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_MIPS_CPS "mips-cps"
+#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
+
+typedef struct MIPSCPSState {
+    SysBusDevice parent_obj;
+
+    uint32_t num_vp;
+    uint32_t num_irq;
+    char *cpu_model;
+
+    MemoryRegion container;
+} MIPSCPSState;
+
+qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
+
+#endif
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 02/11] target-mips: add CMGCRBase register
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 03/11] hw/mips: add initial Global Config Register support Leon Alrae
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

From: Yongbok Kim <yongbok.kim@imgtec.com>

Physical base address for the memory-mapped Coherency Manager Global
Configuration Register space.
The MIPS default location for the GCR_BASE address is 0x1FBF_8.
This register only exists if Config3 CMGCR is set to one.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com: move CMGCR enabling to a separate patch]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/cpu.h       |  3 ++-
 target-mips/translate.c | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4f3ebb9..55d3224 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -395,6 +395,7 @@ struct CPUMIPSState {
     target_ulong CP0_EPC;
     int32_t CP0_PRid;
     int32_t CP0_EBase;
+    target_ulong CP0_CMGCRBase;
     int32_t CP0_Config0;
 #define CP0C0_M    31
 #define CP0C0_K23  28
@@ -437,7 +438,7 @@ struct CPUMIPSState {
     int32_t CP0_Config3;
 #define CP0C3_M    31
 #define CP0C3_BPG  30
-#define CP0C3_CMCGR 29
+#define CP0C3_CMGCR 29
 #define CP0C3_MSAP  28
 #define CP0C3_BP 27
 #define CP0C3_BI 26
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0f43bf4..8191b92 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1432,6 +1432,7 @@ typedef struct DisasContext {
     int CP0_LLAddr_shift;
     bool ps;
     bool vp;
+    bool cmgcr;
 } DisasContext;
 
 enum {
@@ -5298,6 +5299,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
             rn = "EBase";
             break;
+        case 3:
+            check_insn(ctx, ISA_MIPS32R2);
+            CP0_CHECK(ctx->cmgcr);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+            tcg_gen_ext32s_tl(arg, arg);
+            rn = "CMGCRBase";
+            break;
         default:
             goto cp0_unimplemented;
        }
@@ -6572,6 +6580,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
             rn = "EBase";
             break;
+        case 3:
+            check_insn(ctx, ISA_MIPS32R2);
+            CP0_CHECK(ctx->cmgcr);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+            rn = "CMGCRBase";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -19663,6 +19677,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
     ctx.PAMask = env->PAMask;
     ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
     ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
+    ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
     /* Restore delay slot state from the tb context.  */
     ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
     ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
@@ -20062,6 +20077,9 @@ void cpu_state_reset(CPUMIPSState *env)
     } else {
         env->CP0_EBase |= 0x80000000;
     }
+    if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
+        env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
+    }
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
     /* vectored interrupts not implemented, timer on int 7,
        no performance counters. */
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 03/11] hw/mips: add initial Global Config Register support
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 02/11] target-mips: add CMGCRBase register Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS Leon Alrae
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

From: Yongbok Kim <yongbok.kim@imgtec.com>

Add initial GCR support to indicate number of VPs present in the system,
L2 bypass mode and revision number.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com:
 * removed GIC part,
 * changed commit message,
 * replaced %lx format spec. with PRIx64,
 * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h},
 * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/misc/Makefile.objs        |   1 +
 hw/misc/mips_cmgcr.c         | 106 +++++++++++++++++++++++++++++++++++++++++++
 include/hw/misc/mips_cmgcr.h |  49 ++++++++++++++++++++
 3 files changed, 156 insertions(+)
 create mode 100644 hw/misc/mips_cmgcr.c
 create mode 100644 include/hw/misc/mips_cmgcr.h

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ea6cd3c..61faa05 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,6 +42,7 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 obj-$(CONFIG_ZYNQ) += zynq-xadc.o
 obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
+obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_EDU) += edu.o
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
new file mode 100644
index 0000000..bf3be79
--- /dev/null
+++ b/hw/misc/mips_cmgcr.c
@@ -0,0 +1,106 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ *
+ * Copyright (C) 2015 Imagination Technologies
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "hw/misc/mips_cmgcr.h"
+
+/* Read GCR registers */
+static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
+{
+    MIPSGCRState *gcr = (MIPSGCRState *) opaque;
+
+    switch (addr) {
+    /* Global Control Block Register */
+    case GCR_CONFIG_OFS:
+        /* Set PCORES to 0 */
+        return 0;
+    case GCR_BASE_OFS:
+        return gcr->gcr_base;
+    case GCR_REV_OFS:
+        return gcr->gcr_rev;
+    case GCR_L2_CONFIG_OFS:
+        /* L2 BYPASS */
+        return GCR_L2_CONFIG_BYPASS_MSK;
+        /* Core-Local and Core-Other Control Blocks */
+    case MIPS_CLCB_OFS + GCR_CL_CONFIG_OFS:
+    case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS:
+        /* Set PVP to # of VPs - 1 */
+        return gcr->num_vps - 1;
+    case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:
+        return 0;
+    default:
+        qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx
+                      "\n", size, addr);
+        return 0;
+    }
+    return 0;
+}
+
+/* Write GCR registers */
+static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
+{
+    switch (addr) {
+    default:
+        qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx
+                      " 0x%" PRIx64 "\n", size, addr, data);
+        break;
+    }
+}
+
+static const MemoryRegionOps gcr_ops = {
+    .read = gcr_read,
+    .write = gcr_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .max_access_size = 8,
+    },
+};
+
+static void mips_gcr_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    MIPSGCRState *s = MIPS_GCR(obj);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s,
+                          "mips-gcr", GCR_ADDRSPACE_SZ);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static Property mips_gcr_properties[] = {
+    DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
+    DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
+    DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void mips_gcr_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->props = mips_gcr_properties;
+}
+
+static const TypeInfo mips_gcr_info = {
+    .name          = TYPE_MIPS_GCR,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MIPSGCRState),
+    .instance_init = mips_gcr_init,
+    .class_init    = mips_gcr_class_init,
+};
+
+static void mips_gcr_register_types(void)
+{
+    type_register_static(&mips_gcr_info);
+}
+
+type_init(mips_gcr_register_types)
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h
new file mode 100644
index 0000000..69403c3
--- /dev/null
+++ b/include/hw/misc/mips_cmgcr.h
@@ -0,0 +1,49 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2015 Imagination Technologies
+ *
+ */
+
+#ifndef _MIPS_GCR_H
+#define _MIPS_GCR_H
+
+#define TYPE_MIPS_GCR "mips-gcr"
+#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
+
+#define GCR_BASE_ADDR           0x1fbf8000ULL
+#define GCR_ADDRSPACE_SZ        0x8000
+
+/* Offsets to register blocks */
+#define MIPS_GCB_OFS        0x0000 /* Global Control Block */
+#define MIPS_CLCB_OFS       0x2000 /* Core Local Control Block */
+#define MIPS_COCB_OFS       0x4000 /* Core Other Control Block */
+#define MIPS_GDB_OFS        0x6000 /* Global Debug Block */
+
+/* Global Control Block Register Map */
+#define GCR_CONFIG_OFS      0x0000
+#define GCR_BASE_OFS        0x0008
+#define GCR_REV_OFS         0x0030
+#define GCR_L2_CONFIG_OFS   0x0130
+
+/* Core Local and Core Other Block Register Map */
+#define GCR_CL_CONFIG_OFS   0x0010
+#define GCR_CL_OTHER_OFS    0x0018
+
+/* GCR_L2_CONFIG register fields */
+#define GCR_L2_CONFIG_BYPASS_SHF    20
+#define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
+
+typedef struct MIPSGCRState MIPSGCRState;
+struct MIPSGCRState {
+    SysBusDevice parent_obj;
+
+    int32_t gcr_rev;
+    int32_t num_vps;
+    hwaddr gcr_base;
+    MemoryRegion iomem;
+};
+
+#endif /* _MIPS_GCR_H */
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (2 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 03/11] hw/mips: add initial Global Config Register support Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 05/11] hw/mips: add initial Cluster Power Controller support Leon Alrae
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/cps.c         | 23 +++++++++++++++++++++++
 include/hw/mips/cps.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 782aa2b..cfd808d 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -61,6 +61,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
     CPUMIPSState *env;
     MIPSCPU *cpu;
     int i;
+    Error *err = NULL;
+    target_ulong gcr_base;
 
     for (i = 0; i < s->num_vp; i++) {
         cpu = cpu_mips_init(s->cpu_model);
@@ -75,6 +77,27 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
         cpu_mips_clock_init(env);
         qemu_register_reset(main_cpu_reset, cpu);
     }
+
+    cpu = MIPS_CPU(first_cpu);
+    env = &cpu->env;
+
+    /* Global Configuration Registers */
+    gcr_base = env->CP0_CMGCRBase << 4;
+
+    object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
+    qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
+
+    object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
+    object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
+    object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
+    object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    memory_region_add_subregion(&s->container, gcr_base,
+                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
 }
 
 static Property mips_cps_properties[] = {
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index fb3528a..1b200d6 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -21,6 +21,7 @@
 #define MIPS_CPS_H
 
 #include "hw/sysbus.h"
+#include "hw/misc/mips_cmgcr.h"
 
 #define TYPE_MIPS_CPS "mips-cps"
 #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
@@ -33,6 +34,7 @@ typedef struct MIPSCPSState {
     char *cpu_model;
 
     MemoryRegion container;
+    MIPSGCRState gcr;
 } MIPSCPSState;
 
 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 05/11] hw/mips: add initial Cluster Power Controller support
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (3 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 06/11] hw/mips/cps: create CPC block inside CPS Leon Alrae
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Cluster Power Controller (CPC) is responsible for power management in
multiprocessing system. It provides registers to control the power and the
clock frequency of the individual elements in the system.

This patch implements only three registers that are used to control the
power state of each VP on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/misc/Makefile.objs      |   1 +
 hw/misc/mips_cpc.c         | 176 +++++++++++++++++++++++++++++++++++++++++++++
 include/hw/misc/mips_cpc.h |  47 ++++++++++++
 3 files changed, 224 insertions(+)
 create mode 100644 hw/misc/mips_cpc.c
 create mode 100644 include/hw/misc/mips_cpc.h

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 61faa05..790243f 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -43,6 +43,7 @@ obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 obj-$(CONFIG_ZYNQ) += zynq-xadc.o
 obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
 obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
+obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_EDU) += edu.o
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
new file mode 100644
index 0000000..b53253d
--- /dev/null
+++ b/hw/misc/mips_cpc.c
@@ -0,0 +1,176 @@
+/*
+ * Cluster Power Controller emulation
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+
+#include "hw/misc/mips_cpc.h"
+
+static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
+{
+    return (1ULL << cpc->num_vp) - 1;
+}
+
+static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
+{
+    CPUState *cs = first_cpu;
+
+    CPU_FOREACH(cs) {
+        uint64_t i = 1ULL << cs->cpu_index;
+        if (i & vp_run & ~cpc->vp_running) {
+            cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
+            cpc->vp_running |= i;
+        }
+    }
+}
+
+static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
+{
+    CPUState *cs = first_cpu;
+
+    CPU_FOREACH(cs) {
+        uint64_t i = 1ULL << cs->cpu_index;
+        if (i & vp_stop & cpc->vp_running) {
+            cs->halted = 1;
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
+            cpc->vp_running &= ~i;
+        }
+    }
+}
+
+static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
+                      unsigned size)
+{
+    MIPSCPCState *s = opaque;
+
+    switch (offset) {
+    case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
+    case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
+        cpc_run_vp(s, data & cpc_vp_run_mask(s));
+        break;
+    case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
+    case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
+        cpc_stop_vp(s, data & cpc_vp_run_mask(s));
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+        break;
+    }
+
+    return;
+}
+
+static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
+{
+    MIPSCPCState *s = opaque;
+
+    switch (offset) {
+    case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
+    case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
+        return s->vp_running;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+        return 0;
+    }
+}
+
+static const MemoryRegionOps cpc_ops = {
+    .read = cpc_read,
+    .write = cpc_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .max_access_size = 8,
+    },
+};
+
+static void mips_cpc_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    MIPSCPCState *s = MIPS_CPC(obj);
+
+    memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
+                          CPC_ADDRSPACE_SZ);
+    sysbus_init_mmio(sbd, &s->mr);
+}
+
+static void mips_cpc_realize(DeviceState *dev, Error **errp)
+{
+    MIPSCPCState *s = MIPS_CPC(dev);
+
+    if (s->vp_start_running > cpc_vp_run_mask(s)) {
+        error_setg(errp,
+                   "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
+                   s->vp_running, s->num_vp);
+        return;
+    }
+}
+
+static void mips_cpc_reset(DeviceState *dev)
+{
+    MIPSCPCState *s = MIPS_CPC(dev);
+
+    /* Reflect the fact that all VPs are halted on reset */
+    s->vp_running = 0;
+
+    /* Put selected VPs into run state */
+    cpc_run_vp(s, s->vp_start_running);
+}
+
+static const VMStateDescription vmstate_mips_cpc = {
+    .name = "mips-cpc",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(vp_running, MIPSCPCState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static Property mips_cpc_properties[] = {
+    DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
+    DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void mips_cpc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = mips_cpc_realize;
+    dc->reset = mips_cpc_reset;
+    dc->vmsd = &vmstate_mips_cpc;
+    dc->props = mips_cpc_properties;
+}
+
+static const TypeInfo mips_cpc_info = {
+    .name          = TYPE_MIPS_CPC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MIPSCPCState),
+    .instance_init = mips_cpc_init,
+    .class_init    = mips_cpc_class_init,
+};
+
+static void mips_cpc_register_types(void)
+{
+    type_register_static(&mips_cpc_info);
+}
+
+type_init(mips_cpc_register_types)
diff --git a/include/hw/misc/mips_cpc.h b/include/hw/misc/mips_cpc.h
new file mode 100644
index 0000000..72c834e
--- /dev/null
+++ b/include/hw/misc/mips_cpc.h
@@ -0,0 +1,47 @@
+/*
+ * Cluster Power Controller emulation
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_CPC_H
+#define MIPS_CPC_H
+
+#define CPC_ADDRSPACE_SZ    0x6000
+
+/* CPC blocks offsets relative to base address */
+#define CPC_CL_BASE_OFS     0x2000
+#define CPC_CO_BASE_OFS     0x4000
+
+/* CPC register offsets relative to block offsets */
+#define CPC_VP_STOP_OFS     0x20
+#define CPC_VP_RUN_OFS      0x28
+#define CPC_VP_RUNNING_OFS  0x30
+
+#define TYPE_MIPS_CPC "mips-cpc"
+#define MIPS_CPC(obj) OBJECT_CHECK(MIPSCPCState, (obj), TYPE_MIPS_CPC)
+
+typedef struct MIPSCPCState {
+    SysBusDevice parent_obj;
+
+    uint32_t num_vp;
+    uint64_t vp_start_running; /* VPs running from restart */
+
+    MemoryRegion mr;
+    uint64_t vp_running; /* Indicates which VPs are in the run state */
+} MIPSCPCState;
+
+#endif /* MIPS_CPC_H */
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 06/11] hw/mips/cps: create CPC block inside CPS
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (4 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 05/11] hw/mips: add initial Cluster Power Controller support Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 07/11] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Create Cluster Power Controller and add a link to the CPC MemoryRegion
in GCR. Guest can enable / map CPC to any physical address by writing to
the memory-mapped GCR_CPC_BASE register.

Set vp-start-reset property to 1 to allow only first VP to run from reset.
Others are brought up by the guest via CPC memory-mapped registers.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/cps.c                | 16 +++++++++++++
 hw/misc/mips_cmgcr.c         | 53 ++++++++++++++++++++++++++++++++++++++++++++
 include/hw/mips/cps.h        |  2 ++
 include/hw/misc/mips_cmgcr.h | 10 +++++++++
 4 files changed, 81 insertions(+)

diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index cfd808d..59e7926 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -81,6 +81,21 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
     cpu = MIPS_CPU(first_cpu);
     env = &cpu->env;
 
+    /* Cluster Power Controller */
+    object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
+    qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
+
+    object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
+    object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
+    object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    memory_region_add_subregion(&s->container, 0,
+                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
+
     /* Global Configuration Registers */
     gcr_base = env->CP0_CMGCRBase << 4;
 
@@ -90,6 +105,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
     object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
     object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
     object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
+    object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
     object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
     if (err != NULL) {
         error_propagate(errp, err);
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
index bf3be79..c43b61b 100644
--- a/hw/misc/mips_cmgcr.c
+++ b/hw/misc/mips_cmgcr.c
@@ -14,6 +14,25 @@
 #include "hw/sysbus.h"
 #include "sysemu/sysemu.h"
 #include "hw/misc/mips_cmgcr.h"
+#include "hw/misc/mips_cpc.h"
+
+static inline bool is_cpc_connected(MIPSGCRState *s)
+{
+    return s->cpc_mr != NULL;
+}
+
+static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
+{
+    if (is_cpc_connected(gcr)) {
+        gcr->cpc_base = val & GCR_CPC_BASE_MSK;
+        memory_region_transaction_begin();
+        memory_region_set_address(gcr->cpc_mr,
+                                  gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK);
+        memory_region_set_enabled(gcr->cpc_mr,
+                                  gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK);
+        memory_region_transaction_commit();
+    }
+}
 
 /* Read GCR registers */
 static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
@@ -29,6 +48,10 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
         return gcr->gcr_base;
     case GCR_REV_OFS:
         return gcr->gcr_rev;
+    case GCR_CPC_BASE_OFS:
+        return gcr->cpc_base;
+    case GCR_CPC_STATUS_OFS:
+        return is_cpc_connected(gcr);
     case GCR_L2_CONFIG_OFS:
         /* L2 BYPASS */
         return GCR_L2_CONFIG_BYPASS_MSK;
@@ -50,7 +73,12 @@ static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
 /* Write GCR registers */
 static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
 {
+    MIPSGCRState *gcr = (MIPSGCRState *)opaque;
+
     switch (addr) {
+    case GCR_CPC_BASE_OFS:
+        update_cpc_base(gcr, data);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx
                       " 0x%" PRIx64 "\n", size, addr, data);
@@ -72,11 +100,34 @@ static void mips_gcr_init(Object *obj)
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     MIPSGCRState *s = MIPS_GCR(obj);
 
+    object_property_add_link(obj, "cpc", TYPE_MEMORY_REGION,
+                             (Object **)&s->cpc_mr,
+                             qdev_prop_allow_set_link_before_realize,
+                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
+                             &error_abort);
+
     memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s,
                           "mips-gcr", GCR_ADDRSPACE_SZ);
     sysbus_init_mmio(sbd, &s->iomem);
 }
 
+static void mips_gcr_reset(DeviceState *dev)
+{
+    MIPSGCRState *s = MIPS_GCR(dev);
+
+    update_cpc_base(s, 0);
+}
+
+static const VMStateDescription vmstate_mips_gcr = {
+    .name = "mips-gcr",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(cpc_base, MIPSGCRState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
 static Property mips_gcr_properties[] = {
     DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
     DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
@@ -88,6 +139,8 @@ static void mips_gcr_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     dc->props = mips_gcr_properties;
+    dc->vmsd = &vmstate_mips_gcr;
+    dc->reset = mips_gcr_reset;
 }
 
 static const TypeInfo mips_gcr_info = {
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 1b200d6..88be765 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -22,6 +22,7 @@
 
 #include "hw/sysbus.h"
 #include "hw/misc/mips_cmgcr.h"
+#include "hw/misc/mips_cpc.h"
 
 #define TYPE_MIPS_CPS "mips-cps"
 #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
@@ -35,6 +36,7 @@ typedef struct MIPSCPSState {
 
     MemoryRegion container;
     MIPSGCRState gcr;
+    MIPSCPCState cpc;
 } MIPSCPSState;
 
 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h
index 69403c3..cc60eef 100644
--- a/include/hw/misc/mips_cmgcr.h
+++ b/include/hw/misc/mips_cmgcr.h
@@ -26,6 +26,8 @@
 #define GCR_CONFIG_OFS      0x0000
 #define GCR_BASE_OFS        0x0008
 #define GCR_REV_OFS         0x0030
+#define GCR_CPC_BASE_OFS    0x0088
+#define GCR_CPC_STATUS_OFS  0x00F0
 #define GCR_L2_CONFIG_OFS   0x0130
 
 /* Core Local and Core Other Block Register Map */
@@ -36,6 +38,11 @@
 #define GCR_L2_CONFIG_BYPASS_SHF    20
 #define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
 
+/* GCR_CPC_BASE register fields */
+#define GCR_CPC_BASE_CPCEN_MSK   1
+#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
+#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
+
 typedef struct MIPSGCRState MIPSGCRState;
 struct MIPSGCRState {
     SysBusDevice parent_obj;
@@ -44,6 +51,9 @@ struct MIPSGCRState {
     int32_t num_vps;
     hwaddr gcr_base;
     MemoryRegion iomem;
+    MemoryRegion *cpc_mr;
+
+    uint64_t cpc_base;
 };
 
 #endif /* _MIPS_GCR_H */
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 07/11] hw/mips_malta: remove CPUMIPSState from the write_bootloader()
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (5 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 06/11] hw/mips/cps: create CPC block inside CPS Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 08/11] hw/mips_malta: remove redundant irq and clock init Leon Alrae
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Remove CPUMIPSState from the write_bootloader() argument list as it
is not used in the function.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index f5173c4..cbfdb78 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -606,8 +606,8 @@ static void network_init(PCIBus *pci_bus)
      a3 - RAM size in bytes
 */
 
-static void write_bootloader (CPUMIPSState *env, uint8_t *base,
-                              int64_t run_addr, int64_t kernel_entry)
+static void write_bootloader(uint8_t *base, int64_t run_addr,
+                             int64_t kernel_entry)
 {
     uint32_t *p;
 
@@ -1061,11 +1061,11 @@ void mips_malta_init(MachineState *machine)
         loaderparams.initrd_filename = initrd_filename;
         kernel_entry = load_kernel();
 
-        write_bootloader(env, memory_region_get_ram_ptr(bios),
+        write_bootloader(memory_region_get_ram_ptr(bios),
                          bootloader_run_addr, kernel_entry);
         if (kvm_enabled()) {
             /* Write the bootloader code @ the end of RAM, 1MB reserved */
-            write_bootloader(env, memory_region_get_ram_ptr(ram_low_preio) +
+            write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
                                     ram_low_size,
                              bootloader_run_addr, kernel_entry);
         }
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 08/11] hw/mips_malta: remove redundant irq and clock init
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (6 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 07/11] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 09/11] hw/mips_malta: move CPU creation to a separate function Leon Alrae
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.

These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index cbfdb78..b70948d 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1133,10 +1133,6 @@ void mips_malta_init(MachineState *machine)
     /* Board ID = 0x420 (Malta Board with CoreLV) */
     stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
 
-    /* Init internal devices */
-    cpu_mips_irq_init_cpu(env);
-    cpu_mips_clock_init(env);
-
     /*
      * We have a circular dependency problem: pci_bus depends on isa_irq,
      * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 09/11] hw/mips_malta: move CPU creation to a separate function
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (7 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 08/11] hw/mips_malta: remove redundant irq and clock init Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 10/11] hw/mips_malta: add CPS to Malta board Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c | 68 ++++++++++++++++++++++++++++++----------------------
 1 file changed, 39 insertions(+), 29 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index b70948d..9e8b9ce 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -906,12 +906,45 @@ static void main_cpu_reset(void *opaque)
     }
 }
 
+static void create_cpu(const char *cpu_model,
+                       qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+{
+    CPUMIPSState *env;
+    MIPSCPU *cpu;
+    int i;
+    if (cpu_model == NULL) {
+#ifdef TARGET_MIPS64
+        cpu_model = "20Kc";
+#else
+        cpu_model = "24Kf";
+#endif
+    }
+
+    for (i = 0; i < smp_cpus; i++) {
+        cpu = cpu_mips_init(cpu_model);
+        if (cpu == NULL) {
+            fprintf(stderr, "Unable to find CPU definition\n");
+            exit(1);
+        }
+        env = &cpu->env;
+
+        /* Init internal devices */
+        cpu_mips_irq_init_cpu(env);
+        cpu_mips_clock_init(env);
+        qemu_register_reset(main_cpu_reset, cpu);
+    }
+
+    cpu = MIPS_CPU(first_cpu);
+    env = &cpu->env;
+    *i8259_irq = env->irq[2];
+    *cbus_irq = env->irq[4];
+}
+
 static
 void mips_malta_init(MachineState *machine)
 {
     ram_addr_t ram_size = machine->ram_size;
     ram_addr_t ram_low_size;
-    const char *cpu_model = machine->cpu_model;
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
@@ -928,9 +961,8 @@ void mips_malta_init(MachineState *machine)
     int64_t kernel_entry, bootloader_run_addr;
     PCIBus *pci_bus;
     ISABus *isa_bus;
-    MIPSCPU *cpu;
-    CPUMIPSState *env;
     qemu_irq *isa_irq;
+    qemu_irq cbus_irq, i8259_irq;
     int piix4_devfn;
     I2CBus *smbus;
     int i;
@@ -960,30 +992,8 @@ void mips_malta_init(MachineState *machine)
         }
     }
 
-    /* init CPUs */
-    if (cpu_model == NULL) {
-#ifdef TARGET_MIPS64
-        cpu_model = "20Kc";
-#else
-        cpu_model = "24Kf";
-#endif
-    }
-
-    for (i = 0; i < smp_cpus; i++) {
-        cpu = cpu_mips_init(cpu_model);
-        if (cpu == NULL) {
-            fprintf(stderr, "Unable to find CPU definition\n");
-            exit(1);
-        }
-        env = &cpu->env;
-
-        /* Init internal devices */
-        cpu_mips_irq_init_cpu(env);
-        cpu_mips_clock_init(env);
-        qemu_register_reset(main_cpu_reset, cpu);
-    }
-    cpu = MIPS_CPU(first_cpu);
-    env = &cpu->env;
+    /* create CPUs */
+    create_cpu(machine->cpu_model, &cbus_irq, &i8259_irq);
 
     /* allocate RAM */
     if (ram_size > (2048u << 20)) {
@@ -1024,7 +1034,7 @@ void mips_malta_init(MachineState *machine)
 #endif
     /* FPGA */
     /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
-    malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]);
+    malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
 
     /* Load firmware in flash / BIOS. */
     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@@ -1152,7 +1162,7 @@ void mips_malta_init(MachineState *machine)
 
     /* Interrupt controller */
     /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
-    s->i8259 = i8259_init(isa_bus, env->irq[2]);
+    s->i8259 = i8259_init(isa_bus, i8259_irq);
 
     isa_bus_irqs(isa_bus, s->i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 10/11] hw/mips_malta: add CPS to Malta board
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (8 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 09/11] hw/mips_malta: move CPU creation to a separate function Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

If the user specifies smp > 1 and the CPU with CM GCR support, then
create Coherent Processing System (which takes care of instantiating CPUs)
rather than CPUs directly and connect i8259 and cbus to the pins exposed by
CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use
the same pin numbers as before.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c    | 60 ++++++++++++++++++++++++++++++++++++++++---------
 target-mips/cpu.h       |  1 +
 target-mips/translate.c | 10 +++++++++
 3 files changed, 60 insertions(+), 11 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 9e8b9ce..c26e953 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -55,6 +55,7 @@
 #include "hw/empty_slot.h"
 #include "sysemu/kvm.h"
 #include "exec/semihost.h"
+#include "hw/mips/cps.h"
 
 //#define DEBUG_BOARD_INIT
 
@@ -93,6 +94,7 @@ typedef struct {
 typedef struct {
     SysBusDevice parent_obj;
 
+    MIPSCPSState *cps;
     qemu_irq *i8259;
 } MaltaState;
 
@@ -906,19 +908,12 @@ static void main_cpu_reset(void *opaque)
     }
 }
 
-static void create_cpu(const char *cpu_model,
-                       qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+static void create_cpu_without_cps(const char *cpu_model,
+                                   qemu_irq *cbus_irq, qemu_irq *i8259_irq)
 {
     CPUMIPSState *env;
     MIPSCPU *cpu;
     int i;
-    if (cpu_model == NULL) {
-#ifdef TARGET_MIPS64
-        cpu_model = "20Kc";
-#else
-        cpu_model = "24Kf";
-#endif
-    }
 
     for (i = 0; i < smp_cpus; i++) {
         cpu = cpu_mips_init(cpu_model);
@@ -940,6 +935,49 @@ static void create_cpu(const char *cpu_model,
     *cbus_irq = env->irq[4];
 }
 
+static void create_cps(MaltaState *s, const char *cpu_model,
+                       qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+{
+    Error *err = NULL;
+    s->cps = g_new0(MIPSCPSState, 1);
+
+    object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS);
+    qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
+
+    object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
+    object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
+    object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+    if (err != NULL) {
+        error_report("%s", error_get_pretty(err));
+        exit(1);
+    }
+
+    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+
+    /* FIXME: When GIC is present then we should use GIC's IRQ 3.
+       Until then CPS exposes CPU's IRQs thus use the default IRQ 2. */
+    *i8259_irq = get_cps_irq(s->cps, 2);
+    *cbus_irq = NULL;
+}
+
+static void create_cpu(MaltaState *s, const char *cpu_model,
+                       qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+{
+    if (cpu_model == NULL) {
+#ifdef TARGET_MIPS64
+        cpu_model = "20Kc";
+#else
+        cpu_model = "24Kf";
+#endif
+    }
+
+    if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
+        create_cps(s, cpu_model, cbus_irq, i8259_irq);
+    } else {
+        create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
+    }
+}
+
 static
 void mips_malta_init(MachineState *machine)
 {
@@ -992,8 +1030,8 @@ void mips_malta_init(MachineState *machine)
         }
     }
 
-    /* create CPUs */
-    create_cpu(machine->cpu_model, &cbus_irq, &i8259_irq);
+    /* create CPU */
+    create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
 
     /* allocate RAM */
     if (ram_size > (2048u << 20)) {
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 55d3224..63fea67 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -760,6 +760,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model);
 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 
 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
+bool cpu_supports_cps_smp(const char *cpu_model);
 
 /* TODO QOM'ify CPU reset and remove */
 void cpu_state_reset(CPUMIPSState *s);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8191b92..a5b8805 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19977,6 +19977,16 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
     return cpu;
 }
 
+bool cpu_supports_cps_smp(const char *cpu_model)
+{
+    const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
+    if (!def) {
+        return false;
+    }
+
+    return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
+}
+
 void cpu_state_reset(CPUMIPSState *env)
 {
     MIPSCPU *cpu = mips_env_get_cpu(env);
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU
  2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
                   ` (9 preceding siblings ...)
  2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 10/11] hw/mips_malta: add CPS to Malta board Leon Alrae
@ 2016-03-15  9:59 ` Leon Alrae
  10 siblings, 0 replies; 12+ messages in thread
From: Leon Alrae @ 2016-03-15  9:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: yongbok.kim, peter.maydell, james.hogan, aurelien

Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate_init.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 3192db0..b44df9e 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -663,7 +663,8 @@ static const mips_def_t mips_defs[] =
                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
                        (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+                       (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
                        (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-03-15 10:00 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-15  9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 02/11] target-mips: add CMGCRBase register Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 03/11] hw/mips: add initial Global Config Register support Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 05/11] hw/mips: add initial Cluster Power Controller support Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 06/11] hw/mips/cps: create CPC block inside CPS Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 07/11] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 08/11] hw/mips_malta: remove redundant irq and clock init Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 09/11] hw/mips_malta: move CPU creation to a separate function Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 10/11] hw/mips_malta: add CPS to Malta board Leon Alrae
2016-03-15  9:59 ` [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae

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