* [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support
@ 2016-04-12 12:58 Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
` (8 more replies)
0 siblings, 9 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
v4 - Added code cleanup items:
a. Capitalization of hex constants in softfloat-specialize.h;
b. White spaces in softfloat-specialize.h;
c. Order of Mips helpers for CVT.<L|W>.<S|D>.
v3 - Patch series reorganized into 6 patches instead of 2.
- Commit messages improved.
- Except commit messages, net result of applying v3 and v2 is the same.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01870.html)
v2 - Relevant CPU initialization code changes revisited for all platforms.
- In connection with <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> and
<ABS|NEG>.<S|D> Mips instructions handling, decision on whether
pre-nan2008/pre-abs2008 or nan2008/abs2008 handling will apply
moved from run-time to translate-time.
- For Mips only, in nan2008 cases only, default NaN values fixed.
- For Mips only, in nan2008 cases only, order in pickNaNMulAdd() fixed.
- Code cleanup issues:
a. Constants <floatx80|float128>_default_nan_<low|high> removed;
b. Suffix <l|w>_<s|d> replaced with _<l|w>_<s|d> for some Mips helpers;
c. In vicinity of changes, fixed not-beautiful code formatting.
- Commit messages improved.
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-04/msg01232.html)
V1 - Initial version
(link: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06082.html)
Mips platform represents the most complex case among QEMU-supported
platforms in reference to certain aspects of floating-point arithmetics.
This is mostly a consequence of the fact that Mips platform, for many
reasons, evolved considerably over time related to floating-point
arithmetics standards (significantly more than other platforms).
It has been difficult for emulators like QEMU to support such variety
of configurations.
This patch series provides number of IEEE 754-2008-related features to
Mips platform. It addresses the most sensitive changes that require
modification of SoftFloat library, that is used by most other platforms.
In order to make develpoment, testing, and integration easier, the patch
is split into two distinct parts:
1. Part 1 (patches 1/6, 2/6, 3/6) that does not change any calculation
or behavior on any platform (and, for that matter, even on Mips
platform). Its sole purpose is to address platform independant
issues in a non-invasive manner, and to make Part 2 possible.
2. Part 2 (patches 4/6, 5/6, 6/6) that sets some Mips architecures to
use provisions from Part 1, and additionally implements some of
IEEE 754-2008-relates features for Mips, but, at the same time,
dealing with files located in directory target-mips only.
A limitation of this patch series is that it does not cover all IEEE 754-2008
Mips issues (for example, handling FCR31's FS bit, handling R3 architectures,
some gdb issues, ELF header nan2008-related changes). However, hopefully all
remaining such issues will touch only Mips-specific source code files, and
thus will be much easier to integrate in QEMU, and, of course, will not be
disruptive to orher platforms.
This patch series is based on the original set of patches proposed by Maciej W.
Rozycki: http://lists.nongnu.org/archive/html/qemu-devel/2014-12/msg00968.html
Aleksandar Markovic (9):
softfloat: Implement run-time-configurable meaning of signaling NaN bit
softfloat: For Mips only, correct default NaN values
softfloat: For Mips only, correct order in pickNaNMulAdd()
softfloat: Clean up hex constants capitalization in softfloat-specialize.h
softfloat: Clean up white spaces in softfloat-specialize.h
target-mips: Activate IEEE 274-2008 support
target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
target-mips: Clean up order of helpers for CVT.<L|W>.<S|D>
fpu/softfloat-specialize.h | 648 +++++++++++++++++++++--------------------
fpu/softfloat.c | 172 +++++------
include/fpu/softfloat.h | 45 +--
target-alpha/cpu.c | 2 +
target-arm/helper-a64.c | 14 +-
target-arm/helper.c | 40 +--
target-m68k/helper.c | 6 +-
target-microblaze/cpu.c | 2 +
target-microblaze/op_helper.c | 6 +-
target-mips/helper.h | 22 +-
target-mips/msa_helper.c | 96 +++---
target-mips/op_helper.c | 402 +++++++++++++++++++++----
target-mips/translate.c | 157 ++++++++--
target-mips/translate_init.c | 18 +-
target-ppc/fpu_helper.c | 120 ++++----
target-ppc/translate_init.c | 2 +
target-s390x/cpu.c | 1 +
target-s390x/fpu_helper.c | 28 +-
target-s390x/helper.h | 6 +-
target-s390x/translate.c | 6 +-
target-sh4/cpu.c | 1 +
target-sparc/cpu.c | 1 +
target-tricore/helper.c | 1 +
target-unicore32/cpu.c | 2 +
target-xtensa/cpu.c | 3 +
25 files changed, 1125 insertions(+), 676 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-12 18:45 ` Eduardo Habkost
` (2 more replies)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values Aleksandar Markovic
` (7 subsequent siblings)
8 siblings, 3 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in the next patch.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform.
In order to be at the same time accurate in relation to floating point
arithmetics and consistent with a particular platform code, following
principle is adopted related to invocations of new function
set_snan_bit_is_one():
1. If a target platform doesn't use SoftFloat library, nothing is added.
(cris, lm32, moxie)
2. Else, if a target platform's signaling bit meaning is "1 is
signaling", explicit invocation of set_snan_bit_is_one(1) is added.
(mips, sh4, unicore32)
(for mips this will change in the second patch of this
series, but this very patch leaves mips features as
they currently are.)
3. Else, if a target platform explicitly sets other fields of its
float_status structure(s), explicit invocation of
set_snan_bit_is_one(0) is added.
(ppc, s390x, tricore)
4. Else, if a target platform doesn't explicitly set its structure
CPUXXXState, explicit invocation of set_snan_bit_is_one(0) is added.
(alpha, xtensa)
5. For remaining cases, nothing is added. (Those cases explicitly set
their CPUXXXState/float_status structures to 0, and thus implicitly
perform set_snan_bit_is_one(0).)
(arm, i386, m68k, microblaze, openrisc, sparc)
Or, by platform:
A. alpha - structure CPUAlphaState not explicitly set to 0s, explicit
invocation of set_snan_bit_is_one(0) added
B. arm - relevant parts of CPUARMState structure explicitly set to 0,
nothing added (implicit set_snan_bit_is_one(0))
C. cris - does not use SoftFloat library, nothing added
D. i386 - structure CPUX86State explicitly set to 0s, nothing added
(implicit set_snan_bit_is_one(0))
E. lm32 - does not use SoftFloat library, nothing added
F. m68k - structure CPUM68KState explicitly set to 0s,
nothing added (implicit set_snan_bit_is_one(0))
G. microblaze - structure CPUMBState explicitly set to 0s, nothing added
(implicit set_snan_bit_is_one(0))
H. mips - must explicitly invoke set_snan_bit_is_one(1)
I. moxie - does not use SoftFloat library, nothing added
J. openrisc - structure CPUOpenRISCState explicitly set to 0s, nothing
added (implicit set_snan_bit_is_one(0))
K. ppc - explicitly sets other fields of float_status, explicit
invocation of set_snan_bit_is_one(0) added
L. s390x - explicitely sets other fields of float_status, explicit
invocation of set_snan_bit_is_one(0) added
M. sh4 - must explicitly invoke set_snan_bit_is_one(1)
N. sparc - structure CPUSPARCState explicitly set to 0s, nothing added
(implicit set_snan_bit_is_one(0))
O. tricore - explicitly sets other fields of float_status, explicit
invocation of set_snan_bit_is_one(0) added
P. unicore32 - must explicitely invoke set_snan_bit_is_one(1)
Q. xtensa - structure CPUXtensaState not explicitly set to 0s, explicit
invocation of set_snan_bit_is_one(0) added
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Tested-by: Bastian Koppelmann <address@hidden> (TriCore part)
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
fpu/softfloat-specialize.h | 565 ++++++++++++++++++++---------------------
fpu/softfloat.c | 172 ++++++-------
include/fpu/softfloat.h | 45 ++--
target-alpha/cpu.c | 2 +
target-arm/helper-a64.c | 14 +-
target-arm/helper.c | 40 +--
target-m68k/helper.c | 6 +-
target-microblaze/cpu.c | 2 +
target-microblaze/op_helper.c | 6 +-
target-mips/helper.h | 4 +-
target-mips/msa_helper.c | 96 ++++---
target-mips/op_helper.c | 16 +-
target-mips/translate.c | 5 +-
target-mips/translate_init.c | 2 +
target-ppc/fpu_helper.c | 120 ++++-----
target-ppc/translate_init.c | 2 +
target-s390x/cpu.c | 1 +
target-s390x/fpu_helper.c | 28 +-
target-s390x/helper.h | 6 +-
target-s390x/translate.c | 6 +-
target-sh4/cpu.c | 1 +
target-sparc/cpu.c | 1 +
target-tricore/helper.c | 1 +
target-unicore32/cpu.c | 2 +
target-xtensa/cpu.c | 3 +
25 files changed, 577 insertions(+), 569 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index a4cbdad..53dae9b 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -79,16 +79,6 @@ this code that are retained.
* version 2 or later. See the COPYING file in the top-level directory.
*/
-/* Does the target distinguish signaling NaNs from non-signaling NaNs
- * by setting the most significant bit of the mantissa for a signaling NaN?
- * (The more common choice is to have it be zero for SNaN and one for QNaN.)
- */
-#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
-#define SNAN_BIT_IS_ONE 1
-#else
-#define SNAN_BIT_IS_ONE 0
-#endif
-
#if defined(TARGET_XTENSA)
/* Define for architectures which deviate from IEEE in not supporting
* signaling NaNs (so all NaNs are treated as quiet).
@@ -99,73 +89,92 @@ this code that are retained.
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
+float16 float16_default_nan(float_status *status)
+{
#if defined(TARGET_ARM)
-const float16 float16_default_nan = const_float16(0x7E00);
-#elif SNAN_BIT_IS_ONE
-const float16 float16_default_nan = const_float16(0x7DFF);
+ return const_float16(0x7E00);
#else
-const float16 float16_default_nan = const_float16(0xFE00);
+ if (status->snan_bit_is_one) {
+ return const_float16(0x7DFF);
+ } else {
+ return const_float16(0xFE00);
+ }
#endif
+}
/*----------------------------------------------------------------------------
| The pattern for a default generated single-precision NaN.
*----------------------------------------------------------------------------*/
+float32 float32_default_nan(float_status *status)
+{
#if defined(TARGET_SPARC)
-const float32 float32_default_nan = const_float32(0x7FFFFFFF);
+ return const_float32(0x7FFFFFFF);
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE)
-const float32 float32_default_nan = const_float32(0x7FC00000);
-#elif SNAN_BIT_IS_ONE
-const float32 float32_default_nan = const_float32(0x7FBFFFFF);
+ return const_float32(0x7FC00000);
#else
-const float32 float32_default_nan = const_float32(0xFFC00000);
+ if (status->snan_bit_is_one) {
+ return const_float32(0x7FBFFFFF);
+ } else {
+ return const_float32(0xFFC00000);
+ }
#endif
+}
/*----------------------------------------------------------------------------
| The pattern for a default generated double-precision NaN.
*----------------------------------------------------------------------------*/
+float64 float64_default_nan(float_status *status)
+{
#if defined(TARGET_SPARC)
-const float64 float64_default_nan = const_float64(LIT64( 0x7FFFFFFFFFFFFFFF ));
+ return const_float64(LIT64( 0x7FFFFFFFFFFFFFFF ));
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_S390X)
-const float64 float64_default_nan = const_float64(LIT64( 0x7FF8000000000000 ));
-#elif SNAN_BIT_IS_ONE
-const float64 float64_default_nan = const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
+ return const_float64(LIT64( 0x7FF8000000000000 ));
#else
-const float64 float64_default_nan = const_float64(LIT64( 0xFFF8000000000000 ));
+ if (status->snan_bit_is_one) {
+ return const_float64(LIT64( 0x7FF7FFFFFFFFFFFF ));
+ } else {
+ return const_float64(LIT64( 0xFFF8000000000000 ));
+ }
#endif
+}
/*----------------------------------------------------------------------------
| The pattern for a default generated extended double-precision NaN.
*----------------------------------------------------------------------------*/
-#if SNAN_BIT_IS_ONE
-#define floatx80_default_nan_high 0x7FFF
-#define floatx80_default_nan_low LIT64(0xBFFFFFFFFFFFFFFF)
-#else
-#define floatx80_default_nan_high 0xFFFF
-#define floatx80_default_nan_low LIT64( 0xC000000000000000 )
-#endif
+floatx80 floatx80_default_nan(float_status *status) {
+ floatx80 r;
-const floatx80 floatx80_default_nan
- = make_floatx80_init(floatx80_default_nan_high, floatx80_default_nan_low);
+ if (status->snan_bit_is_one) {
+ r.low = LIT64( 0xBFFFFFFFFFFFFFFF );
+ r.high = 0x7FFF;
+ } else {
+ r.low = LIT64( 0xC000000000000000 );
+ r.high = 0xFFFF;
+ }
+ return r;
+}
/*----------------------------------------------------------------------------
-| The pattern for a default generated quadruple-precision NaN. The `high' and
-| `low' values hold the most- and least-significant bits, respectively.
+| The pattern for a default generated quadruple-precision NaN.
*----------------------------------------------------------------------------*/
-#if SNAN_BIT_IS_ONE
-#define float128_default_nan_high LIT64(0x7FFF7FFFFFFFFFFF)
-#define float128_default_nan_low LIT64(0xFFFFFFFFFFFFFFFF)
-#elif defined(TARGET_S390X)
-#define float128_default_nan_high LIT64( 0x7FFF800000000000 )
-#define float128_default_nan_low LIT64( 0x0000000000000000 )
+float128 float128_default_nan(float_status *status) {
+ float128 r;
+
+ if (status->snan_bit_is_one) {
+ r.low = LIT64( 0xFFFFFFFFFFFFFFFF );
+ r.high = LIT64( 0x7FFF7FFFFFFFFFFF );
+ } else {
+ r.low = LIT64( 0x0000000000000000 );
+#if defined(TARGET_S390X)
+ r.high = LIT64( 0x7FFF800000000000 );
#else
-#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
-#define float128_default_nan_low LIT64( 0x0000000000000000 )
+ r.high = LIT64( 0xFFFF800000000000 );
#endif
-
-const float128 float128_default_nan
- = make_float128_init(float128_default_nan_high, float128_default_nan_low);
+ }
+ return r;
+}
/*----------------------------------------------------------------------------
| Raises the exceptions specified by `flags'. Floating-point traps can be
@@ -188,12 +197,12 @@ typedef struct {
} commonNaNT;
#ifdef NO_SIGNALING_NANS
-int float16_is_quiet_nan(float16 a_)
+int float16_is_quiet_nan(float16 a_, float_status *status)
{
return float16_is_any_nan(a_);
}
-int float16_is_signaling_nan(float16 a_)
+int float16_is_signaling_nan(float16 a_, float_status *status)
{
return 0;
}
@@ -203,14 +212,14 @@ int float16_is_signaling_nan(float16 a_)
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float16_is_quiet_nan(float16 a_)
+int float16_is_quiet_nan(float16 a_, float_status *status)
{
uint16_t a = float16_val(a_);
-#if SNAN_BIT_IS_ONE
- return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
-#else
- return ((a & ~0x8000) >= 0x7c80);
-#endif
+ if (status->snan_bit_is_one) {
+ return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ } else {
+ return ((a & ~0x8000) >= 0x7c80);
+ }
}
/*----------------------------------------------------------------------------
@@ -218,14 +227,14 @@ int float16_is_quiet_nan(float16 a_)
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float16_is_signaling_nan(float16 a_)
+int float16_is_signaling_nan(float16 a_, float_status *status)
{
uint16_t a = float16_val(a_);
-#if SNAN_BIT_IS_ONE
- return ((a & ~0x8000) >= 0x7c80);
-#else
- return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
-#endif
+ if (status->snan_bit_is_one) {
+ return ((a & ~0x8000) >= 0x7c80);
+ } else {
+ return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ }
}
#endif
@@ -233,20 +242,16 @@ int float16_is_signaling_nan(float16 a_)
| Returns a quiet NaN if the half-precision floating point value `a' is a
| signaling NaN; otherwise returns `a'.
*----------------------------------------------------------------------------*/
-float16 float16_maybe_silence_nan(float16 a_)
+float16 float16_maybe_silence_nan(float16 a_, float_status *status)
{
- if (float16_is_signaling_nan(a_)) {
-#if SNAN_BIT_IS_ONE
-# if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
- return float16_default_nan;
-# else
-# error Rules for silencing a signaling NaN are target-specific
-# endif
-#else
- uint16_t a = float16_val(a_);
- a |= (1 << 9);
- return make_float16(a);
-#endif
+ if (float16_is_signaling_nan(a_, status)) {
+ if (status->snan_bit_is_one) {
+ return float16_default_nan(status);
+ } else {
+ uint16_t a = float16_val(a_);
+ a |= (1 << 9);
+ return make_float16(a);
+ }
}
return a_;
}
@@ -261,7 +266,7 @@ static commonNaNT float16ToCommonNaN(float16 a, float_status *status)
{
commonNaNT z;
- if (float16_is_signaling_nan(a)) {
+ if (float16_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
z.sign = float16_val(a) >> 15;
@@ -280,24 +285,24 @@ static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
uint16_t mantissa = a.high>>54;
if (status->default_nan_mode) {
- return float16_default_nan;
+ return float16_default_nan(status);
}
if (mantissa) {
return make_float16(((((uint16_t) a.sign) << 15)
| (0x1F << 10) | mantissa));
} else {
- return float16_default_nan;
+ return float16_default_nan(status);
}
}
#ifdef NO_SIGNALING_NANS
-int float32_is_quiet_nan(float32 a_)
+int float32_is_quiet_nan(float32 a_, float_status *status)
{
return float32_is_any_nan(a_);
}
-int float32_is_signaling_nan(float32 a_)
+int float32_is_signaling_nan(float32 a_, float_status *status)
{
return 0;
}
@@ -307,14 +312,14 @@ int float32_is_signaling_nan(float32 a_)
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float32_is_quiet_nan( float32 a_ )
+int float32_is_quiet_nan( float32 a_, float_status *status )
{
uint32_t a = float32_val(a_);
-#if SNAN_BIT_IS_ONE
- return (((a >> 22) & 0x1ff) == 0x1fe) && (a & 0x003fffff);
-#else
- return ((uint32_t)(a << 1) >= 0xff800000);
-#endif
+ if (status->snan_bit_is_one) {
+ return (((a >> 22) & 0x1ff) == 0x1fe) && (a & 0x003fffff);
+ } else {
+ return ((uint32_t)(a << 1) >= 0xff800000);
+ }
}
/*----------------------------------------------------------------------------
@@ -322,14 +327,14 @@ int float32_is_quiet_nan( float32 a_ )
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float32_is_signaling_nan( float32 a_ )
+int float32_is_signaling_nan( float32 a_, float_status *status )
{
uint32_t a = float32_val(a_);
-#if SNAN_BIT_IS_ONE
- return ((uint32_t)(a << 1) >= 0xff800000);
-#else
- return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
-#endif
+ if (status->snan_bit_is_one) {
+ return ((uint32_t)(a << 1) >= 0xff800000);
+ } else {
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
+ }
}
#endif
@@ -338,20 +343,16 @@ int float32_is_signaling_nan( float32 a_ )
| signaling NaN; otherwise returns `a'.
*----------------------------------------------------------------------------*/
-float32 float32_maybe_silence_nan( float32 a_ )
+float32 float32_maybe_silence_nan( float32 a_, float_status *status )
{
- if (float32_is_signaling_nan(a_)) {
-#if SNAN_BIT_IS_ONE
-# if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
- return float32_default_nan;
-# else
-# error Rules for silencing a signaling NaN are target-specific
-# endif
-#else
- uint32_t a = float32_val(a_);
- a |= (1 << 22);
- return make_float32(a);
-#endif
+ if (float32_is_signaling_nan(a_, status)) {
+ if (status->snan_bit_is_one) {
+ return float32_default_nan(status);
+ } else {
+ uint32_t a = float32_val(a_);
+ a |= (1 << 22);
+ return make_float32(a);
+ }
}
return a_;
}
@@ -366,7 +367,7 @@ static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
{
commonNaNT z;
- if (float32_is_signaling_nan(a)) {
+ if (float32_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
z.sign = float32_val(a)>>31;
@@ -385,14 +386,15 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
uint32_t mantissa = a.high>>41;
if (status->default_nan_mode) {
- return float32_default_nan;
+ return float32_default_nan(status);
}
- if ( mantissa )
+ if ( mantissa ) {
return make_float32(
( ( (uint32_t) a.sign )<<31 ) | 0x7F800000 | ( a.high>>41 ) );
- else
- return float32_default_nan;
+ } else {
+ return float32_default_nan(status);
+ }
}
/*----------------------------------------------------------------------------
@@ -494,11 +496,10 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
return aIsLargerSignificand ? 0 : 1;
}
return bIsQNaN ? 1 : 0;
- }
- else if (aIsQNaN) {
- if (bIsSNaN || !bIsQNaN)
+ } else if (aIsQNaN) {
+ if (bIsSNaN || !bIsQNaN) {
return 0;
- else {
+ } else {
return aIsLargerSignificand ? 0 : 1;
}
} else {
@@ -556,19 +557,19 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
return 3;
}
- /* Prefer sNaN over qNaN, in the a, b, c order. */
- if (aIsSNaN) {
+ /* Prefer sNaN over qNaN, in the c, a, b order. */
+ if (cIsSNaN) {
+ return 2;
+ } else if (aIsSNaN) {
return 0;
} else if (bIsSNaN) {
return 1;
- } else if (cIsSNaN) {
+ } else if (cIsQNaN) {
return 2;
} else if (aIsQNaN) {
return 0;
- } else if (bIsQNaN) {
- return 1;
} else {
- return 2;
+ return 1;
}
}
#elif defined(TARGET_PPC)
@@ -626,10 +627,10 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
flag aIsLargerSignificand;
uint32_t av, bv;
- aIsQuietNaN = float32_is_quiet_nan( a );
- aIsSignalingNaN = float32_is_signaling_nan( a );
- bIsQuietNaN = float32_is_quiet_nan( b );
- bIsSignalingNaN = float32_is_signaling_nan( b );
+ aIsQuietNaN = float32_is_quiet_nan( a, status );
+ aIsSignalingNaN = float32_is_signaling_nan( a, status );
+ bIsQuietNaN = float32_is_quiet_nan( b, status );
+ bIsSignalingNaN = float32_is_signaling_nan( b, status );
av = float32_val(a);
bv = float32_val(b);
@@ -638,7 +639,7 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
}
if (status->default_nan_mode)
- return float32_default_nan;
+ return float32_default_nan(status);
if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
aIsLargerSignificand = 0;
@@ -650,9 +651,9 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
aIsLargerSignificand)) {
- return float32_maybe_silence_nan(b);
+ return float32_maybe_silence_nan(b, status);
} else {
- return float32_maybe_silence_nan(a);
+ return float32_maybe_silence_nan(a, status);
}
}
@@ -673,12 +674,12 @@ static float32 propagateFloat32MulAddNaN(float32 a, float32 b,
cIsQuietNaN, cIsSignalingNaN;
int which;
- aIsQuietNaN = float32_is_quiet_nan(a);
- aIsSignalingNaN = float32_is_signaling_nan(a);
- bIsQuietNaN = float32_is_quiet_nan(b);
- bIsSignalingNaN = float32_is_signaling_nan(b);
- cIsQuietNaN = float32_is_quiet_nan(c);
- cIsSignalingNaN = float32_is_signaling_nan(c);
+ aIsQuietNaN = float32_is_quiet_nan(a, status);
+ aIsSignalingNaN = float32_is_signaling_nan(a, status);
+ bIsQuietNaN = float32_is_quiet_nan(b, status);
+ bIsSignalingNaN = float32_is_signaling_nan(b, status);
+ cIsQuietNaN = float32_is_quiet_nan(c, status);
+ cIsSignalingNaN = float32_is_signaling_nan(c, status);
if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
float_raise(float_flag_invalid, status);
@@ -692,29 +693,29 @@ static float32 propagateFloat32MulAddNaN(float32 a, float32 b,
/* Note that this check is after pickNaNMulAdd so that function
* has an opportunity to set the Invalid flag.
*/
- return float32_default_nan;
+ return float32_default_nan(status);
}
switch (which) {
case 0:
- return float32_maybe_silence_nan(a);
+ return float32_maybe_silence_nan(a, status);
case 1:
- return float32_maybe_silence_nan(b);
+ return float32_maybe_silence_nan(b, status);
case 2:
- return float32_maybe_silence_nan(c);
+ return float32_maybe_silence_nan(c, status);
case 3:
default:
- return float32_default_nan;
+ return float32_default_nan(status);
}
}
#ifdef NO_SIGNALING_NANS
-int float64_is_quiet_nan(float64 a_)
+int float64_is_quiet_nan(float64 a_, float_status *status)
{
return float64_is_any_nan(a_);
}
-int float64_is_signaling_nan(float64 a_)
+int float64_is_signaling_nan(float64 a_, float_status *status)
{
return 0;
}
@@ -724,15 +725,15 @@ int float64_is_signaling_nan(float64 a_)
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float64_is_quiet_nan( float64 a_ )
+int float64_is_quiet_nan( float64 a_, float_status *status)
{
uint64_t a = float64_val(a_);
-#if SNAN_BIT_IS_ONE
- return (((a >> 51) & 0xfff) == 0xffe)
- && (a & 0x0007ffffffffffffULL);
-#else
- return ((a << 1) >= 0xfff0000000000000ULL);
-#endif
+ if (status->snan_bit_is_one) {
+ return (((a >> 51) & 0xfff) == 0xffe)
+ && (a & 0x0007ffffffffffffULL);
+ } else {
+ return ((a << 1) >= 0xfff0000000000000ULL);
+ }
}
/*----------------------------------------------------------------------------
@@ -740,16 +741,16 @@ int float64_is_quiet_nan( float64 a_ )
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float64_is_signaling_nan( float64 a_ )
+int float64_is_signaling_nan( float64 a_, float_status *status )
{
uint64_t a = float64_val(a_);
-#if SNAN_BIT_IS_ONE
- return ((a << 1) >= 0xfff0000000000000ULL);
-#else
- return
- ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
- && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
-#endif
+ if (status->snan_bit_is_one) {
+ return ((a << 1) >= 0xfff0000000000000ULL);
+ } else {
+ return
+ ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
+ && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
+ }
}
#endif
@@ -758,20 +759,16 @@ int float64_is_signaling_nan( float64 a_ )
| signaling NaN; otherwise returns `a'.
*----------------------------------------------------------------------------*/
-float64 float64_maybe_silence_nan( float64 a_ )
+float64 float64_maybe_silence_nan( float64 a_, float_status *status )
{
- if (float64_is_signaling_nan(a_)) {
-#if SNAN_BIT_IS_ONE
-# if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
- return float64_default_nan;
-# else
-# error Rules for silencing a signaling NaN are target-specific
-# endif
-#else
- uint64_t a = float64_val(a_);
- a |= LIT64( 0x0008000000000000 );
- return make_float64(a);
-#endif
+ if (float64_is_signaling_nan(a_, status)) {
+ if (status->snan_bit_is_one) {
+ return float64_default_nan(status);
+ } else {
+ uint64_t a = float64_val(a_);
+ a |= LIT64( 0x0008000000000000 );
+ return make_float64(a);
+ }
}
return a_;
}
@@ -786,7 +783,7 @@ static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
{
commonNaNT z;
- if (float64_is_signaling_nan(a)) {
+ if (float64_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
z.sign = float64_val(a)>>63;
@@ -805,16 +802,17 @@ static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
uint64_t mantissa = a.high>>12;
if (status->default_nan_mode) {
- return float64_default_nan;
+ return float64_default_nan(status);
}
- if ( mantissa )
+ if ( mantissa ) {
return make_float64(
( ( (uint64_t) a.sign )<<63 )
| LIT64( 0x7FF0000000000000 )
| ( a.high>>12 ));
- else
- return float64_default_nan;
+ } else {
+ return float64_default_nan(status);
+ }
}
/*----------------------------------------------------------------------------
@@ -829,10 +827,10 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
flag aIsLargerSignificand;
uint64_t av, bv;
- aIsQuietNaN = float64_is_quiet_nan( a );
- aIsSignalingNaN = float64_is_signaling_nan( a );
- bIsQuietNaN = float64_is_quiet_nan( b );
- bIsSignalingNaN = float64_is_signaling_nan( b );
+ aIsQuietNaN = float64_is_quiet_nan( a, status );
+ aIsSignalingNaN = float64_is_signaling_nan( a, status );
+ bIsQuietNaN = float64_is_quiet_nan( b, status );
+ bIsSignalingNaN = float64_is_signaling_nan( b, status );
av = float64_val(a);
bv = float64_val(b);
@@ -841,7 +839,7 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
}
if (status->default_nan_mode)
- return float64_default_nan;
+ return float64_default_nan(status);
if ((uint64_t)(av<<1) < (uint64_t)(bv<<1)) {
aIsLargerSignificand = 0;
@@ -853,9 +851,9 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
aIsLargerSignificand)) {
- return float64_maybe_silence_nan(b);
+ return float64_maybe_silence_nan(b, status);
} else {
- return float64_maybe_silence_nan(a);
+ return float64_maybe_silence_nan(a, status);
}
}
@@ -876,12 +874,12 @@ static float64 propagateFloat64MulAddNaN(float64 a, float64 b,
cIsQuietNaN, cIsSignalingNaN;
int which;
- aIsQuietNaN = float64_is_quiet_nan(a);
- aIsSignalingNaN = float64_is_signaling_nan(a);
- bIsQuietNaN = float64_is_quiet_nan(b);
- bIsSignalingNaN = float64_is_signaling_nan(b);
- cIsQuietNaN = float64_is_quiet_nan(c);
- cIsSignalingNaN = float64_is_signaling_nan(c);
+ aIsQuietNaN = float64_is_quiet_nan(a, status);
+ aIsSignalingNaN = float64_is_signaling_nan(a, status);
+ bIsQuietNaN = float64_is_quiet_nan(b, status);
+ bIsSignalingNaN = float64_is_signaling_nan(b, status);
+ cIsQuietNaN = float64_is_quiet_nan(c, status);
+ cIsSignalingNaN = float64_is_signaling_nan(c, status);
if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
float_raise(float_flag_invalid, status);
@@ -895,29 +893,29 @@ static float64 propagateFloat64MulAddNaN(float64 a, float64 b,
/* Note that this check is after pickNaNMulAdd so that function
* has an opportunity to set the Invalid flag.
*/
- return float64_default_nan;
+ return float64_default_nan(status);
}
switch (which) {
case 0:
- return float64_maybe_silence_nan(a);
+ return float64_maybe_silence_nan(a, status);
case 1:
- return float64_maybe_silence_nan(b);
+ return float64_maybe_silence_nan(b, status);
case 2:
- return float64_maybe_silence_nan(c);
+ return float64_maybe_silence_nan(c, status);
case 3:
default:
- return float64_default_nan;
+ return float64_default_nan(status);
}
}
#ifdef NO_SIGNALING_NANS
-int floatx80_is_quiet_nan(floatx80 a_)
+int floatx80_is_quiet_nan(floatx80 a_, float_status *status)
{
return floatx80_is_any_nan(a_);
}
-int floatx80_is_signaling_nan(floatx80 a_)
+int floatx80_is_signaling_nan(floatx80 a_, float_status *status)
{
return 0;
}
@@ -928,19 +926,19 @@ int floatx80_is_signaling_nan(floatx80 a_)
| function for other types as floatx80 has an explicit bit.
*----------------------------------------------------------------------------*/
-int floatx80_is_quiet_nan( floatx80 a )
+int floatx80_is_quiet_nan( floatx80 a, float_status *status )
{
-#if SNAN_BIT_IS_ONE
- uint64_t aLow;
+ if (status->snan_bit_is_one) {
+ uint64_t aLow;
- aLow = a.low & ~0x4000000000000000ULL;
- return ((a.high & 0x7fff) == 0x7fff)
- && (aLow << 1)
- && (a.low == aLow);
-#else
- return ( ( a.high & 0x7FFF ) == 0x7FFF )
- && (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
-#endif
+ aLow = a.low & ~0x4000000000000000ULL;
+ return ((a.high & 0x7fff) == 0x7fff)
+ && (aLow << 1)
+ && (a.low == aLow);
+ } else {
+ return ( ( a.high & 0x7FFF ) == 0x7FFF )
+ && (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
+ }
}
/*----------------------------------------------------------------------------
@@ -949,20 +947,20 @@ int floatx80_is_quiet_nan( floatx80 a )
| function for other types as floatx80 has an explicit bit.
*----------------------------------------------------------------------------*/
-int floatx80_is_signaling_nan( floatx80 a )
+int floatx80_is_signaling_nan( floatx80 a, float_status *status )
{
-#if SNAN_BIT_IS_ONE
- return ((a.high & 0x7fff) == 0x7fff)
- && ((a.low << 1) >= 0x8000000000000000ULL);
-#else
- uint64_t aLow;
+ if (status->snan_bit_is_one) {
+ return ((a.high & 0x7fff) == 0x7fff)
+ && ((a.low << 1) >= 0x8000000000000000ULL);
+ } else {
+ uint64_t aLow;
- aLow = a.low & ~ LIT64( 0x4000000000000000 );
- return
- ( ( a.high & 0x7FFF ) == 0x7FFF )
- && (uint64_t) ( aLow<<1 )
- && ( a.low == aLow );
-#endif
+ aLow = a.low & ~ LIT64( 0x4000000000000000 );
+ return
+ ( ( a.high & 0x7FFF ) == 0x7FFF )
+ && (uint64_t) ( aLow<<1 )
+ && ( a.low == aLow );
+ }
}
#endif
@@ -971,20 +969,15 @@ int floatx80_is_signaling_nan( floatx80 a )
| `a' is a signaling NaN; otherwise returns `a'.
*----------------------------------------------------------------------------*/
-floatx80 floatx80_maybe_silence_nan( floatx80 a )
+floatx80 floatx80_maybe_silence_nan( floatx80 a, float_status *status )
{
- if (floatx80_is_signaling_nan(a)) {
-#if SNAN_BIT_IS_ONE
-# if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
- a.low = floatx80_default_nan_low;
- a.high = floatx80_default_nan_high;
-# else
-# error Rules for silencing a signaling NaN are target-specific
-# endif
-#else
- a.low |= LIT64( 0xC000000000000000 );
- return a;
-#endif
+ if (floatx80_is_signaling_nan(a, status)) {
+ if (status->snan_bit_is_one) {
+ a = floatx80_default_nan(status);
+ } else {
+ a.low |= LIT64( 0xC000000000000000 );
+ return a;
+ }
}
return a;
}
@@ -997,9 +990,10 @@ floatx80 floatx80_maybe_silence_nan( floatx80 a )
static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
{
+ floatx80 dflt;
commonNaNT z;
- if (floatx80_is_signaling_nan(a)) {
+ if (floatx80_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
if ( a.low >> 63 ) {
@@ -1007,9 +1001,10 @@ static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
z.low = 0;
z.high = a.low << 1;
} else {
- z.sign = floatx80_default_nan_high >> 15;
+ dflt = floatx80_default_nan(status);
+ z.sign = dflt.high >> 15;
z.low = 0;
- z.high = floatx80_default_nan_low << 1;
+ z.high = dflt.low << 1;
}
return z;
}
@@ -1024,19 +1019,15 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
floatx80 z;
if (status->default_nan_mode) {
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
- return z;
+ return floatx80_default_nan(status);
}
if (a.high >> 1) {
z.low = LIT64( 0x8000000000000000 ) | a.high >> 1;
z.high = ( ( (uint16_t) a.sign )<<15 ) | 0x7FFF;
} else {
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
+ z = floatx80_default_nan(status);
}
-
return z;
}
@@ -1052,19 +1043,17 @@ static floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b,
flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
flag aIsLargerSignificand;
- aIsQuietNaN = floatx80_is_quiet_nan( a );
- aIsSignalingNaN = floatx80_is_signaling_nan( a );
- bIsQuietNaN = floatx80_is_quiet_nan( b );
- bIsSignalingNaN = floatx80_is_signaling_nan( b );
+ aIsQuietNaN = floatx80_is_quiet_nan( a, status );
+ aIsSignalingNaN = floatx80_is_signaling_nan( a, status );
+ bIsQuietNaN = floatx80_is_quiet_nan( b, status );
+ bIsSignalingNaN = floatx80_is_signaling_nan( b, status );
if (aIsSignalingNaN | bIsSignalingNaN) {
float_raise(float_flag_invalid, status);
}
if (status->default_nan_mode) {
- a.low = floatx80_default_nan_low;
- a.high = floatx80_default_nan_high;
- return a;
+ return floatx80_default_nan(status);
}
if (a.low < b.low) {
@@ -1077,19 +1066,19 @@ static floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b,
if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
aIsLargerSignificand)) {
- return floatx80_maybe_silence_nan(b);
+ return floatx80_maybe_silence_nan(b, status);
} else {
- return floatx80_maybe_silence_nan(a);
+ return floatx80_maybe_silence_nan(a, status);
}
}
#ifdef NO_SIGNALING_NANS
-int float128_is_quiet_nan(float128 a_)
+int float128_is_quiet_nan(float128 a_, float_status *status)
{
return float128_is_any_nan(a_);
}
-int float128_is_signaling_nan(float128 a_)
+int float128_is_signaling_nan(float128 a_, float_status *status)
{
return 0;
}
@@ -1099,16 +1088,16 @@ int float128_is_signaling_nan(float128 a_)
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float128_is_quiet_nan( float128 a )
+int float128_is_quiet_nan( float128 a, float_status *status )
{
-#if SNAN_BIT_IS_ONE
- return (((a.high >> 47) & 0xffff) == 0xfffe)
- && (a.low || (a.high & 0x00007fffffffffffULL));
-#else
- return
- ((a.high << 1) >= 0xffff000000000000ULL)
- && (a.low || (a.high & 0x0000ffffffffffffULL));
-#endif
+ if (status->snan_bit_is_one) {
+ return (((a.high >> 47) & 0xffff) == 0xfffe)
+ && (a.low || (a.high & 0x00007fffffffffffULL));
+ } else {
+ return
+ ((a.high << 1) >= 0xffff000000000000ULL)
+ && (a.low || (a.high & 0x0000ffffffffffffULL));
+ }
}
/*----------------------------------------------------------------------------
@@ -1116,17 +1105,17 @@ int float128_is_quiet_nan( float128 a )
| signaling NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
-int float128_is_signaling_nan( float128 a )
+int float128_is_signaling_nan( float128 a, float_status *status )
{
-#if SNAN_BIT_IS_ONE
- return
- ((a.high << 1) >= 0xffff000000000000ULL)
- && (a.low || (a.high & 0x0000ffffffffffffULL));
-#else
- return
- ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
- && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
-#endif
+ if (status->snan_bit_is_one) {
+ return
+ ((a.high << 1) >= 0xffff000000000000ULL)
+ && (a.low || (a.high & 0x0000ffffffffffffULL));
+ } else {
+ return
+ ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
+ && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
+ }
}
#endif
@@ -1135,20 +1124,15 @@ int float128_is_signaling_nan( float128 a )
| a signaling NaN; otherwise returns `a'.
*----------------------------------------------------------------------------*/
-float128 float128_maybe_silence_nan( float128 a )
+float128 float128_maybe_silence_nan( float128 a, float_status *status )
{
- if (float128_is_signaling_nan(a)) {
-#if SNAN_BIT_IS_ONE
-# if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
- a.low = float128_default_nan_low;
- a.high = float128_default_nan_high;
-# else
-# error Rules for silencing a signaling NaN are target-specific
-# endif
-#else
- a.high |= LIT64( 0x0000800000000000 );
- return a;
-#endif
+ if (float128_is_signaling_nan(a, status)) {
+ if (status->snan_bit_is_one) {
+ a = float128_default_nan(status);
+ } else {
+ a.high |= LIT64( 0x0000800000000000 );
+ return a;
+ }
}
return a;
}
@@ -1163,7 +1147,7 @@ static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
{
commonNaNT z;
- if (float128_is_signaling_nan(a)) {
+ if (float128_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
z.sign = a.high>>63;
@@ -1181,9 +1165,7 @@ static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
float128 z;
if (status->default_nan_mode) {
- z.low = float128_default_nan_low;
- z.high = float128_default_nan_high;
- return z;
+ return float128_default_nan(status);
}
shift128Right( a.high, a.low, 16, &z.high, &z.low );
@@ -1203,19 +1185,17 @@ static float128 propagateFloat128NaN(float128 a, float128 b,
flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
flag aIsLargerSignificand;
- aIsQuietNaN = float128_is_quiet_nan( a );
- aIsSignalingNaN = float128_is_signaling_nan( a );
- bIsQuietNaN = float128_is_quiet_nan( b );
- bIsSignalingNaN = float128_is_signaling_nan( b );
+ aIsQuietNaN = float128_is_quiet_nan( a, status );
+ aIsSignalingNaN = float128_is_signaling_nan( a, status );
+ bIsQuietNaN = float128_is_quiet_nan( b, status );
+ bIsSignalingNaN = float128_is_signaling_nan( b, status );
if (aIsSignalingNaN | bIsSignalingNaN) {
float_raise(float_flag_invalid, status);
}
if (status->default_nan_mode) {
- a.low = float128_default_nan_low;
- a.high = float128_default_nan_high;
- return a;
+ return float128_default_nan(status);
}
if (lt128(a.high<<1, a.low, b.high<<1, b.low)) {
@@ -1228,9 +1208,8 @@ static float128 propagateFloat128NaN(float128 a, float128 b,
if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
aIsLargerSignificand)) {
- return float128_maybe_silence_nan(b);
+ return float128_maybe_silence_nan(b, status);
} else {
- return float128_maybe_silence_nan(a);
+ return float128_maybe_silence_nan(a, status);
}
}
-
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 166c48e..414788b 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2105,7 +2105,7 @@ static float32 subFloat32Sigs(float32 a, float32 b, flag zSign,
return propagateFloat32NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
if ( aExp == 0 ) {
aExp = 1;
@@ -2234,7 +2234,7 @@ float32 float32_mul(float32 a, float32 b, float_status *status)
}
if ( ( bExp | bSig ) == 0 ) {
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
return packFloat32( zSign, 0xFF, 0 );
}
@@ -2244,7 +2244,7 @@ float32 float32_mul(float32 a, float32 b, float_status *status)
}
if ( ( aExp | aSig ) == 0 ) {
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
return packFloat32( zSign, 0xFF, 0 );
}
@@ -2299,7 +2299,7 @@ float32 float32_div(float32 a, float32 b, float_status *status)
return propagateFloat32NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
return packFloat32( zSign, 0xFF, 0 );
}
@@ -2313,7 +2313,7 @@ float32 float32_div(float32 a, float32 b, float_status *status)
if ( bSig == 0 ) {
if ( ( aExp | aSig ) == 0 ) {
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
float_raise(float_flag_divbyzero, status);
return packFloat32( zSign, 0xFF, 0 );
@@ -2367,7 +2367,7 @@ float32 float32_rem(float32 a, float32 b, float_status *status)
return propagateFloat32NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
if ( bExp == 0xFF ) {
if (bSig) {
@@ -2378,7 +2378,7 @@ float32 float32_rem(float32 a, float32 b, float_status *status)
if ( bExp == 0 ) {
if ( bSig == 0 ) {
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
normalizeFloat32Subnormal( bSig, &bExp, &bSig );
}
@@ -2493,7 +2493,7 @@ float32 float32_muladd(float32 a, float32 b, float32 c, int flags,
if (infzero) {
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
if (flags & float_muladd_negate_c) {
@@ -2514,7 +2514,7 @@ float32 float32_muladd(float32 a, float32 b, float32 c, int flags,
if (pInf && (pSign ^ cSign)) {
/* addition of opposite-signed infinities => InvalidOperation */
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
/* Otherwise generate an infinity of the same sign */
return packFloat32(cSign ^ signflip, 0xff, 0);
@@ -2690,12 +2690,12 @@ float32 float32_sqrt(float32 a, float_status *status)
}
if ( ! aSign ) return a;
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
if ( aSign ) {
if ( ( aExp | aSig ) == 0 ) return a;
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return float32_zero;
@@ -2828,7 +2828,7 @@ float32 float32_log2(float32 a, float_status *status)
}
if ( aSign ) {
float_raise(float_flag_invalid, status);
- return float32_default_nan;
+ return float32_default_nan(status);
}
if ( aExp == 0xFF ) {
if (aSig) {
@@ -2974,7 +2974,8 @@ int float32_eq_quiet(float32 a, float32 b, float_status *status)
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
- if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
+ if ( float32_is_signaling_nan( a, status )
+ || float32_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -3000,7 +3001,8 @@ int float32_le_quiet(float32 a, float32 b, float_status *status)
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
- if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
+ if ( float32_is_signaling_nan( a, status )
+ || float32_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -3031,7 +3033,8 @@ int float32_lt_quiet(float32 a, float32 b, float_status *status)
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
- if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
+ if ( float32_is_signaling_nan( a, status )
+ || float32_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -3060,7 +3063,8 @@ int float32_unordered_quiet(float32 a, float32 b, float_status *status)
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
- if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
+ if ( float32_is_signaling_nan( a, status )
+ || float32_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 1;
@@ -3896,7 +3900,7 @@ static float64 subFloat64Sigs(float64 a, float64 b, flag zSign,
return propagateFloat64NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
if ( aExp == 0 ) {
aExp = 1;
@@ -4023,7 +4027,7 @@ float64 float64_mul(float64 a, float64 b, float_status *status)
}
if ( ( bExp | bSig ) == 0 ) {
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
return packFloat64( zSign, 0x7FF, 0 );
}
@@ -4033,7 +4037,7 @@ float64 float64_mul(float64 a, float64 b, float_status *status)
}
if ( ( aExp | aSig ) == 0 ) {
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
return packFloat64( zSign, 0x7FF, 0 );
}
@@ -4090,7 +4094,7 @@ float64 float64_div(float64 a, float64 b, float_status *status)
return propagateFloat64NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
return packFloat64( zSign, 0x7FF, 0 );
}
@@ -4104,7 +4108,7 @@ float64 float64_div(float64 a, float64 b, float_status *status)
if ( bSig == 0 ) {
if ( ( aExp | aSig ) == 0 ) {
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
float_raise(float_flag_divbyzero, status);
return packFloat64( zSign, 0x7FF, 0 );
@@ -4162,7 +4166,7 @@ float64 float64_rem(float64 a, float64 b, float_status *status)
return propagateFloat64NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
if ( bExp == 0x7FF ) {
if (bSig) {
@@ -4173,7 +4177,7 @@ float64 float64_rem(float64 a, float64 b, float_status *status)
if ( bExp == 0 ) {
if ( bSig == 0 ) {
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
normalizeFloat64Subnormal( bSig, &bExp, &bSig );
}
@@ -4275,7 +4279,7 @@ float64 float64_muladd(float64 a, float64 b, float64 c, int flags,
if (infzero) {
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
if (flags & float_muladd_negate_c) {
@@ -4296,7 +4300,7 @@ float64 float64_muladd(float64 a, float64 b, float64 c, int flags,
if (pInf && (pSign ^ cSign)) {
/* addition of opposite-signed infinities => InvalidOperation */
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
/* Otherwise generate an infinity of the same sign */
return packFloat64(cSign ^ signflip, 0x7ff, 0);
@@ -4494,12 +4498,12 @@ float64 float64_sqrt(float64 a, float_status *status)
}
if ( ! aSign ) return a;
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
if ( aSign ) {
if ( ( aExp | aSig ) == 0 ) return a;
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return float64_zero;
@@ -4547,7 +4551,7 @@ float64 float64_log2(float64 a, float_status *status)
}
if ( aSign ) {
float_raise(float_flag_invalid, status);
- return float64_default_nan;
+ return float64_default_nan(status);
}
if ( aExp == 0x7FF ) {
if (aSig) {
@@ -4694,7 +4698,8 @@ int float64_eq_quiet(float64 a, float64 b, float_status *status)
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
- if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
+ if ( float64_is_signaling_nan( a, status )
+ || float64_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -4722,7 +4727,8 @@ int float64_le_quiet(float64 a, float64 b, float_status *status)
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
- if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
+ if ( float64_is_signaling_nan( a, status )
+ || float64_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -4753,7 +4759,8 @@ int float64_lt_quiet(float64 a, float64 b, float_status *status)
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
- if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
+ if ( float64_is_signaling_nan( a, status )
+ || float64_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -4782,7 +4789,8 @@ int float64_unordered_quiet(float64 a, float64 b, float_status *status)
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
- if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
+ if ( float64_is_signaling_nan( a, status )
+ || float64_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 1;
@@ -5207,7 +5215,6 @@ static floatx80 subFloatx80Sigs(floatx80 a, floatx80 b, flag zSign,
int32_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig0, zSig1;
int32_t expDiff;
- floatx80 z;
aSig = extractFloatx80Frac( a );
aExp = extractFloatx80Exp( a );
@@ -5221,9 +5228,7 @@ static floatx80 subFloatx80Sigs(floatx80 a, floatx80 b, flag zSign,
return propagateFloatx80NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
- return z;
+ return floatx80_default_nan(status);
}
if ( aExp == 0 ) {
aExp = 1;
@@ -5317,7 +5322,6 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_status *status)
flag aSign, bSign, zSign;
int32_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig0, zSig1;
- floatx80 z;
aSig = extractFloatx80Frac( a );
aExp = extractFloatx80Exp( a );
@@ -5341,9 +5345,7 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_status *status)
if ( ( aExp | aSig ) == 0 ) {
invalid:
float_raise(float_flag_invalid, status);
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
- return z;
+ return floatx80_default_nan(status);
}
return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
}
@@ -5377,7 +5379,6 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status)
int32_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig0, zSig1;
uint64_t rem0, rem1, rem2, term0, term1, term2;
- floatx80 z;
aSig = extractFloatx80Frac( a );
aExp = extractFloatx80Exp( a );
@@ -5409,9 +5410,7 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status)
if ( ( aExp | aSig ) == 0 ) {
invalid:
float_raise(float_flag_invalid, status);
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
- return z;
+ return floatx80_default_nan(status);
}
float_raise(float_flag_divbyzero, status);
return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
@@ -5461,7 +5460,6 @@ floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status)
int32_t aExp, bExp, expDiff;
uint64_t aSig0, aSig1, bSig;
uint64_t q, term0, term1, alternateASig0, alternateASig1;
- floatx80 z;
aSig0 = extractFloatx80Frac( a );
aExp = extractFloatx80Exp( a );
@@ -5485,9 +5483,7 @@ floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status)
if ( bSig == 0 ) {
invalid:
float_raise(float_flag_invalid, status);
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
- return z;
+ return floatx80_default_nan(status);
}
normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
}
@@ -5559,7 +5555,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status)
int32_t aExp, zExp;
uint64_t aSig0, aSig1, zSig0, zSig1, doubleZSig0;
uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;
- floatx80 z;
aSig0 = extractFloatx80Frac( a );
aExp = extractFloatx80Exp( a );
@@ -5575,9 +5570,7 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status)
if ( ( aExp | aSig0 ) == 0 ) return a;
invalid:
float_raise(float_flag_invalid, status);
- z.low = floatx80_default_nan_low;
- z.high = floatx80_default_nan_high;
- return z;
+ return floatx80_default_nan(status);
}
if ( aExp == 0 ) {
if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );
@@ -5745,8 +5738,8 @@ int floatx80_eq_quiet(floatx80 a, floatx80 b, float_status *status)
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
) {
- if ( floatx80_is_signaling_nan( a )
- || floatx80_is_signaling_nan( b ) ) {
+ if ( floatx80_is_signaling_nan( a, status )
+ || floatx80_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -5776,8 +5769,8 @@ int floatx80_le_quiet(floatx80 a, floatx80 b, float_status *status)
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
) {
- if ( floatx80_is_signaling_nan( a )
- || floatx80_is_signaling_nan( b ) ) {
+ if ( floatx80_is_signaling_nan( a, status )
+ || floatx80_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -5812,8 +5805,8 @@ int floatx80_lt_quiet(floatx80 a, floatx80 b, float_status *status)
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
) {
- if ( floatx80_is_signaling_nan( a )
- || floatx80_is_signaling_nan( b ) ) {
+ if ( floatx80_is_signaling_nan( a, status )
+ || floatx80_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -5845,8 +5838,8 @@ int floatx80_unordered_quiet(floatx80 a, floatx80 b, float_status *status)
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
) {
- if ( floatx80_is_signaling_nan( a )
- || floatx80_is_signaling_nan( b ) ) {
+ if ( floatx80_is_signaling_nan( a, status )
+ || floatx80_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 1;
@@ -6385,7 +6378,6 @@ static float128 subFloat128Sigs(float128 a, float128 b, flag zSign,
int32_t aExp, bExp, zExp;
uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;
int32_t expDiff;
- float128 z;
aSig1 = extractFloat128Frac1( a );
aSig0 = extractFloat128Frac0( a );
@@ -6403,9 +6395,7 @@ static float128 subFloat128Sigs(float128 a, float128 b, flag zSign,
return propagateFloat128NaN(a, b, status);
}
float_raise(float_flag_invalid, status);
- z.low = float128_default_nan_low;
- z.high = float128_default_nan_high;
- return z;
+ return float128_default_nan(status);
}
if ( aExp == 0 ) {
aExp = 1;
@@ -6515,7 +6505,6 @@ float128 float128_mul(float128 a, float128 b, float_status *status)
flag aSign, bSign, zSign;
int32_t aExp, bExp, zExp;
uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;
- float128 z;
aSig1 = extractFloat128Frac1( a );
aSig0 = extractFloat128Frac0( a );
@@ -6541,9 +6530,7 @@ float128 float128_mul(float128 a, float128 b, float_status *status)
if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
invalid:
float_raise(float_flag_invalid, status);
- z.low = float128_default_nan_low;
- z.high = float128_default_nan_high;
- return z;
+ return float128_default_nan(status);
}
return packFloat128( zSign, 0x7FFF, 0, 0 );
}
@@ -6582,7 +6569,6 @@ float128 float128_div(float128 a, float128 b, float_status *status)
int32_t aExp, bExp, zExp;
uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;
uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;
- float128 z;
aSig1 = extractFloat128Frac1( a );
aSig0 = extractFloat128Frac0( a );
@@ -6616,9 +6602,7 @@ float128 float128_div(float128 a, float128 b, float_status *status)
if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
invalid:
float_raise(float_flag_invalid, status);
- z.low = float128_default_nan_low;
- z.high = float128_default_nan_high;
- return z;
+ return float128_default_nan(status);
}
float_raise(float_flag_divbyzero, status);
return packFloat128( zSign, 0x7FFF, 0, 0 );
@@ -6673,7 +6657,6 @@ float128 float128_rem(float128 a, float128 b, float_status *status)
uint64_t aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2;
uint64_t allZero, alternateASig0, alternateASig1, sigMean1;
int64_t sigMean0;
- float128 z;
aSig1 = extractFloat128Frac1( a );
aSig0 = extractFloat128Frac0( a );
@@ -6699,9 +6682,7 @@ float128 float128_rem(float128 a, float128 b, float_status *status)
if ( ( bSig0 | bSig1 ) == 0 ) {
invalid:
float_raise(float_flag_invalid, status);
- z.low = float128_default_nan_low;
- z.high = float128_default_nan_high;
- return z;
+ return float128_default_nan(status);
}
normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
}
@@ -6782,7 +6763,6 @@ float128 float128_sqrt(float128 a, float_status *status)
int32_t aExp, zExp;
uint64_t aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0;
uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;
- float128 z;
aSig1 = extractFloat128Frac1( a );
aSig0 = extractFloat128Frac0( a );
@@ -6799,9 +6779,7 @@ float128 float128_sqrt(float128 a, float_status *status)
if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;
invalid:
float_raise(float_flag_invalid, status);
- z.low = float128_default_nan_low;
- z.high = float128_default_nan_high;
- return z;
+ return float128_default_nan(status);
}
if ( aExp == 0 ) {
if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );
@@ -6969,8 +6947,8 @@ int float128_eq_quiet(float128 a, float128 b, float_status *status)
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
) {
- if ( float128_is_signaling_nan( a )
- || float128_is_signaling_nan( b ) ) {
+ if ( float128_is_signaling_nan( a, status )
+ || float128_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -7000,8 +6978,8 @@ int float128_le_quiet(float128 a, float128 b, float_status *status)
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
) {
- if ( float128_is_signaling_nan( a )
- || float128_is_signaling_nan( b ) ) {
+ if ( float128_is_signaling_nan( a, status )
+ || float128_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -7036,8 +7014,8 @@ int float128_lt_quiet(float128 a, float128 b, float_status *status)
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
) {
- if ( float128_is_signaling_nan( a )
- || float128_is_signaling_nan( b ) ) {
+ if ( float128_is_signaling_nan( a, status )
+ || float128_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 0;
@@ -7070,8 +7048,8 @@ int float128_unordered_quiet(float128 a, float128 b, float_status *status)
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
) {
- if ( float128_is_signaling_nan( a )
- || float128_is_signaling_nan( b ) ) {
+ if ( float128_is_signaling_nan( a, status )
+ || float128_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return 1;
@@ -7351,8 +7329,8 @@ static inline int float ## s ## _compare_internal(float ## s a, float ## s b,\
( ( extractFloat ## s ## Exp( b ) == nan_exp ) && \
extractFloat ## s ## Frac( b ) )) { \
if (!is_quiet || \
- float ## s ## _is_signaling_nan( a ) || \
- float ## s ## _is_signaling_nan( b ) ) { \
+ float ## s ## _is_signaling_nan( a, status ) || \
+ float ## s ## _is_signaling_nan( b, status ) ) { \
float_raise(float_flag_invalid, status); \
} \
return float_relation_unordered; \
@@ -7401,8 +7379,8 @@ static inline int floatx80_compare_internal(floatx80 a, floatx80 b,
( ( extractFloatx80Exp( b ) == 0x7fff ) &&
( extractFloatx80Frac( b )<<1 ) )) {
if (!is_quiet ||
- floatx80_is_signaling_nan( a ) ||
- floatx80_is_signaling_nan( b ) ) {
+ floatx80_is_signaling_nan( a, status ) ||
+ floatx80_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return float_relation_unordered;
@@ -7447,8 +7425,8 @@ static inline int float128_compare_internal(float128 a, float128 b,
( ( extractFloat128Exp( b ) == 0x7fff ) &&
( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )) {
if (!is_quiet ||
- float128_is_signaling_nan( a ) ||
- float128_is_signaling_nan( b ) ) {
+ float128_is_signaling_nan( a, status ) ||
+ float128_is_signaling_nan( b, status ) ) {
float_raise(float_flag_invalid, status);
}
return float_relation_unordered;
@@ -7508,11 +7486,11 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \
if (float ## s ## _is_any_nan(a) || \
float ## s ## _is_any_nan(b)) { \
if (isieee) { \
- if (float ## s ## _is_quiet_nan(a) && \
+ if (float ## s ## _is_quiet_nan(a, status) && \
!float ## s ##_is_any_nan(b)) { \
return b; \
- } else if (float ## s ## _is_quiet_nan(b) && \
- !float ## s ## _is_any_nan(a)) { \
+ } else if (float ## s ## _is_quiet_nan(b, status) && \
+ !float ## s ## _is_any_nan(a )) { \
return a; \
} \
} \
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index c937062..689a089 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -205,6 +205,7 @@ typedef struct float_status {
/* should denormalised inputs go to zero and set the input_denormal flag? */
flag flush_inputs_to_zero;
flag default_nan_mode;
+ flag snan_bit_is_one;
} float_status;
static inline void set_float_detect_tininess(int val, float_status *status)
@@ -236,6 +237,10 @@ static inline void set_default_nan_mode(flag val, float_status *status)
{
status->default_nan_mode = val;
}
+static inline void set_snan_bit_is_one(flag val, float_status *status)
+{
+ status->snan_bit_is_one = val;
+}
static inline int get_float_detect_tininess(float_status *status)
{
return status->float_detect_tininess;
@@ -342,9 +347,9 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
/*----------------------------------------------------------------------------
| Software half-precision operations.
*----------------------------------------------------------------------------*/
-int float16_is_quiet_nan( float16 );
-int float16_is_signaling_nan( float16 );
-float16 float16_maybe_silence_nan( float16 );
+int float16_is_quiet_nan( float16, float_status *status );
+int float16_is_signaling_nan( float16, float_status *status );
+float16 float16_maybe_silence_nan( float16, float_status *status );
static inline int float16_is_any_nan(float16 a)
{
@@ -354,7 +359,7 @@ static inline int float16_is_any_nan(float16 a)
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
-extern const float16 float16_default_nan;
+float16 float16_default_nan(float_status *status);
/*----------------------------------------------------------------------------
| Software IEC/IEEE single-precision conversion routines.
@@ -404,9 +409,9 @@ float32 float32_minnum(float32, float32, float_status *status);
float32 float32_maxnum(float32, float32, float_status *status);
float32 float32_minnummag(float32, float32, float_status *status);
float32 float32_maxnummag(float32, float32, float_status *status);
-int float32_is_quiet_nan( float32 );
-int float32_is_signaling_nan( float32 );
-float32 float32_maybe_silence_nan( float32 );
+int float32_is_quiet_nan( float32, float_status *status );
+int float32_is_signaling_nan( float32, float_status *status );
+float32 float32_maybe_silence_nan( float32, float_status *status );
float32 float32_scalbn(float32, int, float_status *status);
static inline float32 float32_abs(float32 a)
@@ -466,7 +471,7 @@ static inline float32 float32_set_sign(float32 a, int sign)
/*----------------------------------------------------------------------------
| The pattern for a default generated single-precision NaN.
*----------------------------------------------------------------------------*/
-extern const float32 float32_default_nan;
+float32 float32_default_nan(float_status *status);
/*----------------------------------------------------------------------------
| Software IEC/IEEE double-precision conversion routines.
@@ -516,9 +521,9 @@ float64 float64_minnum(float64, float64, float_status *status);
float64 float64_maxnum(float64, float64, float_status *status);
float64 float64_minnummag(float64, float64, float_status *status);
float64 float64_maxnummag(float64, float64, float_status *status);
-int float64_is_quiet_nan( float64 a );
-int float64_is_signaling_nan( float64 );
-float64 float64_maybe_silence_nan( float64 );
+int float64_is_quiet_nan( float64 a, float_status *status );
+int float64_is_signaling_nan( float64, float_status *status );
+float64 float64_maybe_silence_nan( float64, float_status *status );
float64 float64_scalbn(float64, int, float_status *status);
static inline float64 float64_abs(float64 a)
@@ -578,7 +583,7 @@ static inline float64 float64_set_sign(float64 a, int sign)
/*----------------------------------------------------------------------------
| The pattern for a default generated double-precision NaN.
*----------------------------------------------------------------------------*/
-extern const float64 float64_default_nan;
+float64 float64_default_nan(float_status *status);
/*----------------------------------------------------------------------------
| Software IEC/IEEE extended double-precision conversion routines.
@@ -611,9 +616,9 @@ int floatx80_lt_quiet(floatx80, floatx80, float_status *status);
int floatx80_unordered_quiet(floatx80, floatx80, float_status *status);
int floatx80_compare(floatx80, floatx80, float_status *status);
int floatx80_compare_quiet(floatx80, floatx80, float_status *status);
-int floatx80_is_quiet_nan( floatx80 );
-int floatx80_is_signaling_nan( floatx80 );
-floatx80 floatx80_maybe_silence_nan( floatx80 );
+int floatx80_is_quiet_nan( floatx80, float_status *status );
+int floatx80_is_signaling_nan( floatx80, float_status *status );
+floatx80 floatx80_maybe_silence_nan( floatx80, float_status *status );
floatx80 floatx80_scalbn(floatx80, int, float_status *status);
static inline floatx80 floatx80_abs(floatx80 a)
@@ -663,7 +668,7 @@ static inline int floatx80_is_any_nan(floatx80 a)
/*----------------------------------------------------------------------------
| The pattern for a default generated extended double-precision NaN.
*----------------------------------------------------------------------------*/
-extern const floatx80 floatx80_default_nan;
+floatx80 floatx80_default_nan(float_status *status);
/*----------------------------------------------------------------------------
| Software IEC/IEEE quadruple-precision conversion routines.
@@ -696,9 +701,9 @@ int float128_lt_quiet(float128, float128, float_status *status);
int float128_unordered_quiet(float128, float128, float_status *status);
int float128_compare(float128, float128, float_status *status);
int float128_compare_quiet(float128, float128, float_status *status);
-int float128_is_quiet_nan( float128 );
-int float128_is_signaling_nan( float128 );
-float128 float128_maybe_silence_nan( float128 );
+int float128_is_quiet_nan( float128, float_status *status );
+int float128_is_signaling_nan( float128, float_status *status );
+float128 float128_maybe_silence_nan( float128, float_status *status );
float128 float128_scalbn(float128, int, float_status *status);
static inline float128 float128_abs(float128 a)
@@ -744,6 +749,6 @@ static inline int float128_is_any_nan(float128 a)
/*----------------------------------------------------------------------------
| The pattern for a default generated quadruple-precision NaN.
*----------------------------------------------------------------------------*/
-extern const float128 float128_default_nan;
+float128 float128_default_nan(float_status *status);
#endif /* !SOFTFLOAT_H */
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 8a155ca..a8b1e13 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -278,6 +278,8 @@ static void alpha_cpu_initfn(Object *obj)
#endif
env->lock_addr = -1;
env->fen = 1;
+
+ set_snan_bit_is_one(0, &env->fp_status);
}
static void alpha_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index c7bfb4d..50f0c8b 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -343,12 +343,12 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
if (float32_is_any_nan(a)) {
float32 nan = a;
- if (float32_is_signaling_nan(a)) {
+ if (float32_is_signaling_nan(a, fpst)) {
float_raise(float_flag_invalid, fpst);
- nan = float32_maybe_silence_nan(a);
+ nan = float32_maybe_silence_nan(a, fpst);
}
if (fpst->default_nan_mode) {
- nan = float32_default_nan;
+ nan = float32_default_nan(fpst);
}
return nan;
}
@@ -372,12 +372,12 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
if (float64_is_any_nan(a)) {
float64 nan = a;
- if (float64_is_signaling_nan(a)) {
+ if (float64_is_signaling_nan(a, fpst)) {
float_raise(float_flag_invalid, fpst);
- nan = float64_maybe_silence_nan(a);
+ nan = float64_maybe_silence_nan(a, fpst);
}
if (fpst->default_nan_mode) {
- nan = float64_default_nan;
+ nan = float64_default_nan(fpst);
}
return nan;
}
@@ -406,7 +406,7 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
set_float_rounding_mode(float_round_to_zero, &tstat);
set_float_exception_flags(0, &tstat);
r = float64_to_float32(a, &tstat);
- r = float32_maybe_silence_nan(r);
+ r = float32_maybe_silence_nan(r, &tstat);
exflags = get_float_exception_flags(&tstat);
if (exflags & float_flag_inexact) {
r = make_float32(float32_val(r) | 1);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 09638b2..6ef4450 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8648,7 +8648,7 @@ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
/* ARM requires that S<->D conversion of any kind of NaN generates
* a quiet NaN by forcing the most significant frac bit to 1.
*/
- return float64_maybe_silence_nan(r);
+ return float64_maybe_silence_nan(r, &env->vfp.fp_status);
}
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
@@ -8657,7 +8657,7 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
/* ARM requires that S<->D conversion of any kind of NaN generates
* a quiet NaN by forcing the most significant frac bit to 1.
*/
- return float32_maybe_silence_nan(r);
+ return float32_maybe_silence_nan(r, &env->vfp.fp_status);
}
/* VFP3 fixed point conversion. */
@@ -8756,7 +8756,7 @@ static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float32 r = float16_to_float32(make_float16(a), ieee, s);
if (ieee) {
- return float32_maybe_silence_nan(r);
+ return float32_maybe_silence_nan(r, s);
}
return r;
}
@@ -8766,7 +8766,7 @@ static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float16 r = float32_to_float16(a, ieee, s);
if (ieee) {
- r = float16_maybe_silence_nan(r);
+ r = float16_maybe_silence_nan(r, s);
}
return float16_val(r);
}
@@ -8796,7 +8796,7 @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
if (ieee) {
- return float64_maybe_silence_nan(r);
+ return float64_maybe_silence_nan(r, &env->vfp.fp_status);
}
return r;
}
@@ -8806,7 +8806,7 @@ uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
if (ieee) {
- r = float16_maybe_silence_nan(r);
+ r = float16_maybe_silence_nan(r, &env->vfp.fp_status);
}
return float16_val(r);
}
@@ -8956,12 +8956,12 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
if (float32_is_any_nan(f32)) {
float32 nan = f32;
- if (float32_is_signaling_nan(f32)) {
+ if (float32_is_signaling_nan(f32, fpst)) {
float_raise(float_flag_invalid, fpst);
- nan = float32_maybe_silence_nan(f32);
+ nan = float32_maybe_silence_nan(f32, fpst);
}
if (fpst->default_nan_mode) {
- nan = float32_default_nan;
+ nan = float32_default_nan(fpst);
}
return nan;
} else if (float32_is_infinity(f32)) {
@@ -9010,12 +9010,12 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
/* Deal with any special cases */
if (float64_is_any_nan(f64)) {
float64 nan = f64;
- if (float64_is_signaling_nan(f64)) {
+ if (float64_is_signaling_nan(f64, fpst)) {
float_raise(float_flag_invalid, fpst);
- nan = float64_maybe_silence_nan(f64);
+ nan = float64_maybe_silence_nan(f64, fpst);
}
if (fpst->default_nan_mode) {
- nan = float64_default_nan;
+ nan = float64_default_nan(fpst);
}
return nan;
} else if (float64_is_infinity(f64)) {
@@ -9117,12 +9117,12 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
if (float32_is_any_nan(f32)) {
float32 nan = f32;
- if (float32_is_signaling_nan(f32)) {
+ if (float32_is_signaling_nan(f32, s)) {
float_raise(float_flag_invalid, s);
- nan = float32_maybe_silence_nan(f32);
+ nan = float32_maybe_silence_nan(f32, s);
}
if (s->default_nan_mode) {
- nan = float32_default_nan;
+ nan = float32_default_nan(s);
}
return nan;
} else if (float32_is_zero(f32)) {
@@ -9130,7 +9130,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
return float32_set_sign(float32_infinity, float32_is_neg(f32));
} else if (float32_is_neg(f32)) {
float_raise(float_flag_invalid, s);
- return float32_default_nan;
+ return float32_default_nan(s);
} else if (float32_is_infinity(f32)) {
return float32_zero;
}
@@ -9181,12 +9181,12 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
if (float64_is_any_nan(f64)) {
float64 nan = f64;
- if (float64_is_signaling_nan(f64)) {
+ if (float64_is_signaling_nan(f64, s)) {
float_raise(float_flag_invalid, s);
- nan = float64_maybe_silence_nan(f64);
+ nan = float64_maybe_silence_nan(f64, s);
}
if (s->default_nan_mode) {
- nan = float64_default_nan;
+ nan = float64_default_nan(s);
}
return nan;
} else if (float64_is_zero(f64)) {
@@ -9194,7 +9194,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
return float64_set_sign(float64_infinity, float64_is_neg(f64));
} else if (float64_is_neg(f64)) {
float_raise(float_flag_invalid, s);
- return float64_default_nan;
+ return float64_default_nan(s);
} else if (float64_is_infinity(f64)) {
return float64_zero;
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index a8f6d9d..4a1c623 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -557,10 +557,10 @@ float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
/* ??? Should flush denormals to zero. */
float64 res;
res = float64_sub(a, b, &env->fp_status);
- if (float64_is_quiet_nan(res)) {
+ if (float64_is_quiet_nan(res, &env->fp_status)) {
/* +/-inf compares equal against itself, but sub returns nan. */
- if (!float64_is_quiet_nan(a)
- && !float64_is_quiet_nan(b)) {
+ if (!float64_is_quiet_nan(a, &env->fp_status)
+ && !float64_is_quiet_nan(b, &env->fp_status)) {
res = float64_zero;
if (float64_lt_quiet(a, res, &env->fp_status))
res = float64_chs(res);
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index fdfb019..31f78cb 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -121,6 +121,8 @@ static void mb_cpu_reset(CPUState *s)
env->mmu.c_mmu_tlb_access = 3;
env->mmu.c_mmu_zones = 16;
#endif
+
+ set_snan_bit_is_one(0, &env->fp_status);
}
static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 9733388..45fc94d 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -287,12 +287,14 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
fa.l = a;
fb.l = b;
- if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
+ if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
+ float32_is_signaling_nan(fb.f, &env->fp_status)) {
update_fpu_flags(env, float_flag_invalid);
r = 1;
}
- if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
+ if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
+ float32_is_quiet_nan(fb.f, &env->fp_status)) {
r = 1;
}
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 594341d..133dcfb 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -222,8 +222,8 @@ DEF_HELPER_2(float_cvtw_d, i32, env, i64)
DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
-DEF_HELPER_FLAGS_1(float_class_s, TCG_CALL_NO_RWG_SE, i32, i32)
-DEF_HELPER_FLAGS_1(float_class_d, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_3(float_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(float_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64, i32)
#define FOP_PROTO(op) \
DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c
index 654a0d2..a079fe4 100644
--- a/target-mips/msa_helper.c
+++ b/target-mips/msa_helper.c
@@ -1494,11 +1494,11 @@ MSA_UNOP_DF(pcnt)
#define FLOAT_ONE32 make_float32(0x3f8 << 20)
#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
-#define FLOAT_SNAN16 (float16_default_nan ^ 0x0220)
+#define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
/* 0x7c20 */
-#define FLOAT_SNAN32 (float32_default_nan ^ 0x00400020)
+#define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
/* 0x7f800020 */
-#define FLOAT_SNAN64 (float64_default_nan ^ 0x0008000000000020ULL)
+#define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
/* 0x7ff0000000000020 */
static inline void clear_msacsr_cause(CPUMIPSState *env)
@@ -1611,7 +1611,7 @@ static inline float16 float16_from_float32(int32_t a, flag ieee,
float16 f_val;
f_val = float32_to_float16((float32)a, ieee, status);
- f_val = float16_maybe_silence_nan(f_val);
+ f_val = float16_maybe_silence_nan(f_val, status);
return a < 0 ? (f_val | (1 << 15)) : f_val;
}
@@ -1621,7 +1621,7 @@ static inline float32 float32_from_float64(int64_t a, float_status *status)
float32 f_val;
f_val = float64_to_float32((float64)a, status);
- f_val = float32_maybe_silence_nan(f_val);
+ f_val = float32_maybe_silence_nan(f_val, status);
return a < 0 ? (f_val | (1 << 31)) : f_val;
}
@@ -1632,7 +1632,7 @@ static inline float32 float32_from_float16(int16_t a, flag ieee,
float32 f_val;
f_val = float16_to_float32((float16)a, ieee, status);
- f_val = float32_maybe_silence_nan(f_val);
+ f_val = float32_maybe_silence_nan(f_val, status);
return a < 0 ? (f_val | (1 << 31)) : f_val;
}
@@ -1642,7 +1642,7 @@ static inline float64 float64_from_float32(int32_t a, float_status *status)
float64 f_val;
f_val = float32_to_float64((float64)a, status);
- f_val = float64_maybe_silence_nan(f_val);
+ f_val = float64_maybe_silence_nan(f_val, status);
return a < 0 ? (f_val | (1ULL << 63)) : f_val;
}
@@ -1788,7 +1788,8 @@ static inline int32_t float64_to_q32(float64 a, float_status *status)
c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
@@ -2387,7 +2388,8 @@ void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
@@ -2523,7 +2525,8 @@ void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
@@ -2642,7 +2645,8 @@ void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
@@ -2693,7 +2697,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## XBITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## XBITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
@@ -2730,9 +2735,9 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_move_v(pwd, pwx);
}
-#define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS) \
- !float ## BITS ## _is_any_nan(ARG1) \
- && float ## BITS ## _is_quiet_nan(ARG2)
+#define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
+ !float ## BITS ## _is_any_nan(ARG1) \
+ && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
#define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
do { \
@@ -2744,18 +2749,19 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
c = update_msacsr(env, 0, 0); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
-#define FMAXMIN_A(F, G, X, _S, _T, BITS) \
+#define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
do { \
uint## BITS ##_t S = _S, T = _T; \
uint## BITS ##_t as, at, xs, xt, xd; \
- if (NUMBER_QNAN_PAIR(S, T, BITS)) { \
+ if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
T = S; \
} \
- else if (NUMBER_QNAN_PAIR(T, S, BITS)) { \
+ else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
S = T; \
} \
as = float## BITS ##_abs(S); \
@@ -2769,6 +2775,7 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t wt)
{
+ float_status *status = &env->active_tc.msa_fp_status;
wr_t wx, *pwx = &wx;
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
@@ -2780,9 +2787,9 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
- if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
+ if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
- } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
+ } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
} else {
MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
@@ -2791,9 +2798,9 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
break;
case DF_DOUBLE:
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
- if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
+ if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
- } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
+ } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
} else {
MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
@@ -2812,6 +2819,7 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t wt)
{
+ float_status *status = &env->active_tc.msa_fp_status;
wr_t wx, *pwx = &wx;
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
@@ -2823,12 +2831,12 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
- FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32);
+ FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
}
break;
case DF_DOUBLE:
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
- FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64);
+ FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
}
break;
default:
@@ -2843,6 +2851,7 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t wt)
{
+ float_status *status = &env->active_tc.msa_fp_status;
wr_t wx, *pwx = &wx;
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
@@ -2854,9 +2863,9 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
- if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
+ if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
- } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
+ } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
} else {
MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
@@ -2865,9 +2874,9 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
break;
case DF_DOUBLE:
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
- if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
+ if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
- } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
+ } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
} else {
MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
@@ -2886,6 +2895,7 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t wt)
{
+ float_status *status = &env->active_tc.msa_fp_status;
wr_t wx, *pwx = &wx;
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
@@ -2897,12 +2907,12 @@ void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
- FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32);
+ FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
}
break;
case DF_DOUBLE:
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
- FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64);
+ FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
}
break;
default:
@@ -2920,13 +2930,13 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
if (df == DF_WORD) {
- pwd->w[0] = helper_float_class_s(pws->w[0]);
- pwd->w[1] = helper_float_class_s(pws->w[1]);
- pwd->w[2] = helper_float_class_s(pws->w[2]);
- pwd->w[3] = helper_float_class_s(pws->w[3]);
+ pwd->w[0] = helper_float_class_s(env, pws->w[0], 1);
+ pwd->w[1] = helper_float_class_s(env, pws->w[1], 1);
+ pwd->w[2] = helper_float_class_s(env, pws->w[2], 1);
+ pwd->w[3] = helper_float_class_s(env, pws->w[3], 1);
} else {
- pwd->d[0] = helper_float_class_d(pws->d[0]);
- pwd->d[1] = helper_float_class_d(pws->d[1]);
+ pwd->d[0] = helper_float_class_d(env, pws->d[0], 1);
+ pwd->d[1] = helper_float_class_d(env, pws->d[1], 1);
}
}
@@ -2940,7 +2950,8 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} else if (float ## BITS ## _is_any_nan(ARG)) { \
DEST = 0; \
} \
@@ -3044,12 +3055,14 @@ void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
- float ## BITS ## _is_quiet_nan(DEST) ? \
+ float ## BITS ## _is_quiet_nan(DEST, \
+ &env->active_tc.msa_fp_status) ? \
0 : RECIPROCAL_INEXACT, \
IS_DENORMAL(DEST, BITS)); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
@@ -3165,7 +3178,8 @@ void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
\
if (get_enabled_exceptions(env, c)) { \
- DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
+ DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status) \
+ >> 6) << 6) | c; \
} \
} while (0)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 8ec1bef..ce7ec9c 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2660,7 +2660,7 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
uint64_t fdt2;
fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
- fdt2 = float64_maybe_silence_nan(fdt2);
+ fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return fdt2;
}
@@ -2750,7 +2750,7 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
uint32_t fst2;
fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
- fst2 = float32_maybe_silence_nan(fst2);
+ fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return fst2;
}
@@ -3200,11 +3200,17 @@ FLOAT_RINT(rint_d, 64)
#define FLOAT_CLASS_POSITIVE_ZERO 0x200
#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
+uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
+ uint ## bits ## _t arg, uint32_t is_msa) \
{ \
- if (float ## bits ## _is_signaling_nan(arg)) { \
+ float_status* fst; \
+ \
+ fst = (is_msa == 1) ? \
+ &env->active_tc.msa_fp_status : &env->active_fpu.fp_status; \
+ \
+ if (float ## bits ## _is_signaling_nan(arg, fst)) { \
return FLOAT_CLASS_SIGNALING_NAN; \
- } else if (float ## bits ## _is_quiet_nan(arg)) { \
+ } else if (float ## bits ## _is_quiet_nan(arg, fst)) { \
return FLOAT_CLASS_QUIET_NAN; \
} else if (float ## bits ## _is_neg(arg)) { \
if (float ## bits ## _is_infinity(arg)) { \
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a3a05ec..496216d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9110,7 +9110,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_class_s(fp0, fp0);
+ gen_helper_float_class_s(fp0, cpu_env, fp0, 0);
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -9608,7 +9608,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_class_d(fp0, fp0);
+ gen_helper_float_class_d(fp0, cpu_env, fp0, 0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -20129,6 +20129,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
+ set_snan_bit_is_one(1, &env->active_fpu.fp_status);
env->msair = env->cpu_model->MSAIR;
env->insn_flags = env->cpu_model->insn_flags;
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 5af077d..e81a831 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -892,4 +892,6 @@ static void msa_reset(CPUMIPSState *env)
/* clear float_status nan mode */
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+ set_snan_bit_is_one(1, &env->active_tc.msa_fp_status);
}
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index b67ebca..48e9f40 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -73,7 +73,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
isneg = float64_is_neg(farg.d);
if (unlikely(float64_is_any_nan(farg.d))) {
- if (float64_is_signaling_nan(farg.d)) {
+ if (float64_is_signaling_nan(farg.d, &env->fp_status)) {
/* Signaling NaN: flags are undefined */
fprf = 0x00;
} else {
@@ -534,8 +534,8 @@ uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
/* Magnitude subtraction of infinities */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status))) {
/* sNaN addition */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -558,8 +558,8 @@ uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
/* Magnitude subtraction of infinities */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status))) {
/* sNaN subtraction */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -582,8 +582,8 @@ uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
/* Multiplication of zero by infinity */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status))) {
/* sNaN multiplication */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -609,8 +609,8 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
/* Division of zero by zero */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status))) {
/* sNaN division */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -632,7 +632,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
if (unlikely(env->fp_status.float_exception_flags)) { \
if (float64_is_any_nan(arg)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
- if (float64_is_signaling_nan(arg)) { \
+ if (float64_is_signaling_nan(arg, &env->fp_status)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
} \
farg.ll = nanval; \
@@ -681,7 +681,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(farg.d))) {
+ if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
/* sNaN round */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
farg.ll = arg | 0x0008000000000000ULL;
@@ -737,9 +737,9 @@ uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
/* Multiplication of zero by infinity */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d) ||
- float64_is_signaling_nan(farg3.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg3.d, &env->fp_status))) {
/* sNaN operation */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -780,9 +780,9 @@ uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
/* Multiplication of zero by infinity */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d) ||
- float64_is_signaling_nan(farg3.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg3.d, &env->fp_status))) {
/* sNaN operation */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -821,9 +821,9 @@ uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
/* Multiplication of zero by infinity */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d) ||
- float64_is_signaling_nan(farg3.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg3.d, &env->fp_status))) {
/* sNaN operation */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -866,9 +866,9 @@ uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
/* Multiplication of zero by infinity */
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
} else {
- if (unlikely(float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d) ||
- float64_is_signaling_nan(farg3.d))) {
+ if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg3.d, &env->fp_status))) {
/* sNaN operation */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -903,7 +903,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(farg.d))) {
+ if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
/* sNaN square root */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -921,7 +921,7 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
if (unlikely(float64_is_any_nan(farg.d))) {
- if (unlikely(float64_is_signaling_nan(farg.d))) {
+ if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
/* sNaN reciprocal square root */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
farg.ll = float64_snan_to_qnan(farg.ll);
@@ -942,7 +942,7 @@ uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(farg.d))) {
+ if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
/* sNaN reciprocal */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -958,7 +958,7 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(farg.d))) {
+ if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
/* sNaN reciprocal */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -977,7 +977,7 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
if (unlikely(float64_is_any_nan(farg.d))) {
- if (unlikely(float64_is_signaling_nan(farg.d))) {
+ if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
/* sNaN reciprocal square root */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
farg.ll = float64_snan_to_qnan(farg.ll);
@@ -1100,8 +1100,8 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
env->fpscr |= ret << FPSCR_FPRF;
env->crf[crfD] = ret;
if (unlikely(ret == 0x01UL
- && (float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d)))) {
+ && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
/* sNaN comparison */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
@@ -1131,8 +1131,8 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
env->fpscr |= ret << FPSCR_FPRF;
env->crf[crfD] = ret;
if (unlikely(ret == 0x01UL)) {
- if (float64_is_signaling_nan(farg1.d) ||
- float64_is_signaling_nan(farg2.d)) {
+ if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
+ float64_is_signaling_nan(farg2.d, &env->fp_status)) {
/* sNaN comparison */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
POWERPC_EXCP_FP_VXVC, 1);
@@ -1168,7 +1168,7 @@ static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(float32_is_quiet_nan(u.f))) {
+ if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
return 0;
}
@@ -1181,7 +1181,7 @@ static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(float32_is_quiet_nan(u.f))) {
+ if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
return 0;
}
@@ -1194,7 +1194,7 @@ static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(float32_is_quiet_nan(u.f))) {
+ if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
return 0;
}
@@ -1207,7 +1207,7 @@ static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(float32_is_quiet_nan(u.f))) {
+ if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
return 0;
}
@@ -1245,7 +1245,7 @@ static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(float32_is_quiet_nan(u.f))) {
+ if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
return 0;
}
tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
@@ -1261,7 +1261,7 @@ static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(float32_is_quiet_nan(u.f))) {
+ if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
return 0;
}
tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
@@ -1839,8 +1839,8 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
- } else if (tp##_is_signaling_nan(xa.fld) || \
- tp##_is_signaling_nan(xb.fld)) { \
+ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
+ tp##_is_signaling_nan(xb.fld, &tstat)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
} \
} \
@@ -1894,8 +1894,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \
(tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \
- } else if (tp##_is_signaling_nan(xa.fld) || \
- tp##_is_signaling_nan(xb.fld)) { \
+ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
+ tp##_is_signaling_nan(xb.fld, &tstat)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
} \
} \
@@ -1948,8 +1948,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} else if (tp##_is_zero(xa.fld) && \
tp##_is_zero(xb.fld)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
- } else if (tp##_is_signaling_nan(xa.fld) || \
- tp##_is_signaling_nan(xb.fld)) { \
+ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
+ tp##_is_signaling_nan(xb.fld, &tstat)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
} \
} \
@@ -1990,7 +1990,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
helper_reset_fpstatus(env); \
\
for (i = 0; i < nels; i++) { \
- if (unlikely(tp##_is_signaling_nan(xb.fld))) { \
+ if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
} \
xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \
@@ -2039,7 +2039,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
- } else if (tp##_is_signaling_nan(xb.fld)) { \
+ } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
} \
} \
@@ -2089,7 +2089,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
- } else if (tp##_is_signaling_nan(xb.fld)) { \
+ } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
} \
} \
@@ -2274,9 +2274,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- if (tp##_is_signaling_nan(xa.fld) || \
- tp##_is_signaling_nan(b->fld) || \
- tp##_is_signaling_nan(c->fld)) { \
+ if (tp##_is_signaling_nan(xa.fld, &tstat) || \
+ tp##_is_signaling_nan(b->fld, &tstat) || \
+ tp##_is_signaling_nan(c->fld, &tstat)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
tstat.float_exception_flags &= ~float_flag_invalid; \
} \
@@ -2358,8 +2358,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
\
if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
float64_is_any_nan(xb.VsrD(0)))) { \
- if (float64_is_signaling_nan(xa.VsrD(0)) || \
- float64_is_signaling_nan(xb.VsrD(0))) { \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
} \
if (ordered) { \
@@ -2406,8 +2406,8 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
\
for (i = 0; i < nels; i++) { \
xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \
- if (unlikely(tp##_is_signaling_nan(xa.fld) || \
- tp##_is_signaling_nan(xb.fld))) { \
+ if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) || \
+ tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
} \
} \
@@ -2446,8 +2446,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
for (i = 0; i < nels; i++) { \
if (unlikely(tp##_is_any_nan(xa.fld) || \
tp##_is_any_nan(xb.fld))) { \
- if (tp##_is_signaling_nan(xa.fld) || \
- tp##_is_signaling_nan(xb.fld)) { \
+ if (tp##_is_signaling_nan(xa.fld, &env->fp_status) || \
+ tp##_is_signaling_nan(xb.fld, &env->fp_status)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
} \
if (svxvc) { \
@@ -2500,7 +2500,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
\
for (i = 0; i < nels; i++) { \
xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
- if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
+ if (unlikely(stp##_is_signaling_nan(xb.sfld, \
+ &env->fp_status))) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
} \
@@ -2555,7 +2556,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
\
for (i = 0; i < nels; i++) { \
if (unlikely(stp##_is_any_nan(xb.sfld))) { \
- if (stp##_is_signaling_nan(xb.sfld)) { \
+ if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
} \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
@@ -2664,7 +2665,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
for (i = 0; i < nels; i++) { \
- if (unlikely(tp##_is_signaling_nan(xb.fld))) { \
+ if (unlikely(tp##_is_signaling_nan(xb.fld, \
+ &env->fp_status))) { \
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
xt.fld = tp##_snan_to_qnan(xb.fld); \
} else { \
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f515725..2f47854 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -573,6 +573,7 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
/* Altivec always uses round-to-nearest */
set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
set_flush_to_zero(vscr_nj, &env->vec_status);
+ set_snan_bit_is_one(0, &env->vec_status);
}
#ifdef CONFIG_USER_ONLY
@@ -9930,6 +9931,7 @@ static void ppc_cpu_reset(CPUState *s)
}
env->spr[i] = spr->default_value;
}
+ set_snan_bit_is_one(0, &env->fp_status);
/* Flush all TLBs */
tlb_flush(s, 1);
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 4bfff34..93a11d7 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -173,6 +173,7 @@ static void s390_cpu_full_reset(CPUState *s)
/* tininess for underflow is detected before rounding */
set_float_detect_tininess(float_tininess_before_rounding,
&env->fpu_status);
+ set_snan_bit_is_one(0, &env->fpu_status);
/* Reset state inside the kernel that we cannot access yet from QEMU. */
if (kvm_enabled()) {
diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
index 1c7f673..d527c98 100644
--- a/target-s390x/fpu_helper.c
+++ b/target-s390x/fpu_helper.c
@@ -266,7 +266,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2)
{
float64 ret = float32_to_float64(f2, &env->fpu_status);
handle_exceptions(env, GETPC());
- return float64_maybe_silence_nan(ret);
+ return float64_maybe_silence_nan(ret, &env->fpu_status);
}
/* convert 128-bit float to 64-bit float */
@@ -274,7 +274,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al)
{
float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status);
handle_exceptions(env, GETPC());
- return float64_maybe_silence_nan(ret);
+ return float64_maybe_silence_nan(ret, &env->fpu_status);
}
/* convert 64-bit float to 128-bit float */
@@ -282,7 +282,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2)
{
float128 ret = float64_to_float128(f2, &env->fpu_status);
handle_exceptions(env, GETPC());
- return RET128(float128_maybe_silence_nan(ret));
+ return RET128(float128_maybe_silence_nan(ret, &env->fpu_status));
}
/* convert 32-bit float to 128-bit float */
@@ -290,7 +290,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2)
{
float128 ret = float32_to_float128(f2, &env->fpu_status);
handle_exceptions(env, GETPC());
- return RET128(float128_maybe_silence_nan(ret));
+ return RET128(float128_maybe_silence_nan(ret, &env->fpu_status));
}
/* convert 64-bit float to 32-bit float */
@@ -298,7 +298,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2)
{
float32 ret = float64_to_float32(f2, &env->fpu_status);
handle_exceptions(env, GETPC());
- return float32_maybe_silence_nan(ret);
+ return float32_maybe_silence_nan(ret, &env->fpu_status);
}
/* convert 128-bit float to 32-bit float */
@@ -306,7 +306,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al)
{
float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status);
handle_exceptions(env, GETPC());
- return float32_maybe_silence_nan(ret);
+ return float32_maybe_silence_nan(ret, &env->fpu_status);
}
/* 32-bit FP compare */
@@ -623,7 +623,7 @@ uint64_t HELPER(msdb)(CPUS390XState *env, uint64_t f1,
}
/* test data class 32-bit */
-uint32_t HELPER(tceb)(uint64_t f1, uint64_t m2)
+uint32_t HELPER(tceb)(CPUS390XState *env, uint64_t f1, uint64_t m2)
{
float32 v1 = f1;
int neg = float32_is_neg(v1);
@@ -632,7 +632,8 @@ uint32_t HELPER(tceb)(uint64_t f1, uint64_t m2)
if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
(float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
(float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
- (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
+ (float32_is_signaling_nan(v1, &env->fpu_status) &&
+ (m2 & (1 << (1-neg))))) {
cc = 1;
} else if (m2 & (1 << (9-neg))) {
/* assume normalized number */
@@ -643,7 +644,7 @@ uint32_t HELPER(tceb)(uint64_t f1, uint64_t m2)
}
/* test data class 64-bit */
-uint32_t HELPER(tcdb)(uint64_t v1, uint64_t m2)
+uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, uint64_t m2)
{
int neg = float64_is_neg(v1);
uint32_t cc = 0;
@@ -651,7 +652,8 @@ uint32_t HELPER(tcdb)(uint64_t v1, uint64_t m2)
if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
(float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
(float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
- (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
+ (float64_is_signaling_nan(v1, &env->fpu_status) &&
+ (m2 & (1 << (1-neg))))) {
cc = 1;
} else if (m2 & (1 << (9-neg))) {
/* assume normalized number */
@@ -662,7 +664,8 @@ uint32_t HELPER(tcdb)(uint64_t v1, uint64_t m2)
}
/* test data class 128-bit */
-uint32_t HELPER(tcxb)(uint64_t ah, uint64_t al, uint64_t m2)
+uint32_t HELPER(tcxb)(CPUS390XState *env, uint64_t ah,
+ uint64_t al, uint64_t m2)
{
float128 v1 = make_float128(ah, al);
int neg = float128_is_neg(v1);
@@ -671,7 +674,8 @@ uint32_t HELPER(tcxb)(uint64_t ah, uint64_t al, uint64_t m2)
if ((float128_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
(float128_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
(float128_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
- (float128_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
+ (float128_is_signaling_nan(v1, &env->fpu_status) &&
+ (m2 & (1 << (1-neg))))) {
cc = 1;
} else if (m2 & (1 << (9-neg))) {
/* assume normalized number */
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index 7e06119..207a6e7 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -67,9 +67,9 @@ DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
-DEF_HELPER_FLAGS_2(tceb, TCG_CALL_NO_RWG_SE, i32, i64, i64)
-DEF_HELPER_FLAGS_2(tcdb, TCG_CALL_NO_RWG_SE, i32, i64, i64)
-DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_NO_RWG_SE, i32, i64, i64, i64)
+DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64)
+DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64)
+DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64)
DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index c871ef2..1dadcd7 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -3979,21 +3979,21 @@ static ExitStatus op_svc(DisasContext *s, DisasOps *o)
static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
{
- gen_helper_tceb(cc_op, o->in1, o->in2);
+ gen_helper_tceb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
return NO_EXIT;
}
static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
{
- gen_helper_tcdb(cc_op, o->in1, o->in2);
+ gen_helper_tcdb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
return NO_EXIT;
}
static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
{
- gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
+ gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2);
set_cc_static(s);
return NO_EXIT;
}
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 86ba388..60039ac 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -70,6 +70,7 @@ static void superh_cpu_reset(CPUState *s)
set_flush_to_zero(1, &env->fp_status);
#endif
set_default_nan_mode(1, &env->fp_status);
+ set_snan_bit_is_one(1, &env->fp_status);
}
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index fe4119e..1486a50 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -70,6 +70,7 @@ static void sparc_cpu_reset(CPUState *s)
env->npc = env->pc + 4;
#endif
env->cache_control = 0;
+ set_snan_bit_is_one(0, &env->fp_status);
}
static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index 71b31cd..e4eaec6 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -116,6 +116,7 @@ void fpu_set_state(CPUTriCoreState *env)
set_flush_inputs_to_zero(1, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
set_default_nan_mode(1, &env->fp_status);
+ set_snan_bit_is_one(0, &env->fp_status);
}
uint32_t psw_read(CPUTriCoreState *env)
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 66f43ac..1138687 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -77,6 +77,7 @@ static void unicore_ii_cpu_initfn(Object *obj)
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
+ set_snan_bit_is_one(1, &env->ucf64.fp_status);
}
static void uc32_any_cpu_initfn(Object *obj)
@@ -89,6 +90,7 @@ static void uc32_any_cpu_initfn(Object *obj)
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
+ set_snan_bit_is_one(1, &env->ucf64.fp_status);
}
static const UniCore32CPUInfo uc32_cpus[] = {
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 01b251f..0bb17b7 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -72,6 +72,9 @@ static void xtensa_cpu_reset(CPUState *s)
env->sregs[CONFIGID1] = env->config->configid[1];
env->pending_irq_level = 0;
+
+ set_snan_bit_is_one(0, &env->fp_status);
+
reset_mmu(env);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-13 12:23 ` Leon Alrae
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd() Aleksandar Markovic
` (6 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).
For more info, see [1], page 84, Table 6.3 "Value Supplied When
a New Quiet NaN Is Created", and [2], page 52, table 3.7 "Default
NaN Encodings".
[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
fpu/softfloat-specialize.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 53dae9b..169246e 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
if (status->snan_bit_is_one) {
return const_float16(0x7DFF);
} else {
+#if defined(TARGET_MIPS)
+ return const_float16(0x7E00);
+#else
return const_float16(0xFE00);
+#endif
}
#endif
}
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
if (status->snan_bit_is_one) {
return const_float32(0x7FBFFFFF);
} else {
+#if defined(TARGET_MIPS)
+ return const_float32(0x7FC00000);
+#else
return const_float32(0xFFC00000);
+#endif
}
#endif
}
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
if (status->snan_bit_is_one) {
return const_float64(LIT64( 0x7FF7FFFFFFFFFFFF ));
} else {
+#if defined(TARGET_MIPS)
+ return const_float64(LIT64( 0x7FF8000000000000 ));
+#else
return const_float64(LIT64( 0xFFF8000000000000 ));
+#endif
}
#endif
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-13 12:47 ` Leon Alrae
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 4/9] softfloat: Clean up hex constants capitalization in softfloat-specialize.h Aleksandar Markovic
` (5 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().
For more info, see [2], page 53, section "3.5.3 NaN Propagation".
[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
fpu/softfloat-specialize.h | 41 +++++++++++++++++++++++++++++------------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 169246e..807ecc0 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
return 3;
}
- /* Prefer sNaN over qNaN, in the c, a, b order. */
- if (cIsSNaN) {
- return 2;
- } else if (aIsSNaN) {
- return 0;
- } else if (bIsSNaN) {
- return 1;
- } else if (cIsQNaN) {
- return 2;
- } else if (aIsQNaN) {
- return 0;
+ if (status->snan_bit_is_one) {
+ /* Prefer sNaN over qNaN, in the a, b, c order. */
+ if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (cIsSNaN) {
+ return 2;
+ } else if (aIsQNaN) {
+ return 0;
+ } else if (bIsQNaN) {
+ return 1;
+ } else {
+ return 2;
+ }
} else {
- return 1;
+ /* Prefer sNaN over qNaN, in the c, a, b order. */
+ if (cIsSNaN) {
+ return 2;
+ } else if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (cIsQNaN) {
+ return 2;
+ } else if (aIsQNaN) {
+ return 0;
+ } else {
+ return 1;
+ }
}
}
#elif defined(TARGET_PPC)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 4/9] softfloat: Clean up hex constants capitalization in softfloat-specialize.h
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
` (2 preceding siblings ...)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd() Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 5/9] softfloat: Clean up white spaces " Aleksandar Markovic
` (4 subsequent siblings)
8 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
With this partch, capitals A, B, C, D, E, F are always used for hex
constants in softfloat-specialize.h. The large latter size is chosen
just beacause it is currently prevalent in this file.
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
fpu/softfloat-specialize.h | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 807ecc0..a5680e0 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -230,7 +230,7 @@ int float16_is_quiet_nan(float16 a_, float_status *status)
if (status->snan_bit_is_one) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
} else {
- return ((a & ~0x8000) >= 0x7c80);
+ return ((a & ~0x8000) >= 0x7C80);
}
}
@@ -243,7 +243,7 @@ int float16_is_signaling_nan(float16 a_, float_status *status)
{
uint16_t a = float16_val(a_);
if (status->snan_bit_is_one) {
- return ((a & ~0x8000) >= 0x7c80);
+ return ((a & ~0x8000) >= 0x7C80);
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
}
@@ -328,9 +328,9 @@ int float32_is_quiet_nan( float32 a_, float_status *status )
{
uint32_t a = float32_val(a_);
if (status->snan_bit_is_one) {
- return (((a >> 22) & 0x1ff) == 0x1fe) && (a & 0x003fffff);
+ return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
} else {
- return ((uint32_t)(a << 1) >= 0xff800000);
+ return ((uint32_t)(a << 1) >= 0xFF800000);
}
}
@@ -343,7 +343,7 @@ int float32_is_signaling_nan( float32 a_, float_status *status )
{
uint32_t a = float32_val(a_);
if (status->snan_bit_is_one) {
- return ((uint32_t)(a << 1) >= 0xff800000);
+ return ((uint32_t)(a << 1) >= 0xFF800000);
} else {
return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
}
@@ -758,10 +758,10 @@ int float64_is_quiet_nan( float64 a_, float_status *status)
{
uint64_t a = float64_val(a_);
if (status->snan_bit_is_one) {
- return (((a >> 51) & 0xfff) == 0xffe)
- && (a & 0x0007ffffffffffffULL);
+ return (((a >> 51) & 0xFFF) == 0xFFE)
+ && (a & 0x0007FFFFFFFFFFFFULL);
} else {
- return ((a << 1) >= 0xfff0000000000000ULL);
+ return ((a << 1) >= 0xFFF0000000000000ULL);
}
}
@@ -774,7 +774,7 @@ int float64_is_signaling_nan( float64 a_, float_status *status )
{
uint64_t a = float64_val(a_);
if (status->snan_bit_is_one) {
- return ((a << 1) >= 0xfff0000000000000ULL);
+ return ((a << 1) >= 0xFFF0000000000000ULL);
} else {
return
( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
@@ -961,7 +961,7 @@ int floatx80_is_quiet_nan( floatx80 a, float_status *status )
uint64_t aLow;
aLow = a.low & ~0x4000000000000000ULL;
- return ((a.high & 0x7fff) == 0x7fff)
+ return ((a.high & 0x7FFF) == 0x7FFF)
&& (aLow << 1)
&& (a.low == aLow);
} else {
@@ -979,7 +979,7 @@ int floatx80_is_quiet_nan( floatx80 a, float_status *status )
int floatx80_is_signaling_nan( floatx80 a, float_status *status )
{
if (status->snan_bit_is_one) {
- return ((a.high & 0x7fff) == 0x7fff)
+ return ((a.high & 0x7FFF) == 0x7FFF)
&& ((a.low << 1) >= 0x8000000000000000ULL);
} else {
uint64_t aLow;
@@ -1120,12 +1120,12 @@ int float128_is_signaling_nan(float128 a_, float_status *status)
int float128_is_quiet_nan( float128 a, float_status *status )
{
if (status->snan_bit_is_one) {
- return (((a.high >> 47) & 0xffff) == 0xfffe)
- && (a.low || (a.high & 0x00007fffffffffffULL));
+ return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
+ && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
} else {
return
- ((a.high << 1) >= 0xffff000000000000ULL)
- && (a.low || (a.high & 0x0000ffffffffffffULL));
+ ((a.high << 1) >= 0xFFFF000000000000ULL)
+ && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
}
}
@@ -1138,8 +1138,8 @@ int float128_is_signaling_nan( float128 a, float_status *status )
{
if (status->snan_bit_is_one) {
return
- ((a.high << 1) >= 0xffff000000000000ULL)
- && (a.low || (a.high & 0x0000ffffffffffffULL));
+ ((a.high << 1) >= 0xFFFF000000000000ULL)
+ && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
} else {
return
( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 5/9] softfloat: Clean up white spaces in softfloat-specialize.h
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
` (3 preceding siblings ...)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 4/9] softfloat: Clean up hex constants capitalization in softfloat-specialize.h Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 6/9] target-mips: Activate IEEE 274-2008 support Aleksandar Markovic
` (3 subsequent siblings)
8 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
As the development of SoftFloat library took places, many contributors
had different code styles, and the code was left with inconsistent style,
difficult to read, and hard to maintain.
This patch will make spaces around shift operators and braces consistent
within file fpu/softfloat-specialize.h.
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
fpu/softfloat-specialize.h | 94 ++++++++++++++++++++++----------------------
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index a5680e0..aa2f793 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -283,7 +283,7 @@ static commonNaNT float16ToCommonNaN(float16 a, float_status *status)
}
z.sign = float16_val(a) >> 15;
z.low = 0;
- z.high = ((uint64_t) float16_val(a))<<54;
+ z.high = ((uint64_t) float16_val(a)) << 54;
return z;
}
@@ -345,7 +345,7 @@ int float32_is_signaling_nan( float32 a_, float_status *status )
if (status->snan_bit_is_one) {
return ((uint32_t)(a << 1) >= 0xFF800000);
} else {
- return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
+ return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
}
}
#endif
@@ -382,9 +382,9 @@ static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
if (float32_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
- z.sign = float32_val(a)>>31;
+ z.sign = float32_val(a) >> 31;
z.low = 0;
- z.high = ( (uint64_t) float32_val(a) )<<41;
+ z.high = ((uint64_t)float32_val(a)) << 41;
return z;
}
@@ -395,7 +395,7 @@ static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
{
- uint32_t mantissa = a.high>>41;
+ uint32_t mantissa = a.high >> 41;
if (status->default_nan_mode) {
return float32_default_nan(status);
@@ -403,7 +403,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
if ( mantissa ) {
return make_float32(
- ( ( (uint32_t) a.sign )<<31 ) | 0x7F800000 | ( a.high>>41 ) );
+ (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
} else {
return float32_default_nan(status);
}
@@ -656,10 +656,10 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
flag aIsLargerSignificand;
uint32_t av, bv;
- aIsQuietNaN = float32_is_quiet_nan( a, status );
- aIsSignalingNaN = float32_is_signaling_nan( a, status );
- bIsQuietNaN = float32_is_quiet_nan( b, status );
- bIsSignalingNaN = float32_is_signaling_nan( b, status );
+ aIsQuietNaN = float32_is_quiet_nan(a, status);
+ aIsSignalingNaN = float32_is_signaling_nan(a, status);
+ bIsQuietNaN = float32_is_quiet_nan(b, status);
+ bIsSignalingNaN = float32_is_signaling_nan(b, status);
av = float32_val(a);
bv = float32_val(b);
@@ -670,9 +670,9 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
if (status->default_nan_mode)
return float32_default_nan(status);
- if ((uint32_t)(av<<1) < (uint32_t)(bv<<1)) {
+ if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
aIsLargerSignificand = 0;
- } else if ((uint32_t)(bv<<1) < (uint32_t)(av<<1)) {
+ } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
aIsLargerSignificand = 1;
} else {
aIsLargerSignificand = (av < bv) ? 1 : 0;
@@ -777,8 +777,8 @@ int float64_is_signaling_nan( float64 a_, float_status *status )
return ((a << 1) >= 0xFFF0000000000000ULL);
} else {
return
- ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
- && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
+ (((a >> 51) & 0xFFF) == 0xFFE)
+ && (a & LIT64( 0x0007FFFFFFFFFFFF ));
}
}
#endif
@@ -815,9 +815,9 @@ static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
if (float64_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
- z.sign = float64_val(a)>>63;
+ z.sign = float64_val(a) >> 63;
z.low = 0;
- z.high = float64_val(a)<<12;
+ z.high = float64_val(a) << 12;
return z;
}
@@ -828,7 +828,7 @@ static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
{
- uint64_t mantissa = a.high>>12;
+ uint64_t mantissa = a.high >> 12;
if (status->default_nan_mode) {
return float64_default_nan(status);
@@ -836,9 +836,9 @@ static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
if ( mantissa ) {
return make_float64(
- ( ( (uint64_t) a.sign )<<63 )
+ (((uint64_t)a.sign) << 63)
| LIT64( 0x7FF0000000000000 )
- | ( a.high>>12 ));
+ | (a.high >> 12));
} else {
return float64_default_nan(status);
}
@@ -856,10 +856,10 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
flag aIsLargerSignificand;
uint64_t av, bv;
- aIsQuietNaN = float64_is_quiet_nan( a, status );
- aIsSignalingNaN = float64_is_signaling_nan( a, status );
- bIsQuietNaN = float64_is_quiet_nan( b, status );
- bIsSignalingNaN = float64_is_signaling_nan( b, status );
+ aIsQuietNaN = float64_is_quiet_nan(a, status);
+ aIsSignalingNaN = float64_is_signaling_nan(a, status);
+ bIsQuietNaN = float64_is_quiet_nan(b, status);
+ bIsSignalingNaN = float64_is_signaling_nan(b, status);
av = float64_val(a);
bv = float64_val(b);
@@ -870,9 +870,9 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
if (status->default_nan_mode)
return float64_default_nan(status);
- if ((uint64_t)(av<<1) < (uint64_t)(bv<<1)) {
+ if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
aIsLargerSignificand = 0;
- } else if ((uint64_t)(bv<<1) < (uint64_t)(av<<1)) {
+ } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
aIsLargerSignificand = 1;
} else {
aIsLargerSignificand = (av < bv) ? 1 : 0;
@@ -965,8 +965,8 @@ int floatx80_is_quiet_nan( floatx80 a, float_status *status )
&& (aLow << 1)
&& (a.low == aLow);
} else {
- return ( ( a.high & 0x7FFF ) == 0x7FFF )
- && (LIT64( 0x8000000000000000 ) <= ((uint64_t) ( a.low<<1 )));
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (LIT64( 0x8000000000000000 ) <= ((uint64_t)(a.low << 1)));
}
}
@@ -986,9 +986,9 @@ int floatx80_is_signaling_nan( floatx80 a, float_status *status )
aLow = a.low & ~ LIT64( 0x4000000000000000 );
return
- ( ( a.high & 0x7FFF ) == 0x7FFF )
- && (uint64_t) ( aLow<<1 )
- && ( a.low == aLow );
+ ((a.high & 0x7FFF) == 0x7FFF)
+ && (uint64_t)(aLow << 1)
+ && (a.low == aLow);
}
}
#endif
@@ -1053,7 +1053,7 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
if (a.high >> 1) {
z.low = LIT64( 0x8000000000000000 ) | a.high >> 1;
- z.high = ( ( (uint16_t) a.sign )<<15 ) | 0x7FFF;
+ z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
} else {
z = floatx80_default_nan(status);
}
@@ -1072,10 +1072,10 @@ static floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b,
flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
flag aIsLargerSignificand;
- aIsQuietNaN = floatx80_is_quiet_nan( a, status );
- aIsSignalingNaN = floatx80_is_signaling_nan( a, status );
- bIsQuietNaN = floatx80_is_quiet_nan( b, status );
- bIsSignalingNaN = floatx80_is_signaling_nan( b, status );
+ aIsQuietNaN = floatx80_is_quiet_nan(a, status);
+ aIsSignalingNaN = floatx80_is_signaling_nan(a, status);
+ bIsQuietNaN = floatx80_is_quiet_nan(b, status);
+ bIsSignalingNaN = floatx80_is_signaling_nan(b, status);
if (aIsSignalingNaN | bIsSignalingNaN) {
float_raise(float_flag_invalid, status);
@@ -1142,8 +1142,8 @@ int float128_is_signaling_nan( float128 a, float_status *status )
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
} else {
return
- ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
- && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
+ (((a.high >> 47) & 0xFFFF) == 0xFFFE)
+ && (a.low || (a.high & LIT64( 0x00007FFFFFFFFFFF )));
}
}
#endif
@@ -1179,8 +1179,8 @@ static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
if (float128_is_signaling_nan(a, status)) {
float_raise(float_flag_invalid, status);
}
- z.sign = a.high>>63;
- shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
+ z.sign = a.high >> 63;
+ shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
return z;
}
@@ -1197,8 +1197,8 @@ static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
return float128_default_nan(status);
}
- shift128Right( a.high, a.low, 16, &z.high, &z.low );
- z.high |= ( ( (uint64_t) a.sign )<<63 ) | LIT64( 0x7FFF000000000000 );
+ shift128Right(a.high, a.low, 16, &z.high, &z.low);
+ z.high |= (((uint64_t)a.sign) << 63) | LIT64( 0x7FFF000000000000 );
return z;
}
@@ -1214,10 +1214,10 @@ static float128 propagateFloat128NaN(float128 a, float128 b,
flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
flag aIsLargerSignificand;
- aIsQuietNaN = float128_is_quiet_nan( a, status );
- aIsSignalingNaN = float128_is_signaling_nan( a, status );
- bIsQuietNaN = float128_is_quiet_nan( b, status );
- bIsSignalingNaN = float128_is_signaling_nan( b, status );
+ aIsQuietNaN = float128_is_quiet_nan(a, status);
+ aIsSignalingNaN = float128_is_signaling_nan(a, status);
+ bIsQuietNaN = float128_is_quiet_nan(b, status);
+ bIsSignalingNaN = float128_is_signaling_nan(b, status);
if (aIsSignalingNaN | bIsSignalingNaN) {
float_raise(float_flag_invalid, status);
@@ -1227,9 +1227,9 @@ static float128 propagateFloat128NaN(float128 a, float128 b,
return float128_default_nan(status);
}
- if (lt128(a.high<<1, a.low, b.high<<1, b.low)) {
+ if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
aIsLargerSignificand = 0;
- } else if (lt128(b.high<<1, b.low, a.high<<1, a.low)) {
+ } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
aIsLargerSignificand = 1;
} else {
aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 6/9] target-mips: Activate IEEE 274-2008 support
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
` (4 preceding siblings ...)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 5/9] softfloat: Clean up white spaces " Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> Aleksandar Markovic
` (2 subsequent siblings)
8 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
1) Definitions of Mips processors are updated to reflect supported
IEEE-754-2008-related features. (file target-mips/translate_init.c)
2) Functions mips_cpu_reset() and msa_reset() are updated so that flag
snan_bit_is_one is properly set for any Mips configuration.
(file target-mips/translate_init.c)
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
target-mips/translate.c | 6 +++++-
target-mips/translate_init.c | 18 +++++++++++++++---
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 496216d..de0b224 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
- set_snan_bit_is_one(1, &env->active_fpu.fp_status);
+ if ((env->active_fpu.fcr31 >> FCR31_NAN2008) & 1) {
+ set_snan_bit_is_one(0, &env->active_fpu.fp_status);
+ } else {
+ set_snan_bit_is_one(1, &env->active_fpu.fp_status);
+ }
env->msair = env->cpu_model->MSAIR;
env->insn_flags = env->cpu_model->insn_flags;
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index e81a831..878fef6 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -273,6 +273,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x3678FF1F,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr31 = 0,
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
@@ -303,6 +304,7 @@ static const mips_def_t mips_defs[] =
(0xff << CP0TCSt_TASID),
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
+ .CP1_fcr31 = 0,
.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
.CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
@@ -343,6 +345,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x3778FF1F,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr31 = 0,
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
@@ -434,7 +437,7 @@ static const mips_def_t mips_defs[] =
},
{
/* A generic CPU supporting MIPS32 Release 6 ISA.
- FIXME: Support IEEE 754-2008 FP.
+ FIXME: Complete support for IEEE 754-2008 FP.
Eventually this should be replaced by a real CPU model. */
.name = "mips32r6-generic",
.CP0_PRid = 0x00010000,
@@ -485,6 +488,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x3678FFFF,
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 40,
.PABITS = 36,
.insn_flags = CPU_MIPS3,
@@ -503,6 +507,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x3678FFFF,
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 40,
.PABITS = 32,
.insn_flags = CPU_VR54XX,
@@ -548,6 +553,7 @@ static const mips_def_t mips_defs[] =
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64,
@@ -575,6 +581,7 @@ static const mips_def_t mips_defs[] =
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_D) | (1 << FCR0_S) |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 40,
.PABITS = 36,
.insn_flags = CPU_MIPS64 | ASE_MIPS3D,
@@ -601,6 +608,7 @@ static const mips_def_t mips_defs[] =
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
@@ -653,7 +661,7 @@ static const mips_def_t mips_defs[] =
},
{
/* A generic CPU supporting MIPS64 Release 6 ISA.
- FIXME: Support IEEE 754-2008 FP.
+ FIXME: Complete support for IEEE 754-2008 FP.
Eventually this should be replaced by a real CPU model. */
.name = "MIPS64R6-generic",
.CP0_PRid = 0x00010000,
@@ -704,6 +712,7 @@ static const mips_def_t mips_defs[] =
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x35D0FFFF,
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 40,
.PABITS = 40,
.insn_flags = CPU_LOONGSON2E,
@@ -722,6 +731,7 @@ static const mips_def_t mips_defs[] =
.CCRes = 2,
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 40,
.PABITS = 40,
.insn_flags = CPU_LOONGSON2F,
@@ -749,6 +759,7 @@ static const mips_def_t mips_defs[] =
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
@@ -893,5 +904,6 @@ static void msa_reset(CPUMIPSState *env)
/* clear float_status nan mode */
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
- set_snan_bit_is_one(1, &env->active_tc.msa_fp_status);
+ /* one in signaling nan bit means nan is quiet */
+ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
` (5 preceding siblings ...)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 6/9] target-mips: Activate IEEE 274-2008 support Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-14 10:52 ` Leon Alrae
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 9/9] target-mips: Clean up order of helpers for CVT.<L|W>.<S|D> Aleksandar Markovic
8 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (any NaN operand
signals invalid operation), while abs2008 ones are non-arithmetic, always
changing the sign bit, even for NaN-like operands. Details on these
instructions are documented in [1] p. 35 and 359.
[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
target-mips/translate.c | 27 +++++++++++++++++++++++----
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index de0b224..1d376fc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,8 @@ typedef struct DisasContext {
bool vp;
bool cmgcr;
bool mrp;
+ bool abs2008;
+
} DisasContext;
enum {
@@ -8879,7 +8881,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_abs_s(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
+ } else {
+ gen_helper_float_abs_s(fp0, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -8898,7 +8904,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_chs_s(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+ } else {
+ gen_helper_float_chs_s(fp0, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -9369,7 +9379,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_abs_d(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
+ } else {
+ gen_helper_float_abs_d(fp0, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -9390,7 +9404,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_chs_d(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+ } else {
+ gen_helper_float_chs_d(fp0, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -19775,6 +19793,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
` (6 preceding siblings ...)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 9/9] target-mips: Clean up order of helpers for CVT.<L|W>.<S|D> Aleksandar Markovic
8 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>. Details on these instructions
are presented in [1] p. 129, 130, 149, 155, 222, 223, 393, 394, 504, 505.
[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
target-mips/helper.h | 18 +--
target-mips/op_helper.c | 334 ++++++++++++++++++++++++++++++++++++++++++++---
target-mips/translate.c | 123 ++++++++++++++---
3 files changed, 426 insertions(+), 49 deletions(-)
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 133dcfb..61bbda7 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
DEF_HELPER_2(float_cvtd_l, i64, env, i64)
-DEF_HELPER_2(float_cvtl_d, i64, env, i64)
-DEF_HELPER_2(float_cvtl_s, i64, env, i32)
DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
DEF_HELPER_2(float_cvts_d, i32, env, i64)
@@ -216,8 +214,6 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
DEF_HELPER_2(float_cvts_l, i32, env, i64)
DEF_HELPER_2(float_cvts_pl, i32, env, i32)
DEF_HELPER_2(float_cvts_pu, i32, env, i32)
-DEF_HELPER_2(float_cvtw_s, i32, env, i32)
-DEF_HELPER_2(float_cvtw_d, i32, env, i64)
DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
@@ -242,14 +238,20 @@ FOP_PROTO(mina)
#undef FOP_PROTO
#define FOP_PROTO(op) \
-DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
-DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
-DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
-DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
+DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
+FOP_PROTO(cvt)
FOP_PROTO(round)
FOP_PROTO(trunc)
FOP_PROTO(ceil)
FOP_PROTO(floor)
+FOP_PROTO(cvt_2008)
+FOP_PROTO(round_2008)
+FOP_PROTO(trunc_2008)
+FOP_PROTO(ceil_2008)
+FOP_PROTO(floor_2008)
#undef FOP_PROTO
#define FOP_PROTO(op) \
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ce7ec9c..841f066 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2448,9 +2448,19 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#define FLOAT_TWO32 make_float32(1 << 30)
#define FLOAT_TWO64 make_float64(1ULL << 62)
+
#define FP_TO_INT32_OVERFLOW 0x7fffffff
#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
+#define FLT_TO_INT32_OVERFLOW(x) \
+ float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define FLT_TO_INT64_OVERFLOW(x) \
+ float32_is_any_nan(x) ? 0 : (float32_is_neg(x) ? INT64_MIN : INT64_MAX)
+#define DBL_TO_INT32_OVERFLOW(x) \
+ float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT32_MIN : INT32_MAX)
+#define DBL_TO_INT64_OVERFLOW(x) \
+ float64_is_any_nan(x) ? 0 : (float64_is_neg(x) ? INT64_MIN : INT64_MAX)
+
/* convert MIPS rounding mode in FCR31 to IEEE library */
unsigned int ieee_rm[] = {
float_round_nearest_even,
@@ -2683,7 +2693,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
return fdt2;
}
-uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2696,7 +2706,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
return dt2;
}
-uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2791,7 +2801,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
return wt2;
}
-uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2804,7 +2814,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
return wt2;
}
-uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2817,7 +2827,7 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
return wt2;
}
-uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2832,7 +2842,7 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
return dt2;
}
-uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2847,7 +2857,7 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
return dt2;
}
-uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2862,7 +2872,7 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
return wt2;
}
-uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2877,7 +2887,7 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
return wt2;
}
-uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2890,7 +2900,7 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
return dt2;
}
-uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2903,7 +2913,7 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
return dt2;
}
-uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2916,7 +2926,7 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
return wt2;
}
-uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2929,7 +2939,7 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
return wt2;
}
-uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2944,7 +2954,7 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
return dt2;
}
-uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2959,7 +2969,7 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
return dt2;
}
-uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2974,7 +2984,7 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
return wt2;
}
-uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2989,7 +2999,7 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
return wt2;
}
-uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
+uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -3004,7 +3014,7 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
return dt2;
}
-uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -3019,7 +3029,7 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
return dt2;
}
-uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -3034,7 +3044,7 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
return wt2;
}
-uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
+uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -3049,6 +3059,290 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
return wt2;
}
+uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint64_t dt2;
+
+ dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = DBL_TO_INT64_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint64_t dt2;
+
+ dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FLT_TO_INT64_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint32_t wt2;
+
+ wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = DBL_TO_INT32_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint32_t wt2;
+
+ wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = FLT_TO_INT32_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint64_t dt2;
+
+ set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = DBL_TO_INT64_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint64_t dt2;
+
+ set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FLT_TO_INT64_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint32_t wt2;
+
+ set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = DBL_TO_INT32_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint32_t wt2;
+
+ set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = FLT_TO_INT32_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint64_t dt2;
+
+ dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = DBL_TO_INT64_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint64_t dt2;
+
+ dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FLT_TO_INT64_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint32_t wt2;
+
+ wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = DBL_TO_INT32_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint32_t wt2;
+
+ wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = FLT_TO_INT32_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint64_t dt2;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = DBL_TO_INT64_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint64_t dt2;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FLT_TO_INT64_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint32_t wt2;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = DBL_TO_INT32_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint32_t wt2;
+
+ set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+ wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = FLT_TO_INT32_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint64_t dt2;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = DBL_TO_INT64_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint64_t dt2;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FLT_TO_INT64_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint32_t wt2;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = DBL_TO_INT32_OVERFLOW(fdt0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint32_t wt2;
+
+ set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+ wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
+ restore_rounding_mode(env);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ wt2 = FLT_TO_INT32_OVERFLOW(fst0);
+ }
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
/* unary operations, not modifying fp status */
#define FLOAT_UNOP(name) \
uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1d376fc..9f921aa 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,8 +1434,8 @@ typedef struct DisasContext {
bool vp;
bool cmgcr;
bool mrp;
+ bool nan2008;
bool abs2008;
-
} DisasContext;
enum {
@@ -8920,7 +8920,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_roundl_s(fp64, cpu_env, fp32);
+ if (ctx->nan2008) {
+ gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
+ } else {
+ gen_helper_float_round_l_s(fp64, cpu_env, fp32);
+ }
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -8933,7 +8937,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_truncl_s(fp64, cpu_env, fp32);
+ if (ctx->nan2008) {
+ gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
+ } else {
+ gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
+ }
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -8946,7 +8954,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_ceill_s(fp64, cpu_env, fp32);
+ if (ctx->nan2008) {
+ gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
+ } else {
+ gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
+ }
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -8959,7 +8971,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_floorl_s(fp64, cpu_env, fp32);
+ if (ctx->nan2008) {
+ gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
+ } else {
+ gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
+ }
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -8970,7 +8986,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_roundw_s(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_round_w_s(fp0, cpu_env, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -8980,7 +9000,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_truncw_s(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -8990,7 +9014,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_ceilw_s(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -9000,7 +9028,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_floorw_s(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -9249,7 +9281,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_cvtw_s(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -9261,7 +9297,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_cvtl_s(fp64, cpu_env, fp32);
+ if (ctx->nan2008) {
+ gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
+ } else {
+ gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
+ }
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -9419,7 +9459,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_roundl_d(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_round_l_d(fp0, cpu_env, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -9430,7 +9474,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_truncl_d(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -9441,7 +9489,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_ceill_d(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -9452,7 +9504,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_floorl_d(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -9464,7 +9520,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_roundw_d(fp32, cpu_env, fp64);
+ if (ctx->nan2008) {
+ gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
+ } else {
+ gen_helper_float_round_w_d(fp32, cpu_env, fp64);
+ }
tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
tcg_temp_free_i32(fp32);
@@ -9477,7 +9537,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_truncw_d(fp32, cpu_env, fp64);
+ if (ctx->nan2008) {
+ gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
+ } else {
+ gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
+ }
tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
tcg_temp_free_i32(fp32);
@@ -9490,7 +9554,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_ceilw_d(fp32, cpu_env, fp64);
+ if (ctx->nan2008) {
+ gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
+ } else {
+ gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
+ }
tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
tcg_temp_free_i32(fp32);
@@ -9503,7 +9571,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_floorw_d(fp32, cpu_env, fp64);
+ if (ctx->nan2008) {
+ gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
+ } else {
+ gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
+ }
tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
tcg_temp_free_i32(fp32);
@@ -9776,7 +9848,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvtw_d(fp32, cpu_env, fp64);
+ if (ctx->nan2008) {
+ gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
+ } else {
+ gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
+ }
tcg_temp_free_i64(fp64);
gen_store_fpr32(ctx, fp32, fd);
tcg_temp_free_i32(fp32);
@@ -9788,7 +9864,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtl_d(fp0, cpu_env, fp0);
+ if (ctx->nan2008) {
+ gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
+ } else {
+ gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -19793,6 +19873,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v4 9/9] target-mips: Clean up order of helpers for CVT.<L|W>.<S|D>
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
` (7 preceding siblings ...)
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> Aleksandar Markovic
@ 2016-04-12 12:58 ` Aleksandar Markovic
8 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-12 12:58 UTC (permalink / raw)
To: qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, leon.alrae,
afaerber, aurelien, rth, maciej.rozycki
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
This patch makes position of helpers for CVT.<L|W>.<S|D> consistent with
position of helpers for <CEIL|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>.
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
target-mips/op_helper.c | 60 +++++++++++++++++++++++------------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 841f066..6b3d5bd 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2693,32 +2693,6 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
return fdt2;
}
-uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
-{
- uint64_t dt2;
-
- dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
- if (get_float_exception_flags(&env->active_fpu.fp_status)
- & (float_flag_invalid | float_flag_overflow)) {
- dt2 = FP_TO_INT64_OVERFLOW;
- }
- update_fcr31(env, GETPC());
- return dt2;
-}
-
-uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
-{
- uint64_t dt2;
-
- dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
- if (get_float_exception_flags(&env->active_fpu.fp_status)
- & (float_flag_invalid | float_flag_overflow)) {
- dt2 = FP_TO_INT64_OVERFLOW;
- }
- update_fcr31(env, GETPC());
- return dt2;
-}
-
uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
{
uint32_t fst2;
@@ -2801,11 +2775,37 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
return wt2;
}
-uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
+uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
+{
+ uint64_t dt2;
+
+ dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
+{
+ uint64_t dt2;
+
+ dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
+ dt2 = FP_TO_INT64_OVERFLOW;
+ }
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
- wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
+ wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
if (get_float_exception_flags(&env->active_fpu.fp_status)
& (float_flag_invalid | float_flag_overflow)) {
wt2 = FP_TO_INT32_OVERFLOW;
@@ -2814,11 +2814,11 @@ uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
return wt2;
}
-uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
+uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
- wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
+ wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
if (get_float_exception_flags(&env->active_fpu.fp_status)
& (float_flag_invalid | float_flag_overflow)) {
wt2 = FP_TO_INT32_OVERFLOW;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
@ 2016-04-12 18:45 ` Eduardo Habkost
2016-04-13 18:41 ` Aleksandar Markovic
2016-04-13 12:11 ` Leon Alrae
2016-04-14 15:31 ` Leon Alrae
2 siblings, 1 reply; 23+ messages in thread
From: Eduardo Habkost @ 2016-04-12 18:45 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: qemu-devel, proljc, kbastian, mark.cave-ayland, agraf,
maciej.rozycki, petar.jovanovic, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, edgar.iglesias,
miodrag.dinic, pbonzini, gxt, leon.alrae, afaerber, aurelien,
rth
On Tue, Apr 12, 2016 at 02:58:03PM +0200, Aleksandar Markovic wrote:
[...]
> 4) Updated code for all platforms to reflect changes in SoftFloat library.
> This change is twofolds: it includes modifications of SoftFloat library
> functions invocations, and an addition of invocation of function
> set_snan_bit_is_one() during CPU initialization, with arguments that
> are appropriate for each particular platform.
>
> In order to be at the same time accurate in relation to floating point
> arithmetics and consistent with a particular platform code, following
> principle is adopted related to invocations of new function
> set_snan_bit_is_one():
>
> 1. If a target platform doesn't use SoftFloat library, nothing is added.
> (cris, lm32, moxie)
> 2. Else, if a target platform's signaling bit meaning is "1 is
> signaling", explicit invocation of set_snan_bit_is_one(1) is added.
> (mips, sh4, unicore32)
> (for mips this will change in the second patch of this
> series, but this very patch leaves mips features as
> they currently are.)
> 3. Else, if a target platform explicitly sets other fields of its
> float_status structure(s), explicit invocation of
> set_snan_bit_is_one(0) is added.
> (ppc, s390x, tricore)
> 4. Else, if a target platform doesn't explicitly set its structure
> CPUXXXState, explicit invocation of set_snan_bit_is_one(0) is added.
> (alpha, xtensa)
The CPU struct is zeroed by object_new() when the CPU object is
created, so the field is already set to 0 by default on all
architectures. You shouldn't need set_snan_bit_is_one(0) calls on
CPU initialization on any architecture.
> 5. For remaining cases, nothing is added. (Those cases explicitly set
> their CPUXXXState/float_status structures to 0, and thus implicitly
> perform set_snan_bit_is_one(0).)
> (arm, i386, m68k, microblaze, openrisc, sparc)
>
--
Eduardo
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
2016-04-12 18:45 ` Eduardo Habkost
@ 2016-04-13 12:11 ` Leon Alrae
2016-04-14 15:31 ` Leon Alrae
2 siblings, 0 replies; 23+ messages in thread
From: Leon Alrae @ 2016-04-13 12:11 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, afaerber, aurelien,
rth, maciej.rozycki
On 12/04/16 13:58, Aleksandar Markovic wrote:
> @@ -322,14 +327,14 @@ int float32_is_quiet_nan( float32 a_ )
> | NaN; otherwise returns 0.
> *----------------------------------------------------------------------------*/
>
> -int float32_is_signaling_nan( float32 a_ )
> +int float32_is_signaling_nan( float32 a_, float_status *status )
> {
> uint32_t a = float32_val(a_);
> -#if SNAN_BIT_IS_ONE
> - return ((uint32_t)(a << 1) >= 0xff800000);
> -#else
> - return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
> -#endif
> + if (status->snan_bit_is_one) {
> + return ((uint32_t)(a << 1) >= 0xff800000);
> + } else {
> + return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
> + }
Please correct the style while touching the lines.
Thanks,
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values Aleksandar Markovic
@ 2016-04-13 12:23 ` Leon Alrae
0 siblings, 0 replies; 23+ messages in thread
From: Leon Alrae @ 2016-04-13 12:23 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, afaerber, aurelien,
rth, maciej.rozycki
On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
>
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct default NaN values (in their 16-, 32-, and 64-bit flavors).
>
> For more info, see [1], page 84, Table 6.3 "Value Supplied When
> a New Quiet NaN Is Created", and [2], page 52, table 3.7 "Default
> NaN Encodings".
>
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
>
> [2] "MIPS Architecture for Programmers Volume IV-j:
> The MIPS32® SIMD Architecture Module",
> Imagination Technologies LTD, Revision 1.12, February 3, 2016
>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
> fpu/softfloat-specialize.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 53dae9b..169246e 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
> if (status->snan_bit_is_one) {
> return const_float16(0x7DFF);
> } else {
> +#if defined(TARGET_MIPS)
> + return const_float16(0x7E00);
> +#else
> return const_float16(0xFE00);
> +#endif
> }
> #endif
> }
> @@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
> if (status->snan_bit_is_one) {
> return const_float32(0x7FBFFFFF);
> } else {
> +#if defined(TARGET_MIPS)
> + return const_float32(0x7FC00000);
> +#else
> return const_float32(0xFFC00000);
> +#endif
> }
> #endif
> }
> @@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
> if (status->snan_bit_is_one) {
> return const_float64(LIT64( 0x7FF7FFFFFFFFFFFF ));
> } else {
> +#if defined(TARGET_MIPS)
> + return const_float64(LIT64( 0x7FF8000000000000 ));
Could you remove space after/before the parentheses, please? The
scripts/checkpatch.pl would complain here. Otherwise looks good to me.
Thanks,
Leon
> +#else
> return const_float64(LIT64( 0xFFF8000000000000 ));
> +#endif
> }
> #endif
> }
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd() Aleksandar Markovic
@ 2016-04-13 12:47 ` Leon Alrae
2016-04-13 13:53 ` Aleksandar Markovic
0 siblings, 1 reply; 23+ messages in thread
From: Leon Alrae @ 2016-04-13 12:47 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, afaerber, aurelien,
rth, maciej.rozycki
On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
>
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct the order of argument comparisons in pickNaNMulAdd().
>
> For more info, see [2], page 53, section "3.5.3 NaN Propagation".
>
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
>
> [2] "MIPS Architecture for Programmers Volume IV-j:
> The MIPS32® SIMD Architecture Module",
> Imagination Technologies LTD, Revision 1.12, February 3, 2016
>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
> fpu/softfloat-specialize.h | 41 +++++++++++++++++++++++++++++------------
> 1 file changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 169246e..807ecc0 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
> return 3;
> }
>
> - /* Prefer sNaN over qNaN, in the c, a, b order. */
> - if (cIsSNaN) {
> - return 2;
> - } else if (aIsSNaN) {
> - return 0;
> - } else if (bIsSNaN) {
> - return 1;
> - } else if (cIsQNaN) {
> - return 2;
> - } else if (aIsQNaN) {
> - return 0;
Initially I was confused with this part of diff until I realized that
you had modified the original order in pickNaNMulAdd in patch #1 -- was
that intended?
Otherwise:
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
> + if (status->snan_bit_is_one) {
> + /* Prefer sNaN over qNaN, in the a, b, c order. */
> + if (aIsSNaN) {
> + return 0;
> + } else if (bIsSNaN) {
> + return 1;
> + } else if (cIsSNaN) {
> + return 2;
> + } else if (aIsQNaN) {
> + return 0;
> + } else if (bIsQNaN) {
> + return 1;
> + } else {
> + return 2;
> + }
> } else {
> - return 1;
> + /* Prefer sNaN over qNaN, in the c, a, b order. */
> + if (cIsSNaN) {
> + return 2;
> + } else if (aIsSNaN) {
> + return 0;
> + } else if (bIsSNaN) {
> + return 1;
> + } else if (cIsQNaN) {
> + return 2;
> + } else if (aIsQNaN) {
> + return 0;
> + } else {
> + return 1;
> + }
> }
> }
> #elif defined(TARGET_PPC)
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()
2016-04-13 12:47 ` Leon Alrae
@ 2016-04-13 13:53 ` Aleksandar Markovic
0 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-13 13:53 UTC (permalink / raw)
To: Leon Alrae, Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
qemu-arm, qemu-ppc, Petar Jovanovic, pbonzini, Miodrag Dinic,
edgar.iglesias, gxt, afaerber, aurelien, rth, Maciej Rozycki
Thanks, you are right, this area is changed in patch #1 too. However, it was not intended to be that way. Patch #1 should leave this function as-is, and the entire change for this function should be in this patch. I will organize the code as intended in the next version of the series. Yours, Aleksandar
________________________________________
From: Leon Alrae
Sent: Wednesday, April 13, 2016 5:47 AM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: proljc@gmail.com; kbastian@mail.uni-paderborn.de; mark.cave-ayland@ilande.co.uk; agraf@suse.de; blauwirbel@gmail.com; jcmvbkbc@gmail.com; Aleksandar Markovic; qemu-arm@nongnu.org; qemu-ppc@nongnu.org; Petar Jovanovic; pbonzini@redhat.com; Miodrag Dinic; edgar.iglesias@gmail.com; gxt@mprc.pku.edu.cn; afaerber@suse.de; aurelien@aurel32.net; rth@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd()
On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
>
> Only for Mips platform, and only for cases when snan_bit_is_one is 0,
> correct the order of argument comparisons in pickNaNMulAdd().
>
> For more info, see [2], page 53, section "3.5.3 NaN Propagation".
>
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
>
> [2] "MIPS Architecture for Programmers Volume IV-j:
> The MIPS32® SIMD Architecture Module",
> Imagination Technologies LTD, Revision 1.12, February 3, 2016
>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
> fpu/softfloat-specialize.h | 41 +++++++++++++++++++++++++++++------------
> 1 file changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 169246e..807ecc0 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
> return 3;
> }
>
> - /* Prefer sNaN over qNaN, in the c, a, b order. */
> - if (cIsSNaN) {
> - return 2;
> - } else if (aIsSNaN) {
> - return 0;
> - } else if (bIsSNaN) {
> - return 1;
> - } else if (cIsQNaN) {
> - return 2;
> - } else if (aIsQNaN) {
> - return 0;
Initially I was confused with this part of diff until I realized that
you had modified the original order in pickNaNMulAdd in patch #1 -- was
that intended?
Otherwise:
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
> + if (status->snan_bit_is_one) {
> + /* Prefer sNaN over qNaN, in the a, b, c order. */
> + if (aIsSNaN) {
> + return 0;
> + } else if (bIsSNaN) {
> + return 1;
> + } else if (cIsSNaN) {
> + return 2;
> + } else if (aIsQNaN) {
> + return 0;
> + } else if (bIsQNaN) {
> + return 1;
> + } else {
> + return 2;
> + }
> } else {
> - return 1;
> + /* Prefer sNaN over qNaN, in the c, a, b order. */
> + if (cIsSNaN) {
> + return 2;
> + } else if (aIsSNaN) {
> + return 0;
> + } else if (bIsSNaN) {
> + return 1;
> + } else if (cIsQNaN) {
> + return 2;
> + } else if (aIsQNaN) {
> + return 0;
> + } else {
> + return 1;
> + }
> }
> }
> #elif defined(TARGET_PPC)
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-12 18:45 ` Eduardo Habkost
@ 2016-04-13 18:41 ` Aleksandar Markovic
2016-04-13 19:04 ` Eduardo Habkost
0 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-13 18:41 UTC (permalink / raw)
To: Eduardo Habkost, Aleksandar Markovic
Cc: qemu-devel, proljc, kbastian, mark.cave-ayland, agraf,
Maciej Rozycki, Petar Jovanovic, blauwirbel, jcmvbkbc, qemu-arm,
qemu-ppc, edgar.iglesias, Miodrag Dinic, pbonzini, gxt,
Leon Alrae, afaerber, aurelien, rth
Hello, Eduardo,
I greatly appreciate your time spent on this matter and your unfailing attention to detail.
For Alpha and Xtensa, this is for sure, they will zero their CPU objects, as you hinted:
target-alpha/cpu.c:
162 cpu_class = object_class_by_name(TYPE("ev67"));
163 }
164: cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
165
166 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
target-xtensa/helper.c:
125 }
126
127: cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
128 env = &cpu->env;
129
So, I will remove their set_snan_bit_is_one(0) calls, as you suggested.
This leaves only ppc, s390x, and TriCore calling set_snan_bit_is_one(0) it this
patch series..
I'll take one more look at them tomorrow, and will get back to you.
Yours,
Aleksandar
________________________________________
From: Eduardo Habkost [ehabkost@redhat.com]
Sent: Tuesday, April 12, 2016 11:45 AM
To: Aleksandar Markovic
Cc: qemu-devel@nongnu.org; proljc@gmail.com; kbastian@mail.uni-paderborn.de; mark.cave-ayland@ilande.co.uk; agraf@suse.de; Maciej Rozycki; Petar Jovanovic; blauwirbel@gmail.com; jcmvbkbc@gmail.com; Aleksandar Markovic; qemu-arm@nongnu.org; qemu-ppc@nongnu.org; edgar.iglesias@gmail.com; Miodrag Dinic; pbonzini@redhat.com; gxt@mprc.pku.edu.cn; Leon Alrae; afaerber@suse.de; aurelien@aurel32.net; rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
On Tue, Apr 12, 2016 at 02:58:03PM +0200, Aleksandar Markovic wrote:
[...]
> 4) Updated code for all platforms to reflect changes in SoftFloat library.
> This change is twofolds: it includes modifications of SoftFloat library
> functions invocations, and an addition of invocation of function
> set_snan_bit_is_one() during CPU initialization, with arguments that
> are appropriate for each particular platform.
>
> In order to be at the same time accurate in relation to floating point
> arithmetics and consistent with a particular platform code, following
> principle is adopted related to invocations of new function
> set_snan_bit_is_one():
>
> 1. If a target platform doesn't use SoftFloat library, nothing is added.
> (cris, lm32, moxie)
> 2. Else, if a target platform's signaling bit meaning is "1 is
> signaling", explicit invocation of set_snan_bit_is_one(1) is added.
> (mips, sh4, unicore32)
> (for mips this will change in the second patch of this
> series, but this very patch leaves mips features as
> they currently are.)
> 3. Else, if a target platform explicitly sets other fields of its
> float_status structure(s), explicit invocation of
> set_snan_bit_is_one(0) is added.
> (ppc, s390x, tricore)
> 4. Else, if a target platform doesn't explicitly set its structure
> CPUXXXState, explicit invocation of set_snan_bit_is_one(0) is added.
> (alpha, xtensa)
The CPU struct is zeroed by object_new() when the CPU object is
created, so the field is already set to 0 by default on all
architectures. You shouldn't need set_snan_bit_is_one(0) calls on
CPU initialization on any architecture.
> 5. For remaining cases, nothing is added. (Those cases explicitly set
> their CPUXXXState/float_status structures to 0, and thus implicitly
> perform set_snan_bit_is_one(0).)
> (arm, i386, m68k, microblaze, openrisc, sparc)
>
--
Eduardo
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-13 18:41 ` Aleksandar Markovic
@ 2016-04-13 19:04 ` Eduardo Habkost
0 siblings, 0 replies; 23+ messages in thread
From: Eduardo Habkost @ 2016-04-13 19:04 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Aleksandar Markovic, qemu-devel, proljc, kbastian,
mark.cave-ayland, agraf, Maciej Rozycki, Petar Jovanovic,
blauwirbel, jcmvbkbc, qemu-arm, qemu-ppc, edgar.iglesias,
Miodrag Dinic, pbonzini, gxt, Leon Alrae, afaerber, aurelien,
rth
On Wed, Apr 13, 2016 at 06:41:48PM +0000, Aleksandar Markovic wrote:
> Hello, Eduardo,
>
> I greatly appreciate your time spent on this matter and your unfailing attention to detail.
>
> For Alpha and Xtensa, this is for sure, they will zero their CPU objects, as you hinted:
>
> target-alpha/cpu.c:
> 162 cpu_class = object_class_by_name(TYPE("ev67"));
> 163 }
> 164: cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
> 165
> 166 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> target-xtensa/helper.c:
> 125 }
> 126
> 127: cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
> 128 env = &cpu->env;
> 129
>
> So, I will remove their set_snan_bit_is_one(0) calls, as you suggested.
>
> This leaves only ppc, s390x, and TriCore calling set_snan_bit_is_one(0) it this
> patch series..
All CPU objects are created using object_new(), and are already
zeroed on initialization.
ppc CPUs are created using cpu_ppc_init(), which reuses
cpu_generic_init(), which calls object_new().
s390x CPUs are created by s390x_new_cpu(), which calls
cpu_s390x_create(), which calls object_new().
tricore CPUs are created by cpu_tricore_init(), which reuses
cpu_generic_init().
--
Eduardo
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> Aleksandar Markovic
@ 2016-04-14 10:52 ` Leon Alrae
0 siblings, 0 replies; 23+ messages in thread
From: Leon Alrae @ 2016-04-14 10:52 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, afaerber, aurelien,
rth, maciej.rozycki
On 12/04/16 13:58, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
>
> Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
> (pre-abs2008) ABS and NEG instructions are arithmetic (any NaN operand
> signals invalid operation), while abs2008 ones are non-arithmetic, always
> changing the sign bit, even for NaN-like operands. Details on these
> instructions are documented in [1] p. 35 and 359.
>
> [1] "MIPS® Architecture For Programmers Volume II-A:
> The MIPS64® Instruction Set Reference Manual",
> Imagination Technologies LTD, Revision 6.04, November 13, 2015
>
> Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
> target-mips/translate.c | 27 +++++++++++++++++++++++----
> 1 file changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index de0b224..1d376fc 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1434,6 +1434,8 @@ typedef struct DisasContext {
> bool vp;
> bool cmgcr;
> bool mrp;
> + bool abs2008;
> +
Blank line. Otherwise:
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Regards,
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
2016-04-12 18:45 ` Eduardo Habkost
2016-04-13 12:11 ` Leon Alrae
@ 2016-04-14 15:31 ` Leon Alrae
2016-04-15 8:48 ` Aleksandar Markovic
2 siblings, 1 reply; 23+ messages in thread
From: Leon Alrae @ 2016-04-14 15:31 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
aleksandar.markovic, qemu-arm, qemu-ppc, petar.jovanovic,
pbonzini, miodrag.dinic, edgar.iglesias, gxt, afaerber, aurelien,
rth, maciej.rozycki
On 12/04/2016 13:58, Aleksandar Markovic wrote:
> @@ -3200,11 +3200,17 @@ FLOAT_RINT(rint_d, 64)
> #define FLOAT_CLASS_POSITIVE_ZERO 0x200
>
> #define FLOAT_CLASS(name, bits) \
> -uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
> +uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
> + uint ## bits ## _t arg, uint32_t is_msa) \
> { \
> - if (float ## bits ## _is_signaling_nan(arg)) { \
> + float_status* fst; \
> + \
> + fst = (is_msa == 1) ? \
> + &env->active_tc.msa_fp_status : &env->active_fpu.fp_status; \
> + \
> + if (float ## bits ## _is_signaling_nan(arg, fst)) { \
> return FLOAT_CLASS_SIGNALING_NAN; \
> - } else if (float ## bits ## _is_quiet_nan(arg)) { \
> + } else if (float ## bits ## _is_quiet_nan(arg, fst)) { \
> return FLOAT_CLASS_QUIET_NAN; \
> } else if (float ## bits ## _is_neg(arg)) { \
> if (float ## bits ## _is_infinity(arg)) { \
Let's make it a common function which takes float_status passed from FPU and
MSA helpers and avoid is_msa:
#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
+uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
+ float_status *fst) \
{ \
- if (float ## bits ## _is_signaling_nan(arg)) { \
+ if (float ## bits ## _is_signaling_nan(arg, fst)) { \
return FLOAT_CLASS_SIGNALING_NAN; \
- } else if (float ## bits ## _is_quiet_nan(arg)) { \
+ } else if (float ## bits ## _is_quiet_nan(arg, fst)) { \
return FLOAT_CLASS_QUIET_NAN; \
} else if (float ## bits ## _is_neg(arg)) { \
if (float ## bits ## _is_infinity(arg)) { \
@@ -3227,6 +3228,12 @@ uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
return FLOAT_CLASS_POSITIVE_NORMAL; \
} \
} \
+} \
+ \
+uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
+ uint ## bits ## _t arg) \
+{ \
+ return float_ ## name(arg, &env->active_fpu.fp_status); \
}
FLOAT_CLASS(class_s, 32)
And in MSA:
+ float_status *status = &env->active_tc.msa_fp_status;
if (df == DF_WORD) {
- pwd->w[0] = helper_float_class_s(pws->w[0]);
- pwd->w[1] = helper_float_class_s(pws->w[1]);
- pwd->w[2] = helper_float_class_s(pws->w[2]);
- pwd->w[3] = helper_float_class_s(pws->w[3]);
+ pwd->w[0] = float_class_s(pws->w[0], status);
+ pwd->w[1] = float_class_s(pws->w[1], status);
+ pwd->w[2] = float_class_s(pws->w[2], status);
+ pwd->w[3] = float_class_s(pws->w[3], status);
} else {
- pwd->d[0] = helper_float_class_d(pws->d[0]);
- pwd->d[1] = helper_float_class_d(pws->d[1]);
+ pwd->d[0] = float_class_d(pws->d[0], status);
+ pwd->d[1] = float_class_d(pws->d[1], status);
}
Thanks,
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-14 15:31 ` Leon Alrae
@ 2016-04-15 8:48 ` Aleksandar Markovic
2016-04-15 10:41 ` Leon Alrae
0 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-15 8:48 UTC (permalink / raw)
To: Leon Alrae, Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
qemu-arm, qemu-ppc, Petar Jovanovic, pbonzini, Miodrag Dinic,
edgar.iglesias, gxt, afaerber, aurelien, rth, Maciej Rozycki
Agreed. This looks much better, and is simpler and faster. Though, it looks to me that "fst" should be called "status" instead (just not to break consistency throughout SoftFloat library and in other places of assigning name "status" to the last argument of any function if its type is float_status*). If you agree, I am going to replace name "fst" with name "status" in the code that you provided, otherwise as-is.
________________________________________
From: Leon Alrae
Sent: Thursday, April 14, 2016 8:31 AM
To: Aleksandar Markovic; qemu-devel@nongnu.org
Cc: proljc@gmail.com; kbastian@mail.uni-paderborn.de; mark.cave-ayland@ilande.co.uk; agraf@suse.de; blauwirbel@gmail.com; jcmvbkbc@gmail.com; Aleksandar Markovic; qemu-arm@nongnu.org; qemu-ppc@nongnu.org; Petar Jovanovic; pbonzini@redhat.com; Miodrag Dinic; edgar.iglesias@gmail.com; gxt@mprc.pku.edu.cn; afaerber@suse.de; aurelien@aurel32.net; rth@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
On 12/04/2016 13:58, Aleksandar Markovic wrote:
> @@ -3200,11 +3200,17 @@ FLOAT_RINT(rint_d, 64)
> #define FLOAT_CLASS_POSITIVE_ZERO 0x200
>
> #define FLOAT_CLASS(name, bits) \
> -uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
> +uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
> + uint ## bits ## _t arg, uint32_t is_msa) \
> { \
> - if (float ## bits ## _is_signaling_nan(arg)) { \
> + float_status* fst; \
> + \
> + fst = (is_msa == 1) ? \
> + &env->active_tc.msa_fp_status : &env->active_fpu.fp_status; \
> + \
> + if (float ## bits ## _is_signaling_nan(arg, fst)) { \
> return FLOAT_CLASS_SIGNALING_NAN; \
> - } else if (float ## bits ## _is_quiet_nan(arg)) { \
> + } else if (float ## bits ## _is_quiet_nan(arg, fst)) { \
> return FLOAT_CLASS_QUIET_NAN; \
> } else if (float ## bits ## _is_neg(arg)) { \
> if (float ## bits ## _is_infinity(arg)) { \
Let's make it a common function which takes float_status passed from FPU and
MSA helpers and avoid is_msa:
#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
+uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
+ float_status *fst) \
{ \
- if (float ## bits ## _is_signaling_nan(arg)) { \
+ if (float ## bits ## _is_signaling_nan(arg, fst)) { \
return FLOAT_CLASS_SIGNALING_NAN; \
- } else if (float ## bits ## _is_quiet_nan(arg)) { \
+ } else if (float ## bits ## _is_quiet_nan(arg, fst)) { \
return FLOAT_CLASS_QUIET_NAN; \
} else if (float ## bits ## _is_neg(arg)) { \
if (float ## bits ## _is_infinity(arg)) { \
@@ -3227,6 +3228,12 @@ uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
return FLOAT_CLASS_POSITIVE_NORMAL; \
} \
} \
+} \
+ \
+uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
+ uint ## bits ## _t arg) \
+{ \
+ return float_ ## name(arg, &env->active_fpu.fp_status); \
}
FLOAT_CLASS(class_s, 32)
And in MSA:
+ float_status *status = &env->active_tc.msa_fp_status;
if (df == DF_WORD) {
- pwd->w[0] = helper_float_class_s(pws->w[0]);
- pwd->w[1] = helper_float_class_s(pws->w[1]);
- pwd->w[2] = helper_float_class_s(pws->w[2]);
- pwd->w[3] = helper_float_class_s(pws->w[3]);
+ pwd->w[0] = float_class_s(pws->w[0], status);
+ pwd->w[1] = float_class_s(pws->w[1], status);
+ pwd->w[2] = float_class_s(pws->w[2], status);
+ pwd->w[3] = float_class_s(pws->w[3], status);
} else {
- pwd->d[0] = helper_float_class_d(pws->d[0]);
- pwd->d[1] = helper_float_class_d(pws->d[1]);
+ pwd->d[0] = float_class_d(pws->d[0], status);
+ pwd->d[1] = float_class_d(pws->d[1], status);
}
Thanks,
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-15 8:48 ` Aleksandar Markovic
@ 2016-04-15 10:41 ` Leon Alrae
2016-04-15 11:38 ` Aleksandar Markovic
0 siblings, 1 reply; 23+ messages in thread
From: Leon Alrae @ 2016-04-15 10:41 UTC (permalink / raw)
To: Aleksandar Markovic, Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
qemu-arm, qemu-ppc, Petar Jovanovic, pbonzini, Miodrag Dinic,
edgar.iglesias, gxt, afaerber, aurelien, rth, Maciej Rozycki
On 15/04/16 09:48, Aleksandar Markovic wrote:
> Agreed. This looks much better, and is simpler and faster. Though, it looks to me that "fst" should be called "status" instead (just not to break consistency throughout SoftFloat library and in other places of assigning name "status" to the last argument of any function if its type is float_status*). If you agree, I am going to replace name "fst" with name "status" in the code that you provided, otherwise as-is.
Yes, "status" will be fine.
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-15 10:41 ` Leon Alrae
@ 2016-04-15 11:38 ` Aleksandar Markovic
2016-04-17 18:21 ` Aleksandar Markovic
0 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-15 11:38 UTC (permalink / raw)
To: Leon Alrae, Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
qemu-arm, qemu-ppc, Petar Jovanovic, pbonzini, Miodrag Dinic,
edgar.iglesias, gxt, afaerber, aurelien, rth, Maciej Rozycki
Hi, Leon,
There is one more subtle point here. The question is: Where to put declarations of two new functions? This is a new case in the organization of mips-specific source code files. File helpers.h does not seem to be a good place, cpu.h - maybe, but still looks clumsy to me.
IMHO, my solution from earlier versions of this patch series, in spite of containing code duplication, is superior in the sense of keeping current mips-specific source code file relations intact, respecting autonomy of msa_helpers.c, and is the best overall.
Yours,
Aleksandar
________________________________________
From: Leon Alrae
Sent: Friday, April 15, 2016 3:41 AM
To: Aleksandar Markovic; Aleksandar Markovic; qemu-devel@nongnu.org
Cc: proljc@gmail.com; kbastian@mail.uni-paderborn.de; mark.cave-ayland@ilande.co.uk; agraf@suse.de; blauwirbel@gmail.com; jcmvbkbc@gmail.com; qemu-arm@nongnu.org; qemu-ppc@nongnu.org; Petar Jovanovic; pbonzini@redhat.com; Miodrag Dinic; edgar.iglesias@gmail.com; gxt@mprc.pku.edu.cn; afaerber@suse.de; aurelien@aurel32.net; rth@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
On 15/04/16 09:48, Aleksandar Markovic wrote:
> Agreed. This looks much better, and is simpler and faster. Though, it looks to me that "fst" should be called "status" instead (just not to break consistency throughout SoftFloat library and in other places of assigning name "status" to the last argument of any function if its type is float_status*). If you agree, I am going to replace name "fst" with name "status" in the code that you provided, otherwise as-is.
Yes, "status" will be fine.
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
2016-04-15 11:38 ` Aleksandar Markovic
@ 2016-04-17 18:21 ` Aleksandar Markovic
0 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2016-04-17 18:21 UTC (permalink / raw)
To: Leon Alrae, Aleksandar Markovic, qemu-devel
Cc: proljc, kbastian, mark.cave-ayland, agraf, blauwirbel, jcmvbkbc,
qemu-arm, qemu-ppc, Petar Jovanovic, pbonzini, Miodrag Dinic,
edgar.iglesias, gxt, afaerber, aurelien, rth, Maciej Rozycki
Hi, Leon,
I cannot say thank you enough for all your valuable feedback.
Just wanted to give you a heads up that in the next version of this patch series (planned for tomorrow (Monday) or the day after tomorrow), I am going to integrate all your suggestions from this thread, including name "status" instead of "fst", and also following segment in cpu.h:
/* op_helper.c */
uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);
(unless you tell me not to do so)
Also, I think there will be some improvements in the patch related to <CEIL|CVT|FLOOR|...>, that are currently being analysed and tested here.
Sincerely,
Aleksandar
________________________________________
From: Aleksandar Markovic
Sent: Friday, April 15, 2016 4:38 AM
To: Leon Alrae; Aleksandar Markovic; qemu-devel@nongnu.org
Cc: proljc@gmail.com; kbastian@mail.uni-paderborn.de; mark.cave-ayland@ilande.co.uk; agraf@suse.de; blauwirbel@gmail.com; jcmvbkbc@gmail.com; qemu-arm@nongnu.org; qemu-ppc@nongnu.org; Petar Jovanovic; pbonzini@redhat.com; Miodrag Dinic; edgar.iglesias@gmail.com; gxt@mprc.pku.edu.cn; afaerber@suse.de; aurelien@aurel32.net; rth@twiddle.net; Maciej Rozycki
Subject: RE: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
Hi, Leon,
There is one more subtle point here. The question is: Where to put declarations of two new functions? This is a new case in the organization of mips-specific source code files. File helpers.h does not seem to be a good place, cpu.h - maybe, but still looks clumsy to me.
IMHO, my solution from earlier versions of this patch series, in spite of containing code duplication, is superior in the sense of keeping current mips-specific source code file relations intact, respecting autonomy of msa_helpers.c, and is the best overall.
Yours,
Aleksandar
________________________________________
From: Leon Alrae
Sent: Friday, April 15, 2016 3:41 AM
To: Aleksandar Markovic; Aleksandar Markovic; qemu-devel@nongnu.org
Cc: proljc@gmail.com; kbastian@mail.uni-paderborn.de; mark.cave-ayland@ilande.co.uk; agraf@suse.de; blauwirbel@gmail.com; jcmvbkbc@gmail.com; qemu-arm@nongnu.org; qemu-ppc@nongnu.org; Petar Jovanovic; pbonzini@redhat.com; Miodrag Dinic; edgar.iglesias@gmail.com; gxt@mprc.pku.edu.cn; afaerber@suse.de; aurelien@aurel32.net; rth@twiddle.net; Maciej Rozycki
Subject: Re: [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit
On 15/04/16 09:48, Aleksandar Markovic wrote:
> Agreed. This looks much better, and is simpler and faster. Though, it looks to me that "fst" should be called "status" instead (just not to break consistency throughout SoftFloat library and in other places of assigning name "status" to the last argument of any function if its type is float_status*). If you agree, I am going to replace name "fst" with name "status" in the code that you provided, otherwise as-is.
Yes, "status" will be fine.
Leon
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2016-04-17 18:22 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-04-12 12:58 [Qemu-devel] [PATCH v4 0/9] target-mips: Initiate IEEE 754-2008 support Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
2016-04-12 18:45 ` Eduardo Habkost
2016-04-13 18:41 ` Aleksandar Markovic
2016-04-13 19:04 ` Eduardo Habkost
2016-04-13 12:11 ` Leon Alrae
2016-04-14 15:31 ` Leon Alrae
2016-04-15 8:48 ` Aleksandar Markovic
2016-04-15 10:41 ` Leon Alrae
2016-04-15 11:38 ` Aleksandar Markovic
2016-04-17 18:21 ` Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 2/9] softfloat: For Mips only, correct default NaN values Aleksandar Markovic
2016-04-13 12:23 ` Leon Alrae
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd() Aleksandar Markovic
2016-04-13 12:47 ` Leon Alrae
2016-04-13 13:53 ` Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 4/9] softfloat: Clean up hex constants capitalization in softfloat-specialize.h Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 5/9] softfloat: Clean up white spaces " Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 6/9] target-mips: Activate IEEE 274-2008 support Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> Aleksandar Markovic
2016-04-14 10:52 ` Leon Alrae
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> Aleksandar Markovic
2016-04-12 12:58 ` [Qemu-devel] [PATCH v4 9/9] target-mips: Clean up order of helpers for CVT.<L|W>.<S|D> Aleksandar Markovic
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