From: Yunhui Cui <B56489@freescale.com> To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>, <han.xu@freescale.com> Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>, <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui Cui <yunhui.cui@nxp.com> Subject: [PATCH v2 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Date: Fri, 22 Apr 2016 14:39:52 +0800 [thread overview] Message-ID: <1461307192-866-9-git-send-email-B56489@freescale.com> (raw) In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> From: Yunhui Cui <yunhui.cui@nxp.com> There is a hardware feature that qspi_amba_base is added internally by SOC design on ls2080a. so memmap_phy need not be added in driver. If memmap_phy is added, the flash A1 addr space is [0, memmap_phy] which far more than flash size. The AMBA memory will be divided into four parts and assign to every chipselect. Every channel will has two valid chipselects. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 6a022e7..b415663 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -736,11 +736,17 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q) { int nor_size = q->nor_size; void __iomem *base = q->iobase; + u32 mem_base; - qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); - qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); - qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); - qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); + if (has_added_amba_base_internal(q)) + mem_base = 0x0; + else + mem_base = q->memmap_phy; + + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD); + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD); + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD); + qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD); } /* -- 2.1.0.27.g96db324
WARNING: multiple messages have this Message-ID (diff)
From: B56489@freescale.com (Yunhui Cui) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Date: Fri, 22 Apr 2016 14:39:52 +0800 [thread overview] Message-ID: <1461307192-866-9-git-send-email-B56489@freescale.com> (raw) In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> From: Yunhui Cui <yunhui.cui@nxp.com> There is a hardware feature that qspi_amba_base is added internally by SOC design on ls2080a. so memmap_phy need not be added in driver. If memmap_phy is added, the flash A1 addr space is [0, memmap_phy] which far more than flash size. The AMBA memory will be divided into four parts and assign to every chipselect. Every channel will has two valid chipselects. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 6a022e7..b415663 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -736,11 +736,17 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q) { int nor_size = q->nor_size; void __iomem *base = q->iobase; + u32 mem_base; - qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); - qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); - qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); - qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); + if (has_added_amba_base_internal(q)) + mem_base = 0x0; + else + mem_base = q->memmap_phy; + + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD); + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD); + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD); + qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD); } /* -- 2.1.0.27.g96db324
next prev parent reply other threads:[~2016-04-22 7:22 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-04-22 6:39 [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 2/9] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 3/9] mtd: spi-nor: fsl-quadspi: add fast-read mode support Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-07-21 19:35 ` Han Xu 2016-07-21 19:35 ` Han Xu 2016-08-06 14:27 ` Jagan Teki 2016-08-06 14:27 ` Jagan Teki 2016-08-06 14:27 ` Jagan Teki 2016-08-17 8:57 ` Yunhui Cui 2016-08-17 8:57 ` Yunhui Cui 2016-08-17 8:57 ` Yunhui Cui 2016-08-15 18:02 ` Li Yang 2016-08-15 18:02 ` Li Yang 2016-08-15 18:02 ` Li Yang 2016-08-17 9:07 ` Yunhui Cui 2016-08-17 9:07 ` Yunhui Cui 2016-08-17 9:07 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 7/9] mtd: fsl-quadspi: Solve Micron Spansion flash command conflict Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` [PATCH v2 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui 2016-04-22 6:39 ` Yunhui Cui [this message] 2016-04-22 6:39 ` [PATCH v2 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Yunhui Cui 2016-06-30 1:54 ` [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui 2016-06-30 1:54 ` Yunhui Cui 2016-06-30 1:54 ` Yunhui Cui 2016-07-21 5:58 ` Yunhui Cui 2016-07-21 5:58 ` Yunhui Cui 2016-07-21 5:58 ` Yunhui Cui 2016-07-21 17:09 ` Brian Norris 2016-07-21 17:09 ` Brian Norris 2016-07-21 17:09 ` Brian Norris 2016-07-21 19:34 ` Han Xu 2016-07-21 19:34 ` Han Xu 2016-07-21 19:34 ` Han Xu
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